JP2005291779A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To use only signal wires all required for actual operation for wire connections between a hard macro and a soft macro and prevent the time required for verifying the quality of the wire connections from being prolonged. <P>SOLUTION: This semiconductor integrated circuit is provided with the soft macro 10 having latches FF1-FF3 for signal output; the hard macro 20 having latches FF11-FF13 for signal input; and the wire connections 30 for connecting the soft macro 10 to the hard macro 20. Selectors S1-S3 for separating the latches FF1-FF3 for signal output from normal input signals IN1-IN3 and connecting them to a scan signal SI1 in a shift register form are arranged in the soft macro 10. Logic circuits (NAND11-NAND14, INV11, INV12, S14) for logically processing output of the latches FF11-FF13 for signal input are arranged in the hard macro 20. The quality of the wire connections is verified on the basis of output of the logic circuits when the scan signal SI1 is inputted. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor integrated circuit (LSI) provided with scanning means for verifying the quality of connection between circuit blocks.

  In semiconductor integrated circuits, with advances in technology, serial I / O units such as SerDes that need to operate at high speeds are realized with hard macros as serial high-speed communication exceeds 1 GHz / sec. It is converted into parallel data inside the hard macro and the operation speed is reduced to one-tenth to one-tenth, and then connected to the soft macro in the core part inside the silicon.

  Even though high-speed serial data is converted into parallel data, it is necessary to operate at a frequency exceeding 200 MHz in some cases between soft macro and hard macro. Therefore, the interface usually uses a flip-flop latch to synchronize with the clock. Exchanged with the signal.

  Therefore, Patent Document 1 realizes easy verification of the quality of the boundary area (connection) between blocks in an apparatus that combines a block combining standard cells and a custom block consisting of a macro block or IP (functional block). For this purpose, a method has been proposed in which when a custom block is set in a scan mode, a design such as an EXOR operation that is simpler than the normal operation is performed and output is performed.

Also, generally, when a scan chain is stretched on a hard macro, the quality of the connection between the hard macro and the soft macro is verified using a scan method that combines the scan chain stretched on the soft macro. It is possible.
JP 2001-183424 A

  However, in Patent Document 1, as shown in FIG. 1 and the like, since a signal representing an output result such as EXOR is newly added between the custom block and the macro block, the custom block requiring high-frequency operation. -The boundary area between macroblocks is disadvantageous in the layout.

  In the scanning method, the scan test time is limited by the longer one of the scan chain on the soft macro side or the scan chain on the hard macro side, and the connection between the soft macro and the hard macro is verified. Therefore, since it is necessary to read one register at a time in the scan-out mode, the test time becomes longer.

  An object of the present invention is to verify the quality of connections between circuit blocks such as between hard macros and soft macros, using only signal lines necessary for actual operation for the connections, and the time required for the verification. It is to provide a semiconductor integrated circuit which is not lengthened.

  The invention according to claim 1 is a first circuit block having n (n ≧ 2) signal output latches, a second circuit block having n signal input latches, and the n circuit blocks. In a semiconductor integrated circuit comprising a signal output latch and a wire connecting between the n signal output latches, the n signal output latches are connected to the first circuit block from the normal input signal. N selectors that are separated and connected to scan signals in a shift register form are arranged, and a logic circuit that logically processes the outputs of the n signal input latches is arranged in the second circuit block, The connection quality is verified based on the output of the logic circuit when a scan signal is input.

  According to a second aspect of the present invention, in the semiconductor integrated circuit according to the first aspect, the logic circuit includes first and second logic circuits that calculate outputs of the n signal input latches, and the first logic circuit. And a selector that selects one of the outputs of the second logic circuit according to the logic of the scan signal.

  According to a third aspect of the present invention, in the semiconductor integrated circuit according to the first or second aspect, the first and second circuit blocks are arranged in a soft macro and the first and second circuit blocks are arranged in a hard macro. The first circuit block of the soft macro and the second circuit block of the hard macro are connected by a first connection, and the first circuit block of the hard macro and the soft The second circuit block of the macro is connected by a second connection.

  According to the present invention, a large number of terminal pins and circuits for verification are not required, and connection between circuit blocks such as a soft macro and a hard macro is normally performed using only necessary signals, and the quality of the connection can be verified in a short time. .

  FIG. 1 is a block diagram of a semiconductor integrated circuit according to an embodiment of the present invention. 10 is a soft macro (first circuit block) constituting the core area, 20 is a hard macro (second circuit block) constituting the I / O area, 30 is a connection between the soft macro 10 and the hard macro 20, A semiconductor integrated circuit 40 includes the soft macro 10, the hard macro 20, and the wiring 30.

  The soft macro 10 includes signal output latches FF1 to FF3 made of flip-flops and signal input latches FF4 to FF6 made of flip-flops, and the hard macro 20 has signal input latches FF11 to FF11 made of flip-flops. Signal output latches FF14 to FF16 each including an FF 13 and a flip-flop are provided. The output of the latch FF1 is input to the latch FF11, the output of the latch FF2 is input to the latch FF12, the output of the latch FF3 is input to the latch FF13, the output of the latch FF14 is input to the latch FF4, and the output of the latch FF15 is latched. By connecting the output of the latch FF16 to the input of the FF5 and the input of the latch FF6, respectively, a connection 30 between the soft macro 10 and the hard macro 20 is formed, and transmission / reception between them is possible.

  In this embodiment, in order to verify the quality of the connection 30 between the soft macro 10 and the hard macro 20 as described above, selectors S1 to S3 can be connected to the soft macro 10 side to form a scan chain, NAND gates NAND1 to NAND4, inverters INV1 and INV2, and selector S4 are connected to form a logic circuit. Further, selectors S11 to S13 can also be connected to the hard macro 20 side to form a scan chain, and NAND gates NAND11 to NAND14, inverters INV11 and INV12, and selector S14 are connected to form a logic circuit. These scan chains and logic circuits constitute a scan circuit for verifying the quality of the connection 30 between the soft macro 10 and the hard macro 20.

  In the normal operation mode, the terminal pin selection signals SEL1 and SEL2 are set to "0", and the selectors S1 to S3 and S11 to S13 select the terminal b, so that the input signals IN1 to IN3 on the soft macro 10 side are selected. Are transferred to the hard macro 20 side and become output signals OUT11 to OUT13. Further, the input signals IN11 to IN13 on the hard macro 20 side are transferred to the soft macro 10 side to become output signals OUT1 to OUT3.

  Next, in the scan mode, since the terminal pin selection signals SEL1 and SEL2 are set to “1”, the selectors S1 to S3 and S11 to S13 select the terminal a, and the soft macro 10 side scans from the terminal pin. The signal SI1 is input, and the scan signal SI2 is input to the hard macro 20 from the terminal pin.

  The scan signal SI1 input to the soft macro 10 side appears as a signal X1 at the output of the latch FF1 and is taken into the latch FF2 and the latch FF11 to become signals X2 and X1 ', respectively. Further, the signal X2 is taken into the latch FF3 and the latch FF12 to become signals X3 and X2 ', respectively. Further, the signal X3 is taken into the latch FF 13 and becomes a signal X3 '. The outputs X1 'to X3' of the latches FF11 to FF13 are calculated by NAND gates NAND11 to NAND14 and inverters INV11 and INV12, and input to the selector S14 as signals X4 and X5. The selector S14 selects the terminal a when the scan signal SI1 is "1", and selects the terminal b when the scan signal SI1 is "0".

  From the above, when the scan signal SI1 is input to the soft macro 10 side, the connection scan from the soft macro 10 side to the hard macro 20 side is performed, and the operation waveform signals X1 to X3, X1 as shown in FIG. 'To X3', X4, and X5 can be obtained, and the quality of the connection from the soft macro 10 side to the hard macro 20 side can be verified by verifying the output signal OUTa of the selector S14. As the output signal OUTa, the signal X4 is output when the scan signal SI1 is “1”, and the signal X5 is output when the scan signal SI1 is “0”.

  Even when the scan signal SI2 is input to the hard macro 20 side, the quality of the connection from the hard macro 20 side to the soft macro 10 side can be verified by verifying the output signal OUTb of the selector S4 in the same manner as described above. It becomes possible.

  As described above, in the present embodiment, the selectors S1 to S4, S11 to S14, the NAND gates NAND1 to NAND4, NAND11 to NAND14, Only by adding the inverters INV1, INV2, INV11, and INV12, it is possible to verify the quality of the transmission / reception connection 30 between the soft macro 10 and the hard macro 20. At this time, a new line arrangement is not necessary at the boundary between the soft macro 10 and the hard macro 20, and the quality of the connection can be verified in a short time by inputting the scan signal once.

It is a block diagram of the semiconductor integrated circuit of the Example of this invention. 2 is a time chart at the time of scanning of the semiconductor integrated circuit of FIG.

Explanation of symbols

10: Soft macro 20: Hard macro 30: Connection 40: Semiconductor integrated circuit

Claims (3)

a first circuit block having n (n ≧ 2) signal output latches, a second circuit block having n signal input latches, the n signal output latches, and the n signal output latches. In a semiconductor integrated circuit comprising a connection for connecting the signal output latches of
In the first circuit block, n selectors for separating the n signal output latches from the normal input signal and connecting the scan signal in a shift register form are arranged,
In the second circuit block, a logic circuit for logically processing the outputs of the n signal input latches is arranged,
A semiconductor integrated circuit characterized in that the quality of the connection is verified by the output of the logic circuit when the scan signal is input. The semiconductor integrated circuit according to claim 1,
The logic circuit is configured to output one of the first and second logic circuits for calculating the outputs of the n signal input latches and one of the outputs of the first and second logic circuits according to the logic of the scan signal. A semiconductor integrated circuit comprising a selector for selecting. The semiconductor integrated circuit according to claim 1 or 2,
Arranging the first and second circuit blocks in a soft macro and arranging the first and second circuit blocks in a hard macro;
Connecting the first circuit block of the soft macro and the second circuit block of the hard macro with a first connection;
2. A semiconductor integrated circuit, wherein the first circuit block of the hard macro and the second circuit block of the soft macro are connected by a second connection.

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