JP2005286846A - Delta sigma modulation circuit and amplifier equipped with it - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a delta sigma modulation circuit capable of managing with both reduction in a switching count per unit time and improvement in a magnitude utilization ratio, and to provide an amplifier equipped with the circuit. <P>SOLUTION: A delta sigma modulation circuit 10 comprises an input terminal 1 inputted with an audio signal, and a quantifying device 4 cascade connected with a plurality of integrators for quantizing an output value of the plurality of integrators. The circuit 10 conducts delta sigma modulation for the signal inputted into the input terminal 1. Furthermore, the circuit 10 comprises an input signal amplitude detection unit 9 for detecting a magnitude of the signal inputted into the input terminal 1, a clock counter 6 for changing a pulse width of an output signal of the quantifying device 4, and a minimum pulse width restriction unit 5 for controlling pulse width variance by the clock counter 6, based on the detection result of the input signal amplitude detection unit 9. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a system for reproducing or amplifying an audio signal, and a delta-sigma modulation circuit that digitally encodes an audio signal with a relatively small number of bits, and a signal generated by the delta-sigma modulation circuit as control signals. The present invention relates to an amplifier that performs an amplification operation by switching a plurality of voltages.

  A conventional technique related to a delta-sigma modulation circuit and an amplifier including the same will be described below.

  For example, Non-Patent Document 1 discloses a delta-sigma modulation technique for digitally encoding an audio signal with a relatively small number of bits.

  Further, the idea of the pulse width limiting means for limiting the minimum pulse width is common to RLLC (Run Length Limited Code) which is a kind of binary coding modulation system. 2 is disclosed.

  Further, amplifiers that perform an amplification operation by switching a plurality of voltages using a signal generated by a delta-sigma modulation circuit as a control signal are disclosed in Patent Documents 1 and 2, for example.

That is, as disclosed in Patent Documents 1 and 2, there is a technique for encoding an audio signal into a binary value or a relatively small number of bits by a delta-sigma modulation circuit as in a speaker driving circuit, and controls the encoded signal. An amplification technique for operating a switching circuit as a signal and supplying audio power has already been put into practical use. Since the switching speed of the switching circuit is limited, the concept of generating a control signal by limiting the minimum pulse width so that the switching time interval does not become too short is also applied to the switching amplifier.
Patent 2683310 (Registered August 8, 1997) Patent 2828543 (Registered on September 18, 1998) "Acoustic systems and digital processing": The Institute of Electronics, Information and Communication Engineers (published first edition on March 25, 1995) / Author: Toshiro Oga, Yoshio Yamazaki, Yutaka Kaneda / P78-95 "Digital audio for sound engineers": Kenrokukan Publishing (first edition issued on December 20, 1987) / Supervision: Seiya Nikaido, Yoshio Yamazaki / P114

  However, the conventional delta-sigma modulation circuit and the amplifier including the same have the following problems.

First, a performance variable called “amplitude utilization factor” is defined. For example, when a binary signal generated by a delta sigma modulator is assigned to two voltages having a potential difference to form a pulse waveform, the amplitude of the analog signal that can be extracted from this pulse waveform is smaller than the amplitude of the pulse waveform. Therefore, this ratio is referred to as “amplitude utilization rate”.
(1) Generally, there is a limit to the amplitude of an audio signal that can be modulated without oscillation in delta-sigma modulation of the third order or higher. However, as a property of delta-sigma modulation, the higher the sampling frequency, the higher the amplitude utilization rate. Can be made.
(2) On the other hand, when viewed from the switching amplifier side, by increasing the sampling frequency, the number of times of switching per unit time increases and heat loss increases.
(3) In order to reduce the load on the switching circuit, the time width that is the same as the pre-sampled value (quantized value before one clock) is set to a predetermined value or more by the preset number of sampling clocks. Although the number of times of switching per unit time can be reduced by using the minimum pulse width limiting means for limiting, the amplitude utilization factor is reduced by increasing the minimum pulse width.

Here, if the sampling period of (1) and the minimum pulse width of (3) are the same,
Amplitude utilization factor of (1) ≦ amplitude utilization factor of (3). The above inequality sign is due to the following reason.

That is, for (1), the value of the pulse (quantization result: Low or High) can be set independently for each sampling period, while the higher the sampling frequency, the higher the amplitude utilization rate can be improved. For (3), for example, the sampling frequency is set to 10 times that in (1), and the “minimum pulse width” is set so that the “time width equal to the previous quantized value” is 10 times the sampling period. In this case,
[Sampling period of (1)] = [Minimum pulse width of (3)]
It becomes. It is obvious that this time width is a possible [minimum pulse width] in each case. This is Tw. Here, the time width that each pulse can change is
In the case of (1): 1 × Tw, 2 × Tw, 3 × Tw, ...
In the case of (3): 1 × Tw, 1.1 × Tw, 1.2 × Tw, 1.3 × Tw,.
As described above, since (3) can be changed with higher time resolution, the amplitude utilization factor can be increased in accordance with the improvement of time resolution.

  Incidentally, as shown in FIG. 5, in the delta-sigma modulation circuit 100 in which (1) and (3) are simply combined, the number of times the output changes per unit time is reduced, that is, when combined with a switching amplifier (not shown). There has been a limit to satisfy both the reduction of the number of switchings per unit time and the improvement of the amplitude utilization rate.

  The present invention has been made in view of the above-described conventional problems, and an object of the present invention is to provide a delta-sigma modulation circuit capable of reducing both the number of switching times per unit time and improving the amplitude utilization factor, and the same. It is to provide an amplifier.

  In order to solve the above-described problem, the delta-sigma modulation circuit of the present invention includes an input unit to which an audio signal is input and a plurality of integrators connected in cascade, and a quantization that quantizes output values of the plurality of integrators. A delta-sigma modulation circuit for delta-sigma modulating the signal input to the input unit, and an input signal amplitude detecting means for detecting the amplitude of the signal input to the input unit, and an output of the quantizer Pulse width changing means for changing the pulse width of the signal and pulse width control means for controlling the pulse width change by the pulse width changing means based on the detection result of the input signal amplitude detecting means are provided. It is said.

  According to the invention, the input signal amplitude detecting means for detecting the amplitude of the signal input to the input unit is provided, and the pulse width control means is configured to detect the pulse based on the detection result of the input signal amplitude detecting means. The pulse width change by the width changing means is controlled.

  Therefore, the pulse width change by the pulse width changing means is controlled according to the amplitude of the signal input to the input unit. For example, when the absolute value of the input signal amplitude is small, control is performed so that the minimum pulse width is wide. can do. As a result, the amplitude utilization factor is reduced, but the influence of the amplitude utilization factor is small because the input signal itself is small. In addition, the number of times that the output per unit time changes can be reduced by controlling the minimum pulse width to be wide. For this reason, the electric power consumed by switching can be reduced.

  On the other hand, when the absolute value of the input signal amplitude is large, for example, the number of clocks for determining the minimum pulse width can be decreased and the minimum pulse width can be shortened. As a result, the amplitude utilization rate increases, so that the power that can be extracted from the power source having the same voltage value increases.

  When the amplitude is large, the output density of the same quantized value (positive quantized value or negative quantized value) increases from the quantizer, and the number of times the output per unit time changes does not increase. . For this reason, since the sampling frequency does not increase, an increase in the number of switching times per unit time can be prevented.

  Therefore, it is possible to provide a delta-sigma modulation circuit that can simultaneously reduce the number of times of switching per unit time and improve the amplitude utilization rate.

  In the delta-sigma modulation circuit according to the present invention, in the delta-sigma modulation circuit described above, the pulse width control unit sets a minimum pulse time width based on a detection result of the input signal amplitude detection unit. It is characterized by.

  According to the above invention, the minimum pulse time width is set based on the detection result of the input signal amplitude detection means. For this reason, the minimum pulse time width for preventing the sampling period from becoming too small can be set according to the amplitude of the input signal instead of being set constant.

  The delta-sigma modulation circuit of the present invention is characterized in that, in the above-described delta-sigma modulation circuit, the output information of the pulse width limiting means is negatively fed back to the input side.

  According to the above invention, since the output information of the pulse width limiting means is negatively fed back to the input side, an output following the input signal can be obtained.

The delta-sigma modulation circuit of the present invention is the above-described delta-sigma modulation circuit, wherein the pulse width limiting means is a quantized value one clock before the plurality of quantized values output from the quantizer. The time width that is the same as the pre-sampled value is a sampling clock count set in advance,
It is characterized in that it is limited to a time width equal to the pre-sampled value = sampling clock time width × time width equal to the number of counts.

  According to the above invention, the pulse width limiting means limits the time width of the pulse by “time width equal to the pre-sampled value = sampling clock time width × count number”. Accordingly, since the minimum pulse time width can be set according to the number of pulse counts, the pulse time width can be easily set.

  In the delta-sigma modulation circuit according to the present invention, in the delta-sigma modulation circuit described above, the input signal amplitude detection unit detects an absolute value of the input signal, while the pulse width limiting unit detects the absolute value of the input signal. Is characterized in that the sampling clock count is changed when the threshold value exceeds a preset threshold value.

  According to the above invention, the input signal amplitude detection means detects the absolute value of the input signal. That is, since the input signal takes positive and negative values, it is preferable to detect the absolute value of the input signal in order to detect the magnitude of the amplitude. The pulse width limiting means changes the number of sampling clocks when the absolute value of the input signal exceeds a preset threshold value. Therefore, when controlling the pulse width change by the pulse width changing means based on the amplitude of the input signal, the control is easy because it is controlled by whether or not the threshold value is exceeded.

  Further, in the delta sigma modulation circuit according to the present invention, in the delta sigma modulation circuit described above, a threshold value set in advance for the information on the absolute value of the input signal from the input signal amplitude detection unit is “the absolute value increases. It is characterized in that it is set so as to maintain the relationship of “threshold value when threshold value ≧ threshold value when absolute value decreases”.

  According to the above invention, the threshold value set in advance for the information on the absolute value of the input signal from the input signal amplitude detection means is “threshold when the absolute value increases ≧ threshold when the absolute value decreases”. Is set to keep the relationship.

In other words, the delta-sigma modulator is composed of a plurality of integrators, and a signal whose amplitude changes is input to this. Here, the change in the amplitude of the input signal and the change in the integrator output, in particular, the change in the integrator output in the vicinity of the integration value (hereinafter referred to as the oscillation integration value) leading to oscillation are compared. First, when the input signal increases, the absolute value of the input signal amplitude when the integrator output reaches the oscillation integration value is A, and when the input signal decreases, the integrator output that has exceeded the oscillation integration value is If the absolute value of the input signal amplitude when recovering below the oscillation integral value is B,
A> B
It becomes. This is because, as is well known, the change in the integrator output is delayed by the time constant of the integrator with respect to the change in the input signal.

Therefore, as in the present invention,
[Threshold value when the absolute value of the input signal amplitude increases] ≧ [Threshold value when the absolute value of the input signal amplitude decreases]
Therefore, when the limit value of the minimum pulse width is switched, for example, the minimum pulse width can be controlled narrowly at the limit of oscillation, and the minimum pulse width is switched in the process of decreasing the input signal amplitude. In this case, it can be designed to reliably avoid oscillation.

  That is, the above relationship makes it possible to reduce the number of times of switching per unit time while avoiding oscillation, and when the switching amplifier is configured with this delta-sigma modulator, the power efficiency is relatively improved. be able to.

  The delta sigma modulation circuit according to the present invention is the delta sigma modulation circuit described above, wherein the pulse width limiting means increases the sampling clock as the absolute value of the input signal detected by the input signal amplitude detection means increases. It is characterized by changing so that the count number becomes small.

  According to the above invention, the pulse width limiting unit changes the count number of the sampling clock to be smaller as the absolute value of the input signal detected by the input signal amplitude detection unit is larger.

  Therefore, if the absolute value of the input signal amplitude is large, the amplitude utilization factor increases by reducing the count of the clock that determines the minimum pulse width and shortening the minimum pulse width, so the same voltage value The amount of power that can be taken out from the power source increases.

  When the amplitude is large, the output density of the same quantized value (positive quantized value or negative quantized value) increases from the quantizer, and the number of times the output per unit time changes does not increase. . For this reason, since the sampling frequency does not increase, an increase in the number of switching times per unit time can be prevented.

  In order to solve the above-described problems, the amplifier of the present invention is characterized by including pulse amplification means for performing pulse amplification at the subsequent stage of the delta-sigma modulation circuit described above.

  According to the invention described above, the amplifier includes the pulse amplification means for performing pulse amplification on the subsequent stage of the delta-sigma modulation circuit described above.

  Therefore, since the output signal from the delta-sigma modulation having the above-described effects is amplified by the pulse amplifying means, an amplifier capable of both reducing the number of switching times per unit time and improving the amplitude utilization rate is provided. be able to.

  An amplifier according to the present invention includes the delta sigma modulation circuit described above and a pulse amplification unit that performs pulse amplification after the pulse width limiting unit, and the amplified output information of the pulse amplification unit is supplied to the delta sigma modulation circuit. It is characterized by negative feedback to the input side.

  According to the above invention, the amplifier negatively feeds back the amplified output information of the pulse amplification means to the input side of the delta-sigma modulation circuit.

  Therefore, even if the output signal of the delta sigma modulation circuit is amplified and then returned to the input side of the delta sigma modulation circuit, an output signal that follows the input signal can be obtained similarly.

  As described above, the delta-sigma modulation circuit of the present invention includes an input signal amplitude detection unit that detects the amplitude of the signal input to the input unit, and a pulse width change unit that changes the pulse width of the output signal of the quantizer. And pulse width control means for controlling the pulse width change by the pulse width changing means based on the detection result of the input signal amplitude detecting means.

  Therefore, since the pulse width change by the pulse width changing means is controlled according to the amplitude of the signal input to the input unit, for example, when the absolute value of the input signal amplitude is small, the minimum pulse width should be widened. Can be controlled. As a result, the amplitude utilization factor is reduced, but the influence of the amplitude utilization factor is small because the input signal itself is small. In addition, the number of times that the output per unit time changes can be reduced by controlling the minimum pulse width to be wide. For this reason, the electric power consumed by switching can be reduced.

  On the other hand, when the absolute value of the input signal amplitude is large, for example, the number of clocks for determining the minimum pulse width can be decreased and the minimum pulse width can be shortened. As a result, the amplitude utilization rate increases, so that the power that can be extracted from the power source having the same voltage value increases.

  When the amplitude is large, the output density of the same quantized value (positive quantized value or negative quantized value) increases from the quantizer, and the number of times the output per unit time changes does not increase. . For this reason, since the sampling frequency does not increase, an increase in the number of switching times per unit time can be prevented.

  Therefore, it is possible to provide a delta-sigma modulation circuit capable of reducing both the number of switching times per unit time and improving the amplitude utilization rate.

  In addition, as described above, the amplifier of the present invention includes pulse amplification means for performing pulse amplification on the subsequent stage of the delta-sigma modulation circuit described above.

  Therefore, there is an effect that it is possible to provide an amplifier that can simultaneously reduce the number of times of switching per unit time and improve the amplitude utilization factor.

[Embodiment 1]
An embodiment of the present invention will be described with reference to FIGS. 1 and 2 as follows.

  As shown in FIG. 1, the delta sigma modulation circuit 10 of the present embodiment includes an input terminal 1 as an input unit to which an audio signal is input, an adder 2, an integrator adder group 3, and the integrator. A quantizer 4 that quantizes the output value of the adder group 3, a minimum pulse width limiter 5 as pulse width changing means, a clock counter 6 as pulse width changing means, and an output terminal 7 are provided. The signal input to the terminal 1 is delta-sigma modulated and output from the output terminal 7.

  As shown in FIG. 2, the integrator adder group 3 includes a plurality of integrators 3a and adders 3b connected in cascade.

The operation of the quantizer 4 and the minimum pulse width limiter 5 is controlled by a sampling clock 8 as shown in FIG. The minimum pulse width limiter 5 changes the pulse width of the output signal of the quantizer 4.
The output of the output terminal 7 is negatively fed back to the adder 2.

  Further, the delta sigma modulation circuit 10 of the present embodiment has an input signal amplitude detection unit 9 as input signal amplitude detection means for detecting the amplitude of the signal input to the input terminal 1, and has a minimum pulse width limit. The unit 5 controls the change in pulse width based on the detection result of the amplitude of the input signal by the input signal amplitude detection unit 9.

  That is, according to the output from the input signal amplitude detector 9, the clock counter 6 controls the minimum pulse width limiter 5 by changing the count number of the clock that determines the minimum pulse width.

Specifically, the delta-sigma modulation circuit 10 decreases the clock count that determines the minimum pulse width when the absolute value of the input signal amplitude detected by the input signal amplitude detector 9 increases above a certain value. And operate to shorten the minimum pulse width. That is, when the amplitude of the input signal is small, by taking a wide minimum pulse width,
(1) Although the amplitude utilization factor is small, the input signal itself is small, so that it operates well.

(2) The number of times the output per unit time changes can be reduced.
The operation is obtained.

Also, if the amplitude of the input signal increases above a certain value, by shortening the minimum pulse width,
(3) Since the amplitude utilization factor is increased, the operation is good even if the input signal amplitude is large.

(4) When the amplitude is large, the output density of the same quantized value (plus side quantized value or minus side quantized value) is increased from the quantizer 4, and the number of times the output per unit time changes is Does not increase.
The operation is obtained.

  As described above, in the delta sigma modulation circuit 10 of the present embodiment, the input signal amplitude detection unit 9 that detects the amplitude of the signal input to the input terminal 1 is provided, and the minimum pulse width limiting unit 5 Based on the detection result of the signal amplitude detector 9, the pulse width change by the clock counter 6 is controlled.

  Therefore, since the pulse width change by the clock counter 6 is controlled according to the amplitude of the signal input to the input terminal 1, for example, when the absolute value of the input signal amplitude is small, control is performed so that the minimum pulse width is wide. can do. As a result, the amplitude utilization factor is reduced, but the influence of the amplitude utilization factor is small because the input signal itself is small. In addition, the number of times that the output per unit time changes can be reduced by controlling the minimum pulse width to be wide. For this reason, the electric power consumed by switching can be reduced.

  On the other hand, when the absolute value of the input signal amplitude is large, for example, the number of clocks for determining the minimum pulse width can be decreased and the minimum pulse width can be shortened. As a result, the amplitude utilization rate increases, so that the power that can be extracted from the power source having the same voltage value increases.

  When the amplitude is large, the output density of the same quantized value (positive quantized value or negative quantized value) increases from the quantizer, and the number of times the output per unit time changes does not increase. . For this reason, since the sampling frequency does not increase, an increase in the number of switching times per unit time can be prevented.

  Therefore, it is possible to provide the delta-sigma modulation circuit 10 that can simultaneously reduce the number of times of switching per unit time and improve the amplitude utilization rate.

  In the delta-sigma modulation circuit 10 of the present embodiment, the minimum pulse time width is set based on the detection result of the input signal amplitude detection unit 9. For this reason, the minimum pulse time width for preventing the sampling period from becoming too small can be set according to the amplitude of the input signal instead of being set constant.

  Further, in the delta sigma modulation circuit 10 of the present embodiment, the output information of the minimum pulse width limiting unit 5 is negatively fed back to the input side, so that an output following the input signal can be obtained.

  In the delta-sigma modulation circuit 10 of the present embodiment, the minimum pulse width limiter 5 sets the pulse time width by “time width equal to the pre-sampled value = sampled clock time width × count number”. Restrict. Accordingly, since the minimum pulse time width can be set according to the number of pulse counts, the pulse time width can be easily set.

  Further, in the delta-sigma modulation circuit 10 of the present embodiment, the input signal amplitude detector 9 detects the absolute value of the input signal. That is, since the input signal takes positive and negative values, it is preferable to detect the absolute value of the input signal in order to detect the magnitude of the amplitude. Furthermore, the minimum pulse width limiter 5 changes the number of sampling clocks when the absolute value of the input signal exceeds a preset threshold value. Therefore, when the pulse width change by the clock counter 6 is controlled based on the amplitude of the input signal, the control is easy because it is controlled by whether or not the threshold value is exceeded.

  Further, in the delta-sigma modulation circuit 10 of the present embodiment, the threshold value set in advance for the information on the absolute value of the input signal from the input signal amplitude detection unit 9 is “threshold when the absolute value increases ≧ absolute It is set so as to maintain the relationship of “threshold value when the value decreases”.

That is, the delta-sigma modulation circuit 10 is composed of a plurality of integrators, and a signal whose amplitude changes is input to this. Here, the change in the amplitude of the input signal and the change in the integrator output, in particular, the change in the integrator output in the vicinity of the integration value (hereinafter referred to as the oscillation integration value) leading to oscillation are compared. First, when the input signal increases, the absolute value of the input signal amplitude when the integrator output reaches the oscillation integration value is A, and when the input signal decreases, the integrator output that has exceeded the oscillation integration value is If the absolute value of the input signal amplitude when recovering below the oscillation integral value is B,
A> B
It becomes. This is because, as is well known, the change in the integrator output is delayed by the time constant of the integrator with respect to the change in the input signal.

Therefore, as in this embodiment,
[Threshold value when the absolute value of the input signal amplitude increases] ≧ [Threshold value when the absolute value of the input signal amplitude decreases]
Therefore, when the limit value of the minimum pulse width is switched, for example, the minimum pulse width can be controlled narrowly at the limit of oscillation, and the minimum pulse width is switched in the process of decreasing the input signal amplitude. In this case, it can be designed to reliably avoid oscillation.

  That is, the above relationship makes it possible to reduce the number of times of switching per unit time while avoiding oscillation, and when the switching amplifier is configured by the delta-sigma modulation circuit 10, the power efficiency is relatively improved. Can be made.

  In the delta-sigma modulation circuit 10 of the present embodiment, the minimum pulse width limiter 5 has a smaller number of sampling clock counts as the absolute value of the input signal detected by the input signal amplitude detector 9 is larger. Change to

  Therefore, if the absolute value of the input signal amplitude is large, the amplitude utilization factor increases by reducing the count of the clock that determines the minimum pulse width and shortening the minimum pulse width, so the same voltage value The amount of power that can be taken out from the power source increases.

  When the amplitude is large, the output density of the same quantized value (positive quantized value or negative quantized value) increases from the quantizer, and the number of times the output per unit time changes does not increase. . For this reason, since the sampling frequency does not increase, an increase in the number of switching times per unit time can be prevented.

[Embodiment 2]
The following will describe another embodiment of the present invention with reference to FIGS. Configurations other than those described in the present embodiment are the same as those in the first embodiment. For convenience of explanation, members having the same functions as those shown in the drawings of the first embodiment are given the same reference numerals, and explanation thereof is omitted.

  As shown in FIG. 1, the amplifier 20 of the present embodiment has the delta-sigma modulation circuit 10 described in the first embodiment in the previous stage, and a pulse amplification section 30 as pulse amplification means for performing pulse amplification in the subsequent stage. Have. The pulse amplifier 30 includes a switching circuit 31 and a low-pass filter (LPF () 32).

  In the amplifier 20, the input audio signal is input to the delta sigma modulation circuit 10, and at the same time, the input signal amplitude detector 9 continuously detects the absolute value of the amplitude. The count number of the clock counter 6 is set in advance for the detected value, and the count information is transmitted to the clock counter.

  On the other hand, the audio signal input to the delta-sigma modulation circuit 10 is processed by the integrator adder group 3 and the result is input to the quantizer 4. In the case of quantization to binary, the quantized value is determined depending on whether the calculation result by the integrator adder group 3 is positive or negative. This operation is performed by a sampling clock (sampling clock). ) Every time.

  The quantization result is input to the next-stage minimum pulse width limiter 5 for each sampling clock. In this block, even if the output of the quantizer 4 changes, the quantization result is set for a certain period, that is, For the time corresponding to the minimum pulse width, a value holding the quantized value at the time of pre-sampling is output. This holding time is set by counting the sampling clock by the clock counter 6, and the count number is determined by the input signal amplitude detector 9.

  The pulse information output from the minimum pulse width limiting unit 5 is negatively fed back to the adder 2 which is an input unit of the integrator adder group 3, and the delta-sigma modulation operation is performed in a state where the pulse width is controlled. At the same time, by using the pulse information as a control signal, another DC voltage source, here, the switching circuit 31 for turning ON / OFF + Eo and -Eo is operated to perform pulse amplification.

  Since the pulse-amplified signal contains a quantization noise component in a band higher than the audio band, the signal corresponding to the input audio signal is amplified by passing through a low-pass filter (LPF) 32 for blocking this. The signal can be extracted.

  In the signal flow as described above, the delta sigma modulation circuit 10 according to the present embodiment has the minimum pulse when the absolute value of the input signal amplitude detected by the input signal amplitude detection unit 9 increases from a certain value. An operation is performed so as to reduce the count number of the clock that determines the width and to shorten the minimum pulse width.

  Specifically, when the amplitude of the input signal is small, widening the minimum pulse width reduces the amplitude utilization factor, but the input signal itself is small, so it operates well without causing a breakdown such as oscillation. . Therefore, it is possible to reduce the number of times the output per unit time changes.

  On the other hand, when the amplitude of the input signal increases from a certain value, the minimum pulse width is shortened to increase the amplitude utilization factor, so that the operation is good even when the input signal amplitude is large. When the amplitude is large, the output density of the same quantized value (positive quantized value or negative quantized value) is increased from the quantizer 4, and the number of times the output per unit time changes does not increase.

  By the above operation, delta-sigma modulation for expanding the amplitude utilization rate is performed without increasing the number of times the output per unit time changes.

  As a result, it is possible to reduce the number of times the output changes per unit time, which is difficult with the conventional configuration, that is, to reduce the number of switching times per unit time when combined with a switching amplifier. As a result, it is possible to simultaneously improve the amplitude utilization factor.

  As described above, when a binary signal is generated from an audio signal by delta-sigma modulation, according to the present embodiment, a delta that expands the amplitude utilization rate without increasing the number of times the output per unit time changes. A sigma modulation operation can be realized. In particular, when the switching circuit 31 is connected to the amplifier 20 that performs power amplification in the subsequent stage, the number of times of switching per unit time is reduced, so that it is possible to reduce the power consumed by switching.

  In addition, since the amplitude utilization factor is increased, the power that can be taken out is increased with respect to the power source having the same voltage value.

  Furthermore, when the amplitude utilization factor is increased, a low-voltage power source can be used to extract the same power, so that power consumption due to the voltage can be reduced. In addition, when a low voltage power source can be used, there is an advantage that the amplifying unit can be configured with low cost components with low withstand voltage.

  When the delta sigma modulation circuit 10 and the pulse amplification unit 30 are combined as in the amplifier 20 of the present embodiment, a switching circuit 31 is connected to the subsequent stage of the completed delta sigma modulation circuit 10 as shown in FIG. In addition to the method, the same effect can be obtained by an amplifier 20 that employs a method of providing a switching circuit 31 in the loop of the delta-sigma modulation circuit 10 as shown in FIG.

  As described above, the amplifier 20 according to the present embodiment includes the pulse amplification unit 30 that performs pulse amplification on the subsequent stage of the delta-sigma modulation circuit 10.

  Therefore, since the output signal from the delta-sigma modulation circuit 10 having the above-described effects is amplified by the pulse amplifier 30, the amplifier 20 that can achieve both reduction of the number of switching per unit time and improvement of the amplitude utilization factor. Can be provided.

  The amplifier 20 of the present embodiment also includes a delta-sigma modulation circuit 10 and a pulse amplification unit 40 that performs pulse amplification after the minimum pulse width limiting unit 5, and outputs the output information of the switching circuit 31 in the pulse amplification unit 40 as delta. It is also possible to perform negative feedback to the adder 2 on the input side of the sigma modulation circuit 10.

  Therefore, even if the output signal of the delta sigma modulation circuit 10 is amplified and then returned to the input side of the delta sigma modulation circuit 10, an output signal that follows the input signal can be obtained similarly.

  The present invention is not limited to the above-described embodiments, and various modifications can be made within the scope of the claims, and the technical means disclosed in different embodiments can be appropriately combined. Such embodiments are also included in the technical scope of the present invention.

  The present invention relates to a delta-sigma modulation circuit that digitally encodes an audio signal with a relatively small number of bits, and an amplifier that performs an amplification operation by switching a plurality of voltages using a signal generated by the delta-sigma modulation circuit as a control signal In addition, it can be applied to audio products such as CD and MD.

It is a block diagram which shows one Embodiment of the delta-sigma modulation circuit in this invention. It is a block diagram which shows the structure of the integrator adder group in the said delta-sigma modulation circuit. It is a block diagram which shows the structure of the amplifier provided with the said delta-sigma modulation circuit. It is a block diagram which shows the structure of the other amplifier provided with the said delta-sigma modulation circuit. It is a block diagram which shows the structure of the conventional delta-sigma modulation circuit.

Explanation of symbols

1 Input terminal (input section)
2 Adder 3 Integrator adder group 4 Quantizer 5 Minimum pulse width limiter (pulse width control means)
6 Clock counter (pulse width changing means)
7 Output terminal 8 Sampling clock 9 Input signal amplitude detector (input signal amplitude detector)
20 Amplifier 30 Pulse amplification section (pulse amplification means)
31 Switching circuit 32 Low pass filter (LPF)
40 amplifier

Claims (9)

Delta sigma modulation of a signal input to the input unit, including an input unit to which an audio signal is input and a quantizer that cascades a plurality of integrators and quantizes output values of the plurality of integrators In a delta-sigma modulation circuit that
Input signal amplitude detection means for detecting the amplitude of the signal input to the input unit;
Pulse width changing means for changing the pulse width of the output signal of the quantizer;
A delta-sigma modulation circuit, comprising: pulse width control means for controlling a pulse width change by the pulse width changing means based on a detection result of the input signal amplitude detecting means.   2. The delta-sigma modulation circuit according to claim 1, wherein the pulse width control means sets a minimum pulse time width based on a detection result of the input signal amplitude detection means.   3. The delta-sigma modulation circuit according to claim 1, wherein output information of the pulse width limiting means is negatively fed back to the input side. The pulse width limiting means is configured to set a predetermined time width for a plurality of quantized values output from the quantizer to be equal to a pre-sampled value that is a quantized value one clock before. Depending on the clock count,
3. The delta-sigma modulation circuit according to claim 1, wherein the time width is the same as the pre-sampled value = the time width of the sampling clock time width × the number of counts.   The input signal amplitude detecting means detects the absolute value of the input signal, while the pulse width limiting means changes the count number of the sampling clock when the absolute value of the input signal exceeds a preset threshold value. The delta-sigma modulation circuit according to claim 4. The threshold value set in advance for information on the absolute value of the input signal from the input signal amplitude detection means is:
6. The delta-sigma modulation circuit according to claim 5, wherein a threshold value when the absolute value increases ≧ a threshold value when the absolute value decreases is set to be maintained.   7. The pulse width limiting means changes so that the count number of the sampling clock becomes smaller as the absolute value of the input signal detected by the input signal amplitude detecting means is larger. The delta-sigma modulation circuit according to any one of the above.   8. An amplifier comprising pulse amplification means for performing pulse amplification at a subsequent stage of the delta-sigma modulation circuit according to claim 1.   8. A delta-sigma modulation circuit according to claim 1, and a pulse amplification means for performing pulse amplification after the pulse width limiting means, wherein the amplified output information of the pulse amplification means An amplifier characterized by negative feedback to the input side of a delta-sigma modulation circuit.

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