JP2005286617A - Delay line - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a delay line of which the cross-sectional dimension is small, passage loss is small, and the amount of phase change is large. <P>SOLUTION: The delay line is provided with a spiral conductor line which is formed on a substrate and composed of a plurality of coils 10-13, a ground conductor 21 formed on the substrate, a plurality of upper electrodes that are formed on the substrate and respectively connected to the plurality of coils 10-13 of the spiral conductor line, and a plurality of capacitors 22-25 formed between the ground conductors 21. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a delay line in which a recess is provided in a silicon substrate, a conductor pattern is patterned in a spiral shape inside the recess, and a capacitor is partially formed between the recess and a ground conductor.

  In the conventional line, when the first and second MEMS switches near the input terminal and the output terminal are in a passing state, and when the third MEMS switch sandwiched between the first and second stub lines for matching is in an open state, The reflected wave of the third MEMS switch by the first and second stub lines does not affect the circuit pattern that creates a phase of 180 degrees. The impedance of the circuit for obtaining the 180-degree phase by appropriately selecting the inductance value L of the inductor corresponding to the line portion of the circuit pattern that creates the 180-degree phase and the capacitance value C of the MIM capacitor is approximately √ (L / C) = 50 ohms may be possible. Moreover, since the equivalent propagation constant of the line is proportional to √ (LC), the overall length can be shortened by using large L and C, and a small circuit can be obtained (for example, Non-patent document 1).

G. L. Tan, R. E. Mihailovich, J. B. Hacker, J. E. DeNatale and G. M. Rebeiz "A 4-Bit Miniature X-Band MEMS Phase Shifter Using Switched-LC Networks" 2003 IEEE MTT-S Digest, 1477-1480

  Although it is possible to reduce the size of the line that creates a larger phase delay in the above-mentioned device, in order to operate effectively in a wide frequency band, the section composed of the inductor and capacitor corresponding to the line is compared with the wavelength. Need to be short enough.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to obtain a delay line having a small cross-sectional dimension, a small passage loss, and a large phase change amount.

  The delay line according to the present invention is formed on a substrate and formed of a plurality of coils, a spiral conductor line, a ground conductor formed on the substrate, and the spiral conductor line formed on the substrate. A plurality of electrodes respectively connected to the plurality of coils and a plurality of capacitors formed between the ground conductors are provided.

  The delay line according to the present invention has an effect that the cross-sectional dimension is small, the passage loss is small, and the phase change amount is large.

Embodiment 1 FIG.
A delay line according to Embodiment 1 of the present invention will be described with reference to FIGS. 1 is a perspective view showing a configuration of a delay line according to Embodiment 1 of the present invention. FIG. 2 is a diagram showing an equivalent circuit of the delay line in FIG. In addition, in each figure, the same code | symbol shows the same or equivalent part.

  In FIG. 1, the delay line includes input / output terminals 1 and 3, a ground terminal 2 paired with the input / output terminal 1, a ground terminal 4 paired with the input / output terminal 3, a first coil 10, The second coil 11, the third coil 12, the fourth coil 13, the ground conductor 21, the capacitor 22 created between the coil 10 and the ground conductor 21, and the coil 11 and the ground conductor 21. The capacitor 23 formed between the coil 12 and the ground conductor 21, and the capacitor 25 formed between the coil 13 and the ground conductor 21 are provided.

  2, the coil 30 corresponds to the coil 10 in FIG. 1, the coil 31 corresponds to the coil 11 in FIG. 1, the coil 32 corresponds to the coil 12 in FIG. 1, and the coil 33 corresponds to the coil 13 in FIG. doing. Further, the capacitor 34 corresponds to the capacitor 22 in FIG. 1, the capacitor 35 corresponds to the capacitor 23 in FIG. 1, the capacitor 36 corresponds to the capacitor 24 in FIG. 1, and the capacitor 37 corresponds to the capacitor 25 in FIG. Yes. Further, the terminal 40 corresponds to the input / output terminal 1 in FIG. 1, and the terminal 41 corresponds to the input / output terminal 3 in FIG. Note that all the inductances of the coils are L, and the capacitance of the capacitor is C.

  Next, the operation of the delay line according to the first embodiment will be described with reference to the drawings.

  In FIG. 1, the high-frequency signal input from the input / output terminal 1 is output to the input / output terminal 3 through the coils 10, 11, 12, and 13. During this time, capacitors 22, 23, 24 and 25 are inserted. For this reason, the impedance as a line is represented by approximately √ (L / C). On the other hand, the amount of change in phase per unit length is proportional to √ (LC).

  Since a desirable impedance for a high-frequency line is 50 ohms, the ratio of L and C for realizing this impedance is uniquely determined. Further, in order to increase the amount of phase change, the product of L and C may be increased or many LCs may be used. The line shown in FIG. 1 can insert a large amount of L and C per unit length by using microfabrication, and can realize a large L by making the coil spiral, and the interval between the electrodes of the capacitor can be reduced. Large C can be obtained by narrowing.

  In this way, the line of FIG. 1 can obtain an impedance of 50 ohms and a large phase change.

  Also, by changing the size of the coil from place to place and changing the inductance of the coil from place to place, or changing the size of the capacitor from place to place and changing the capacitance of the capacitor from place to place, It is also possible to realize a line that changes the impedance for each place and can pass or block only a signal having a specific frequency, such as a low-pass filter.

Embodiment 2. FIG.
A delay line according to Embodiment 2 of the present invention will be described with reference to FIGS. 3 is a perspective view showing a configuration of a delay line according to Embodiment 2 of the present invention.

  In FIG. 3, a minute recess 101 is opened in a silicon substrate 100 by etching. Gold lines 201, 202, 203, 204, 205 are formed on the bottom and side surfaces of the recess 101. Bridge-shaped gold lines 301, 302, 303, 304, 305, and 306 are formed on the opening surface of the recess 101 and the upper surface of the silicon substrate 100. Among these, bridge-shaped gold lines 305 and 306 are input / output terminals. The ground conductor 316 is provided on the silicon substrate 100. The ground terminal 314 is paired with the input / output terminal 305 and connected to the ground conductor 316. The ground terminal 315 is paired with the input / output terminal 306 and is connected to the ground conductor 316.

  Also, a capacitor upper electrode 310 separated from a ground conductor 316 by a thin dielectric film is electrically connected to one end of the gold line 301, and a ground conductor 316 and a thin dielectric are connected to one end of the gold line 302. The upper electrode 311 of the capacitor separated by the body film is electrically connected, and the upper electrode 312 of the capacitor separated by the ground conductor 316 and the thin dielectric film is electrically connected to one end of the gold line 303. An upper electrode 313 of the capacitor separated from the ground conductor 316 by a thin dielectric film is electrically connected to one end of the gold line 304.

  Here, a delay line manufacturing method according to the second embodiment of the present invention will be described with reference to FIGS. 4 and 5 are diagrams showing a method of manufacturing a delay line according to the second embodiment of the present invention.

  First, as shown in FIG. 4, the silicon substrate 100 is wet-etched to provide a recess 101 having a depth of about 30 μm. In addition to using a silicon wafer as the substrate having the recess 101 and forming the recess 101 by etching or machining, the substrate 101 having the recess 101 is made of glass, and the recess 101 is formed by etching, sandblasting, machining, or the like. May be.

  Next, as shown in FIG. 5, gold is sputtered, and gold lines 201, 202, 203, 204, and 205 having a thickness of about 2 μm are left on the bottom and side surfaces of the recess 101 by photoetching. At this time, both ends of each line are left slightly on the upper surface of the silicon substrate 100. Further, a pattern to be the ground conductor 316 is left on the silicon substrate 100 beside the recess 101.

  Next, as a sacrificial layer, for example, a photoresist is filled in the concave portion 101, and planarized on the same surface as the upper surface of the silicon substrate 100. At this time, the both ends of each of the gold lines 201 to 205 are made visible.

  Next, a dielectric film such as silicon nitride is sputtered and removed by photoetching, leaving only the lower side from the upper electrodes 310 to 313 of the capacitor.

  Next, gold is sputtered, and gold lines 301, 302, 303, 304, 305, 306, 314, and 315 having a thickness of about 2 μm are left by photoetching.

  Finally, the photoresist filling the recess 101 as a sacrificial layer is removed by wet etching, so that the gold lines 305, 201, 301, 202, 302, 203, 303, 204, 304, 205, and 306 are continued. A line of books is obtained.

  Next, the operation of the delay line according to the second embodiment will be described with reference to the drawings.

  In FIG. 3, when a high-frequency signal is input from a gold line 305 serving as an input terminal of the line, the signal is transmitted in the order of the gold lines 201, 301, 202, 302, 203, 303, 204, 304, and 205. , And output from a gold line 306 serving as an output terminal of the line.

  Since the current flows in a spiral manner, the direction of the current flowing through the gold lines 301, 302, 303, and 304 is equal, and the direction of the current flowing through the gold lines 201, 202, 203, 204, and 205 is also equal. Become. For this reason, the inductance value as a coil is large. Moreover, although it generate | occur | produces so that a magnetic field may be confined in the recessed part 101, since this part is hollow, there is almost no loss. For this reason, this line has a low loss. In addition, since the four capacitors provided on one side of the gold lines 301, 302, 303, and 304 are designed so that √ (L / C) = 50, the impedance of the line is 50 suitable for a high-frequency circuit. Ohm. In addition, since a large inductance value and a large capacitance value are obtained by fine processing, the amount of change in phase during the propagation of the signal from the terminal 305 to the terminal 306 is very large.

  The material of the substrate used here can be any material other than silicon, such as glass, that can be finely processed. The metal used for the signal line can be any metal other than gold as long as a pattern can be created by photolithography. The thickness of the metal line is preferably equal to or greater than the skin depth of the frequency used.

  By leaving the etching of the silicon nitride film (dielectric film) so as to cover not only the capacitor portion but also the entire portion, mechanical strength can be obtained when the concave portion 101 is made large. However, in this case, it is necessary to make a hole in a part of the silicon nitride film so that the gold lines 201, 202, 203, 204, 205 and 301, 302, 303, 304, 305, 306 are connected. Further, it is necessary to make a hole in a part of the silicon nitride film so that the ground terminals 314 and 315 and the ground conductor 316 are connected.

  When the silicon nitride film (dielectric film) is left on the entire upper surface of the recess 101 as described above, gold is sputtered before the silicon nitride film is sputtered, and gold lines 301, 302, 303, 304 , 305, 306, 314, 315 can be patterned, and then a silicon nitride film can be sputtered. In this case, the upper electrode patterns 310, 311, 312, 313 of the capacitor provided on the silicon nitride film and gold It is necessary to make holes for connecting the lines 301, 302, 303, 304, 305, 306, 314, and 315 in the silicon nitride film.

  Further, the gold lines 201, 202, 203, 204, 205 are not processed into the bottom surface and side surfaces of the recess 101, and the recess 101 is filled with a photoresist as a sacrificial layer, planarized, and then sputtered with gold, Gold lines 201, 202, 203, 204, 205 and capacitor ground conductor pattern 316 are patterned on the photoresist, and silicon nitride is sputtered to form gold lines 201, 202, 203, 204, 205. After holes for connection are made at both ends, gold is sputtered and gold lines 301, 302, 303, 304, 305, 306, 314, 315 and capacitor upper electrode patterns 310, 311, 312, 313 are formed. By patterning, gold lines 305, 201, 301, 202, 302, 203, 30 , Single line that leads 204,304,205,306 are structured to rotate the upper and lower silicon nitride film (dielectric film) in a spiral shape is obtained. By processing in this way, a delay line that is less affected by the loss of the silicon substrate can be obtained.

Embodiment 3 FIG.
A delay line according to Embodiment 3 of the present invention will be described with reference to FIG. 6 is a perspective view showing a configuration of a delay line according to Embodiment 3 of the present invention.

  In FIG. 6, minute recesses 101 and 102 are opened in a silicon substrate 100 by etching. Gold lines 201, 202, 203, 204, 205, 221, 222, 223, 224, 225 are formed on the bottom and side surfaces of the recesses 101, 102. Bridge-shaped gold lines 301, 302, 303, 304, 305, 306, 321, 322, 323, 324, 325, 326 are formed on the opening surface of the recesses 101, 102 and the upper surface of the silicon substrate 100. . Among these, gold lines 305, 306, 325, and 326 are input / output terminals.

  Further, an upper electrode 310 of a capacitor is electrically connected to one end of the gold line 301, and a lower electrode of the same capacitor separated by a thin dielectric film is connected to the gold line 221. Similarly, an upper electrode 311 of a capacitor is electrically connected to one end of the gold line 302, and a lower electrode of the same capacitor separated by a thin dielectric film is connected to the gold line 222. Similarly, an upper electrode 312 of a capacitor is electrically connected to one end of the gold line 303, and a lower electrode of the same capacitor separated by a thin dielectric film is connected to the gold line 223. Similarly, an upper electrode 313 of the capacitor is electrically connected to one end of the gold line 304, and the lower electrode of the same capacitor separated by a thin dielectric film is connected to the gold line 224.

  Here, a method for manufacturing the delay line according to the third embodiment of the present invention will be described.

  First, wet etching is performed on the silicon substrate 100 to provide two concave portions 101 and 102 having a depth of about 30 μm.

  Next, gold is sputtered and gold lines 201, 202, 203, 204, 205, 221, 222, 223, 224, and 225 having a thickness of about 2 μm are formed by photoetching and the lower electrode of the capacitor is formed in Leave on the bottom and sides. At this time, both ends of each line are left slightly on the upper surface of the silicon substrate 100.

  Next, for example, a photoresist is filled in the recesses 101 and 102 as a sacrificial layer, and is planarized on the same surface as the upper surface of the silicon substrate 100. At this time, both ends of each of the gold lines 201 to 205 and 221 to 225 are made visible.

  Next, a dielectric film such as silicon nitride is sputtered and removed by photoetching leaving only the portions from the upper electrodes 310 to 313 of the capacitor.

  Next, gold is sputtered, and gold lines 301, 302, 303, 304, 305, 306, 321, 322, 323, 324, 325, and 326 having a thickness of about 2 μm and capacitor upper electrodes 310 and 311 are formed by photoetching. , 312 and 313.

  Finally, the photoresist filled in the recesses 101 and 102 as a sacrificial layer is removed by wet etching, so that the gold lines 305, 201, 301, 202, 302, 203, 303, 204, 304, 205, 306 and One line that follows and another line that continues with gold lines 325, 221, 321, 222, 222, 322, 223, 223, 224, 324, 225, and 326 are obtained.

  Next, the operation of the delay line according to the third embodiment will be described with reference to the drawings.

  In FIG. 6, when a high-frequency signal is input from a gold line 305 serving as an input terminal of the line, the signal is transmitted in the order of the gold lines 201, 301, 202, 302, 203, 303, 204, 304, and 205. , And output from a gold line 306 serving as an output terminal of the line.

  Since the current flows in a spiral manner, the direction of the current flowing through the gold lines 301, 302, 303, and 304 is equal, and the direction of the current flowing through the gold lines 201, 202, 203, 204, and 205 is also equal. Become. For this reason, the inductance value as a coil is large. Moreover, although it generate | occur | produces so that a magnetic field may be confined in the recessed part 101, since this part is hollow, there is almost no loss. For this reason, this line has a low loss.

  When a high frequency signal is input from a gold line 325 that is an input terminal of another line, the signal is transmitted in the order of the gold lines 221, 321, 222, 322, 223, 323, 224, 324, 225, and output. It is output from a gold line 326 serving as a terminal.

  Since the current flows spirally, the direction of the current flowing through the gold lines 321, 322, 323, and 324 is equal, and the direction of the current flowing through the gold lines 221, 222, 223, 224, and 225 is also equal. Become. For this reason, the inductance value as a coil is large. Moreover, although it generate | occur | produces so that a magnetic field may be confined in the recessed part 102, since this part is hollow, there is almost no loss. For this reason, this line also has a low loss.

  In addition, since the four capacitors provided between the two lines are designed so that √ (2L / C) = 50, the impedance between the lines is 100 ohms suitable for a high-frequency balanced circuit. Further, since a large inductance value and a large capacitance value are obtained by microfabrication, the amount of phase change during propagation of the balanced signal from the terminal pair 305, 325 to the terminal pair 306, 326 is very large.

  The material of the substrate used here can be any material other than silicon, such as glass, that can be finely processed. The metal used for the signal line can be any metal other than gold as long as a pattern can be created by photolithography. The thickness of the metal line is preferably equal to or greater than the skin depth of the frequency used.

  Further, by leaving etching of the silicon nitride film so as to cover not only the capacitor portion but also the entire portion, mechanical strength can be obtained when the recesses 101 and 102 are made large. However, in this case, the gold lines 201, 202, 203, 204, 205, 221, 222, 223, 224, 225 and 301, 302, 303, 304, 305, 306, 321, 322, 323, 324, 325 It is necessary to make a hole in a part of the silicon nitride film so that 326 are connected.

Embodiment 4 FIG.
A delay line according to Embodiment 4 of the present invention will be described with reference to FIG. FIG. 7 is a perspective view showing a configuration of a delay line according to Embodiment 4 of the present invention.

  In FIG. 7, a minute recess 101 is opened in a silicon substrate 100 by etching. Gold lines 501, 502, 503, 504, 505, 506 are formed on the bottom and side surfaces of the recess 101. Bridge-shaped gold lines 601, 602, 603, 604, 605, 606, 607, and 608 are formed on the upper surface of the opening of the recess 101. Among these, bridge-shaped gold lines 601, 602, 607, and 608 are input / output terminals. The gold lines 601, 501, 603, 503, 605, 505, 607 are connected in a series of spirals, and the gold lines 602, 502, 604, 504, 606, 506, 608 are connected in series. They are connected on the silicon substrate 100 so as to form a spiral.

  Further, a capacitor upper electrode 610 is electrically connected to one end of the gold line 603, and a capacitor upper electrode 611 is electrically connected to one end of the gold line 604, so that a thin dielectric film is formed. It overlaps with the lower electrode 614 of the capacitor separated by. Similarly, an upper electrode 612 of a capacitor is electrically connected to one end of the gold line 605, and an upper electrode 613 of the capacitor is electrically connected to one end of the gold line 606. It overlaps the lower electrode 615 of the capacitor separated by the membrane.

  Here, a method for manufacturing a delay line according to the fourth embodiment of the present invention will be described.

  First, wet etching is performed on the silicon substrate 100 to form a recess 101 having a depth of about 30 μm.

  Next, gold is sputtered, and gold lines 501, 502, 503, 504, 505, 506 and capacitor lower electrodes 614, 615 having a thickness of about 2 μm and the lower electrodes 614, 615 of the capacitor are formed on the bottom and side surfaces of the recess 101 and the upper surface of the silicon substrate 100 To leave. At this time, both ends of each line are left slightly on the upper surface of the silicon substrate 100.

  Next, as a sacrificial layer, for example, a photoresist is filled in the concave portion 101, and planarized on the same surface as the upper surface of the silicon substrate 100. At this time, the both ends of each of the gold lines 501 to 506 are made visible.

  Next, a dielectric film such as silicon nitride is sputtered and removed by photoetching, leaving only the lower side of the upper electrodes 610, 611, 612, and 613 of the capacitor.

  Next, gold is sputtered, and gold lines 601, 602, 603, 604, 605, 606, 607, 608 and capacitor upper electrodes 610, 611, 612, 613 are left by photoetching.

  Finally, the photoresist filled in the recess 101 as a sacrificial layer is removed by wet etching, so that the gold lines 601, 501, 603, 503, 605, 505, 607, the spiral line, and the gold line 602 are removed. , 502, 604, 504, 606, 506, 608 and another spiral line are obtained.

  Next, the operation of the delay line according to the fourth embodiment will be described with reference to the drawings.

  In FIG. 7, when a high frequency signal is input from a gold line 601 serving as an input terminal of the line, the signal is transmitted in the order of gold lines 501, 603, 503, 605, 505, and 607, and gold serving as an output terminal. Output from the line 607.

  Since the current flows in a spiral shape in this way, the directions of the currents flowing through the gold lines 601, 603, 605, and 607 are equal, and the directions of the currents flowing through the gold lines 501, 503, and 505 are also equal. For this reason, the inductance value as a coil is large. Moreover, although it generate | occur | produces so that a magnetic field may be confined in the recessed part 101, since this part is hollow, there is almost no loss. For this reason, this line has a low loss.

  When a high-frequency signal is input from a gold line 602 serving as an input terminal of another line, the signal is transmitted in the order of the gold lines 502, 604, 504, 606, 506, and 608, and the gold line serving as an output terminal. 608 is output.

  Since the current flows in a spiral shape in this way, the direction of the current flowing through the gold lines 602, 604, 606, and 608 is equal, and the direction of the current flowing through the gold lines 502, 504, and 506 is also equal. For this reason, the inductance value as a coil is large. Moreover, although it generate | occur | produces so that a magnetic field may be confined in the recessed part 101, since this part is hollow, there is almost no loss. For this reason, this line also has a low loss.

  Further, a capacitor composed of an upper electrode 610 and a lower electrode 614, a capacitor composed of an upper electrode 611 and a lower electrode 614, a capacitor composed of an upper electrode 612 and a lower electrode 615, an upper electrode 613 and a lower electrode Since the capacitor composed of 615 is designed so that the impedance between the two spiral lines is 100 ohms suitable for a high-frequency balanced circuit, it can be matched with an external circuit. Further, since a large inductance value and a large capacitance value are obtained by microfabrication, the amount of phase change during propagation of the balanced signal from the terminal pair 601 602 to the terminal pair 607 608 is very large.

  The material of the substrate used here can be any material other than silicon, such as glass, that can be finely processed. The metal used for the signal line can be any metal other than gold as long as a pattern can be created by photolithography. The thickness of the metal line is preferably equal to or greater than the skin depth of the frequency used.

  In addition, when the silicon nitride film (dielectric film) is etched so as to cover not only the capacitor portion but also the entire portion, mechanical strength can be obtained when the concave portion 101 is made large. However, in this case, the gold lines 501, 502, 503, 504, 505, 506 provided in the recess 101 and the gold lines 601, 602, 603, 604, 605, 606, 607, 608 on the silicon nitride film are It is necessary to make a hole in a part of the silicon nitride film so as to be connected.

  When the silicon nitride film (dielectric film) is left on the entire upper surface of the recess 101 as described above, gold is sputtered before the silicon nitride film is sputtered, and gold lines 601, 602, 603, 604 are used. , 605, 606, 607, and 608 can be sputtered and then the silicon nitride film can be sputtered. In this case, the upper electrode patterns 610, 611, 612, and 613 of capacitors provided on the silicon nitride film and gold Holes for connecting the lines 601 602 603 604 605 606 607 608 need to be opened in the silicon nitride film.

  In addition, the gold lines 501, 502, 503, 504, 505, and 506 are not processed into the bottom and side surfaces of the recess 101, and the recess 101 is filled with a photoresist as a sacrificial layer, planarized, and then sputtered with gold. Then, the gold lines 501, 502, 503, 504, 505, 506 and the capacitor lower electrode patterns 614, 615 are patterned on the photoresist, and silicon nitride is sputtered to form the gold lines 501, 502, 503, 504, 505, and 506, holes for connection are made in both end portions, and then gold is sputtered, gold lines 601, 602, 603, 604, 605, 606, 607, and 608 and the upper electrode of the capacitor By patterning the patterns 610, 611, 612, 613, the gold lines 601, 501, 603, 5 3, 605, 505, 607 and a spiral line, and gold lines 602, 502, 604, 504, 606, 506, 608 and a spiral line that spirally rotate above and below the silicon nitride film Is obtained. By processing in this way, a delay line that is less affected by the loss of the silicon substrate can be obtained.

It is a perspective view which shows the structure of the delay line which concerns on Embodiment 1 of this invention. It is a figure which shows the equivalent circuit of the delay line which concerns on Embodiment 1 of this invention. It is a perspective view which shows the structure of the delay line which concerns on Embodiment 2 of this invention. It is a perspective view which shows the manufacturing method of the delay line which concerns on Embodiment 2 of this invention. It is a perspective view which shows the manufacturing method of the delay line which concerns on Embodiment 2 of this invention. It is a perspective view which shows the structure of the delay line which concerns on Embodiment 3 of this invention. It is a perspective view which shows the structure of the delay line which concerns on Embodiment 4 of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Input / output terminal, 2 Ground terminal, 3 Input / output terminal, 4 Ground terminal, 10 1st coil, 11 2nd coil, 12 3rd coil, 13 4th coil, 21 Ground conductor, 22 Capacitor, 23 Capacitor, 24 capacitor, 25 capacitor, 100 silicon substrate, 101, 102 recess, 201, 202, 203, 204, 205, 221, 222, 223, 224, 225 gold line, 301, 302, 303, 304, 305, 306, 321, 322, 323, 324, 325, 326 Bridge-shaped gold line, 310, 311, 312, 313 Capacitor upper electrode, 314 Ground terminal, 315 Ground terminal, 316 Ground conductor, 501, 502, 503, 504, 505, 506 Gold line, 601 02,603,604,605,606,607,608 bridges like gold line, the upper electrode of 610,611,612,613 capacitors, 614 and 615 a lower electrode of the capacitor.

Claims (12)

A helical conductor line formed on a substrate and composed of a plurality of coils;
A ground conductor formed on the substrate;
A delay line comprising: a plurality of electrodes formed on the substrate and respectively connected to a plurality of coils of the spiral conductor line; and a plurality of capacitors formed between the ground conductors. A substrate having a recess,
A plurality of first conductor lines patterned on the surface of the recess;
A plurality of second conductor lines formed in a bridge shape on the opening surface of the recess;
A plurality of electrodes respectively connected to the other ends of the plurality of second conductor lines;
A ground conductor formed on the substrate,
One end of the first conductor line and one end of the second conductor line are connected, and the other end of the first conductor line and the other end of the second conductor line are connected to form a plurality of coils. A delay line, wherein one spiral conductor line is formed as a whole, and a plurality of capacitors are formed between the plurality of electrodes and the ground conductor. It further comprises a dielectric film formed so as to cover the opening surface of the recess,
The plurality of second conductor lines are formed on an upper surface of the dielectric film,
One end of the first conductor line and one end of the second conductor line are connected through the dielectric film, and the other end of the first conductor line and the other end of the second conductor line are connected to each other. A plurality of coils are formed by being connected through the dielectric film to form one spiral conductor line as a whole, and a plurality of capacitors are formed between the plurality of electrodes and the ground conductor. The delay line according to claim 2. It further comprises a dielectric film formed so as to cover the opening surface of the recess,
The plurality of second conductor lines are formed on a lower surface of the dielectric film,
The plurality of electrodes are respectively connected to the other ends of the plurality of second conductor lines through the dielectric film, and a plurality of capacitors are formed between the plurality of electrodes and the ground conductor. The delay line according to claim 2, wherein: A substrate having a recess,
A dielectric film formed to cover the opening surface of the recess;
A plurality of first conductor lines formed on the lower surface of the dielectric film;
A plurality of second conductor lines formed on the top surface of the dielectric film;
A plurality of electrodes respectively connected to the other ends of the plurality of second conductor lines;
A ground conductor formed on the substrate,
One end of the first conductor line and one end of the second conductor line are connected through the dielectric film, and the other end of the first conductor line and the other end of the second conductor line are connected to each other. A plurality of coils are formed by being connected through the dielectric film to form one spiral conductor line as a whole, and a plurality of capacitors are formed between the plurality of electrodes and the ground conductor. A delay line. A substrate having a recess,
A plurality of first and second conductor lines patterned adjacent to each other on the surface of the recess;
A plurality of third and fourth conductor lines formed in a bridge shape adjacent to each other on the opening surface of the recess;
A plurality of electrodes respectively connected to the other ends of the plurality of third and fourth conductor lines;
A ground conductor formed on the substrate,
One end of the first and second conductor lines and one end of the third and fourth conductor lines are connected, and the other end of the first and second conductor lines and the third and fourth conductor lines The other end is connected to form a plurality of coils, a total of two spiral conductor lines are formed, and a plurality of capacitors are formed between the plurality of electrodes and the ground conductor. line. It further comprises a dielectric film formed so as to cover the opening surface of the recess,
The plurality of third and fourth conductor lines are formed on an upper surface of the dielectric film,
One end of the first and second conductor lines and one end of the third and fourth conductor lines are connected through the dielectric film, and the other end of the first and second conductor lines and the first The other ends of the third and fourth conductor lines are connected through the dielectric film to form a plurality of coils, so that two spiral conductor lines are formed as a whole, the plurality of electrodes, the ground conductor, The delay line according to claim 6, wherein a plurality of capacitors are formed between the two. It further comprises a dielectric film formed so as to cover the opening surface of the recess,
The plurality of third and fourth conductor lines are formed on a lower surface of the dielectric film,
The plurality of electrodes are connected to the other ends of the plurality of third and fourth conductor lines through the dielectric film, and a plurality of capacitors are formed between the plurality of electrodes and the ground conductor. The delay line according to claim 6, wherein: A substrate having a recess,
A dielectric film formed to cover the opening surface of the recess;
A plurality of first and second conductor lines formed on the lower surface of the dielectric film;
A plurality of third and fourth conductor lines formed on the upper surface of the dielectric film;
A plurality of electrodes respectively connected to the other ends of the plurality of third and fourth conductor lines;
A ground conductor formed on the substrate,
One end of the first and second conductor lines and one end of the third and fourth conductor lines are connected through the dielectric film, and the other end of the first and second conductor lines and the first The other ends of the third and fourth conductor lines are connected through the dielectric film to form a plurality of coils, so that two spiral conductor lines are formed as a whole, the plurality of electrodes, the ground conductor, A delay line characterized in that a plurality of capacitors are formed between the two. The delay line according to any one of claims 2 to 9, wherein the substrate having the recess is a silicon wafer in which the recess is formed by either etching or machining. The delay line according to any one of claims 2 to 9, wherein the substrate having the recess is glass in which the recess is formed by any one of etching, sandblasting, and machining. The √ (L / C) is 50Ω, where C is the capacitance of the capacitor and L is the inductance of the spiral conductor line between adjacent capacitors. The delay line described in 1.

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