JP2005278119A - Phase adjusting method, inphase combining circuit and space diversity inphase combining circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To expand a phase adjustment amount between two signals and to make a device smaller. <P>SOLUTION: A receiving part 10 converts a radio frequency signal received by two antennas into an intermediate frequency signal. A multiplier (MIX) 21 converts a signal of an intermediate frequency band into a baseband band in frequency. An A/D converter (A/D) 22 of a modulating part 20 is operated by a sampling frequency of an output of an oscillator 23 that is subjected to phase adjustment. In shift registers 241 and 242 of an inphase combining circuit (SD COMB) 24, one is fixed and the other outputs a signal of the number of stages selected by a selector (SEL) 243. A product sum computing element 244 detects a phase difference by outputting a time average value of a product sum of two signals. An adder 245 outputs an added signal. A control part 246 controls one of oscillators 23 and the selector 243 so as to make an output of the product sum computing element 24 to be maximum. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an in-phase synthesis circuit, and more particularly to an in-phase synthesis circuit and a space diversity in-phase synthesis circuit that are phase-adjusted on a time axis.

  This type of conventional space diversity in-phase synthesis circuit shifts the phase of the first received signal and the second received signal by the first phase shifting means and the second phase shifting means, respectively. Are in-phase combined, and the phase difference detection means detects the phase difference between the two signals. According to the detection result from the phase difference detecting means, the second phase shifting means for shifting the phase of the second received signal is controlled so that these two signals are in the in-phase state (for example, patent Reference 1).

  However, in the conventional configuration, since the phase difference detection result is expressed by a trigonometric function, there is a problem that the detection range of the phase difference is limited to one period (± 1/2 period) of the signal frequency. For this reason, in order to suppress the delay difference generated in the apparatus to one period, it is necessary to make the cable lengths equal.

JP-A-7-123038

  In the conventional space diversity in-phase synthesis circuit described above, since the phase difference detection result is represented by a trigonometric function, the phase difference detection range is limited to one period (± 1/2 period) of the signal frequency. There are drawbacks.

  An object of the present invention is to eliminate the above-described conventional drawbacks, and to perform a phase delay in the time domain (on the time axis), thereby providing a common phase synthesis circuit and a space diversity common mode with a wide phase adjustment range for performing common phase synthesis. It is to provide a synthesis circuit.

  In the phase adjustment method of the present invention, the first input signal and the second input signal are respectively adjusted in phase, the phase-adjusted signals are phase-shifted, and the phase difference between the phase-shifted signals is calculated. Detecting and controlling the phase amount of the phase adjustment and the phase shift amount of the phase shift based on the result of the phase difference detection so that the phases of the two phase-shifted signals coincide with each other Yes.

  The phase amount of the phase adjustment is controlled as an amount that gives a phase difference to each sampling clock when the first input signal and the second input signal are digitally converted.

  Further, the phase shift amount of the phase shift is controlled as an amount by which the second input signal is phase-shifted in a predetermined cycle unit with respect to the fixed phase shift of the first input signal. It is characterized by.

  The phase difference detection is performed by performing a product-sum operation on each of the phase-shifted signals.

  The phase amount of the phase adjustment and the phase shift amount of the phase shift are controlled such that the result of the product-sum operation is maximized.

  The in-phase synthesis circuit of the present invention is an in-phase synthesis circuit that performs in-phase synthesis of a first received signal and a second received signal, and digitally converts each of the first received signal and the second received signal. First and second digital conversion means, first and second phase shift means for shifting the outputs of the first and second digital conversion means, respectively, and the first and second phase shift means outputs Phase difference detection means for detecting a phase difference, addition means for combining the outputs of the first and second phase shift means, the first and second digital conversion means and the first based on the output of the phase difference detection means And a control unit that controls either one of the first and second phase shifting means.

  Further, the first and second digital conversion means are characterized in that a sampling clock whose phase difference is controlled is supplied.

  The first phase shifting means shifts the first received signal in a fixed manner by a first n-stage shift register, and the second phase shifting means transfers the second received signal to the second received signal. It is composed of a second n-stage shift register and n gate circuits provided corresponding to the outputs of each stage of the n-stage shift register, and one of the n gate circuits is selected. Thus, the phase is shifted according to the number of selected stages.

  Further, the phase difference detecting means is characterized by performing a product-sum operation on each signal output from the first and second phase shifting means.

  Further, the control unit performs phase control on one of the first and second digital conversion means and the first and second phase shift means so that the output of the phase difference detection means becomes maximum. It is characterized by.

  The in-phase synthesizing circuit of the present invention connects any of the above-described in-phase synthesizing circuits in parallel, assigns them to a signal synthesis block and a phase difference detection block, and based on the phase difference detection means output of the phase difference detection block The digital conversion means and the phase shift means of the signal synthesis block are controlled.

  Further, the space diversity in-phase synthesis circuit of the present invention comprises receiving means for converting a radio frequency band signal received by an antenna into an intermediate frequency band or a baseband frequency band, and an in-phase synthesis circuit. It is any one of the common-mode synthesis circuits described above.

  According to the in-phase synthesis circuit and the space diversity in-phase synthesis circuit of the present invention, the delay adjustment range can be expanded by adjusting the delay amount difference between the received signals in the time domain using the phase adjustment unit and the phase shift unit. There is an effect that can be achieved.

  Next, the best mode for carrying out the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a schematic configuration of a space diversity in-phase synthesis circuit according to an embodiment of the present invention.

  The present embodiment shown in FIG. 1 includes receiving units 10a and 10b and a demodulating unit 20. The demodulator (DEM) 20 includes multipliers (MIX) 21a and 21b, A / D converters (A / D) 22a and 22b, oscillators 23a and 23b, an in-phase synthesis circuit (SD COMB) 24, And a demodulator (DEM) 25. Further, the in-phase synthesis circuit 24 includes shift registers 241 and 242, a selector (SEL) 243, a product-sum calculator 244 and an adder 245, and a control unit (CONT) 246.

  Next, the operation of the present embodiment will be described in detail with reference to the drawings. FIG. 1 shows a schematic configuration of a reception system of a space diversity wireless communication apparatus according to the present invention.

  In FIG. 1, receiving units 10a and 10b mainly include RF circuits 11a and 11b, and receive two reception signals MAIN and SUB in a radio frequency band received by two antennas. Convert.

  The multipliers 21a and 21b of the demodulator 20 frequency-convert the intermediate frequency band signals output from the receivers 10a and 10b to the baseband band.

  The A / D converters 22a and 22b sample the signals frequency-converted to the baseband based on the clocks supplied from the oscillators 23a and 23b, and convert them into digital values.

  The oscillator 23a supplies a sampling clock to the A / D converter 22a and outputs it to the control unit 246 as a reference clock.

  The oscillator 23b outputs a sampling clock whose phase is controlled using the output of the oscillator 23a as a reference to the A / D converter 22b.

  The shift register 241 of the in-phase synthesis circuit 24 outputs a signal obtained by delaying the output of the A / D converter 22a converted to a digital value by the number of register stages (M) (Mτ) by a sampling clock (period τ).

  The shift register 242 performs the same operation as that of the shift register 241, but an arbitrary register value (m; 1 ≦ l) in the shift register 242 is selected by the selector 243 used in combination with the shift register 242 corresponding to the two stages of the shift register 241. m ≦ 2M) is selected.

  The selector 243 selects and outputs an arbitrary register value (m) in the range of 1 to 2M in the number of stages (2M) of the shift register 242 according to a control signal from the control unit 246.

  The product-sum operation unit 244 performs a product-sum operation on the outputs of the shift register 241 and the selector 243 within a predetermined period, and outputs the result to the control unit 246.

  The adder 245 outputs the in-phase combined signal obtained by adding the output of the shift register 241 and the output of the selector 243 to the demodulator 25 at the subsequent stage.

  The control unit 246 controls the output phase of the oscillator 23b, which is the sampling clock of the A / D converter 22b, so that the power value becomes maximum based on the result of the product-sum operation performed by the product-sum operation unit 244. Further, by selecting an optimum register value in the shift register 242, the delay difference between the two signals MAIN and SUB is adjusted in the time domain.

  Here, the control unit 246 includes a PLL circuit, and controls the phase of the oscillator 23b within a variable range of −τ to + τ using the output of the oscillator 23a as a reference clock. That is, the control unit 246 selects the register value of the shift register 242 and adjusts it roughly (sampling clock cycle unit), and further finely adjusts the sampling frequency of the A / D converter 22b.

  The demodulator 25 demodulates and outputs the in-phase synthesized signal.

  With the above configuration, the two received signals MAIN and SUB are combined in phase as a result of the phase (delay) difference being adjusted in the time domain using the phase adjusting means and the phase shifting means. Therefore, since the adjustment range of the phase difference is expanded, it is possible to eliminate the restriction that the electrical length from the antenna end to the A / D converter input is within one wavelength with a cable or the like.

  In addition, since digital signal processing can be performed, many of the demodulation units 20 can be integrated to reduce the size of the apparatus.

  Next, the operation of the space diversity in-phase synthesis circuit of this embodiment will be described. FIG. 2 is a block diagram for explaining the operation of the space diversity in-phase synthesis circuit.

  The delay difference ΔT between MAIN and SUB input to the adder 245 is ΔT, where θ is the delay difference between the MAIN and SUB signals at the time of reception, and φ (−τ ≦ φ ≦ τ) is the phase difference between the oscillators 23a and 23b. = Θ−φ.

  Since the signal on the MAIN side is output with a passage delay corresponding to the number of stages of the shift register 241, the delay amount is Mτ. On the other hand, since the value of an arbitrary register in the shift register 242 is output by the selector 243, the delay amount of the signal on the SUB side is mτ when the position of the arbitrary register is m (1 to 2M). Therefore, the delay difference ΔT between MAIN and SUB input to the adder 245 is ΔT = θ, where M is the number of stages of the shift register 241 and m is the register position selected by the selector 246 (1 ≦ m ≦ 2M). It is represented by −φ + (Mτ−mτ).

  Here, from the two conditions, −τ ≦ φ ≦ τ and 1 ≦ m ≦ 2M, the adjustable delay amount range is − (M + 1) τ to + (M + 1) τ.

  As described above, it is clear that the range of the delay amount that can be adjusted is greatly expanded while the conventional technique using the infinite phase shifter (EPS) is limited to one period of the signal frequency.

  Next, the state transition of this embodiment will be described. FIG. 3 is a state transition diagram for explaining the operation of the present embodiment.

  In the initial state (S11) when the apparatus is powered on, the control unit 246 searches the register position of the shift register 242 in order from 1 to 2M by the selector 243, and checks the output of the product-sum calculator 244. Then, the register value m is changed from the register position 1 to 2M to obtain the register value m that maximizes the time average value of the product-sum calculator 244 (S12).

  When the value of m is determined, the value of the phase difference φ of the sample timing of the A / D converter 22b is changed from −τ to + τ by adjusting the PLL unit, and the time average value of the product-sum calculator 244 is maximized. Is obtained (S13).

  By performing the above two controls, the obtained register value m and the phase difference φ are fixed, a threshold value is determined based on the value of SUM (S14), and a transition is made to a steady state (S15).

  As a result, the output of the adder 245 converges to a delay difference ΔT of 0 (θ = −φ−Mτ + mτ), and is output as an in-phase synthesized signal as the output of the adder 245.

  After the transition to the steady state, the phase difference is always monitored based on the determined threshold value in order to cope with the dynamic phase fluctuation. In this steady state, if the time-average value SUM of the product-sum operation is equal to or larger than the threshold value, the steady state is maintained (S15). A search is performed for φ in which the SUM is greater than or equal to the threshold value (S16).

  When φ that is equal to or greater than the threshold value can be determined, the process returns to the state (S15). Is searched (S17). As a result, when m that is equal to or greater than the threshold value can be determined, the process proceeds to S13 to determine φ, and the process proceeds to a steady state, but when m cannot be determined, the process proceeds to S12.

  The state transition is repeated as described above, and the in-phase synthesis circuit 24 controls the selector 243 and the oscillators 23a and 23b, and performs in-phase synthesis with the delay difference between MAIN and SUB set to zero.

  Next, the operation of another embodiment of the present invention will be described. FIG. 4 is a block diagram showing the configuration of another embodiment of the present invention.

  According to FIG. 4, the outputs of the multipliers 21a and 21b are branched into two at the hybrid (HYB) 26a and 26b, respectively. One of the two branched signals is input to the in-phase synthesis circuit (SD COMB) 27 via the A / D converters 22a and 22b, and the other is input to the detection unit 28 that detects the phase difference. Is different.

  The main parts of the in-phase synthesis circuit 27 and the detection unit 28 have the same functions and operations as the corresponding ones in FIG. 1, so the description thereof will be omitted, and only the parts different from the operations in FIG.

  The A / D converters 22a, 22b, 281 and 282 receive signals equally distributed by the HYBs 26a and 26b.

  The oscillator 283 of the detection unit 28 outputs a synchronized signal to the A / D converter 281 using the output of the oscillator 23a as a reference clock. Similarly to the oscillator 23b, the oscillator 284 uses the output of the oscillator 23a as a reference clock, but outputs it as a phase-adjusted signal. Therefore, while the oscillator 283 is phase-controlled with the oscillator 23a on the basis of zero phase difference, the oscillators 23b and 284 both output signals having a phase difference of a maximum of one cycle.

  The shift registers 271 and 285 and the shift registers 272 and 286 perform the same operation. Therefore, the adder 275 and the product-sum operation unit 288 respectively input signals having the same phase difference (delay difference).

  The control unit 289 controls the oscillators 23a, 23b, 283, 284 and the selectors 273, 287 based on the output of the product-sum calculator 288 that detects the phase difference under the same condition as the input phase difference of the adder 275. The contents to be controlled are the same as those in FIG. 1 except for the control of the A / D converters 22a, 22b, 281, and 282 described above.

  Next, state transition in the configuration of FIG. 4 will be described. FIG. 5 is a state transition diagram in the configuration of FIG.

  In FIG. 5, the control unit 289 searches the register position of the shift register 286 in order from 1 to 2M by the selector 287 and checks the output of the product-sum calculator 288 in the initial state (S21) when the apparatus is turned on. To do. Then, the register position m is changed from the register position 1 to 2M, and the register value m that maximizes the time average value of the product-sum calculator 288 is obtained (S22).

  When the value of m is determined, the value of the phase difference φ of the sample timing of the A / D converter 282 is changed from −τ to + τ by adjusting the PLL unit, and the time average value of the product-sum calculator 288 is maximized. Is obtained (S23).

  When the obtained register value m and the phase difference φ are fixed (determined) by performing the above two controls, this result is reflected in the oscillator 23b and the selector 273, and the respective set values are updated.

  According to the configuration of the above embodiment, since the phase control can be performed in the detection unit different from the main system used for signal synthesis, the optimum m, φ with the instantaneous fluctuation suppressed in the main system. The value of can be applied.

  In addition, even when the space diversity is configured in a multifaceted manner, the in-phase synthesis circuit can be configured in the demodulation unit, and the apparatus configuration can be reduced in size.

It is a block diagram which shows schematic structure of the space diversity in-phase synthesis circuit of embodiment of this invention. The operation of the space diversity in-phase synthesis circuit of this embodiment will be described. It is a block diagram for demonstrating operation | movement of a space diversity in-phase synthesis circuit. It is a state transition diagram explaining operation | movement of this Embodiment. It is a state transition diagram of a space diversity in-phase synthesis circuit. It is a block diagram which shows the structure of other embodiment of this invention. It is a block diagram which shows the structure of other embodiment of this invention. FIG. 5 is a state transition diagram in the configuration of FIG. 4.

Explanation of symbols

10a, 10b Receiver 11a, 11b RF circuit 20 Demodulator 21a, 21b Multiplier (MIX)
22a, 22b A / D converter (A / D)
23a, 23b Oscillator 24, 27 In-phase synthesis circuit (SD COMB)
25 Demodulator (DEM)
26a, 26b Hybrid (HYB)
28 detectors 241 and 242 shift register 243 selector (SEL)
244 Multiply-Accumulator 245 Adder 246 Control Unit (CONT)
271 and 272 Shift register 285 and 286 Shift register 273 and 287 Selector 275 Adder 283 and 284 Oscillator 288 Multiply-add calculator 289 Control unit

Claims (12)

The first input signal and the second input signal are phase-adjusted, the phase-adjusted signals are phase-shifted, the phase difference between the phase-shifted signals is detected, and the phase-shifted signals are detected. A phase adjustment method comprising: controlling a phase amount of the phase adjustment and a phase shift amount of the phase shift based on a result of the phase difference detection so that the phases of the two signals coincide with each other. 2. The phase amount of the phase adjustment is controlled as an amount that gives a phase difference to each sampling clock when the first input signal and the second input signal are digitally converted. The phase adjustment method described. The phase shift amount of the phase shift is controlled as an amount by which the second input signal is phase-shifted in a predetermined cycle unit with respect to the fixed phase shift of the first input signal. The phase adjustment method according to claim 1. The phase adjustment method according to claim 1, wherein the phase difference detection is performed by performing a product-sum operation on each of the phase-shifted signals. 5. The phase adjustment method according to claim 1, wherein the phase amount of the phase adjustment and the phase shift amount of the phase shift are controlled so that a result of the product-sum operation is maximized. . A common-mode synthesis circuit for performing in-phase synthesis on a first reception signal and a second reception signal, and first and second digital conversion means for digitally converting the first reception signal and the second reception signal, respectively , First and second phase shift means for shifting the first and second digital conversion means outputs, and phase difference detection means for detecting the phase difference of the first and second phase shift means outputs; Any one of an adding means for combining the outputs of the first and second phase shift means, the first and second digital conversion means, and the first and second phase shift means based on the output of the phase difference detection means And a control unit for controlling one of them. 7. The in-phase synthesis circuit according to claim 6, wherein said first and second digital conversion means are supplied with a sampling clock whose phase difference is controlled. The first phase shifting means shifts the first received signal in a fixed manner by a first n-stage shift register, and the second phase shifting means transfers the second received signal to the second N stages of shift registers and n gate circuits provided corresponding to outputs of the respective stages of the n stages of shift registers, and by selecting one of the n gate circuits, 7. The in-phase synthesis circuit according to claim 6, wherein the phase is shifted according to the number of stages selected. 9. The in-phase synthesizing circuit according to claim 6, wherein the phase difference detecting unit performs a product-sum operation on each of the signals output from the first and second phase shifting units. The control unit performs phase control on one of the first and second digital conversion units and the first and second phase shift units so that the output of the phase difference detection unit is maximized. The in-phase synthesis circuit according to claim 6 or 9. 11. The in-phase synthesis circuit according to claim 6 is connected in parallel, assigned to a signal synthesis block and a phase difference detection block, and based on the phase difference detection means output of the phase difference detection block, the signal An in-phase synthesis circuit which controls digital conversion means and phase shift means of a synthesis block. The in-phase synthesis circuit according to any one of claims 6 to 11, further comprising: reception means for converting a radio frequency band signal received by an antenna into an intermediate frequency band or a baseband frequency band; and the in-phase synthesis circuit. Space diversity in-phase synthesis circuit characterized by being a circuit.

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