JP2005276136A - Bus device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a bus device capable of simultaneously transferring the data more than the number of transfer systems, and reducing the amount of wiring in a bus system in comparison with a conventional one. <P>SOLUTION: Switch parts 411-4n1, 412-4m2 are respectively mounted on contact points with a bus 3, of masters 11-1n and slave 21-2m, and a transfer passage corresponding to data transfer request is divided from the bus 3 by the switch part to simultaneously transfer the plurality of data even in the data transfer system of one system. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a bus device in which a plurality of masters and a plurality of slaves are connected by a bus, and data is transferred between the master and the slaves.

  In a bus device of a single bus system, if a data transfer requested by a master is being executed, the data transfer request from another master is controlled to wait until the data transfer being executed is completed. The For this reason, the performance of the entire bus device may be deteriorated depending on the frequency and timing of the waiting state for the data transfer request.

  In order to solve such problems, conventionally, a bus apparatus has been proposed in which a plurality of bus systems for data transfer are provided to simultaneously multiplex transfer data requested to be transferred from a plurality of masters.

  An example of the bus device as described above is disclosed in Patent Document 1. In the bus device of Patent Document 1, each of a plurality of masters is provided with a dedicated bus system for multiplex transfer, and a switch unit is provided between the slave and these bus systems (hereinafter referred to as Conventional Example 1). ). The switch unit allows the slave to select the bus system, and the bus systems can be used simultaneously. Thus, data multiplex transfer is realized.

  In addition to this, in Patent Document 1, a switch unit is provided between each master and a plurality of bus systems, and a bus system is selected also in the master and slaves (hereinafter referred to as Conventional Example 2). It is disclosed. By configuring in this way, multiple transfers for the maximum number of bus systems can be realized.

Japanese Patent Laid-Open No. 11-282794

  The conventional bus device has a problem that an enormous amount of wiring is required for data multiplex transfer, and if the bus system is reduced, multiplexing becomes insufficient accordingly.

  For example, in the bus device according to the conventional example 1, a bus system for data transfer is provided for each of a plurality of masters, so that multiple data transfer is possible, but the amount of wiring corresponding to bus signals becomes enormous, and the entire device The cost of will become high.

  Further, in the conventional example 2, the master can select the data transfer system of the bus by the switch unit, so that the number of bus systems can be reduced compared to the conventional example 1. However, in the configuration of Conventional Example 2, when the number of data transfer systems is n, the maximum multiplexing is up to n, and thus the performance of the entire apparatus cannot be sufficiently increased.

  The present invention has been made to solve the above-described problem, and by dividing the bus by the switch units provided at the connection parts with the master and slave buses and assigning the data transfer, the number of transfer systems can be increased. It is an object of the present invention to provide a bus device that can execute data transfer simultaneously and can reduce the amount of wiring in a bus system as compared with the prior art.

  A bus device according to the present invention is provided at each connection point between a plurality of master devices, a plurality of slave devices, and a bus in a bus device including a plurality of master devices and a plurality of slave devices connected to each other via a bus. A switch unit is provided that divides the bus at the connection point according to data transfer by these devices to form a data transfer path.

  According to the present invention, in a bus device including a plurality of master devices and a plurality of slave devices connected to each other via a bus, the bus devices are provided at connection points between the plurality of master devices and the plurality of slave devices and the bus. Since it has a switch unit that divides the bus at the connection point according to data transfer by the device to form a data transfer path, more data transfer than the number of transfer systems can be executed at the same time, and compared to the conventional bus There is an effect that the amount of wiring in the system can be reduced.

Embodiment 1 FIG.
1 is a diagram showing a configuration of a bus device according to Embodiment 1 of the present invention. In FIG. The bus device according to the first embodiment includes a plurality of masters 11 to 1n and switch units 411 to 4n1 that connect these masters to the bus 3, and a plurality of slaves 21 to 2m and a switch unit 412 that connects these masters to the bus 3, respectively. The data transfer is controlled by the arbiter 5 connected to the master, slave, and switch unit via signal lines. However, n and m are natural numbers. The bus 3 transfers commands, addresses, and data related to data transfer between the master and the slave.

  FIG. 2 is a diagram showing the configuration around the master and slave in FIG. 1, and shows the configuration when a plurality of masters and a plurality of slaves are connected to one system bus 3, for example. The masters 11 to 1n and the slaves 21 to 2m are respectively connected to one bus 3 and switch units 411 to 4n1 and 412 to 4m2 are provided at the connection points. Data transfer 61 to 6n is executed between the masters 11 to 1n and the slaves 21 to 2m via the switch units 411 to 4n1 and 412 to 4m2. In the figure, the masters 11 to 1n and the slaves 21 to 2m are arranged in order. However, any order may be used.

  The masters 11 to 1n are, for example, CPUs, and the slaves 21 to 2m are, for example, storage devices such as RAMs and ROMs that exchange data with the CPUs. The switch units 411 to 4n1 and 412 to 4m2 may be configured so as to transfer data between a desired master and slave by opening and closing a signal flow in the bus 3, and for example, the one shown in FIG. .

  FIG. 3 shows the switch 421 in FIG. 2 as an example. The switch 421 according to the illustrated example is configured by connecting two PMOS transistors 4211 and 4212 in series and providing a signal line to the master 12 at the contact. The gates of the PMOS transistors 4211 and 4212 are connected to the signal line from the arbiter 5. Thereby, the PMOS transistors 4211 and 4212 are controlled to be turned on / off by the control signal transmitted from the arbiter 5 through the signal line. The other switch units 411, 431-4n1, 412-4m2 are assumed to have the same configuration.

  For example, consider the case where the PMOS transistor 4211 is turned off and the PMOS transistor 4212 is turned on by the control signal from the arbiter 5 in the switch unit 412. At this time, the master 12 can transfer data via the bus 3 on the PMOS transistor 4212 side and is separated from the bus 3 on the PMOS transistor 4211 side.

  Note that FIG. 3 shows a simplified configuration for facilitating understanding of the function of the switch unit, and the present invention is not limited to this, and the signal flow in the bus 3 can be turned on and off. Any circuit may be used.

Next, the operation will be described.
As shown in FIG. 1, the masters 11 to 1n output to the arbiter 5 a data transfer request signal composed of a slave ID for identifying a transfer destination slave and a request signal that is a data transfer request.

  Based on the data transfer request signal from the master, the arbiter 5 determines whether or not there is a transfer path according to the request, and outputs the result as a sw_busy signal to the master. For example, the switch unit corresponding to the slave identified by the slave ID in the data transfer request signal or the master that made the request is used for other data transfer, and the data transfer path corresponding to the request is configured. If it is not possible, it is determined that the transfer path does not exist.

  In this case, the arbiter 5 outputs a sw_busy signal to the H (high) level to the master indicating that the switch unit is used for other data transfer and that there is no transfer path corresponding to the data transfer request. On the other hand, if there is a transfer path corresponding to the data transfer request, the sw_busy signal is set to L (low) level and output to the master.

  Further, when there is no transfer path corresponding to the data transfer request, the arbiter 5 sets the request2 signal to the L (low) level and outputs it to the slave specified by the slave ID in the request signal. On the other hand, if there is a transfer path corresponding to the data transfer request, the request2 signal is set to H (high) level and output to the slave. At this time, the slave outputs an Ack signal indicating that the data transfer is accepted to the master that has requested the data transfer, and the data transfer is executed.

  Next, processing when data transfer requests are simultaneously made between a plurality of masters and a plurality of slaves will be described. Here, as shown in FIG. 4A, data transfer from the master 11 to the slave 21, data transfer from the master 12 to the slave 23, and data transfer from the master 13 to the slave 22 are shown in FIG. As shown in the drawing, a case where an execution request is made before the end of the mutual transfer processing will be described as an example.

  When the masters 11, 12, and 13 execute data transfer to the slaves 21, 23, and 22, the masters 11, 12, and 13 output the above-described data transfer request signal (H-level request signal, slave ID) to the arbiter 5. The master continues to output an H level request signal until the data transfer is completed. As a result, the arbiter 5 can determine whether or not there is existing data transfer based on the level of the request signal from the master when there is another data transfer request.

  When there is a data transfer request from the master 12 to the slave 23, the arbiter 5 uses the switch units 421, 422, 431, and 432 between the slave 23 and the master 12 specified by the slave ID for other data transfer. Determine whether or not.

  In FIG. 4B, since the data transfer request from the master 12 to the slave 23 is made earliest and the switch unit is not used for other data transfer, the arbiter 5 has the switch units 421, 422, 431, 432 Control to turn on. For example, in the configuration shown in FIG. 3, the PMOS transistors of the switch units 421, 422, 431, and 432 are turned on to set the data transfer path from the master 12 to the slave 23. Further, the other PMOS transistors of the switch units 421 and 432 are controlled to be off to divide the bus 3 so that a data transfer path from the master 12 to the slave 23 is formed independently of the other transfer paths.

  As a result, the arbiter 5 outputs an L level sw_busy signal indicating that a transfer path corresponding to the data transfer request exists to the master 12 and outputs an H level request 2 signal to the slave 23. Upon receiving the request 2 signal at the H level, the slave 23 outputs an Ack signal indicating that the data transfer is accepted via the transfer path to the master 12, and the data transfer is executed (Data in FIG. 4B). Column).

  Thereafter, as shown in FIG. 4B, if a data transfer request from the master 11 to the slave 21 is made before the data transfer from the master 12 to the slave 23 is completed, the arbiter 5 uses the slave ID. It is determined whether or not the switch units 411 and 412 between the identified slave 21 and master 11 are used for other data transfer.

  In the example of FIG. 4B, since the switch units 411 and 412 are not used for other data transfer, the arbiter 5 performs control so that they are turned on. At this time, the switch unit is controlled so that the data transfer path from the master 12 to the slave 23 is divided from the bus 3 so as not to affect the data transfer from the master 12 to the slave 23.

  For example, in the configuration shown in FIG. 3, the PMOS transistor on the master 11 side of the switch unit 412 is turned on, and the data transfer from the master 12 to the slave 23 is not affected. Side PMOS transistor is turned off. As a result, the data transfer path from the master 11 to the slave 21 is formed independently of the data transfer path from the master 12 to the slave 23 by dividing the bus 3.

  Next, the arbiter 5 outputs an L level sw_busy signal indicating that a transfer path corresponding to the data transfer request exists to the master 11 and outputs an H level request 2 signal to the slave 21. When receiving the request 2 signal at the H level, the slave 21 outputs an Ack signal indicating that the data transfer is accepted to the master 11 via the transfer path. In this way, the data transfer from the master 11 to the slave 21 is executed simultaneously with the data transfer from the master 12 to the slave 23 (refer to the Data column in FIG. 4B). That is, data transfer of the number of data transfer systems + 1 by the bus 3 is executed simultaneously.

  Subsequently, as shown in FIG. 4B, the data transfer request from the master 13 to the slave 22 is completed before the data transfer from the master 12 to the slave 23 and the data transfer from the master 11 to the slave 21 are completed. When the arbiter 5 is executed, the arbiter 5 determines whether or not the switch units 431 and 422 between the slave 22 and the master 13 specified by the slave ID are used for other data transfer.

  At this time, since the switch units 431 and 422 are used for data transfer from the master 12 to the slave 23, the arbiter 5 outputs an H level sw_busy signal to the master 13 while the switch unit is used. (See FIG. 4B). The master 13 outputs the H level request signal to the arbiter 5 to continue the request, but enters a data transfer waiting state while the H level sw_busy signal is output from the arbiter 5.

  Thereafter, when the request signal from the master 12 becomes L level and the arbiter 5 determines that the data transfer between the master 12 and the slave 23 is completed, the arbiter 5 responds accordingly from the master 13 to the slave 22. The switch units 431 and 422 are controlled to be in an ON state so as to set the data transfer path, and an L level sw_busy signal is output to the master 13.

  For example, in the configuration shown in FIG. 3, the PMOS transistor on the slave 22 side of the switch unit 431 is on-controlled and separated from the bus 3 region on the slave 23 side. Control off. Further, the PMOS transistor on the master 13 side of the switch unit 422 is turned on, and the PMOS transistor on the master 12 side of the switch unit 422 is turned off in order to separate it from the bus 3 region on the master 12 side. Thereby, the bus 3 is divided to form a data transfer path from the master 13 to the slave 22. That is, a data transfer path from the master 13 to the slave 22 is set independently of other data transfer paths.

  Further, the arbiter 5 outputs an L level sw_busy signal to the master 13 and simultaneously outputs an H level request 2 signal to the slave 22. Upon receipt of the H level request 2 signal, the slave 22 outputs an Ack signal indicating that the data transfer has been accepted to the master 13 via the transfer path. In this way, data transfer from the master 13 to the slave 22 is executed simultaneously with data transfer from the master 11 to the slave 21 (see the Data column in FIG. 4B).

  As described above, according to the first embodiment, the switch units 411 to 4n1 and 412 to 4m2 are provided at the connection points of the masters 11 to 1n and the slaves 21 to 2m with the bus 3, and data transfer is performed by these switch units. By dividing the transfer path according to the request from the bus 3, even with a single data transfer system, a plurality of data transfers can be executed simultaneously, and the amount of wiring in the bus system is reduced compared to the conventional system. Can be made.

  In the switch section having the configuration shown in FIG. 3, any one of the PMOS transistors may be omitted for the switch sections adjacent to each other. For example, as shown in FIG. 2, since the switch parts 412 and 421 are connected to each other by PMOS transistors, any one of these transistors may be deleted.

  For example, even if the PMOS transistor 4211 of the switch unit 421 is deleted, the PMOS transistor of the switch unit 412 can divide the bus 3 as necessary when setting the data transfer path. As described above, the switch unit according to the present invention does not use a PMOS transistor as shown in FIG. 3, and may be any configuration that can divide the bus 3 as necessary.

  Further, in the configuration of the switch section shown in FIG. 3, signal lines for controlling on / off of the two PMOS transistors 4211 and 4212 are necessary, respectively. However, as shown in FIG. And the serial / parallel conversion circuit 4213 may be connected, and the PMOS transistors 4211 and 4212 may be controlled to be turned on / off by two signal lines from the serial / parallel conversion circuit 4213.

  In this configuration, the arbiter 5 serially transmits a control signal for ON / OFF control of the PMOS transistors 4211 and 4212 of the switch unit 421 via one signal line, and the serial / parallel conversion circuit 4213 receives the control signal. The serial / parallel conversion circuit 4213 converts a serial signal related to the received control signal into a parallel signal and outputs the parallel signal to the corresponding PMOS transistors 4211 and 4212. With this configuration, the number of wires between the switch unit and the arbiter 5 can be reduced, and the cost of the entire apparatus can be reduced.

Embodiment 2. FIG.
FIG. 6 is a diagram showing a configuration of a bus device according to Embodiment 2 of the present invention, in which a plurality of masters and a plurality of slaves are connected to two buses. The bus device according to the second embodiment includes a plurality of masters 11 to 1n and switch units 411 to 4n1 and 413 to 4n3 that connect these masters to the buses 31 and 32, and a plurality of slaves 21 to 2m and these masters to the bus 31, 32 includes switch parts 412 to 4m2 and 414 to 4m4, respectively. Similarly to the first embodiment, the data transfer 71, 72, 73 is controlled by the arbiter 5 connected to the master, slave, and switch unit via signal lines. However, n and m are natural numbers.

  Data transfer 71 to 7n is performed between the masters 11 to 1n and the slaves 21 to 2m via the switch units 411 to 4n1, 412 to 4m2, 413 to 4n3, 414 to 4m4 and the buses 31 and 32. In the figure, the masters 11 to 1n and the slaves 21 to 2m are arranged in order. However, any order may be used.

  The masters 11 to 1n are, for example, CPUs, and the slaves 21 to 2m are, for example, storage devices such as RAMs and ROMs that exchange data with the CPUs. The switch units 411 to 4n1, 412 to 4m2, 413 to 4n3, and 414 to 4m4 may be configured so as to transfer data between a desired master and slave by opening and closing a signal flow in the buses 31 and 32. The one shown in FIG. 7 can be considered.

  In FIG. 7, the switch 414 in FIG. 6 is shown as an example. The switch 414 according to the illustrated example includes six PMOS transistors 4141 to 4146. The PMOS transistors 4141 and 4142 are connected in series on the bus 32, and the PMOS transistors 4143 and 4144 are connected in series on the signal line to the bus system 31. The PMOS transistors 4145 and 4146 are connected so as to straddle the connected PMOS transistor pairs in series.

  Each gate of the PMOS transistors 4141 to 4146 is connected to a signal line from the arbiter 5. As a result, the PMOS transistors 4141 to 4146 are on / off controlled by the control signal transmitted from the arbiter 5 through the signal line. The other switch units 411 to 4n1, 412 to 4m2, 413 to 4n3, and 414 to 4m4 are assumed to have the same configuration.

  For example, consider a case where the PMOS transistors 4142, 4143, 4145, 4146 are turned off and the PMOS transistors 4141, 4144 are turned on by the control signal from the arbiter 5 in the switch unit 414. At this time, the slave 21 can transfer data via the bus 32 on the PMOS transistor 4141 side, and is separated from the bus system 31 and the bus 32 on the PMOS transistor 4142 side.

  Note that FIG. 7 shows a simplified configuration for easy understanding of the function of the switch unit, and the present invention is not limited to this, and the signal flow in the buses 31 and 32 is turned on and off. Any circuit can be used. That is, the switch unit according to the present embodiment has a function of dividing the bus as in the first embodiment, and a signal transferred from the bus system 31 to the slave 21 does not affect the bus system 32. It has a function.

Next, the operation will be described.
When transferring data, the masters 11 to 1n send a data transfer request signal including a slave ID for identifying a transfer destination slave and a request signal that is a data transfer request to the arbiter 5 as described in the first embodiment. Output.

  Based on the data transfer request signal from the master, the arbiter 5 determines whether or not there is a transfer path according to the request, and outputs the result as a sw_busy signal to the master. For example, the switch unit corresponding to the slave identified by the slave ID in the data transfer request signal or the master that made the request is used for other data transfer, and the data transfer path corresponding to the request is configured. If it is not possible, it is determined that the transfer path does not exist.

  In this case, the arbiter 5 outputs a sw_busy signal to the H (high) level to the master indicating that the switch unit is used for other data transfer and that there is no transfer path corresponding to the data transfer request. On the other hand, if there is a transfer path corresponding to the data transfer request, the sw_busy signal is set to L (low) level and output to the master.

  Further, when there is no transfer path corresponding to the data transfer request, the arbiter 5 sets the request2 signal to the L (low) level and outputs it to the slave specified by the slave ID in the request signal. On the other hand, if there is a transfer path corresponding to the data transfer request, the request2 signal is set to H (high) level and output to the slave. At this time, the slave outputs an Ack signal indicating that the data transfer is accepted to the master that has requested the data transfer, and the data transfer is executed. The basic operation so far is the same as that of the first embodiment.

  Next, processing when data transfer requests are simultaneously made between a plurality of masters and a plurality of slaves will be described. Here, as shown in FIG. 8, a data transfer request a from the master 11 to the slave 23 is performed while the data transfer B from the master 12 to the slave 21 and the data transfer C from the master 13 to the slave 22 are being executed. The case where is done will be described.

  When the masters 11, 12, and 13 execute data transfer to the slaves 21, 23, and 22, the masters 11, 12, and 13 output the above-described data transfer request signal (H-level request signal, slave ID) to the arbiter 5. The master continues to output an H level request signal until the data transfer is completed. As a result, the arbiter 5 can determine whether or not there is existing data transfer based on the level of the request signal from the master when there is another data transfer request.

  First, when there is a data transfer request b from the master 12 to the slave 21, the arbiter 5 uses the switch units 421, 423, and 414 between the slave 21 and the master 12 specified by the slave ID for other data transfer. Judge whether or not.

  If the switch unit is not used by another data transfer, the arbiter 5 controls the switch units 421, 423, and 414 to be turned on. For example, in the configuration shown in FIG. 7, the PMOS transistors of the switch units 421, 423, and 414 are turned on to set the data transfer path from the master 12 to the slave 21.

  At this time, the arbiter 5 divides the buses 31 and 32 and allocates a data transfer path from the master 12 to the slave 21 so as not to affect other data transfer, so that the switch units 421, 423, and 414 On / off control of the PMOS transistor is executed.

  As a result, the arbiter 5 outputs an L-level sw_busy signal indicating that there is a transfer path corresponding to the data transfer request b to the master 12 and outputs an H-level request 2 signal to the slave 21. When receiving the request2 signal at the H level, the slave 21 outputs an Ack signal indicating that the data transfer is accepted to the master 12 via the transfer path, and the data transfer B is executed.

  When there is a data transfer request c from the master 13 to the slave 22, the arbiter 5 uses the switch units 431, 433, and 424 between the slave 22 and the master 13 specified by the slave ID for other data transfer. Judge whether or not.

  Since these switch units are not used for other data transfer, the arbiter 5 controls the switch units 431, 433, and 424 to be turned on. For example, in the configuration shown in FIG. 7, the data transfer path from the master 13 to the slave 22 is set by turning on the PMOS transistors of the switch units 431, 433, and 424.

  At this time, the arbiter 5 divides from the buses 31 and 32 to form a data transfer path from the master 13 to the slave 22 so as not to affect other data transfer. On / off control of the PMOS transistor is executed.

  As a result, the arbiter 5 outputs an L level sw_busy signal indicating that a transfer path corresponding to the data transfer request c exists to the master 13 and outputs an H level request 2 signal to the slave 22. When receiving the request 2 signal of H level, the slave 22 outputs an Ack signal indicating that the data transfer is accepted to the master 13 via the transfer path, and the data transfer C is executed.

  Thereafter, when a data transfer request a from the master 11 to the slave 23 is made before the data transfer B, C is completed, the arbiter 5 switches the switch unit between the slave 23 and the master 11 specified by the slave ID. It is determined whether 411 to 434 are used for other data transfer.

  Here, the switch units 411, 412, 422, 432, and 434 are not used for the other data transfers B and C. Therefore, the arbiter 5 performs control so that these are turned on. At this time, the data transfer path from the master 11 to the slave 23 is formed by dividing the buses 31 and 32 so as not to affect the data transfers B and C.

  For example, in the case of the switch unit 411 having the configuration shown in FIG. 7, the PMOS transistor on the bus 32 side is controlled to be separated from the signal line to the bus 32, and the PMOS transistor on the master 11 and switch unit 412 side is turned on. Control. The switch unit 412 controls the PMOS transistor on the slave 21 side to be off and controls the PMOS transistors on the switch units 411 and 421 side to be separated from the transfer path via the slave 21.

  In the switch unit 422, the PMOS transistor on the slave 22 side is turned off so as to be separated from the transfer path via the slave 22, and the PMOS transistor on the switch units 421 and 431 side is turned on.

  In the switch unit 432, only the switch unit 431 and the PMOS transistor on the bus 32 side are turned on so that the transfer path becomes a corner to the bus 32 and is separated from the bus 31. Further, in the switch unit 434, the PMOS transistor on the switch unit 433 side is turned off so as to be separated from the transfer path on the slave 22 side, and the PMOS transistor on the switch unit 432 and the slave 23 side is turned on.

  On the other hand, the switch units 421 and 431 are used for data transfer B and C, respectively. At this time, the arbiter 5 determines whether or not a transfer path corresponding to the data transfer request a can be set by switching the switch unit. For example, in the switch section having the configuration shown in FIG. 7, a plurality of transfer paths can be set by on / off control of the PMOS transistor.

  In particular, the PMOS transistor 4145 can be turned on when the PMOS transistors 4141 and 4142 are in the off state, so that the bus 32 can be used as another transfer path separately from the path between the bus system 31 and the slave 21. it can. The PMOS transistor 4146 is also turned on when the PMOS transistors 4142 and 4143 are in the off state, so that the path between the bus system 31 and the slave 21 can be used as another transfer path independently of the bus 32. it can.

  If it is determined in the above determination process that the transfer path corresponding to the data transfer request a cannot be set no matter how the switch sections used for the data transfers B and C are switched, the arbiter 5 uses these switch sections. During this time, an H level sw_busy signal is output to the master 11. The master 11 outputs an H level request signal to the arbiter 5 and continues the request, but enters a data transfer waiting state while the H level sw_busy signal is output from the arbiter 5.

  In the example of FIG. 8, the arbiter 5 determines the pattern of the transfer path that can be constructed by switching the switch units 421 and 431 used for the data transfers B and C, and the PMOS transistors as described above for these switch units. With the on / off control, it is determined that the transfer path as shown in the lower part of FIG. 8 can be set as the transfer path corresponding to the data transfer request a.

  Thereafter, in the data transfer B, the arbiter 5 performs on / off control of the PMOS transistor of the switch unit 421 so as to separate the data transfer path from the master 13 to the slave 22 from the buses 31 and 32. The switch unit 421 is switched independently of the transfer path, that is, so that the buses 31 and 32 are divided to form a transfer path corresponding to the data transfer request a.

  Here, the switch units 421 and 431 in FIG. 7 change “connect to bus system 31” to “connect to master 12 (master 13)” and “connect to slave 21” to “switch unit 423 (switch unit 433)”. And “bus 32” are read as “bus 31”.

  At this time, in the switch unit 421, for example, only the PMOS transistor 4146 is on-controlled so as to separate the path from the master 12 to the switch unit 423 from the buses 31 and 32, but the arbiter 5 also turns on the PMOS transistor 4145. Put it in a state. Similarly, in the switch unit 431, for example, only the PMOS transistor 4146 is on-controlled so that the path from the master 13 to the switch unit 433 is separated from the buses 31 and 32. For example, the arbiter 5 also turns on the PMOS transistor 4145. Put it in a state. As a result, a path between the switch unit 421 and the switch unit 431 which is a part of the transfer path corresponding to the data transfer request a is set.

  Next, the arbiter 5 outputs an L level sw_busy signal indicating that there is a transfer path corresponding to the data transfer request a to the master 11 and outputs an H level request 2 signal to the slave 23. When receiving the request2 signal at the H level, the slave 23 outputs an Ack signal indicating that the data transfer is accepted to the master 11 via the transfer path. In this way, the data transfer A from the master 11 to the slave 23 is executed simultaneously with the data transfers B and C. That is, data transfer of the number of data transfer systems + 1 by the buses 31 and 32 is executed simultaneously.

  As described above, according to the second embodiment, the switch units 411 to 4n1, 413 to 4n3, 412 to 4m2, and 414 to 4m4 are connected to the connection points of the masters 11 to 1n and the slaves 21 to 2m with the buses 31 and 32. By dividing the transfer path according to the data transfer request from the buses 31 and 32 by these switch units, even if there is a data transfer request exceeding the number of data transfer systems, the data transfer according to these requests can be performed simultaneously. This can be executed, and the amount of wiring in the bus system can be reduced as compared with the prior art.

  In the switch section having the configuration shown in FIG. 7, any one of the PMOS transistors may be omitted for the switch sections adjacent to each other. For example, as shown in FIG. 6, since the switch units 413 and 414 are connected to each other by PMOS transistors, any one of these transistors may be deleted.

  For example, even if the PMOS transistor 4142 of the switch unit 413 is deleted, the PMOS transistor 4141 of the switch unit 414 can divide the bus 32 as necessary when setting the data transfer path. As described above, the switch unit according to the present invention is not required to use a PMOS transistor as shown in FIG. 7, but may be any configuration as long as the buses 31 and 32 can be divided as necessary.

  Further, in the configuration of the switch section shown in FIG. 7, signal lines for controlling the on / off of the six PMOS transistors 4141 to 4146 are required, respectively. However, the arbiter 5 and the serial / parallel conversion circuit are configured with one signal line. , And the PMOS transistors 4141 to 4146 may be controlled to be turned on / off by six signal lines from the serial / parallel conversion circuit.

  In this configuration, the arbiter 5 serially transmits a control signal for ON / OFF control of the PMOS transistors 4141 to 4146 of the switch unit via one signal line, and the serial / parallel conversion circuit receives it. The serial / parallel conversion circuit converts a serial signal related to the received control signal into a parallel signal and outputs the parallel signal to a corresponding PMOS transistor. With this configuration, the number of wires between the switch unit and the arbiter 5 can be reduced, and the cost of the entire apparatus can be reduced.

  In the second embodiment, an example has been shown in which three or more data transfers can be simultaneously made to two buses. However, as shown in FIG. It can be easily assumed that the same effect as described above can be obtained.

  FIG. 9 is a bus device having three buses in which the bus 33 is further added to the configuration of FIG. 6. Switch units 415, 425, and 435 are provided at connection points between the masters 11 to 13 and the bus 33, and the slave 21. ˜23 and the bus 33 are connected at switch points 416, 426, 436. The switch units 415, 425, 435, 416, 426, and 436 have a configuration as shown in FIG. 7, for example, and the arbiter 5 can set transfer paths corresponding to a plurality of data transfer requests independently of each other. it can.

  In the illustrated example, as in the second embodiment, the data transfer path a1 through the bus 32 of the master 11 is controlled by the on / off control of the switch units 411 and 413, and the switch units 421, 412, 431, 422, 424, and 426 are provided. The data transfer path b1 between the master 12 and the slave 22 is switched by the on / off control of the data, and the data transfer path c1 between the master 13 and the slave 21 is switched by the on / off control of the switch units 431, 433, 435, and 416. The data transfer path d1 through the buses 32 and 33 of the slave 23 is set by the on / off control of the units 415, 413, 423, 414, 433, 424, 434, and 436.

  In addition, the number of bus systems is limited to 1 to 3 as long as a switch unit capable of separating the transfer path from the bus system for each data transfer is provided at each connection point between the master and slave and the bus system, which is a feature of the present invention. It may be 4 or more.

  As described above, the bus device according to the present invention executes a plurality of data transfers at the same time by dividing the bus by the switch units provided at the connection portions with the master and slave buses and allocating them to the data transfer. Can be reduced and the amount of wiring in the bus system can be reduced compared to the conventional one, so it can be applied to multiprocessor systems in which multiple processor devices (CPU, etc.) and multiple storage devices exchange data via the bus. It is.

It is a figure which shows the structure of the bus apparatus by Embodiment 1 of this invention. FIG. 2 is a diagram illustrating a configuration around a master and a slave in FIG. 1. It is a figure which shows the structural example of the switch part in FIG. FIG. 6 is a diagram for explaining the operation of the bus device according to the first embodiment. It is a figure which shows the other structural example of the switch part in FIG. It is a figure which shows the structure of the bus apparatus by Embodiment 2 of this invention. It is a figure which shows the structural example of the switch part in FIG. FIG. 10 is a diagram for explaining the operation of the bus device according to the second embodiment. It is a figure which shows the other structural example of the bus apparatus by Embodiment 2. FIG.

Explanation of symbols

  11 to 1n master (master device), 21 to 2m slave (slave device), 3, 31 to 33 bus, 411 to 4n1, 412 to 4m2, 413 to 4n3, 414 to 4m4, 415, 416, 425, 426, 435 , 436 switch unit, 4211, 4212, 4141-4146 PMOS transistor, 4213 serial-parallel conversion circuit, 5 arbiter, 61-6n, 71-73, a1, b1, c1, A, B, C data transfer, a, b , C Data transfer request.

Claims (3)

  A bus device including a plurality of master devices and a plurality of slave devices connected to each other via a bus, provided at each connection point between the plurality of master devices and the plurality of slave devices and the bus, and data by these devices A bus device comprising a switch unit that divides a bus at the connection point according to transfer to form a data transfer path.   The switch unit divides the bus at connection points in accordance with a plurality of data transfers by a plurality of master devices and a plurality of slave devices to form data transfer paths, and simultaneously executes a plurality of data transfers through these data transfer paths. The bus device according to claim 1.   The plurality of master devices and the plurality of slave devices are connected to each other via a plurality of buses, and the switch unit connects the bus at a connection point according to a plurality of data transfers by the plurality of master devices and the plurality of slave devices. 2. The bus device according to claim 1, wherein a data transfer path is divided to form a plurality of data transfers, and a plurality of data transfers are simultaneously executed by the data transfer paths.

Images