JP2005275889A - Electronic controller and memory control method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To restore holding information of a RAM as a main storage device without erroneously performing initialization or the like of a nonvolatile memory, to prevent losing of the information by easy memory control even when sudden power shutoff is generated, and to update the storage information of the nonvolatile memory. <P>SOLUTION: The RAM 4b is provided with areas of main and sub banks 7m, 7s of capacity of an EEPROM 5, a bank monitoring means recognizes a request of information storage of the EEPROM 5 on the basis of discordance detection of bit inversion states of the banks 7m, 7s by the bank monitoring means, the holding state of the regular bank 7m is written in the EEPROM 5, and the holding information of the banks 7m, 7s is rewritten into the latest storage information of the EEPROM 5 after the update. When the bank monitoring means detects discordance except the bit inversion state to recognize bank abnormality, a bank information correction means writes the storage information of the EEPROM 5 into the banks 7m, 7s. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention reads and processes storage information of a rewritable nonvolatile memory to a random access memory as a main storage device, and the nonvolatile memory to which the information stored in the random access memory is written based on a request for information storage, The present invention relates to a computer-configured electronic control device and a memory control method thereof in which information is not lost when a computer is turned off.

  Conventionally, in the field of the automobile industry, in order to improve vehicle safety, comfort, etc., a microcomputer ECU as an electronic control device of a computer configuration is used, and vehicle control such as acceleration, gear shifting, braking, Electronic control of body control such as wiper control and light control has been attempted.

  In these electronic control, in order to prevent the information loss during the power cut-off due to the ignition key being turned off, the EEPROM (Electrically-Erasable-Programmable-Ready-Only-Memory) A rewritable nonvolatile memory represented by the above is used for storing information during power shut-off.

  An electronic control device for storing information during power shut-off using an EE ROM ROM (hereinafter referred to as an EEPROM) is configured as shown in FIG. 3, for example, and includes a CPU 1a of the ECU 1 having a microcomputer configuration, a main memory. A random access memory (hereinafter referred to as “RAM”) 1 b and an EEPROM 2, which are devices, are connected by a bus 3.

  When the power supply of the ECU 1 is started by turning on the ignition key, the stored data d21, d22,..., D2n of the addresses 1, 2,..., N of the EEPROM 2 are read and expanded in the RAM 1b. During the power feeding operation of the ECU 1, the vehicle control and the body control are performed based on the information d11, d12, ..., d2n of the data 1, 2, ..., n developed in the RAM 1b.

  Also, when new data is obtained while the vehicle is running, etc., a request to store information in the EEPROM 2 occurs and the information held in the RAM 1b is rewritten, each time or until just before the power is shut off by turning off the ignition key The contents held in the RAM 1b are written into the EEPROM 2, and the stored contents in the EEPROM 2 are updated.

  In the case of memory control in which information stored in the RAM 1b is written and stored in the EEPROM 2 each time a request for information storage occurs, for example, it is based on a sudden power interruption due to, for example, a fuse being blown or a power supply cable being disconnected from a battery terminal. There is an advantage that loss of information is prevented.

  Further, in the case of memory control in which the information held in the RAM 1b is written and stored in the EEPROM 2 until just before the power is cut off, other processing of the ECU 1 is not interrupted, and the number of times the EEPROM 2 is rewritten is small. There is an advantage that the life of the EEPROM 2 having a limited number of rewrites can be extended (for example, see Patent Document 1).

  Next, in this type of electronic control device, in order to monitor, detect and repair abnormalities such as destruction of information (retained information) developed in the RAM 1b, in addition to the original stored information, its bit inversion information and checksum Are simultaneously written and stored in the EEPROM 2, and when the stored information is read out from the EEPROM 2 to the RAM 1b, the bit inversion information and check sum information are also read out, and the bit comparison and check sum processing are executed, thereby The occurrence of abnormality such as destruction is detected.

  The use of a rewritable non-volatile memory such as EEPROM 2 to prevent the loss of information in the RAM as the main storage device when the power is shut off is performed in electronic control devices having various computer configurations. Even in the apparatus, the memory control for writing and reading information as described above is performed.

JP 2000-20407 (paragraph [0002], FIG. 7)

  In the case of the conventional electronic control device of this type, for example, for information read from the EEPROM 2 of FIG. 3 to the RAM 1b, an abnormality such as destruction of information held in the RAM 1b is detected from the bit comparison, checksum processing, etc. Even if this abnormality is caused by destruction of information stored in the EEPROM 2 or caused by writing / reading in the RAM 1b (hereinafter referred to as an abnormality on the RAM side), it cannot be recognized separately. There is a problem that the memory of the EEPROM 2 is erroneously initialized when it occurs due to an abnormality on the RAM side.

  In addition, when information is written to the EEPROM 2 each time a request for information storage is generated and the stored information in the EEPROM 2 is updated, the information is conventionally held randomly in the RAM 1b, so that other processing by writing to the EEPROM 2 is performed. In order to minimize the influence of interruptions, etc., it is desirable to write some changed information in the EEPROM 2. In this case, the memory control program always determines where (to which address) the information is written in the EEPROM 2. It is necessary to manage and recognize, and there is a problem that memory control becomes extremely complicated.

  In order to simplify the memory control, the number of times the EEPROM 2 is written when the information stored in the EEPROM 2 is rewritten and updated unconditionally regardless of whether there is a change in the information held in the RAM 1b when a request for information storage occurs. Therefore, there is a problem that the life of the EEPROM 2 cannot be extended.

  On the other hand, when the information stored in the EEPROM 2 is updated until just before the power is turned off, the writing time of the EEPROM 2 hardly becomes a problem, and all the stored information in the RAM 1b may be written back to the EEPROM 2 unconditionally. The above address management on the control program side becomes unnecessary, and the writing memory control can be simplified. However, when the sudden power interruption occurs, it is not possible to deal with it, and there is a possibility that information may be lost. is there.

  Various electronic control devices that use a non-volatile memory such as EEPROM 2 to prevent information loss when the power is turned off have the above-mentioned various problems.

  The present invention has been made in consideration of the above-mentioned points, and in this type of electronic control device, when an abnormality in the RAM occurs, the RAM can be retained without erroneously initializing the nonvolatile memory. When information is restored and information storage is requested, the memory information in the non-volatile memory is rewritten and updated by simple memory control so that the information is not lost even when sudden power interruption occurs. In this case, it is also an object to extend the life of the nonvolatile memory by reducing the number of times of writing information in the nonvolatile memory as much as possible.

  In order to achieve the above-described object, the electronic control device of the present invention has a capacity of the non-volatile memory in which storage information read from the non-volatile memory is written and set in a RAM as a main storage device. Bank monitoring means for providing main and sub-bank areas, repeatedly comparing the holding information of both banks, and monitoring and detecting the matching and mismatching of the holding information of both banks, and a request for storing information in the nonvolatile memory The bank monitoring is performed when the holding information of the primary bank is rewritten to the information to be stored in the nonvolatile memory and the holding information of the sub bank is rewritten to the bit inversion information of the holding information of the primary bank. The information storage request is recognized by detecting a bit inversion state mismatch of the means, and based on the recognition, the retained information of the primary bank is written to the nonvolatile memory. Information storage processing means for updating the storage information of the nonvolatile memory, and after the update, reading the storage information of the nonvolatile memory and rewriting the retained information of each of the banks to the latest storage information of the nonvolatile memory; When the bank monitoring means detects a mismatch other than the bit inversion state and recognizes a bank abnormality based on the detection, the storage information of the nonvolatile memory is read and written to each of the two banks. Bank information correcting means for resetting the stored information to the storage information of the non-volatile memory and correcting the stored information is provided (claim 1).

  Further, the electronic control unit of the present invention causes the information storage processing unit to detect the mismatch of the bit inversion state of the bank monitoring unit and to detect the mismatch between the stored information in the positive bank and the stored information in the nonvolatile memory. Storage update restriction means for permitting writing of the stored information to the nonvolatile memory is provided (claim 2), and the rewritable nonvolatile memory is also an EEPROM (claim). 3).

  Next, according to the memory control method of the electronic control device of the present invention, the main of the capacity of the nonvolatile memory in which the storage information read from the nonvolatile memory is written and set in the RAM as the main storage device, A sub-bank area is provided, and the holding information of both banks is monitored and detected by repeatedly comparing the holding information of both banks, and a request for storing information in the nonvolatile memory is generated, When the holding information of the primary bank is rewritten to the information to be stored in the nonvolatile memory and the holding information of the sub bank is rewritten to the bit inversion information of the holding information of the primary bank, the bits of the holding information of both banks Recognizing the information storage request by detecting the inconsistency of the inversion state, and based on the recognition, writing the retained information of the primary bank into the nonvolatile memory Update the storage information of the memory, and after the update, read the storage information of the nonvolatile memory, rewrite the holding information of each of the banks to the latest storage information of the nonvolatile memory, and the bits of the holding information of the both banks When a mismatch other than the inversion state is detected and a bank abnormality is recognized based on the detection, the storage information of the nonvolatile memory is read and written to each of the banks, and the retention information of the banks is stored in the nonvolatile memory The stored information is reset and corrected. (Claim 4)

  Also, the memory control method of the electronic control device of the present invention is based on the condition that the holding information of the primary bank and the holding information of the nonvolatile memory are mismatched by detecting the mismatch of the bit inversion state of the holding information of the primary and secondary banks. The storage information of the primary bank is permitted to be written into the nonvolatile memory (Claim 5), and the rewritable nonvolatile memory is an EEPROM (Claim 6).

  According to the first and fourth aspects of the present invention, the main and sub banks provided in the RAM as the main storage device have the same capacity of the nonvolatile memory, and the storage information read from the nonvolatile memory respectively. Is written and set, and when a request to store information in the non-volatile memory occurs, the retained information in the primary bank is rewritten to the information to be stored in the non-volatile memory, and the retained information in the secondary bank is bit-inverted from the retained information in the primary bank Rewritten with information.

  Based on the repeated comparison of the holding information of both banks, when a request for storing information in the non-volatile memory occurs, the holding information of the secondary bank becomes the bit inversion information of the holding information of the primary bank. A mismatch in the bit inversion state of the information is detected, and the information storage request is recognized based on this detection.

  At this time, if the information in both banks does not match due to an abnormality such as information destruction in the RAM, the information in both banks does not enter the bit inversion state. The storage request is accurately and reliably recognized, and based on this recognition, the information held in the primary bank is written into the nonvolatile memory, and the storage information in the nonvolatile memory is updated.

  And since both banks have the capacity of non-volatile memory, the main bank holds information with the data structure of the non-volatile memory, and the information held in the main bank is directly written into the non-volatile memory, so that complicated memory control such as address management The information stored in the non-volatile memory is updated reliably and in a short time with simple control.

  Moreover, since the information stored in the non-volatile memory is updated when a request for information storage occurs, the latest information is always retained in the non-volatile memory even if a sudden power interruption occurs, and the information is lost. Does not occur.

  Next, if the information held in one or both banks becomes abnormal due to an abnormality on the RAM side, the information held in both banks does not match, and at this time, the mismatch does not become a mismatch in the bit inversion state. The information stored in the nonvolatile memory is detected again and written in both banks, and the information in the RAM is restored without erroneously initializing the information stored in the nonvolatile memory.

  Then, when an abnormality such as destruction occurs in the storage information itself of the nonvolatile memory, the same information is written in the primary and secondary banks, so the information in both banks coincides. In this case, the storage in the nonvolatile memory Information is not read out and written to both banks, and an abnormality such as destruction of information stored in the nonvolatile memory itself is reliably distinguished from an abnormality on the RAM side.

  Therefore, when an abnormality on the RAM side occurs, the information retained in the RAM can be restored without accidentally initializing the nonvolatile memory. When a request for storing information occurs, the memory is suddenly controlled by simple memory control. The information stored in the non-volatile memory can be rewritten and updated in such a manner that the information is not lost even when a general power interruption occurs, and in this type of electronic control device, a highly reliable memory with simple control Control can be realized.

  Next, according to the second and fifth aspects of the present invention, when a mismatch in the bit inversion state of the retained information in the primary and secondary banks is detected and a request for storing information in the nonvolatile memory occurs, the nonvolatile memory If the retention information of the primary bank to be written is the same as the storage information of the nonvolatile memory and rewriting is not required, the retention information of the primary bank is not written to the nonvolatile memory, and unnecessary storage information of the nonvolatile memory is stored. There is also an advantage that rewriting is prevented and the life of the nonvolatile memory is extended.

  Next, according to the configurations of claims 3 and 6, the electronic control device having a practical configuration in which the rewritable nonvolatile memory is an EEPROM can exhibit the various effects described above.

  Next, in order to describe the present invention in more detail, an embodiment thereof will be described in detail according to the block diagram of FIG. 1 and the flowchart for explaining the operation of FIG.

(Constitution)
FIG. 1 is a block diagram of an electronic control device for vehicle AT control, for example. This electronic control device is formed by connecting an ECU 4 and an EEPROM 5 by a bus 6.

  The ECU 4 includes a CPU 4a and a RAM 4b as a main storage device. The RAM 4b exchanges information with the EEPROM 5, and therefore, the capacity of the EEPROM 5 is set in the areas of the positive and sub banks 7m and 7s, and both banks 7m and 7s. Are fixed-capacity areas of continuous addresses in the data structure of the EEPROM 5, respectively. Further, the CPU 4a includes, for example, the following units that are formed by executing the memory control program of the flowchart of steps S1 to S6 in FIG.

(I) Bank monitoring means This means periodically repeats the comparison of the holding information of the banks 7m and 7s to monitor and detect the matching and mismatching of the holding information of both banks 7m and 7s.

(Ii) Information storage processing means In this means, a request to store information in the EEPROM 5 is generated, and the information held in the primary bank 7m is rewritten with the information stored in the EEPROM 5, so that the information held in the sub bank 7s is the information held in the primary bank 7m. When the bit inversion information is rewritten, the bank monitoring means recognizes the information storage request by detecting the mismatch of the bit inversion state, and based on this recognition, the information held in the primary bank 7m is written into the EEPROM 5 to store the information stored in the EEPROM 5. After the update, the storage information in the EEPROM 5 is read out, and the retained information in the banks 7m and 7s is rewritten with the latest storage information in the EEPROM 5.

(Iii) Bank information correcting means This means reads bank information stored in the EEPROM 5 when the bank monitoring means detects a mismatch other than the bit inversion state and recognizes a bank abnormality on the basis of this detection. And the information held in both banks 7m and 7s is reset to the storage information in the EEPROM 5 for correction.

(Iv) Storage Update Limiting Unit This unit is provided in the information storage processing unit, and when a mismatch in bit inversion of the stored information in the primary and secondary banks 7m and 7s is detected, the stored information in the primary bank 7m and the EEPROM 5 On condition that there is a discrepancy with the stored information, writing of the information held in the primary bank 7m to the EEPROM 5 is permitted.

(Operation)
The electronic control device configured as described above operates as described below.

  First, when the ignition key of the vehicle is turned on, the power source of the in-vehicle battery is supplied to the ECU 4, and the ECU 4 operates to read and execute the memory control program and the set AT control application program.

  Then, by the initial setting in step S0 of FIG. 2, the address unit data 1, 2,..., N stored in the EEPROM 5 is stored in the primary bank 7m as the address unit data 1, 2,. , N holding information d71m, d72m,..., D7nm, and data 1, 2,..., N holding information d71s, d72s, ..., d7ns are written to the same information content in the banks 7m, 7s. Initial setting.

  The stored information d51 to d5n of the EEPROM 5 is rewritable latest information such as AT control measurement data according to the daily driving characteristics of the driver, for example.

  Also, the initially stored information d71m to d7nm of the primary bank 7m is copied to a so-called work memory area or the like of the RAM 4b, is referred to by execution of AT control, and is also used for the measurement result of the AT control characteristics during operation. Rewritten based on this.

  Then, after the initial setting, the process proceeds to step S1, where the bank monitoring means periodically compares the holding information d71m to d7nm of the primary bank 7m with the holding information d71s to d7ns of the sub bank 7s at intervals of 1 to several seconds, for example. Repeat.

  Next, when an information storage request to the EEPROM 5 is generated periodically or irregularly by an AT control application program or the like, all or part of the retained information d71m to d7nm of the primary bank 7m is changed as necessary. The retained information d71m to d7nm is information to be written in the EEPROM 5.

  Further, the holding information d71s to d7ns of the sub bank 7s is rewritten to, for example, hexadecimal bit inversion information of information to be written in the EEPROM 5 of the holding information d71m to d7nm.

  When the information storage request is generated due to the rewriting of the bit inversion information, the comparison result in step S1 becomes inconsistent regardless of whether the retained information d71m to d7nm is rewritten, and the memory control program side Recognizing the occurrence of a storage request, the process proceeds from step S1 to step S2, and the stored information d51 to d5n of the EEPROM 5 is read to a temporary holding area (not shown) of the RAM 4b, and then the process proceeds to step S3. Transition.

  In step S3, the information storage processing unit determines whether the holding information d71s to d7ns of the secondary bank 7s is the bit inversion information with respect to the holding information d71m to d7nm of the primary bank 7m. At this time, because of the bit inversion based on the information storage request to the EEPROM 5, the comparison result in step S1 in FIG. 2 becomes inconsistent regardless of whether or not the retained information d71m to d7nm is rewritten. Recognizing the occurrence of the information storage request, the information storage information means operates, and the process proceeds from step S3 to step S5.

  In order to extend the life of the EEPROM 5 by minimizing the number of times the EEPROM 5 is rewritten, in this embodiment, the storage update restriction means of the information storage processing means uses the retained information d71m to d7nm of the primary bank 7m, The stored information d51 to d5n in the EEPROM 5 is compared. If the two information are different and do not match, writing of the retained information d71m to d7nm in the primary bank 7m to the EEPROM 5 is permitted.

  If the stored information d71m to d7nm of the primary bank 7m and the stored information d51 to d5n of the EEPROM 5 are the same and match, writing to the EEPROM 5 is prohibited because it is not necessary to rewrite the EEPROM 5.

  If writing of the holding information d71m to d7nm of the primary bank 7m to the EEPROM 5 is permitted, the process proceeds from step S5 to step S6, and the holding information d71m to d7nm of the primary bank 7m is written to the EEPROM 5, and the storage information of the EEPROM 5 is stored. d51 to d5n are updated to the contents of the holding information d71m to d7nm.

  At this time, since the primary bank 7m is an area in which the addresses of the same data structure as the EEPROM 5 are continuous, the information d71m to d7nm held in the primary bank 7m is sequentially read out and written to the EEPROM 5, whereby the information d71m to d7nm is read from the EEPROM5. The storage information d51 to d5n of the EEPROM 5 can be updated without managing and recognizing where (in which address) the data is to be written, and the memory control is complicated because the information write address management is unnecessary. I don't have to.

  Further, when the information storage request is generated, the stored information d51 to d5n in the EEPROM 5 is rewritten and updated without waiting until the ignition key is turned off and the power of the ECU 4 is cut off. Even if the power is cut off, the latest information immediately before that is written and stored in the EEPROM 5, and the information is not lost.

  When the storage information d51 to d5n in the EEPROM 5 is updated to the contents of the holding information d71m to d7nm, the process proceeds from step S6 to step S4, the updated storage information d51 to d5n in the EEPROM 5 is read, and the holding information d71m in the primary bank 7m is read. Retention information d71s to d7ns of .about.d7nm and sub bank 7s are rewritten to the latest storage information d51 to d5n of the updated EEPROM 5.

  As a result of this rewriting, the holding information d71m to d7nm of the primary bank 7m and the holding information d71s to d7ns of the sub bank 7s coincide with each other. Therefore, when the information storage in the EEPROM 5 is completed and the process returns from step S4 to step S1, the original information is stored. The information stored in the EEPROM 5 is not erroneously repeated based on the stored information d71m to d7nm and d71s to d7ns.

  Next, for some reason, the RAM 4b malfunctions, such as so-called data destruction or data refresh error, and the stored information d51 to d5n in the EEPROM 5 is normal, but the retained information d71m to d7nm in the primary bank 7m is If any one or both of the holding information d71s to d7ns of the bank 7s become abnormal, the holding information d71m to d7nm of the primary bank 7m and the holding information d71s to d7ns of the sub bank 7s become inconsistent, and the steps S1 to s2 Through step s3.

  At this time, the holding information d71s to d7ns of the secondary bank 7s is not in a bit-inverted state with respect to the holding information d71m to d7nm of the primary bank 7m, and the holding information d71m to d7nm and the holding information d71s to d7ns The bank monitoring means detects this mismatch and recognizes a bank abnormality.

  Further, the bank information correcting means operates by recognizing this bank abnormality, and the process proceeds from step S3 to step S4. The storage information d51 to d5n of the EEPROM 5 is read and written to both banks 7m and 7s, and the main bank 7m is held. The information d71m to d7nm and the holding information d71s to d7ns of the sub bank 7s are reset to the latest stored information d51 to d5n, corrected, and restored.

  By the way, even if abnormality such as destruction occurs in the storage information itself of the EEPROM 5 after reading and writing the storage information d51 to d5n of the EEPROM 5 in the primary and secondary banks 7m and 7s, the EEPROM 5 is abnormal in the primary and secondary banks 7m and 7s. Since the same information before the occurrence of the error is written, the information in both banks 7m and 7s coincides and the storage information in the EEPROM 5 is not read and written in both banks 7m and 7s.

  Then, abnormalities such as destruction of the stored information itself of the EEPROM 5 are reliably distinguished from abnormalities on the RAM side, and when the abnormalities on the RAM side occur, the stored information d51 to d5n of the EEPROM 5 is not erroneously initialized. .

  Note that the information management program of FIG. 2 operates and the exchange of information between the RAM 4b and the EEPROM 5 is controlled until the ignition key is turned off, the power supply of the ECU 4 is shut off, and the power supply is stopped.

  Therefore, when an abnormality in the RAM occurs, the information held in the RAM 4b can be restored without erroneously initializing the EEPROM 5, and when a request for storing information in the EEPROM 5 occurs, the memory is suddenly controlled by simple memory control. The information stored in the EEPROM 5 can be rewritten and updated in such a manner that the information is not lost even when a general power interruption occurs. In this type of electronic control device, highly reliable memory control can be performed with simple control. Can be realized.

  In this case, since the memory control program is executed independently of other processing programs and operates, there is an advantage that the program is highly independent, its operation can be easily confirmed, and maintainability is improved. is there.

  By the way, step S0 of FIG. 2 may be omitted, and when step S0 is omitted, when the ignition key of the vehicle is turned on and the power source of the in-vehicle battery is supplied to ECU 4 to operate ECU 4, the step of FIG. The bank monitoring means of S1 compares the holding information d71m to d7nm of the primary bank 7m with the holding information d71s to d7ns of the secondary bank 7s, and information is not read into both banks 7m and 7s immediately after the start of power feeding. Since the holding information of both banks 7m and 7s becomes inconsistent, the storage information d51 to d5n of the EEPROM 5 held during power-off is transferred from the step S1 to the step S2, and the temporary holding area (not shown) of the RAM 4b is read. After that, the process proceeds from step S2 to step S3, and the information storage processing means performs the holding information d7 of the primary bank 7m. Holding information d71s~d7ns sub bank 7s it is determined whether or not it is information of the bit inverted with respect to M～d7nm.

  When the power supply is started, there is almost no bit inversion information, and the bank information correcting means operates by detecting a mismatch other than the bit inversion state to recognize a RAM side abnormality, that is, a bank abnormality. The process proceeds to S4, and the storage information d51 to d5n of the EEPROM 5 read in step S2 is written as the holding information d71m to d7nm and d71s to d7ns in the banks 7m and 7s, so that the banks 7m and 7s are initialized to the same information contents. Is done.

  The present invention is not limited to the above-described embodiment, and various modifications other than those described above can be made without departing from the spirit of the present invention, and the nonvolatile memory can be rewritten other than the EEPROM. Of course, it may be a memory.

  Further, depending on the usage of the apparatus, the storage update limiting means may be omitted, and the stored information in the EEPROM may be updated without performing the determination in step S5 of FIG.

  In addition, the present invention provides various electronic control devices having a computer configuration in which information is not lost when the power of the computer is cut off by a nonvolatile memory in which information held in the RAM is written based on a request for information storage, and the like It can be applied to a memory control method.

It is a block diagram of one embodiment. It is a flowchart for operation | movement description of FIG. It is a block diagram of a prior art example.

Explanation of symbols

4 ECU
4a CPU
4b RAM
5 EEPROM
7m primary bank 7s secondary bank

Claims (6)

Computer-controlled electronic control device that reads and processes storage information in a rewritable nonvolatile memory into a random access memory as a main storage device, and writes information held in the random access memory into the nonvolatile memory in response to a request for information storage In
The random access memory is provided with areas of main and sub banks of the capacity of the nonvolatile memory in which storage information read from the nonvolatile memory is written and set.
Bank monitoring means for repeatedly comparing the holding information of both banks and monitoring and detecting the matching and mismatching of the holding information of both banks;
When a request to store information in the nonvolatile memory occurs, the retained information in the primary bank is rewritten to information to be stored in the nonvolatile memory, and the retained information in the sub bank becomes the bit inversion information of the retained information in the primary bank. When rewritten, the bank monitoring means recognizes the information storage request by detecting a bit inversion state mismatch, and based on the recognition, writes the information held in the primary bank into the nonvolatile memory Information storage processing means for reading the storage information of the nonvolatile memory after the update, and rewriting the retained information of each of the banks to the latest storage information of the nonvolatile memory after the update,
When the bank monitoring means detects a mismatch other than the bit inversion state and recognizes a bank abnormality based on the detection, the storage information of the nonvolatile memory is read and written to each of the banks, and the both banks are held. An electronic control device comprising: bank information correcting means for resetting and correcting information stored in the nonvolatile memory.   When the information storage processing means detects a mismatch of the bit inversion state of the bank monitoring means, the information stored in the primary bank is stored in the nonvolatile memory on the condition that the information held in the primary bank does not match the information stored in the nonvolatile memory. 2. An electronic control unit according to claim 1, further comprising storage update limiting means for permitting the writing of.   The electronic control device according to claim 1, wherein the rewritable nonvolatile memory is an EEPROM (Electrically, Erasable, Programmable, Read-Only Memory). An electronic control device having a computer configuration in which information stored in a rewritable nonvolatile memory is read and processed in a random access memory as a main storage device, and information held in the random access memory is written in the nonvolatile memory in response to a request for information storage In the memory control method of
The random access memory is provided with areas of main and sub banks of the capacity of the nonvolatile memory in which storage information read from the nonvolatile memory is written and set.
By repeatedly comparing the holding information of both banks, it is possible to monitor and detect the matching and mismatching of the holding information of both banks,
When a request to store information in the nonvolatile memory occurs, the retained information in the primary bank is rewritten to information to be stored in the nonvolatile memory, and the retained information in the sub bank becomes the bit inversion information of the retained information in the primary bank. When the information is rewritten, the information storage request is recognized by detecting the mismatch of the bit inversion states of the information held in both banks, and based on the recognition, the information held in the primary bank is written into the nonvolatile memory and the nonvolatile memory is written. Update the storage information of the non-volatile memory, and after the update, read the storage information of the non-volatile memory and rewrite the holding information of each of the banks to the latest storage information of the non-volatile memory,
When a mismatch other than the bit inversion state of the holding information of both banks is detected and a bank abnormality is recognized based on the detection, the storage information of the nonvolatile memory is read and written to each of the banks. A memory control method for an electronic control device, wherein the stored information is reset to the storage information of the non-volatile memory for correction.   By detecting the mismatch of the bit inversion state of the holding information of the primary and secondary banks, writing the holding information of the primary bank to the nonvolatile memory on condition that the holding information of the primary bank and the holding information of the nonvolatile memory are inconsistent. 5. The memory control method for an electronic control device according to claim 4, wherein the memory control method is permitted.   6. The electronic control device according to claim 4, wherein the rewritable nonvolatile memory is EEPROM (Electrically, Erasable, Programmable, Read-Only, Memory). Memory control method.

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