JP2005275473A - Memory control adapter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a memory control adapter that can suppress an increase in access latency. <P>SOLUTION: At the start of uploading direct memory access, a CPU sets a read pointer register for designing from which location of a buffer memory 14 data should be taken. The read pointer register, which is set in a register group 16 via an I/F conversion/analysis part 22 from a PCI bus, is stored also in a buffer control part 24 by the I/F conversion/analysis part 22. According to the read pointer register, data are read ahead from the buffer memory 14 to a read buffer 26. As the CPU later sets a control register in the register group, the read buffer 26 passes the data to an interface controller 12. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a memory control adapter, and in particular, an interface having an interface function for a central processing unit such as a CPU (Central Processing Unit), an external device connected to the CPU, and an external storage device such as a memory buffer. The present invention relates to a memory control adapter connected between a controller and a CPU and connected to an external storage device.

  In general, data writing to and reading from a memory such as a DRAM is performed by an interface controller such as a DRAM controller, as described in Non-Patent Document 1.

  In many cases, the interface controller is directly connected to the bus of the CPU that controls the interface controller. As an example, FIG. 6 shows an example of a system using MC68030.

  An interface controller (IFC) 42 in FIG. 6 is an interface controller of the external device 40 having a function such as direct memory access (DMA). The interface controller 42 includes a buffer memory (for example, SRAM: Static Random Access Memory or DRAM: Dynamic Random Access Memory etc.) 14 is connected and used for the primary storage of the data that has undergone direct memory access.

  The CPU interface of the interface controller 42 conforms to the MC68030 CPU bus protocol and is directly controlled by the MC68030 bus.

  The CPU 44 controls whether to store data at an address in the buffer memory by register setting in the interface controller 42 and controls direct memory access. Data stored in the buffer memory is read and written via the CPU interface of the interface controller 42.

  In recent years, with the increase in CPU bus speed, the number of systems that can directly connect target devices to the CPU bus has decreased, and a PCI bus interface via a host PCI bridge (Host-PCI Bridge) 46 as shown in FIG. In general, systems for connecting target devices have become common. FIG. 7 shows an example in which an MPC 750 is used as the CPU 44 in a system for connecting a target device with a PCI interface via a host PCI bridge.

  In this case, a PCI adapter (PCIADP) 48 is connected between the interface controller 42 and the PCI bus to perform interface conversion. However, such a configuration requires a large number of parts and is disadvantageous in terms of mounting and cost. Therefore, the buffer memory 14 is moved toward the PCI adapter 48 so that the PCI adapter 48 can absorb the interface controller 42 in the end. There is a case to connect.

  Further, by connecting the buffer memory 14 to the PCI adapter 48, it is possible to directly access the buffer memory from the PIC bus via the PCI adapter 48 without passing through the interface controller 42. Access can be speeded up.

In particular, hardware that requires immediate design, such as the PCI adapter 48, is almost always designed with an FPGA (Field Programmable Gate Array). Typically, 42 functions are designed to be integrated into the PCI adapter 48.
Atsushi Oshima “New Computer Disassembly New Book”, 1st Edition, Softbank Publishing Co., Ltd., July 20, 2000, p52-53

  By the way, when the buffer memory 14 is connected to the PCI adapter 48, the simplest configuration for accessing the buffer memory from the CPU is to use the address and data from the interface controller 42 as shown in FIG. It will be shaped to pass through. However, there is a problem that the delay of the signal increases due to the bus buffer sandwiched between them, leading to an increase in read and write access latency.

  In addition to simply passing through, it is possible to adopt a configuration in which the address and data are received and relayed by a flip-flop inside the PCI adapter 48. Although an increase in access latency can be suppressed, there is a problem that an increase in read access latency cannot be suppressed.

  As described above, when the PCI adapter is sandwiched between the interface controller and the buffer memory, generally, the read access latency from the interface controller to the buffer memory increases. Alternatively, when the interface controller has a specification in which the access speed to the buffer memory cannot be adjusted, the increase in the read access latency is fatal.

  The present invention has been made to solve the above problem, and an object thereof is to provide a memory control adapter capable of suppressing an increase in access latency.

  In order to achieve the above object, an invention according to claim 1 includes an interface controller having an interface function for each of a central processing unit that performs various data processing, an external device connected externally, and an external storage device that stores data. A memory control adapter connected between the central processing units and connected to the external storage device; a read buffer for temporarily storing data read from the external storage device; and a read buffer from the external storage device to the read buffer A buffer control unit that controls data storage and reading; and a control unit that controls information transmitted from the central processing unit to the interface, and the control unit transmits the data to the interface controller from the central processing unit. Stored in the external storage device Read information representing an address to be read out from the external storage device based on the read information, and the central processing is performed after the read information is transmitted. Data is transferred from the read buffer to the interface controller on the basis of control information sent from the apparatus via the interface controller and indicating the start of data reading from the external storage device.

  According to the first aspect of the present invention, the memory control adapter includes: a read buffer that temporarily stores data read from an external storage device such as a memory buffer; and a buffer control unit that controls data storage and reading to the read buffer; Control means for controlling information sent from the central processing unit such as a CPU to the interface controller.

  Then, read information such as a read pointer register set in the interface controller from the central processing unit is acquired by the control means.

  Further, the buffer control unit controls the read target data from the buffer memory to the read buffer based on the acquired read information.

  The data stored in the read buffer is transferred to the interface controller based on control information such as a control register set by the CPU after the read information is sent to the interface controller.

  That is, since the data to be transferred is stored in advance in the read buffer, data transfer can be performed as if the external storage device is directly connected to the interface controller. Therefore, an increase in access latency when reading data from the external storage device can be suppressed.

  For example, as in the invention described in claim 2, when transferring data stored in the external storage device to the external device, the control means obtains the read information, and the buffer control means obtains the read information based on the read information. Then, the read buffer may be controlled so that the data is prefetched, and the data may be transferred from the read buffer to the external device via the interface controller based on the control information. When the central processing unit reads the data stored in the external storage device, the control unit acquires the read information, and the buffer control unit controls the read buffer to pre-read data based on the read information, Data is transferred from the read buffer to the central processing unit via the interface controller based on the control information. It may be.

  When the central processing unit reads out the data stored in the external storage device, the control means acquires the read information and the control information, and the buffer control means Data stored in the external storage device may be read based on the read information and directly transferred to the central processing unit based on the control information. That is, data transfer may be performed without an interface controller, and this can also suppress an increase in access latency when reading data from the external storage device.

  The control means delays sending the control information to the interface controller until the data storage in the read buffer is completed, as in the invention described in claim 5. Synchronization with the start of reading data stored in the read buffer can be achieved, and problems caused by differences in access speeds can be solved.

  The memory control adapter, as in the sixth aspect of the present invention, includes a write buffer for temporarily storing data to be stored in the external storage device, and data to be transferred to the write buffer when data is read from the external storage device. Is further provided with a determination unit that determines whether or not the data to be transferred is stored in the write buffer, and the buffer control unit stores the transfer stored in the write buffer when the determination unit determines that the data to be transferred is stored in the write buffer. You may make it control so that target data may be written in a read buffer. As a result, data can be read from the external storage device immediately even when data is read, such as uploading, with data still remaining in the write buffer, such as immediately after downloading, thereby suppressing an increase in access latency. Can do.

  As described above, according to the present invention, an increase in access latency can be suppressed by providing a read buffer in the memory control adapter and performing control so as to perform prefetching.

  Hereinafter, an example of an embodiment of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a block diagram showing a configuration of a PCI adapter and an interface controller as a memory control adapter according to an embodiment of the present invention.

  The PCI adapter (PCIADP) 10 and the interface controller (IFC) 12 are connected to the PCI bus via the host PCI bridge 46 connected to the CPU 44 as shown in FIG. Note that a ROM 43 and a RAM 45 are also connected to the host PCI bridge 46.

  The interface controller 12 functions as an interface controller of an external device 40 having a direct memory access function or the like connected to a subsequent stage, and the PCI adapter 10 is connected between the interface controller 12 and the PCI bus via a CPU bus. A memory buffer 14 is connected to the adapter 10.

  The interface controller 12 has a register group 16 for the CPU 44. The register group 16 specifies, for example, a write pointer register that specifies where data is stored in the buffer memory 14 during direct memory access in the download direction, and specifies from where the data is read out in the buffer memory 14. A read point register, a command register for specifying the start and transfer direction of direct memory access, and the like are set.

  The interface controller 12 also includes an I / F control unit 18 and a direct memory access (DMA) control unit 20, and the I / F control unit 18 requests a direct memory access from an external device 40 connected at a subsequent stage. On the other hand, the direct memory access to the memory buffer 14 connected to the PCI adapter 10 is controlled by controlling the DMA control unit 20.

  The interface controller 12 functions like a memory or a FiFo (First in First out) port when accessing the buffer memory 14 from the CPU bus.

  The PCI adapter 10 includes an interface (I / F) conversion / analysis unit 22, a buffer control unit 24, a read buffer 26, and a write buffer 28.

  The I / F converter / analyzer 22 sets the read pointer register that specifies the read address of the buffer memory 14 and the write point that specifies the write address of the buffer memory 14 set from the CPU 44 to the register group 16 of the interface controller 12. The register setting, the setting of a control register indicating the start of reading from and writing to the buffer memory 14, and the like are performed, and the control of the buffer control unit 24 is performed.

  The buffer control unit 24 writes data into or reads data from the buffer memory 14 in response to an access request to the buffer memory 14 from the CPU 44 or the DMA control unit 20. At this time, the buffer control unit 24 uses the read buffer 26 and the write buffer 28 to write data to and read data from the buffer memory 14.

  The read buffer 26 temporarily stores data corresponding to the value of the read pointer register when reading data from the buffer memory 14, and the write buffer 28 stores data in the write pointer register when writing data to the buffer memory 14. Temporarily stores the data to be written to the value. It is assumed that the read buffer 26 prefetches data as needed whenever there is a free space.

  For example, the read buffer 24 pre-reads and stores the data of the read point register value under the control of the buffer control unit 24, and when a read request is made from the DMA control unit 20 of the interface controller 12 to the buffer memory 14, that is, When the control register is set in the register group 16 from the CPU 44, the data stored in the read buffer 14 is output.

  The write buffer 28 also has a comparator function, and the address data read by the read buffer 26 is still stored in the write buffer 28 when uploading is performed immediately after downloading to the buffer memory 14. It is determined whether or not the state is not. The comparator function of the write buffer 28 may be provided on the read buffer 26 side or may be provided in the buffer control unit 24.

  Next, operations of the PCI adapter and interface controller configured as described above will be described.

  FIG. 2 is a flowchart illustrating an example of the flow of operations of the PCI adapter 10 and the interface controller 12.

  In step 100, it is determined whether or not the CPU 44 has accessed the memory buffer 14 by the I / F conversion / analysis unit 22. The determination is made by the I / F conversion / analysis unit 22 determining whether or not the CPU 44 has instructed reading of data from the buffer memory 14 via the PCI bus. Move on to step 102.

  In step 102, it is determined whether upload is instructed. This determination is based on whether the CPU 44 has instructed the upload of data stored in the C buffer memory 14 by the I / F conversion / analysis unit 22 or the CPU 44 has instructed download to store data in the buffer memory 14. The determination is made when the upload is instructed, and the determination is affirmed, and when the download is instructed, the determination is denied. If the determination is affirmative, the routine proceeds to step 104.

  In step 104, the read pointer register setting set from the CPU 44 to the register group 16 of the interface controller 12 is also stored in the buffer control unit 24 by the I / F conversion / analysis unit 22, and the process proceeds to step 106.

  In step 106, data corresponding to the address set in the read pointer register is prefetched by the buffer control unit 24 and stored in the read buffer 26.

  Next, in step 108, it is determined whether or not the upload is immediately after downloading. If the determination is negative, the process proceeds to step 110.

  In step 110, it is determined by the I / F conversion / analysis unit 22 whether or not the control register is set in the register group 16 from the CPU 44, and the process waits until the determination is affirmed and the process proceeds to step 112.

  In step 112, the setting of the control register in the register group 16 set by the CPU 44 is waited (delayed) by the I / F conversion / analysis unit 22, and the process proceeds to step 114 where the completion of storage in the read buffer 26 is buffered. When the storage of data in the read buffer 26 is completed as monitored by the control unit 24, the determination in step 114 is affirmed, and the process proceeds to step 116.

  In step 116, the control register is set in the register group 16 by the I / F conversion / analysis unit 22, and the process proceeds to step 118.

  In step 118, the control register setting is set in the register group 16 of the interface controller 12, whereby the reading of data from the read buffer 26 is started, and the prefetched data stored in the read buffer 26 is transferred to the DMA control unit 20. Is uploaded to the external device 40 connected to the subsequent stage of the interface controller 12.

  That is, when direct memory access in the upload direction is started, the CPU 44 sets a read pointer register for designating from which position in the buffer memory 14 data is to be extracted. At this time, the setting of the read pointer register is written to the register group 16 of the interface controller 12 from the PCI bus via the I / F conversion / analysis unit 22, and this value is set by the I / F conversion / analysis unit 22. The data is also stored in the buffer control unit 24 of the adapter 10, and the buffer control unit 24 prefetches data from the buffer memory 14 based on the value written to the read pointer register and stores the data in the read buffer 26.

  Thereafter, when the CPU 44 sets a control register that activates the direct memory access, the direct memory access is activated and the data in the buffer memory specified by the read pointer register is read from the PCI adapter 10 under the control of the DMA control unit 20. At this time, however, since the designated value is already stored in the read buffer 26, the PCI adapter 10 can immediately pass the data to the interface controller 12. Therefore, the delay caused by sandwiching the PCI adapter 10 between the interface controller 12 and the buffer memory 14 can be eliminated.

  When the interface controller 12 receives data from the read buffer 26, the direct memory access is started by setting the control register from the CPU 44, and the DMA control unit 20 receives data from the read buffer 26 and performs I / F control. Data is uploaded to the external device 40 at the subsequent stage via the unit 18. At this time, the PCI adapter 10 stores the control register to the register group 16 of the interface controller 12 until the data is completely stored in the read buffer 26. Since the setting is delayed, the completion of data storage in the read buffer 26 and the data reception of the interface controller 12 can be synchronized, and the problem caused by the difference in access speed can be solved.

  On the other hand, if the determination in step 102 is negative, that is, if download is instructed by the CPU 44, the process proceeds to step 120, and the write pointer register set in the register group 16 by the CPU 44 is transferred from the DMA control unit 20 to the buffer control unit. 24, the process proceeds to step 122, and the downloaded data is stored in the write buffer 28 via the DMA control unit 20.

  In step 124, the process waits for whether or not data storage in the write buffer 28 is completed, and then the process proceeds to step 126, where a download end notification is sent to the DMA control unit 20 to end the download. Then, the process proceeds to step 128, and the data stored in the write buffer 28 is sequentially stored at the address of the buffer memory 14 corresponding to the write pointer register received by the buffer control unit 24.

  If the determination in step 104 is affirmative, that is, if uploading immediately after downloading is instructed by the CPU 44, the process proceeds to step 130, where it is determined whether there is data downloaded to the write buffer 28. . This determination is made by comparing the head address pointer and the tail address pointer stored in the read buffer 26 by the comparator function of the write buffer 28 to determine whether the data read to the read buffer 26 is still stored in the write buffer 28. It is done by judging. That is, it is determined whether or not the write buffer 28 has data within the range of the start address pointer and the end address pointer to be read to the read buffer 26. If the determination is negative, the process proceeds to step 110 described above. The above processing is performed.

  If the determination in step 130 is affirmative, that is, if the data to be downloaded is still stored in the write buffer 28, the process proceeds to step 132 and the sub-upload process is performed in order to maintain the coherency of the data in the buffer memory 14. Is done.

  Here, the sub-upload process performed to instruct the coherency of the data in the buffer memory 14 will be described in detail. FIG. 3 is a flowchart illustrating an example of the flow of sub-upload processing.

  In step 200, the buffer controller 24 controls the data corresponding to the read pointer register so that the data is overwritten from the write buffer 28 to the read buffer 26.

  Subsequently, in step 202, it is determined by the I / F conversion / analysis unit 22 whether or not the control register is set in the register group 16 from the CPU 44, and the process waits until the determination is affirmed, and the process proceeds to step 204.

  In step 204, the setting of the control register in the register group 16 set by the CPU 44 is waited by the I / F conversion / analysis unit 22, and the process proceeds to step 206, where the storage in the read buffer 26 is completed by the buffer control unit 24. When the storage of data in the read buffer 26 is completed, the determination at step 206 is affirmed and the routine proceeds to step 208.

  In step 208, the control register is set in the register group 16 by the I / F conversion / analysis unit 22, and the process proceeds to step 210.

  In step 210, the control register setting is set in the register group 16 of the interface controller 12, whereby reading of data from the read buffer 26 is started, and the pre-read data stored in the read buffer 26 is transferred to the DMA control unit 20. Is uploaded to the external device 40 connected to the subsequent stage of the interface controller 12.

  That is, when upload is instructed immediately after downloading, if the data to be uploaded still remains in the write buffer 28, the data in the write buffer 28 is overwritten in the read buffer 26. Even if data corresponding to the upload is still stored in the write buffer 28, the upload can be performed immediately, the increase in read access latency can be eliminated, and the coherency of the data in the buffer memory 14 can be maintained. it can.

  Returning to the flowchart of FIG.

  When the determination in step 100 is affirmative, that is, when the CPU 44 accesses the memory buffer 14 (when the data stored in the memory buffer 14 is read from the CPU 44), the process proceeds to step 134. CPU access processing is performed.

  Here, the CPU access process will be described in detail. FIG. 4 is a flowchart illustrating an example of the flow of CPU access processing.

  In step 300, the read pointer register from the CPU 44 is set in the buffer control unit 24 by the I / F conversion / analysis unit 22.

  In step 302, data corresponding to the read pointer register set in the buffer control unit 24 is read by the buffer control unit 24 and output to the CPU 44 via the I / F conversion / analysis unit 22.

  That is, the CPU 44 can access the buffer memory 14 without going through the interface controller 12, and processing can be performed at high speed.

  FIG. 5 is a flowchart illustrating an example of a modification of the CPU access process. In FIG. 4, the buffer memory 14 is directly accessed from the PCI adapter 10 without using the interface controller 12. However, in a modified example, the buffer memory 14 is accessed from the CPU 44 through the interface controller 12.

  In step 350, a read pointer register is set in the register group 16 from the CPU 44 via the I / F conversion / analysis unit 22, and the process proceeds to step 352.

  In step 352, the read pointer register setting set from the CPU 44 to the register group 16 of the interface controller 12 is also stored in the buffer control unit 24 by the I / F conversion / analysis unit 22, and the process proceeds to step 354.

  In step 354, data corresponding to the read pointer register setting address is prefetched by the buffer control unit 24 and stored in the read buffer 26.

  Next, in step 356, the I / F conversion / analysis unit 22 determines whether or not the control register is set in the register group 16 from the CPU 44, and waits until the determination is affirmed, and the process proceeds to step 358.

  In step 358, the setting of the control register in the register group 16 set by the CPU 44 is waited (delayed) by the I / F conversion / analysis unit 22, and the process proceeds to step 360 where the storage in the read buffer 26 is completed. When the storage of the data in the read buffer 26 is completed as monitored by the control unit 24, the determination in step 360 is affirmed and the process proceeds to step 362.

  In step 362, the control register is set in the register group 16 by the I / F conversion / analysis unit 22, and the process proceeds to step 364.

  In step 364, the control register setting is set in the register group 16 of the interface controller 12, whereby the reading of data from the read buffer 26 is started, and the pre-read data stored in the read buffer 26 is DMA-controlled. The data is sent to the CPU 44 under the control of the unit 24.

  That is, as in the case of uploading to the external device 40 connected to the subsequent stage of the interface controller 12 described above (steps 104 to 118), the access from the CPU 44 can also be processed, thereby increasing the read access latency. Can be resolved.

  As described above, according to the present embodiment, the PCI adapter 10 is provided with the read buffer 26 to control the buffer so as to pre-read data, and to read the data when the data is stored in the read buffer 26. By designing the PCI adapter 10 to be connected to the general-purpose bus (PCI bus), the memory access latency increases when the buffer memory 14 connected to the interface controller 12 is connected to the PCI adapter 10 side. And the problem of access speed limitation can be solved.

It is a block diagram which shows the structure of the PCI adapter and interface controller as a memory control adapter concerning embodiment of this invention. It is a flowchart which shows an example of the operation | movement flow of a PCI adapter and an interface controller. It is a flowchart which shows an example of the flow of a sub upload process. It is a flowchart which shows an example of CPU access processing. It is a flowchart which shows an example of the modification of CPU access processing. It is a figure which shows the prior art example in which the interface controller was directly connected to the bus | bath of CPU. An example in which an MPC 750 is used as a CPU in a system in which a target device is connected via a PCI interface via a host PCI bridge is shown. It is a figure which shows the simplest conventional structure at the time of connecting a buffer memory to a PCI adapter.

Explanation of symbols

10 PCI adapter 12 interface controller 14 buffer memory 22 I / F conversion / analysis unit 24 buffer control unit 26 read buffer 28 write buffer

Claims (6)

Connected between the central processing unit and an interface controller having an interface function for a central processing unit that performs various data processing, an externally connected external device, and an external storage device that stores data, and the external storage device is connected Memory control adapter,
A read buffer for temporarily storing data read from the external storage device;
A buffer control unit for controlling data storage and reading from the external storage device to the read buffer;
Control means for controlling information sent from the central processing unit to the interface;
With
The control means obtains read information representing an address to be read from the data stored in the external storage device, which is sent from the central processing unit to the interface controller;
The buffer control means controls to pre-read data from the external storage device to the read buffer based on the read information, and is sent from the central processing unit via the interface controller after the read information is sent. A memory control adapter for transferring data from the read buffer to the interface controller based on control information indicating the start of data reading from the external storage device.   When the data stored in the external storage device is transferred to the external device, the control means acquires the read information, and the buffer control means prefetches the data to the read buffer based on the read information. 2. The memory control adapter according to claim 1, wherein the data is transferred from the read buffer to an external device via the interface controller based on the control information.   When the central processing unit reads data stored in the external storage device, the control unit acquires the read information, and the buffer control unit prefetches data into the read buffer based on the read information. 3. The memory control adapter according to claim 1, wherein the memory control adapter performs control to transfer data from the read buffer to the central processing unit via the interface controller based on the control information.   When the central processing unit reads the data stored in the external storage device, the control unit acquires the read information and the control information, and the buffer control unit acquires the external storage device based on the read information. 3. The memory control adapter according to claim 1, wherein the data stored in the memory controller is read out and directly transferred to the central processing unit based on the control information.   4. The control unit according to claim 1, wherein the control unit delays transmission of the control information to the interface controller until data storage in the read buffer is completed. 5. Memory control adapter.   A write buffer that temporarily stores data to be stored in the external storage device; and a determination unit that determines whether data to be transferred is stored in the write buffer when data is read from the external storage device, The control unit controls the buffer control unit to write the data stored in the write buffer to the read buffer when the determination unit determines that the data to be transferred is stored. The memory control adapter according to any one of claims 1 to 5.

Images