WO2016070431A1

WO2016070431A1 - Memory access method and apparatus, and computer device

Info

Publication number: WO2016070431A1
Application number: PCT/CN2014/090649
Authority: WO
Inventors: 张广飞; 崔晓松; 陈云
Original assignee: 华为技术有限公司
Priority date: 2014-11-07
Filing date: 2014-11-07
Publication date: 2016-05-12
Also published as: CN105900060B; CN105900060A

Abstract

Embodiments of the present invention provide a memory access method and apparatus, and a computer device. The method comprises: a buffer device receives N read commands from a processor, wherein N is an integer greater than or equal to 2, each read command comprises addresses of to-be-read characters, the addresses of the to-be-read characters comprise an address of a memory row to which the to-be-read characters belong and addresses of the to-be-read characters in the memory row, and the read command is used for reading the to-be-read characters; when N to-be-read characters are not temporarily stored in the buffer device, the buffer device forwards the N read commands to a memory controller; the buffer device receives the N to-be-read characters sent by the memory controller, and sends the N to-be-read characters to the processor; and the buffer device receives other characters except the N to-be-read characters in the memory row to which the N to-be-read characters sent by the memory controller belong. In a process in which the buffer device acquires the N to-be-read characters, the buffer device does not need to acquire other characters in the memory row in which the N to-be-read characters are located, the time delay of reading the N to-be-read characters is not increased, and accordingly, the time delay of reading the characters to be read is decreased.

Description

Memory access method, device and computer device

Technical field

The embodiments of the present invention relate to the field of computer technologies, and in particular, to a memory access method, apparatus, and computer device.

Background technique

The data that the processor needs to use is generally stored in the memory. The processor needs to obtain data from the memory and store it in the cache for use. The data acquired by the processor is obtained in units of words (English: word). In the prior art, when the processor needs to acquire a certain data, a read instruction for the data is sent to the cache, and the read instruction is used to acquire a word required by the processor, that is, a keyword; if the data is found, The data is returned to the processor; if the data is not found in the cache, the read instruction is forwarded to the memory by the cache, and the memory returns the memory line to which the keyword belongs to the cache according to the read instruction, so as to A cache line is formed in the cache (English: cacheline). Wherein, a memory line can include 8 words, for example, 8 words including 0, 1, 2, 3, 4, 5, 6, and 7. When the read command is used to read the 6th word, the memory will be the whole. The memory lines are returned to the cache in the order of the sixth, seventh, first, second, third, fourth, and fifth words, that is, the keywords required for the read instruction are preferentially returned inside the memory line, and the words other than the keywords in the cache line are deleted. It is called a prefetch word; then the cache returns the keyword to the processor.

However, if the processor simultaneously sends multiple read instructions to the memory through the cache, the memory needs to return all the words in one memory line corresponding to one read instruction to the cache, and the memory can return another cache to the cache according to another read instruction. The word in the memory line, at which point the cache can return the keyword indicated by the other read instruction to the processor, thereby increasing the read latency of other keywords.

Summary of the invention

Embodiments of the present invention provide a memory access method, apparatus, and computer apparatus for reducing a read delay of a word required by a processor.

In a first aspect, an embodiment of the present invention provides a memory access method, including:

The cache device receives N read commands sent by the processor, where N is an integer greater than or equal to 2, Each of the read commands includes an address of a word to be read, the address of the word to be read includes an address of a memory line to which the word to be read belongs, and an address of the word to be read in the memory line, the read command For reading the word to be read;

When the N words to be read are not cached in the cache device, the cache device forwards the N read commands to the memory controller;

The cache device receives the N to-be-sent words sent by the memory controller, and sends the N to-be-read words to the processor;

The cache device receives other words in the memory row to which the N words to be read are sent by the memory controller, except the N to-be-read words.

In a first possible implementation manner of the first aspect, the receiving, by the cache device, the first word sent by the memory controller includes:

Receiving, by the cache device, a priority of the first word and the first word sent by the memory controller;

The method further includes:

The cache device caches the first word according to a priority of the first word from high to low;

The first word is a word other than the N to-be-read words in the memory lines to which the N to-be-read words or the N to-be-read words belong.

In a second aspect, an embodiment of the present invention provides a memory access method, including:

The memory controller receives N read commands sent by the cache device, the N is an integer greater than or equal to 2, each read command includes an address of a word to be read, and the address of the word to be read includes the word to be read An address of the associated memory line and an address of the word to be read in the memory line, the read command is used to read the word to be read;

The memory controller acquires the N to-be-read words from the memory lines to which the N to-be-read words belong according to the address of the N words to be read, and sends the N to be read to the cache device. word;

The memory controller acquires words other than the N to-be-read words from the memory lines to which the N words to be read belong, and sends the other words to the cache device.

In a first possible implementation manner of the second aspect, the memory controller sends the other words to the cache device, including:

The memory controller belongs to the same memory particle according to the memory line to which the N words to be read belong The other words are transmitted to the cache device in descending order of priority of the words other than the N words to be read.

With reference to the second aspect, or the first possible implementation manner of the second aspect, in a second possible implementation manner of the second aspect, the memory controller sends the first word to the cache device, including:

The memory controller sends a priority of the first word and the first word to the cache device, where the first word is the N words to be read or the N words to be read belong to A word other than the N words to be read in the memory line.

With the second possible implementation of the second aspect, in a third possible implementation manner of the second aspect, before the sending, by the memory controller, the first word to the cache device, the method further includes:

The memory controller determines the priority of each word according to the read/write frequency of each word in the memory line to which the N words to be read belong.

With reference to the second aspect, or any one of the first to the third possible implementation manners of the second aspect, in the fourth possible implementation manner of the second aspect, the memory lines of the N to-be-read words belong to Each word in it is stored in a memory particle.

In a third aspect, an embodiment of the present invention provides a cache device, including:

a receiving unit, configured to receive N read commands sent by the processor, where N is an integer greater than or equal to 2, each read command includes an address of a word to be read, and the address of the word to be read includes the to-be-read Reading the address of the memory line to which the word belongs and the address of the word to be read in the memory line, the read command is used to read the word to be read;

a processing unit, configured to determine whether the N to-be-read words are cached in the cache device;

a sending unit, configured to: when the processing unit determines that the N to-be-read words are not cached in the cache device, forward the N read commands to a memory controller;

The receiving unit is further configured to receive the N to-be-sent words sent by the memory controller, and

The sending unit is further configured to send the N to-be-read words to the processor;

The receiving unit is further configured to receive, in the memory row to which the N to-be-read words are sent by the memory controller, other words than the N to-be-read words.

In a first possible implementation manner of the third aspect, the receiving unit is configured to receive the first word sent by the memory controller, where: the receiving unit is configured to receive, by the memory controller, Describe the priority of the first word and the first word;

The processing unit is further configured to cache the first word according to a priority of the first word from high to low;

In a fourth aspect, an embodiment of the present invention provides a memory controller, including:

a receiving unit, configured to receive N read commands sent by the cache device, where N is an integer greater than or equal to 2, each read command includes an address of a word to be read, and the address of the word to be read includes the to-be-read Reading the address of the memory line to which the word belongs and the address of the word to be read in the memory line, the read command is used to read the word to be read;

a processing unit, configured to acquire the N to-be-read words from the memory lines to which the N to-be-read words belong according to the addresses of the N to-be-read words;

a sending unit, configured to send the N to-be-read words to the cache device;

The processing unit is further configured to obtain, from the memory lines to which the N to-be-read words belong, words other than the N to-be-read words;

The sending unit is further configured to send the other words to the cache device.

In a first possible implementation manner of the fourth aspect, the sending unit is configured to send the other words to the cache device, where: the sending unit is configured to: according to the memory line to which the N to-be-read words belong The other words belonging to the same memory particle in a descending order of priority of each of the N words to be read are sent to the cache device.

With reference to the fourth aspect, or the first possible implementation manner of the fourth aspect, in a second possible implementation manner of the fourth aspect, the sending unit is configured to send the first word to the cache device, including: The sending unit is configured to send a priority of the first word and the first word to the cache device, where the first word is the N words to be read or the N words to be read A word other than the N words to be read in the associated memory line.

In conjunction with the second possible implementation of the fourth aspect, in a third possible implementation manner of the fourth aspect, the processing unit is further configured to send, by the sending unit, the first to the cache device Before the word, the priority of each word is determined according to the frequency of reading and writing of each word in the memory line to which the N words to be read belong.

With reference to the fourth aspect, or any one of the first to the third possible implementation manners of the fourth aspect, in the fourth possible implementation manner of the fourth aspect, the memory lines of the N to-be-read words belong to Medium Each word is stored in a memory granule.

In a fifth aspect, the embodiment of the present invention provides a computer device, including: a cache device provided by the third aspect of the embodiment or the first possible implementation manner of the third aspect, the fourth aspect or the fourth embodiment of the present invention Various possible implementations of aspects provide memory controllers, processors, and memory devices.

The memory access method, device, and computer device provided by the embodiment of the present invention receive at least two read commands sent by the processor through the cache device, and when the N to-be-read words are not cached in the cache device, the memory controller is Forwarding the at least two read commands, receiving the N to-be-read words sent by the memory controller, and sending the N to-be-read words to the processor, and then receiving the location sent by the memory controller The words other than the N to-be-read words in the memory line to which the N words to be read belong are described. Since the cache device does not need to acquire other words in the memory row to which the N words to be read belong in the process of acquiring the N words to be read, the delay of reading the N words to be read is not increased, and the existing Compared with the technology, the read delay of the word to be read can be reduced.

DRAWINGS

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, a brief description of the drawings used in the embodiments or the prior art description will be briefly described below. Obviously, the drawings in the following description It is a certain embodiment of the present invention, and other drawings can be obtained from those skilled in the art without any creative work.

1 is a flowchart of Embodiment 1 of a memory access method according to the present invention;

2 is a flowchart of Embodiment 2 of a memory access method according to the present invention;

3 is a flowchart of Embodiment 3 of a memory access method according to the present invention;

4 is a schematic diagram of accessing a word to be read according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of a memory line according to an embodiment of the present invention;

6 is a flowchart of Embodiment 4 of a memory access method according to the present invention;

FIG. 7 is a schematic diagram of access to be written according to an embodiment of the present invention;

8 is a flowchart of Embodiment 5 of a memory access method according to the present invention;

FIG. 9 is a schematic diagram of accessing a word to be read according to an embodiment of the present invention;

10 is a schematic structural diagram of Embodiment 1 of a cache device according to the present invention;

11 is a schematic structural diagram of Embodiment 1 of a memory controller according to the present invention;

FIG. 12 is a schematic structural diagram of Embodiment 1 of a computer device according to the present invention.

detailed description

The technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the drawings in the embodiments of the present invention. It is a partial embodiment of the invention, and not all of the embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative efforts are within the scope of the present invention.

1 is a flowchart of Embodiment 1 of a memory access method according to the present invention. As shown in FIG. 1, the method in this embodiment may include:

S101. The cache device receives N read commands sent by the processor, where N is an integer greater than or equal to 2. Each read command includes an address of a word to be read, and the address of the word to be read includes the to-be-read The address of the memory line to which the word belongs and the address of the word to be read in the memory line, the read command is used to read the word to be read.

In this embodiment, the cache device may receive N read commands sent by one processor core of the processor, or the cache device may receive N read commands sent by multiple processor cores of the processor, among the N read commands. Each of the read commands includes an address of the word to be read, wherein the address of the word to be read included in each read command may be different, and the address of the word to be read includes the address of the memory line to which the word to be read belongs and the word to be read is The address in the associated memory line, each read command is used to read the word to be read corresponding to the address included in the read command.

S102. When the N to-be-read words are not cached in the cache device, the cache device forwards the N read commands to the memory controller.

In this embodiment, the cache device may determine, according to the addresses of the N words to be read, whether the N words to be read have been cached. If the N words to be read are cached in the cache device, the cache device substitutes the N. The words to be read are sent to the processor, that is, the N words are stored in corresponding registers in the processor. If the N words to be read are not cached in the cache device, that is, the cache miss, the cache device needs to be The N words to be read are obtained in the memory, and the cache device sends the N read commands to the memory controller.

S103. The cache device receives the N to-be-sent words sent by the memory controller, and sends the N to-be-read words to the processor.

In this embodiment, after receiving the N read commands, the memory is based on the addresses of the N words to be read. Obtaining the N words to be read from the memory lines of the N to-be-read words stored in the memory, and sending the N words to be read to the cache device, so the cache device can receive the N to be sent by the memory controller. Read the word and send the N words to be read to the processor. .

S104. The cache device receives a word other than the N to-be-read words in the memory line to which the N to-be-read words are sent by the memory controller.

In this embodiment, after receiving the N words to be read, the cache device receives the words other than the N words to be read in the memory line to which the N words to be read are sent by the memory controller. Since the cache device does not receive the words other than the N words to be read in the memory line to which the N words to be read are sent by the memory controller when receiving the N words to be read, the cache device acquires the N items to be read. When the word is read, it is not interfered by the reading of other words, so that the delay of reading the N words to be read is not increased, and the reading delay of the word to be read can be reduced compared with the prior art.

The memory access method provided by the embodiment of the present invention receives at least two read commands sent by the processor by the cache device, and forwards the at least two to the memory controller when the N to-be-read words are not cached in the cache device. Reading the command, receiving the N to-be-sent words sent by the memory controller, and sending the N to-be-read words to the processor, and then receiving the N to-be-sents sent by the memory controller A word other than the N words to be read in the memory line to which the word belongs. Since the cache device does not need to acquire other words in the memory row to which the N words to be read belong in the process of acquiring the N words to be read, the delay of reading the N words to be read is not increased, and the existing Compared with the technology, the read delay of the word to be read can be reduced.

2 is a flowchart of Embodiment 2 of a memory access method according to the present invention. As shown in FIG. 2, the method in this embodiment may include:

S201. The memory controller receives N read commands sent by the cache device, where N is an integer greater than or equal to 2. Each read command includes an address of a word to be read, and the address of the word to be read includes the to-be-read address. The address of the memory line to which the word belongs and the address of the word to be read in the memory line, the read command is used to read the word to be read.

S202. The memory controller acquires the N to-be-read words from the memory lines to which the N to-be-read words belong according to the address of the N to-be-read words, and sends the N to the cache device. The word to be read.

In this embodiment, the memory controller determines, according to the address of the N words to be read, the memory line to which the N words to be read belong, and then obtains the N from the memory line to which the N words to be read are stored in the memory. The words to be read are sent to the cache device.

S203. The memory controller acquires words other than the N to-be-read words from the memory lines to which the N to-be-read words belong, and sends the other words to the cache device.

In this embodiment, the memory controller obtains other words other than the N words to be read from the memory lines of the N to-be-read words stored in the memory, and sends the acquired other words to the cache device.

In this embodiment, after the memory controller obtains the N words to be read, the words other than the N words to be read in the memory line to which the N words to be read are not temporarily processed are not processed, but are preferentially The N words to be read are sent to the cache device, so the cache device does not interfere with the reading of other words when acquiring the N words to be read, thereby not increasing the delay of the cache device reading the N words to be read. Compared with the prior art, the read delay of the word to be read can be reduced.

The memory access method provided by the embodiment of the present invention receives the N read commands sent by the cache device through the memory controller, and obtains the N from the memory lines to which the N to-be-read words belong according to the addresses of the N to-be-read words. Reading the words, and preferentially transmitting the N words to be read to the cache device, and then acquiring words other than the N words to be read from the memory lines to which the N words to be read belong, and The other words are sent to the cache device. Since the memory controller does not need to acquire other words in the memory row of the N words to be read in the process of acquiring the N words to be read, and the cache device does not receive other words when acquiring the N words to be read. The interference is read so that the delay of reading the N words to be read is not increased, and the read delay of the word to be read can be reduced as compared with the prior art.

3 is a flowchart of Embodiment 3 of a memory access method according to the present invention. As shown in FIG. 3, the method in this embodiment may include:

S301. The processor sends N read commands to the cache device.

Each read command includes an address of the word to be read, and each read command may further include an identifier of the register. Specifically, the read command is used to indicate that the word to be read is stored in the register of the processor.

In this embodiment, the N is 2, and the cache device receives two read commands sent by the processor. As shown in FIG. 4, the two read commands are, for example, LoadR0, Addr1+8, LoadR1, and addr1+16. These two read commands are used to read different words in the same memory line. LoadR0 and Addr1+8 are used to indicate that the address of the memory line with the address Addr1 is 8 is stored in register R0, LoadR1, addr1 +16 is used to indicate that the word with address 16 in the memory line at address Addr1 is stored in register R1.

S302. The cache device determines that the N to-be-read words are not cached.

S303. The cache device forwards the N read commands to the memory controller.

In this embodiment, the cache device receives the read command to determine whether the word to be read is cached, and the cache device can determine, according to the address of the word to be read, whether the words to be read have been cached, if the cache device has Cache the words to be read, and the cache device stores the words to be read in the corresponding registers. If the two words to be read are not cached in the cache device, that is, the cache miss, the cache device forwards to the memory controller. The two read commands; this embodiment is an example in which the cache device does not cache all the words to be read. If one of the words to be read has been cached in the cache device, the cache device stores the word to be read in the corresponding register, and the cache device sends another read command to the memory controller.

S304. The memory controller acquires the N to-be-read words from the memory lines to which the N to-be-read words belong according to the addresses of the N to-be-read words.

In this embodiment, the memory controller preferentially obtains the to-be-read word with address 8 and the address to be read 16 from the memory row with the address Addr1 according to the addresses of the two words to be read: Addr1+8 and Addr1+16. word. Each of the words to be read in the embodiment is stored in one of the memory pixels of the memory line to which the word to be read belongs. As shown in Figure 5, each memory row in the memory controller stores 8 words, which are stored in different memory particles, for example: word 0 in the memory row (representing the 0th in the memory row) The word is stored in the memory particle 0, the word 1 in the memory line (representing the first word in the memory line) is stored in the memory particle 1, and so on, and will not be described here. Specifically, as shown in FIG. 4, the memory controller can determine the memory line to which the word to be read belongs according to the address Addr1, and then obtain the word 1 from the memory particle 1 corresponding to the address 8 according to the address 8 and the address 16, the word 1 is to be The word is read, and word 2 is obtained from the memory particle 2 corresponding to address 16, which is the word to be read.

S305. The memory controller sends the priority of the N to-be-read words and the N to-be-read words to the cache device.

In this embodiment, after the memory controller acquires the two words to be read, the word 1 and the word 2, the memory controller takes the priority of the word 1 and the word 1 and the priority of the word 2. Accordingly, the cache device also receives the priority of word 1 and word 1 transmitted by the memory controller, and the priority of word 2 and word 2.

The memory controller determines the priority of all words according to the read/write frequency of all words in the memory line, that is, if the read/write frequency of the word 0 is higher than the read/write frequency of the word 1, the priority of the word 0 is higher than The priority of word 1, as shown in Figure 4, the order of priority in the memory line from high to low is: word 0 to word 7.

S306. The cache device sends the N to-be-read words to the processor.

Specifically, the cache device may store each of the to-be-read words in the corresponding register of the processor according to the identifier of the register. The address of the word 1 carried by the cache device according to word 1 (Addr1+8), it can be determined that the corresponding read command is: LoadR0, Addr1+8, and then the cache device stores the received word 1 in the register R0 according to R0. The cache device can determine that the corresponding read command is: LoadR1, Addr1+16 according to the address of the word 2 carried by the word 2 (Addr1+16), and then the cache device stores the received word 2 in the register R1 according to R1.

S307. The cache device caches the N to-be-read words according to a priority of the N to-be-read words from high to low.

In this embodiment, the cache device may also cache the two words to be read: word 1 and word 2. Specifically, the cache line in the cache device has a corresponding relationship with the memory line in the memory controller, and the cache device is based on the word. Addr1 in the address of 1 determines the cache line corresponding to the memory line of the address Addr1, and then stores the word 1 at the position where the cache line address is 8 according to the address 8 in the address of the word 1. The cache device determines the cache line corresponding to the memory line of the address Addr1 according to Addr1 in the address of the word 2, and then stores the word 2 at the position where the cache line address is 16 according to the address 16 in the address of the word 2.

In this embodiment, the cache device may further cache the word 1 and then cache the word 2 according to the priority of the word 1 being higher than the priority of the word 2 (as shown in FIG. 4).

It should be noted that the execution order of S306 and S307 is in no particular order.

S308. The memory controller acquires words other than the N to-be-read words from the memory lines to which the N to-be-read words belong.

S309. The memory controller sends a priority of the other words and the other words to the cache device.

In this embodiment, after the memory controller sends the word 1 and the word 2 to the cache device, the memory controller acquires words other than the word 1 and the word 2 in the memory line to which the word 1 and the word 2 belong, such as a memory controller. Then obtain word 0, word 3, word 4, word 5, word 6, word 7, these words can be called prefetch words, and then send the priority of word 0 and word 0, the priority of word 3 and word 3 to the cache device. The priority of the level, word 4 and word 4, the priority of word 5 and word 5, the priority of word 6 and word 6, the priority of word 7 and word 7. Correspondingly, the cache device can receive the priority of word 0 and word 0 sent by the memory controller, the priority of word 3 and word 3, the priority of word 4 and word 4, the priority of word 5 and word 5, word 6 And the priority of word 6, the priority of word 7 and word 7.

S310. The cache device caches the other words according to a priority of the other words from high to low.

In this embodiment, the cache device may further cache words other than the two words to be read: word 0, word 3, word 4, word 5, word 6, and word 7. Specifically, the cache device may be based on the word. The address of 0 determines the Addr1 in the address of the word 0, determines the cache line corresponding to the memory line of the address Addr1, and then stores the word 0 at the position where the cache line address is 0 according to the address 0 in the address of the word 0. . The caching process of word 3, word 4, word 5, word 6, and word 7 is similar, and will not be described here.

In this embodiment, the cache device may also cache the respective words according to the order of priority from high to low: word 0>word 3>word 4>word 5>word 6>word 7, and the cache order is: word 0, word 3 , word 4, word 5, word 6, word 7.

In this embodiment, the memory controller does not need to acquire and send other words in the memory row of the N to-be-read words in the process of acquiring and transmitting the N words to be read, and the cache device is acquiring the N to During the process of reading a word, it is not necessary to obtain other words in the memory row of the N words to be read, so that the delay of reading the N words to be read is not increased, and the word to be read can be reduced compared with the prior art. Read latency.

FIG. 6 is a flowchart of Embodiment 4 of a memory access method according to the present invention. As shown in FIG. 6, the method in this embodiment is based on any one of Embodiments 1 to 3 or 5 of the method of the present invention, and further, the embodiment is The method can also include:

S401. The processor sends M write commands to the cache device.

Wherein, M is an integer greater than or equal to 1, each of the write commands includes an address to be written and the address to be written, and the address to be written includes an address of the memory row to be written and the writing to be written The address in the belonging memory row, the write command is used to write the to-be-written.

In this embodiment, the M is 1 as an example. The cache device receives a write command sent by the processor. As shown in FIG. 7, the write command is, for example, StoreR0, Addr1+16, and Addr1+16 indicates the address to be written. That is, the address in the memory row of the address Addr1 is 8 address, R0 means to store the register to be written, and StoreR0 and Addr1+16 are used to indicate that the word in the register R0 is stored to the address of the address Addr1+16.

S402. The cache device writes each of the to-be-written words into a corresponding position in a corresponding cache line of each memory line to be written according to the address to be written.

In this embodiment, the cache line in the cache device has a corresponding relationship with the memory line in the memory controller, and the cache device determines the cache line corresponding to the memory line with the address Addr1 according to Addr1 in the address to be written, and then according to the Address 16, in the address of the letter, stores the word to be written in the cache The row address is 16 locations.

S403. The cache device forwards M write commands to the memory controller.

In this embodiment, the cache device may determine, according to the write command, whether the memory line with the address of Addr1 is cached. If it is cached, execute S406. If not, the cache device memory controller forwards the write command. This embodiment is described as an example of a memory behavior of a cache device that is not cached to be written.

S404, the memory controller sends, according to the write command, a word other than the word corresponding to the M addresses to be written in the M memory lines to be written to the cache device.

In this embodiment, the memory controller receives a write command that is sent by the cache device, including the address to be written, and the memory controller may stop acquiring the word corresponding to the address to be written according to the write command, and obtain the memory to be written. In addition to the word corresponding to the word to be written in the line, in this embodiment, the word other than word 2 (the word corresponding to the address 16) in the memory line with the address Addr1 is obtained, and these words are Word 0, word 1, word 3, word 4, word 5, word 6, word 7, these words can also be called prefetch words, and then send the address of word 0 and word 0 (Addr1+0), word to the cache device Address of 1 and word 1 (Addr1+8), address of word 3 and word 3 (Addr1+24), address of word 4 and word 4 (Addr1+32), address of word 5 and word 5 (Addr1+40) , the address of Word 6 and Word 6 (Addr1+48), the address of Word 7 and Word 7 (Addr1+56). Accordingly, the cache device can receive the above words sent by the memory controller.

Alternatively, the memory controller can prioritize word 0 and word 0, priority of word 1 and word 1, priority of word 3 and word 3, priority of word 4 and word 4, word 5 and word 5 The priority, the priority of word 6 and word 6, the priority of word 7 and word 7 are sent to the cache device.

S405. The cache device caches words other than words corresponding to the M addresses to be written in the M memory lines to be written.

In this embodiment, the cache device may cache the word 0, word 1, word 3, word 4, word 5, word 6, and word 7 sent by the received memory controller. Specifically, the cache device may determine Addr1 in the address of the word 0 according to the address of the word 0, determine a cache line corresponding to the memory line of the address Addr1, and then store the word 0 according to the address 0 in the address of the word 0. The location where the cache line address is 0. The caching process of word 1, word 3, word 4, word 5, word 6, and word 7 is similar, and will not be described here.

Optionally, the cache device may also cache the individual words according to the order of priority from high to low: word 0>word 1>word 3>word 4>word 5>word 6>word 7. The cache order is: word 0, Word 1, word 3, word 4, word 5. Word 6, word 7.

S406. The cache device sends, to the memory controller, a cache line corresponding to the M memory lines to be written.

In this embodiment, after the cache device caches all the words in the memory row, the cache device sends a cache line corresponding to the memory row to be written to the memory controller, that is, the cache device uses the word 0, the word 1, the word to be written, and the word. 3. Word 4, Word 5, Word 6, and Word 7 are sent to the memory controller.

S407. The memory controller rewrites the M memory lines to be written into the cache lines corresponding to the M memory lines to be written.

In this embodiment, the memory controller receives the cache line corresponding to the memory line to be written by the cache device, and the memory controller rewrites the memory line with the address Addr1 to the cache line sent by the received cache device, that is, the memory with the address Addr1. All words in the line are rewritten as word 0, word 1, to be written, word 3, word 4, word 5, word 6, word 7, thereby realizing the word rewriting process.

In this embodiment, since the memory controller does not need to send all the words in the entire memory row to the cache device after receiving the write command, the overhead can be saved.

FIG. 8 is a flowchart of Embodiment 5 of the memory access method of the present invention. As shown in FIG. 8, the method in this embodiment may include:

S501. The processor sends N read commands to the cache device.

Where N is an integer greater than or equal to 2, each read command includes an address of the word to be read and an identifier of the register, the read command is used to indicate that the word to be read is stored in the register.

In this embodiment, the N is 3, and the cache device receives three read commands sent by the processor. As shown in FIG. 9, the three read commands are, for example, LoadR0, Addr0+16, LoadR1, and addr1+32. LoadR1, addr2+48, these three read commands are used to read the words in different memory lines, LoadR0, Addr0+16 is used to indicate that the address of the memory line with the address Addr0 is 16 is stored in register R0. , LoadR1, addr1+32 are used to indicate that the address of the memory line with the address Addr1 is 32 is stored in the register R1, and LoadR2, addr2+48 is used to indicate that the address in the memory line with the address Addr2 is 48. The word is stored in register R2.

S502. The cache device determines that the N to-be-read words are not cached.

S503. The cache device forwards the N read commands to a memory controller.

In this embodiment, the cache device receives the read command to determine whether the word to be read has been cached, and the cache device can determine, according to the address of the word to be read, whether the word to be read is cached, if the cache If the word to be read is cached in the device, the cache device stores the word to be read in the corresponding register. If the three words to be read are not cached in the cache device, that is, the cache miss, the cache device is directed to the memory controller. The three read commands are forwarded; this embodiment is an example in which the cache device does not cache all the words to be read.

S504. The memory controller acquires the N to-be-read words from the memory lines to which the N to-be-read words belong according to the addresses of the N to-be-read words.

In this embodiment, the memory controller preferentially obtains the to-be-read word and the slave address with the address of 16 from the memory row with the address Addr0 according to the addresses of the three words to be read: Addr0+16, Addr1+32, and Addr2+48. For the memory line of Addr1, the word to be read with the address of 32 is preferentially obtained, and the word to be read with the address of 48 is preferentially obtained from the memory line with the address of Addr2. Moreover, the memory controller stops acquiring the word of the address 56 from the memory line of the address Addr3 according to the address to be written: Addr3+56, wherein each word in the embodiment is stored in the memory line of the word. One of the memory particles. As shown in Figure 9, each memory row in the memory controller stores 8 words, which are stored in different memory particles, for example, word 00 in memory row 0 (representing memory row 0) The 0th word is stored in the memory granule 0, the word 11 in the memory line 1 (representing the first word in the memory line 1) is stored in the memory granule 1, and so on, and will not be described again here. The word 00, the word 10, and the word 20 are stored in the memory granule 0, and the word 01, the word 11, and the word 21 are stored in the memory granule 1, and so on, and are not described herein again. Specifically, as shown in FIG. 9, the memory controller can determine the memory line 0 to which the word to be read belongs according to the address Addr0, and then obtain the word 02 from the memory particle 2 corresponding to the address 16 according to the address 16, the word 02 is to be read. The memory controller can determine the memory line 1 to which the word to be read belongs according to the address Addr1, and then obtain the word 14 from the memory particle 4 corresponding to the address 32 according to the address 32, the word 14 is the word to be read; the memory controller can be based on The address Addr2 determines the memory line 2 to which the word to be read belongs, and then obtains the word 26 from the memory grain 6 corresponding to the address 48 according to the address 48, which is the word to be read.

S505. The memory controller sends the priority of the N to-be-read words and the N to-be-read words to the cache device.

In this embodiment, after the memory controller acquires the three words to be read, namely word 02, word 14 and word 26, the memory controller sets the priority of word 01, word 01, the priority of word 14 and word 14, and the word. The priority of 26 and the word 26 is sent to the cache device, so that the cache device can distinguish which of the received three words is the word to be read according to the address of the word 01, the address of the word 14, and the address of the word 26. . It should be noted that, similar to the prior art, each of the above words carries the address of each word.

S506. The cache device sends the N to-be-read words to the processor.

In this embodiment, the cache device stores each of the words to be read in the corresponding register according to the identifier of the register. For example, the cache device can determine that the corresponding read command is: LoadR0, Addr0+16 according to the address of the word 02 (Addr0+16), and then the cache device stores the received word 02 in the register R0 according to R0. Based on the address of the word 14 (Addr1+32), the cache device can determine that the corresponding read command is: LoadR1, Addr1+32, and then the cache device stores the received word 14 in the register R1 according to R1. Based on the address of word 26 (Addr1+32), the cache device can determine that the corresponding read command is: LoadR2, Addr2+48, and then the cache device stores the received word 26 in register R2 according to R2.

S507. The cache device caches the N to-be-read words according to an order of priority of the N to-be-read words.

In this embodiment, the cache device may also cache the three words to be read: word 02, word 14, and word 26. Specifically, the cache line in the cache device has a corresponding relationship with the memory line in the memory controller, and the cache The device determines the cache line 0 corresponding to the memory line 0 of the address Addr0 according to Addr0 in the address of the word 02, and then stores the word 02 in the position of the cache line 0 address 16 according to the address 16 in the address of the word 02. . The cache device determines the cache line 1 corresponding to the memory line 1 of the address Addr1 according to Addr1 in the address of the word 14, and then stores the word 14 in the cache line 1 address 32 according to the address 32 in the address of the word 14. position. The cache device determines the cache line 2 corresponding to the memory line 2 of the address Addr2 according to Addr2 in the address of the word 26, and then stores the word 26 in the cache line 2 address 48 according to the address 48 in the address of the word 26. position.

As shown in FIG. 9, the cache device may also have a priority higher than the priority of the word 14 according to the priority of the word 14, the priority of the word 14 is higher than the priority of the word 02, the word 26 is cached first, then the word 14 is cached, and then the word 02 is cached. .

It should be noted that the execution order of S506 and S507 is in no particular order.

S508. The memory controller acquires words other than the N to-be-read words from the memory lines to which the N to-be-read words belong.

S509, the memory controller according to the order of priority of each word except the N to-be-read words belonging to the same memory particle in the memory line to which the N to-be-read words belong, to the The cache device transmits the priority of the other words and the other words.

In this embodiment, after the memory controller acquires the word 02, the word 14 and the word 26, the memory controller acquires the word in the memory line 0 of the word 02, except the word 02, and the memory line 1 of the word 14 belongs to Words other than the word 14, words 26 of the memory line 2 other than the word 26, which may be referred to as prefetched words, are then sent to the cache device for the words and the addresses of the words. Accordingly, the cache device can receive the words sent by the memory controller and the addresses of the words.

In this embodiment, the memory controller may send, to the cache device, the N to-be-read words in the memory row to which the N words to be read belong according to the priority of the respective words belonging to the same memory particle from high to low. Other words than words. For memory granule 0, the memory controller sequentially sends word 20, word 10, and word 00 to the cache device. For the memory granule 1, the memory controller sequentially sends the word 21, the word 11, and the word 01 to the cache device. For the memory granule 2, the memory controller sequentially sends the word 22, word 12 to the cache device. For the memory granule 3, the memory controller sequentially sends the word 23, word 13, and word 03 to the cache device. For the memory granule 4, the memory controller sequentially sends the word 24, word 04 to the cache device. For the memory granule 5, the memory controller sequentially sends the word 25, word 15, and word 05 to the cache device. For the memory granule 6, the memory controller sequentially sends the word 16, word 06 to the cache device. For memory particles 7, the memory controller sequentially sends word 27, word 17, word 07 to the cache device.

If the memory controller can simultaneously send 8 words to the cache device, the memory controller first sends word 27, word 26, word 25, word 14, word 23, word 02, word 21, word 20 to the cache device, and then sends the word. 17. Word 16, Word 15, Word 24, Word 13, Word 22, Word 11, Word 10, and then send word 07, word 06, word 05, word 04, word 03, word 12, word 01, word 00.

If the memory controller can send less than 8 words to the cache device at the same time, the memory controller first sends the word 26, the word 14, the word 02, the word 27, the word 25, to the cache device according to the order of priority from high to low. Word 23, word 21, word 20; then send word 17, word 16, word 15, word 24, word 13, word 22, word 11, word 10 according to the order of priority from high to low, and then according to the priority In the high to low order, word 07, word 06, word 05, word 04, word 03, word 12, word 01, and word 00 are transmitted.

If the memory controller can send less than 8 words to the cache device at the same time, the memory controller can first send the word 26, the word 14, the word 02, and then send the word to the cache device according to the order of priority from high to low: word 27 , word 25, word 23, word 21, word 20, word 17, word 16, word 15, word 24, word 13, word 22, word 11, word 10, word 07, word 06, word 05, word 04, word 03, word 12, word 01, word 00.

In this embodiment, the memory controller may also send the priority of each of the above words to the cache device.

S510. The cache device caches the order according to the priority of the other words from high to low. Said other words.

In this embodiment, the cache device caches the other words to corresponding locations in the cache line corresponding to the memory lines to which the other words belong according to the addresses of the other words. For example, word 07 is stored at the location where the cache line 0 address is 56, based on address 40 in the address of word 07. The caching process for other words is similar and will not be described here.

The cache device may also cache the above words according to the priority of each word described in S509 from high to low. For example, the cache device first caches the word 27, the word 25, and the word according to the order of priority from high to low. 23, word 21, word 20; according to the order of priority from high to low, cache word 17, word 16, word 15, word 24, word 13, word 22, word 11, word 10; then according to the priority from high In the low order, cache word 07, word 06, word 05, word 04, word 03, word 12, word 01, word 00.

In this embodiment, the memory controller does not need to acquire and send other words in the memory row of the N to-be-read words in the process of acquiring and transmitting the N words to be read, and the cache device is acquiring the N to During the process of reading a word, it is not necessary to obtain other words in the memory row of the N words to be read, so that the delay of reading the N words to be read is not increased, and the word to be read can be reduced compared with the prior art. Read latency. At the same time, since the memory controller receives the second write command, it does not need to send all the words in the entire memory row to the cache device, thereby saving the overhead.

10 is a schematic structural diagram of Embodiment 1 of a cache device according to the present invention. As shown in FIG. 10, the cache device of this embodiment includes: a receiving unit 11, a processing unit 12, and a sending unit 13; wherein, the receiving unit 11 is configured to receive processing. N read commands sent by the device, the N is an integer greater than or equal to 2, each read command includes an address of a word to be read, and the address of the word to be read includes an address of a memory line to which the word to be read belongs And the address of the word to be read in the memory line, the read command is used to read the word to be read; the processing unit 12 is configured to determine whether the N words to be read are cached in the cache device The sending unit 13 is configured to: when the processing unit 12 determines that the N words to be read are not cached in the cache device, forward the N read commands to the memory controller; the receiving unit 11 is further configured to receive the The N words to be read sent by the memory controller, and the sending unit 13 are further configured to send the N to be read words to the processor; the receiving unit 11 is further configured to receive the sending by the memory controller The N waiting to be read in the memory line to which the word to be read belongs Read words other than words.

Optionally, the receiving unit 11 is configured to receive the first word sent by the memory controller, where the receiving unit 11 is configured to receive the first word and the first word sent by the memory controller. The processing unit 12 is further configured to cache the location according to the priority of the first word from high to low. a first word; wherein the first word is a word other than the N to-be-read words in the memory line to which the N to-be-read words or the N to-be-read words belong.

The cache device of this embodiment may be used to perform the technical solution executed by the cache device in the foregoing method embodiment of the present invention. The implementation principle and technical effects are similar, and details are not described herein again.

FIG. 11 is a schematic structural diagram of Embodiment 1 of a memory controller according to the present invention. As shown in FIG. 11, the memory controller of this embodiment includes: a receiving unit 21, a processing unit 22, and a sending unit 23; wherein, the receiving unit 21 is configured to Receiving N read commands sent by the cache device, where N is an integer greater than or equal to 2, each read command includes an address of a word to be read, and an address of the word to be read includes an memory line to which the word to be read belongs And an address of the word to be read in the memory line, the read command is used to read the word to be read, and the processing unit 22 is configured to: according to the address of the N words to be read, Obtaining the N to-be-read words in the memory row to which the N words to be read belong; the sending unit 23 is configured to send the N to-be-read words to the cache device; the processing unit 22 is further configured to use the N The words in the memory line to which the word to be read belong are obtained other than the N words to be read; the sending unit 23 is further configured to send the other words to the cache device.

Optionally, the sending unit 23 is configured to send the other words to the cache device, where: the sending unit 23 is configured to: according to the N memory cells belonging to the same memory particle in the memory row to which the N to be read words belong The other words are transmitted to the cache device in a descending order of priority of the words other than the read word.

Optionally, the sending unit 23 is configured to send the first word to the cache device, where the sending unit 23 is configured to send, to the cache device, a priority of the first word and the first word, where The first word is a word other than the N to-be-read words in the memory lines to which the N to-be-read words or the N to-be-read words belong.

Optionally, the processing unit 22 is further configured to: before the transmitting unit 23 sends the first word to the cache device, determine, according to the read/write frequency of each word in the memory line to which the N to-be-read words belong, The priority of the word.

Optionally, each word in the memory row to which the N words to be read belong is stored in one memory particle.

The memory controller of this embodiment may be used to perform the technical solution executed by the memory controller in the foregoing method embodiment of the present invention, and the implementation principle and technical effects thereof are similar, and details are not described herein again.

FIG. 12 is a schematic structural diagram of Embodiment 1 of a computer device according to the present invention. As shown in FIG. 12, the computer device provided in this embodiment may include computing capability. The host server, or a personal computer (English: Personal Computer, PC for short), or a portable computer or terminal, etc., the present invention is not limited thereto, and the specific embodiment of the present invention is not specific to the computer device 700. Realization is limited. The computer device 700 may include: a cache device 710, a memory controller 720, a processor 730, and a memory device 740; the computer device 700 may further include: a communication bus 750, wherein the cache device 710, the memory controller 720, and the processing The memory device 730 and the memory device 740 can complete communication between the devices through the communication bus 750. The computer device 700 can also include a communication interface 760 through which the processor 730 can communicate with external devices.

The cache device 710 can adopt the structure shown in FIG. 10, and correspondingly, the technical solution executed by the cache device in the foregoing method embodiment of the present invention can be executed, and details are not described herein; the memory controller 720 can be configured as shown in the figure. The configuration shown in FIG. 11 can perform the execution scheme executed by the memory controller in the foregoing method embodiment of the present invention, and details are not described herein again.

A person skilled in the art can understand that all or part of the steps of implementing the above method embodiments may be completed by using hardware related to the program instructions. The foregoing program may be stored in a computer readable storage medium, and the program is executed when executed. The foregoing storage medium includes: read-only memory (English: Read-Only Memory, ROM for short), random access memory (English: Random Access Memory, RAM), disk or A variety of media such as optical discs that can store program code.

Finally, it should be noted that the above embodiments are merely illustrative of the technical solutions of the present invention, and are not intended to be limiting; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art will understand that The technical solutions described in the foregoing embodiments may be modified, or some or all of the technical features may be equivalently replaced; and the modifications or substitutions do not deviate from the technical solutions of the embodiments of the present invention. range.

Claims

A memory access method, comprising:

The cache device receives N read commands sent by the processor, the N is an integer greater than or equal to 2, the read command includes an address of the word to be read, and the address of the word to be read includes the word to be read An address of the memory line and an address of the word to be read in the memory line, the read command is used to read the word to be read;

When the N words to be read are not cached in the cache device, the cache device forwards the N read commands to the memory controller;

The cache device receives the N to-be-sent words sent by the memory controller, and sends the N to-be-read words to the processor;

The cache device receives other words in the memory row to which the N words to be read are sent by the memory controller, except the N to-be-read words.
The method according to claim 1, wherein the buffering device receives the first word sent by the memory controller, including:

Receiving, by the cache device, a priority of the first word and the first word sent by the memory controller;

The method further includes:

The cache device caches the first word according to a priority of the first word from high to low;

The first word is a word other than the N to-be-read words in the memory lines to which the N to-be-read words or the N to-be-read words belong.
A memory access method, comprising:

The memory controller receives N read commands sent by the cache device, the N is an integer greater than or equal to 2, each read command includes an address of a word to be read, and the address of the word to be read includes the word to be read An address of the associated memory line and an address of the word to be read in the memory line, the read command is used to read the word to be read;

The memory controller acquires the N to-be-read words from the memory lines to which the N to-be-read words belong according to the address of the N words to be read, and sends the N to be read to the cache device. word;

The memory controller acquires words other than the N to-be-read words from the memory lines to which the N words to be read belong, and sends the other words to the cache device.
The method of claim 3 wherein said memory controller is responsive to said The storage device sends the other words, including:

The memory controller sends the cache device to the cache device according to the priority of each of the N memory words belonging to the same memory particle belonging to the same memory particle from the highest to the lowest according to the N memory strings to be read. Send the other words.
The method according to claim 3 or 4, wherein the memory controller sends the first word to the cache device, including:

The memory controller sends a priority of the first word and the first word to the cache device, where the first word is the N words to be read or the N words to be read belong to A word other than the N words to be read in the memory line.
The method according to claim 5, wherein before the memory controller sends the first word to the cache device, the method further includes:

The memory controller determines the priority of each word according to the read/write frequency of each word in the memory line to which the N words to be read belong.
The method according to any one of claims 3-6, wherein each of the memory lines to which the N words to be read belong is stored in a memory particle.
A cache device, comprising:

a receiving unit, configured to receive N read commands sent by the processor, where N is an integer greater than or equal to 2, each read command includes an address of a word to be read, and the address of the word to be read includes the to-be-read Reading the address of the memory line to which the word belongs and the address of the word to be read in the memory line, the read command is used to read the word to be read;

a processing unit, configured to determine whether the N to-be-read words are cached in the cache device;

a sending unit, configured to: when the processing unit determines that the N to-be-read words are not cached in the cache device, forward the N read commands to a memory controller;

The receiving unit is further configured to receive the N to-be-sent words sent by the memory controller, and

The sending unit is further configured to send the N to-be-read words to the processor;

The receiving unit is further configured to receive, in the memory row to which the N to-be-read words are sent by the memory controller, other words than the N to-be-read words.
The cache device according to claim 8, wherein the receiving unit is configured to receive the first word sent by the memory controller, and the receiving unit is configured to receive the location sent by the memory controller Describe the priority of the first word and the first word;

The processing unit is further configured to cache the first word according to a priority of the first word from high to low;

The first word is a word other than the N to-be-read words in the memory lines to which the N to-be-read words or the N to-be-read words belong.
A memory controller, comprising:

a receiving unit, configured to receive N read commands sent by the cache device, where N is an integer greater than or equal to 2, each read command includes an address of a word to be read, and the address of the word to be read includes the to-be-read Reading the address of the memory line to which the word belongs and the address of the word to be read in the memory line, the read command is used to read the word to be read;

a processing unit, configured to acquire the N to-be-read words from the memory lines to which the N to-be-read words belong according to the addresses of the N to-be-read words;

a sending unit, configured to send the N to-be-read words to the cache device;

The processing unit is further configured to obtain, from the memory lines to which the N to-be-read words belong, words other than the N to-be-read words;

The sending unit is further configured to send the other words to the cache device.
The memory controller according to claim 10, wherein the sending unit is configured to send the other words to the cache device, and the sending unit is configured to: according to the memory of the N to-be-read words The other words of the same memory particle belonging to the same memory particle in a descending order of priority of each of the N words to be read are sent to the cache device.
The memory controller according to claim 10 or 11, wherein the sending unit is configured to send the first word to the cache device, where the sending unit is configured to send the a first word and a priority of the first word; wherein the first word is the N to-be-read words or the N to-be-read words belong to a memory line other than the N to-be-read words Other words.
The memory controller according to claim 12, wherein the processing unit is further configured to: before the sending unit sends the first word to the cache device, according to the N to-be-read words The frequency of reading and writing of each word in the memory line determines the priority of each word.
A memory controller according to any one of claims 10-13, wherein each of the memory lines to which the N words to be read belong is stored in a memory chip.
A computer device, comprising: the cache device according to claim 8 or 9, the memory controller, the processor and the memory device according to any one of claims 10-14.