JP2005269296A - Voltage current conversion circuit, agc circuit, and integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To convert an input voltage into an output current that changes in terms of an exponential function. <P>SOLUTION: This voltage current conversion circuit includes: conversion circuits 61, Q61 and R61 each converting an input voltage VCTL into a current ICTL proportional to the input voltage; a resistor R62, and transistors Q 64, Q71 to which the currents ICTL are supplied; and a voltage comparison circuit 63 for comparing a voltage across the resistor R62 through which the current ICTL flows with a collector voltage of the transistor Q64. Outputs of the voltage comparison circuit 63 are fed to bases of the transistors Q64, Q71 and an output current changing in terms of an exponential function with respect to the input voltage VCTL is obtained from a collector of the transistor Q71. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a voltage / current conversion circuit, an AGC circuit, and an integrated circuit.

  As a superheterodyne receiver, there is a so-called low IF receiver in which the intermediate frequency is made considerably lower than the reception frequency by bringing the local oscillation frequency close to the reception frequency. There is also a so-called direct conversion system in which the intermediate frequency is made zero by making the local oscillation frequency equal to the reception frequency. These receivers convert the received signal into a pair of intermediate frequency signals orthogonal to each other and improve image characteristics by phase processing.

  FIG. 4 shows an example of a low-IF receiver. That is, a reception signal SRX having a target reception frequency is taken out from the electronic tuning antenna tuning circuit 11, and this reception signal SRX is supplied to the pair of mixer circuits 13A and 13B through the high-frequency amplifier 12.

  In addition, the local oscillation circuit 31 is constituted by a PLL, and two signals whose phases are 90 ° different from each other at a frequency close to the frequency of the reception signal SRX (for example, when receiving digital audio broadcasting, a frequency higher by 500 kHz than the reception frequency). SLOA and SLOB are formed, and the signals SLOA and SLOB are supplied to the mixer circuits 13A and 13B as local oscillation signals.

  Thus, in the mixer circuits 13A and 13B, the received signal SRX is frequency-converted into a pair of intermediate frequency signals SIFA and SIFB by the local oscillation signals SLOA and SLOB. In this case, the intermediate frequency signals SIFA and SIFB include a signal component of the intended reception frequency (original signal component) and a signal component of the image frequency. The signal components of the reception frequency are called intermediate frequency signals SIFA and SIFB, and the signal components of the image frequency are called image components.

  Since the local oscillation signals SLOA and SLOB have a phase difference of 90 °, the intermediate frequency signals SIFA and SIFB are orthogonal with a phase difference of 90 °, and the image components are the intermediate frequency signals SIFA and SIFB. It is orthogonal with a phase difference of 90 ° in the opposite relationship.

  Further, a part of the control voltage supplied to the variable capacitance diode of the VCO (not shown) of the PLL is extracted from the PLL constituting the local oscillation circuit 31, and this control voltage is supplied to the tuning circuit 11 as a tuning voltage. Thus, tuning with respect to the received signal SRX is realized.

  Then, the intermediate frequency signals SIFA and SIFB from the mixer circuits 13A and 13B are supplied to the amplitude phase correction circuit 14 to correct the relative amplitude error and phase error of the intermediate frequency signals SIFA and SIFB, and this error is corrected. The intermediate frequency signals SIFA and SIFB are supplied to the phase shift circuits 16A and 16B through the bandpass filters 15A and 15B. For example, the phase shift is performed so that the intermediate frequency signals SIFA and SIFB are in phase and the image components are out of phase. Is done. Then, the intermediate frequency signals SIFA and SIFB after the phase shift are supplied to and added to the arithmetic circuit 17, and the intermediate frequency signal SIF from which the image component is canceled is extracted from the arithmetic circuit 17.

  Subsequently, the intermediate frequency signal SIF is supplied to the digital processing circuit 20 through the intermediate frequency amplifier 18 and the band pass filter 19 and A / D converted, and predetermined digital processing corresponding to the format of the received signal SRX. And audio signals L and R are extracted.

  The amplifiers 12 and 18 are variable gain amplifiers, and a part of the intermediate frequency signal SIF is supplied from the bandpass filter 19 to the AGC voltage forming circuit 32 to form the AGC voltage VAGC. The AGC voltage VAGC is the amplifier. 18 is supplied as a gain control signal, and AGC is performed for the intermediate frequency stage. Further, the AGC voltage VAGC is supplied as a gain control signal to the high-frequency amplifier 12 through the adding circuit 34, and AGC is performed for the high-frequency stage.

  Further, the intermediate frequency signals SIFA and SIFB output from the mixer circuits 13A and 13B are supplied to the over-input AGC voltage forming circuit 33, and the AGC voltage VOL is increased when the reception level becomes a specified value or more due to an interference wave or the like. The AGC voltage VOL is formed and supplied as a gain control signal to the high frequency amplifier 12 through the adding circuit 34, and a delay AGC is performed on the high frequency stage.

  The above receiving circuit is integrated into a one-chip IC (integrated circuit) except for the tuning circuit 11, the resonance circuit of the PLL 31, and the digital processing circuit 20. Further, the digital processing circuit 20 is also integrated on a single chip.

  Further, a microcomputer 40 is provided as a system control circuit, and an operation switch 41 such as a channel selection switch is connected to the microcomputer 40. When the switch 41 is operated, a predetermined control signal is supplied from the microcomputer 40 to the local oscillation circuit 31, the oscillation frequencies of the local oscillation signals SLOA and SLOB are changed, and the reception frequency is changed.

Further, for example, when the power is turned on, a correction control signal is supplied from the microcomputer 40 to the correction circuit 14, and as described above, the image components included in the intermediate frequency signals SIFA and SIFB are canceled as inverse homologous amplitudes in the arithmetic circuit 17. Thus, the amplitude / phase correction circuit 14 is controlled.
The above is an example of a low IF receiver. In this receiver, AGC is performed by the amplifiers 12 and 18, and therefore the gains of the amplifiers 12 and 18 need to be variable.

FIG. 5 shows an example of a variable gain amplifier. That is, in the circuit shown in FIG. 5, the input signal is taken out through the differential amplifier 51. At this time, the gain AV of the differential amplifier 51 is proportional to the collector current I51 of the transistor Q51 which is a constant current source.
AV = a · I51 [times]
a: a constant.
And at this time
I51 = I52-VCTL / R51
I52: Output current of the constant current source 52
VCTL: Gain control voltage (AGC voltage)
It is.

Therefore,
AV = a (I52−VCTL / R51)
= Aa / R51 · VCTL [times]
A = a ・ I52
Thus, when VCTL = 0, the maximum gain A can be obtained. Further, as shown by a solid line in FIG. 6, when the control voltage VCTL is changed, the gain AV changes linearly.

  Further, in the circuit shown in FIG. 7, an input signal is taken out through resistors R52 and R53 and a differential amplifier 53. At this time, the differential amplifier 53 has a fixed gain. Attenuator circuit 54 is constituted by resistors R52 and R53 and the collector-emitter impedances of transistors Q52 to Q55.

When the control voltage VCTL is changed, the collector currents of the transistors Q52 to Q55 are changed to change the collector-emitter impedance, so that the circuit 54 operates as a variable attenuator circuit. As a result, the total gain AV of the circuit of FIG.
AV = B / (b · VCTL + 1) [times]
B and b are constants and change inversely proportional to the control voltage VCTL as shown by a solid line in FIG.

  Therefore, it is conceivable to perform AGC using the variable gain circuit of FIG. 5 or 7 as the amplifiers 12 and 18 in the receiver of FIG.

For example, there are the following prior art documents.
JP 2001-53564 A

  By the way, when AGC is performed in the receiver, if a constant AGC response characteristic is obtained from a very small reception level to a large reception level, the variable gain amplifier used for the AGC has a gain as shown in FIG. Are required to be linear with respect to the AGC voltage VAGC. That is, the log (AV) is required to have a linear characteristic with respect to the AGC voltage VAGC.

  However, in the variable gain circuit of FIG. 5 or FIG. 7, the gain AV changes with respect to the control voltage VCTL as shown by the solid line in FIG. 6 or FIG. 8, so the decibel value log (AV) of the gain AV is a broken line. It changes as shown by and does not become a linear characteristic. As a result, in general, the response characteristics of AGC are greatly different depending on whether the reception level is low or high.

  Therefore, in conventional receivers, the time constant of the AGC response is determined in consideration of the distortion of the demodulated signal and the rate of change of the received signal. For example, a medium wave receiver has a sufficiently large time constant to obtain good distortion characteristics, and a short wave receiver has a response characteristic that sacrifices the distortion characteristics because the reception level changes relatively quickly due to fading. The speed of was secured.

  However, in the case of a digital broadcasting receiver, since the digital broadcasting system employs OFDM, the signal must always be amplified linearly. In mobile reception, since signal changes due to fading are fast, signal distortion is also important. For this reason, it is difficult to compromise the AGC characteristics as before.

  For example, when the digital broadcast receiver is configured as shown in FIG. 4, the reception level is amplified without distortion over a range of −100 dBm to 0 dBm, and the level of the intermediate frequency signal SIF supplied to the digital processing circuit 20 is Therefore, it is necessary to control the signal level so as to be properly within the dynamic range of the A / D converter circuit in the input stage of the digital processing circuit 20. Therefore, gain control characteristics and total AGC response characteristics in the amplifiers 12 and 18 are extremely important.

  The present invention is intended to solve the above problems.

In this invention,
A conversion circuit that converts an input voltage into an input current proportional to the input voltage;
A resistor to which the input current is supplied;
Grounded first and second transistors;
A voltage comparison circuit for comparing a voltage generated in the resistor by the input current and a collector voltage of the first transistor;
The output of the voltage comparison circuit is supplied to the base of the first transistor, and is also supplied to the base of the second transistor to change exponentially with respect to the input voltage from the collector of the second transistor. The voltage-current converter circuit is designed to obtain the output current.

  According to the present invention, the input voltage can be converted into an input current that changes exponentially. Therefore, when applied to an AGC circuit, an AGC operation with a constant response characteristic can be obtained over a wide input range from a weak signal to a large signal. This also makes it possible to accurately regulate the response characteristics of AGC. Furthermore, when controlling the gain of the variable gain amplifier, the conventional variable gain amplifier can be used.

  FIG. 1 shows an example of a conversion circuit according to the present invention. This conversion circuit converts the control voltage VCTL into the control current ICTL and converts the logarithmic value log (ICTL) so as to change linearly with respect to the control voltage VCTL. Therefore, for example, as shown in FIGS. 5 and 6, a variable gain circuit having a linear relationship between the control current and the gain AV is an object to be controlled.

  In FIG. 1, the control voltage VCTL is supplied to the non-inverting input terminal of the operational amplifier 61, the output terminal is connected to the base of the transistor Q61, and the resistor R61 is connected between the emitter and the ground terminal T62. . The signal voltage obtained at the resistor R61 is supplied to the inverting input terminal of the operational amplifier 61.

  The collector of transistor Q61 is connected to the collector of transistor Q62. This transistor Q62, together with the transistor Q63, constitutes a current mirror circuit 62 with the power supply terminal T61 as a reference potential point. The collector of the transistor Q63 is connected to the inverting input terminal of the operational amplifier 63 for voltage comparison, and is connected to the voltage source of the bias voltage V61 through the resistor R62.

  Further, the output terminal of the operational amplifier 63 is connected to the base of the transistor Q64, the collector thereof is connected to the non-inverting input terminal of the operational amplifier 63, and the emitter thereof is connected to the ground terminal T62. The bases and emitters of n transistors Q71 to Q7n are connected in parallel with the base and emitter of the transistor Q64. As will be described later, the collector currents of the transistors Q71 to Q7n become the control current ICTL.

  The bases of the transistors Q66 and Q67 are connected to each other and to the collector of the transistor Q66, and a constant current source 65 is connected between the collector and the power supply terminal T61. Further, the emitter of the transistor Q66 is connected to the voltage source of the bias voltage V61, the emitter of the transistor Q67 is connected to the collector of the transistor Q64, and the collector of the transistor Q67 is connected to the power supply terminal T61.

  According to such a configuration, the transistors Q64 and Q71 to Q7n are supplied with the same base bias voltage from the collector of the transistor Q64 through the operational amplifier 63. Therefore, the transistors Q64 and Q71 to Q7n It operates as a mirror circuit 65.

And at this time
VA: Potential of the inverting input terminal of the operational amplifier 63 VB: If the potential of the non-inverting input terminal of the operational amplifier 63 is set, 100% negative feedback is applied to the operational amplifier 63 through the transistor Q64.
VB = VA (1)
It becomes.

Also,
VR62: Terminal voltage of resistor R62 VBE66: Base-emitter voltage of transistor Q66 VBE67: Base-emitter voltage of transistor Q67
VA = VR62 + V61 (2)
VBE66 + V61 = VBE67 + VB (3)
It is.

Therefore, from the equations (1) to (3), VBE66−VBE67 = VR62 (4)
It becomes.

Also,
IC66: Collector current (emitter current) of transistor Q66
IC67: Collector current (emitter current) of transistor Q67
given that,
IC66 ＝ α ・ exp （β ・ VBE66） (5)
IC67 ＝ α ・ exp （β ・ VBE67） (6)
α: constant β = q / (K · T)
q: electron charge
K: Boltzmann constant
T: Since it is an absolute temperature, from the formulas (5) and (6), IC66 / IC67 = exp (β (VBE66−VBE67))
By substituting equation (4) for this, IC66 / IC67 = exp (β · VR62) (7)
Is obtained.

And taking the logarithm of this equation (7),
log (IC66) −log (IC67) = β · VR62
And transform this
log (IC67) = -β · VR62 + log (IC66) (8)
It becomes.

On the other hand, since 100% negative feedback is applied to the operational amplifier 61, the terminal voltage of the resistor R61 becomes the voltage VCTL.
IR61: If the current of the resistor R61 is
IR61 = VCTL / R61
It becomes.

This current IR61 is also the collector current of the transistor Q61, and further flows through the current mirror circuit 62 to the resistor R62.
VR62 = IR61 / R62
= R62 / R61 ・ VCTL (9)
It becomes.

Therefore, substituting (9) into (8)
log (IC67) = -γ · VCTL + log (IC66) (10)
γ = β · R62 / R61
It becomes.

Since the transistors Q64 and Q71 to Q7n constitute a current mirror circuit 65,
ICTL: If each collector current of transistors Q71 to Q7n is
ICTL = IC67
And from equation (10)
log (ICTL) = -γ · VCTL + log (IC66) (11)
It becomes.

  Therefore, as indicated by a solid line in FIG. 2, the logarithmic value log (ICTL) of the collector current ICTL is linearly proportional to the control voltage VCTL with a negative coefficient −γ. That is, the control voltage VCTL is converted into the control current ICTL, and its logarithmic value log (ICTL) changes linearly with respect to the control voltage VCTL.

  Accordingly, for example, if the differential amplifier 51 is configured by connecting the transistor Q71 in place of the transistor Q51 in FIG. 5, the decibel value of the gain of the differential amplifier 51 changes linearly with respect to the control voltage VCTL. Become. Further, if each of the amplifiers 12 and 18 in FIG. 4 is composed of a multi-stage differential amplifier, and the constant current source of the differential amplifier is transistors Q71 to Q7n, for example, a wide input range as shown in FIG. The AGC characteristic in which the decibel value of the gain is linear with respect to the AGC voltage VAGC can be obtained.

  Thus, according to the above-described conversion circuit, the control voltage VCTL can be converted into the control current ICTL that changes exponentially. Therefore, the response characteristic is constant over a wide input range from a weak signal to a large signal. AGC operation can be obtained. This also makes it possible to accurately regulate the response characteristics of AGC.

  Furthermore, since the response characteristics of AGC can be made constant over a wide input range, in a digital broadcast receiver, the trade-off between AGC response speed and distortion can be set under more optimal conditions. The equivalent dynamic range in the circuit 20 can be effectively expanded.

  Since the logarithmic value log (ICTL) of the control current ICTL changes linearly with respect to the control voltage VCTL, the gain changes linearly with respect to the control voltage as shown in FIGS. 5 and 6 as a variable gain amplifier. Therefore, the conventional variable gain amplifier can be used as it is. Further, since the relationship between the control voltage VCTL and the control current ICTL is expressed by the equation (11), it is possible to easily cope with a different AGC control voltage range.

  Incidentally, in the conversion circuit shown in FIG. 1, bias currents Ib and Ib of the transistors constituting the operational amplifier 63 flow through the inverting input terminal and the non-inverting input terminal of the operational amplifier 63. When the control voltage VCTL increases, the collector current IC67 of the transistor Q67 decreases and the control current ICTL also decreases. At this time, the current Ib flowing through the non-inverting input terminal of the operational amplifier 63 cannot be ignored, and the conversion characteristics are improved. As shown by a broken line in FIG. Therefore, if gain control is performed, the range in which the decibel value of the gain can be controlled linearly becomes narrow.

  In order to solve such a problem, the collector current IC67 may be set so as to remain sufficiently larger than the base current Ib even when the collector current IC67 becomes small. In this case, the current consumption as the conversion circuit increases.

  Further, in the conversion circuit of FIG. 1, as is clear from the equations (10) and (5), since the absolute temperature T is included in the equation indicating the inclination -γ of the conversion characteristic, as shown in FIG. In addition, the conversion characteristics change depending on the temperature T.

  Therefore, in the conversion circuit shown in FIG. 3, the bias currents Ib and Ib flowing through the operational amplifier 63 can be ignored and temperature compensation is performed.

  First, a compensation circuit for the bias currents Ib and Ib is configured as follows. In other words, in the operational amplifier 63, the differentially connected transistors P61 and P62 and the constant current source transistor P63 constitute a differential amplifier 631, and the transistors P65 and P66 constitute a current mirror circuit 632. A mirror circuit 632 is connected to the differential amplifier 631 as its load.

  Therefore, the operational amplifier 63 is configured in which the base of the transistor P61 is the non-inverting input terminal, the base of the transistor P62 is the inverting input terminal, and the collectors of the transistors P62 and P66 are the output terminals.

  In addition, a transistor Q81 is provided, and a bias voltage V81 is supplied to the base thereof, and a resistor R81 is connected between the emitter and the ground terminal T62 to constitute a constant current source 81. From the collector of the transistor Q81 A constant current Is is taken out. In this case, the bias voltage V81 is connected between the base and emitter of a predetermined number of diode-connected transistors in series, and a DC current is supplied to the series circuit through a resistor, so that both ends of the series circuit are connected. The band gap voltage obtained in

  The current Is is supplied to the transistor Q82. The transistor Q82 constitutes a current mirror circuit 82 together with the transistors Q65 and P63, and is biased by the transistor Q83. The transistor Q65 constitutes the constant current source 65 in FIG. 1. Therefore, the collector current of the transistor Q65 becomes the constant current IC66 in FIG. 1 and IC66 = Is. Further, the collector current of the transistor P63 also has the value Is.

  Further, the collector current of transistor Q83 is supplied to transistor Q84. The transistor Q84, together with the transistors Q85 and Q86, constitutes a current mirror circuit 83. The collectors of the transistors Q85 and Q86 are connected to the bases of the transistors P61 and P62. Therefore, the collector currents of the transistors Q85 and Q86 are supplied to the bases of the transistors P61 and P62 as their bias currents Ib and Ib.

And at this time
hFE: If the current amplification factors of the transistors Q82, Q83, and P61 to P63 are used,
Collector current of transistor Q83 = 3 · Is / hFE
It becomes. In the transistors P61 and P62,
Ib = Is / (2 · hFE)
It is.

Therefore, for example, if the junction area between the base and emitter of the transistors Q85 and Q86 is 1/6 of that of the transistor Q84,
Collector current of transistors Q85 and Q86 = Is / (2 · hFE)
Therefore, the bias currents Ib and Ib flowing through the operational amplifier 63 (bases of the transistors P61 and P62) are canceled by the collector currents of the transistors Q85 and Q86, and linear conversion characteristics are obtained as shown by the solid line in FIG. Can be obtained.

  At this time, the collector current Is (= IC67) of the transistor Q67 is taken out as the base current Is / hFE by the transistor Q87, and the current mirror circuit 84 having an input / output current ratio of 1: (n + 1) by the transistors Q88 and Q89. The base current Is / hFE is supplied as a bias current to the bases of the transistors Q64 and Q71 to Q7n through the current mirror circuit 84, respectively.

  Further, a temperature compensation circuit for conversion characteristics is configured as follows. In other words, the collector of the transistor Q63 constituting the current mirror circuit 62 is connected to the collector of the transistor Q91 on the input side of the current mirror circuit 91, and the transistor Q92 on the output side is used as a constant current source so An amplifier 92 is configured.

  In the differential amplifier 92, a predetermined base bias voltage V92 is supplied to the base of the transistor Q93, and the bias voltage V92 is divided by resistors R91 and R92, and the divided voltage is applied to the base of the transistor Q94. Supplied. The bias voltage V92 is also a band gap voltage similar to the bias voltage V81.

  Therefore, when the control current ICTL is taken out from the collector of the transistor Q63, the control current ICTL flows through the differential amplifier 92 through the current mirror circuit 91. At this time, the control current ICTL is supplied to the resistors R91 and R92. The current is divided into the transistors Q93 and Q94 at a ratio corresponding to the voltage division ratio.

  The control current ICTL shunted to the transistor Q94 is supplied to the resistor R62 through the current mirror circuit 93 constituted by the transistors Q95 and Q96 and further through the diode-connected transistor Q97.

  Therefore, a control current ICTL proportional to the control voltage VCTL flows through the resistor R62. The control current ICTL flowing through the resistor R62 is a current shunted by the differential amplifier 92, and the magnitude thereof is the resistor R91. , R92 and the band gap voltage V92, the control current ICTL flowing through the resistor R62 is a current having a positive temperature coefficient.

  Therefore, the voltage VR62 generated in the resistor R62 also has a positive temperature coefficient. Therefore, by setting the resistors R91 and R92 and the band gap voltage V92 in advance, the temperature change of the conversion characteristic shown in FIG. It can be canceled out by the temperature characteristic of the control current ICTL, and the temperature change of the conversion characteristic can be suppressed.

Further, when the gain AV of the amplifier 51 shown in FIG. 5 is controlled by the control current ICTL, for example, the temperature change of the gain AV can be suppressed. That is, the gain AV of the amplifier 51 shown in FIG.
AV = a · I51 [times]
a: It is indicated by a constant.
a = (1/2) β · RL
RL: load resistance, therefore
AV = β ・ RL ・ I51 / 2 (21)
It is.

Since the current I51 in the equation (21) is the control current ICTL, the equation (21) is
AV = β ・ RL ・ ICTL / 2
= Q / (KT) · RL · ICTL / 2 (22)
It becomes. Therefore, when the load resistance RL is formed in the IC, the load resistance RL changes with temperature, and the transistor has temperature characteristics. Therefore, the gain AV is affected by the temperature.

However, in FIG. 3, the voltage V81 is a band gap voltage and V81 = VBE81 + N / β
VBE81: Base-emitter voltage of transistor Q81
N: represented by a constant, and at this time, the constant N is set so that the temperature characteristic of the voltage V81 can be ignored.

Therefore, the constant current Is taken from the transistor Q81 is
Is = (V81−VBE81) / R81
= (N / β) / R81 (23)
It becomes.

Further, as shown in FIG. 6, the gain AV of the differential amplifier 51 of FIG. 5 has the maximum value A when VCTL = 0, and therefore, for simplicity, when considering the case of VCTL = 0, (11) ceremony,
log (ICTL) = log (IC66)
And
ICTL = IC66 (24)
It becomes. In FIG. 3, the collector current IC66 of the transistor Q66 is equal to the current Is. Therefore, equation (24) is derived from equation (23):
= (N / β) / R81 (25)
It becomes.

So, substituting this equation (25) into equation (22),
AV = β, RL, ICTL / 2 (22)
= Β · RL · ((N / β) / R81) / 2
= (N / 2) ・ RL / R81
It becomes.

  That is, the gain AV of the differential amplifier 51 is determined by a constant that is not affected by temperature and the resistance ratio RL / R81, and the resistance ratio RL / R81 is not affected by temperature. As described above, the conversion characteristics between the control voltage VCTL and the control current ICTL are not affected by the temperature.

  Therefore, when the control voltage VCTL is converted into the control current ICTL by the conversion circuit of FIG. 3 and the gain AV of the differential amplifier 51 as shown in FIG. 5 is controlled by the control current ICTL, for example, the gain AV is reduced to the decibel. The value can be controlled to be linear, and the gain AV is not affected by temperature. Further, since the variation in the resistance ratio RL / R81 is small during the manufacture of the IC, the variation associated with the IC can be suppressed.

  If the variable gain circuit shown in FIG. 7 is connected in multiple stages, the control current ICTL is supplied to the transistors Q52 to Q55, and the portion corresponding to the vicinity of VCTL = 0 in FIG. 8 is not used. A characteristic close to the control characteristic shown in FIG. 9 can also be obtained.

[List of abbreviations]
A / D: Analog to Digital
AGC: Automatic Gain Control
IC: Integrated Circuit
IF: Intermediate Frequency
OFDM: Orthogonal Frequency Division Multiplex
PLL: Phase Locked Loop
VCO: Voltage Controlled Oscillator
Operational Amplifier: Operational Amplifier

It is a connection diagram showing one embodiment of the present invention. It is a characteristic view for demonstrating this invention. It is a connection diagram which shows the other form of this invention. It is a systematic diagram which shows an example of the application object of this invention. It is a connection diagram for explaining the present invention. FIG. 6 is a characteristic diagram for explaining the circuit of FIG. 5. It is a connection diagram for explaining the present invention. It is a characteristic view for demonstrating the circuit of FIG. It is a characteristic view for demonstrating this invention.

Explanation of symbols

  61 and 63 ... operational amplifiers, 62 and 65 ... current mirror circuit, ICTL ... control current, VCTL ... control voltage

Claims (7)

A conversion circuit that converts an input voltage into an input current proportional to the input voltage;
A resistor to which the input current is supplied;
Grounded first and second transistors;
A voltage comparison circuit for comparing a voltage generated in the resistor by the input current and a collector voltage of the first transistor;
The output of the voltage comparison circuit is supplied to the base of the first transistor, and is also supplied to the base of the second transistor to change exponentially with respect to the input voltage from the collector of the second transistor. A voltage-current converter circuit that obtains output current. The voltage-current converter circuit according to claim 1,
The voltage comparison circuit is composed of an operational amplifier,
A voltage-current converter circuit that has a circuit that compensates for the bias current flowing through the input terminal of this operational amplifier. In the voltage-current converter circuit of Claim 1 or Claim 2,
A temperature compensation circuit is provided in the current line between the conversion circuit and the resistor,
A voltage-current conversion circuit configured to perform temperature compensation of conversion characteristics between the input voltage and the output current by the temperature compensation circuit. A variable gain amplifier whose gain varies linearly with respect to the control current;
A conversion circuit for converting the AGC voltage into an AGC current proportional to the AGC voltage;
A resistor to which the AGC current is supplied;
Grounded first and second transistors;
A voltage comparison circuit for comparing a voltage generated in the resistor by the AGC current and a collector voltage of the first transistor;
The output of the voltage comparison circuit is supplied to the base of the first transistor, and is also supplied to the base of the second transistor to change exponentially with respect to the AGC voltage from the collector of the second transistor. Take out the control current,
An AGC circuit that controls the gain of the variable gain amplifier by the control current. A variable attenuator circuit whose gain varies inversely with the control current;
A conversion circuit for converting the AGC voltage into an AGC current proportional to the AGC voltage;
A resistor to which the AGC current is supplied;
Grounded first and second transistors;
A voltage comparison circuit for comparing a voltage generated in the resistor by the AGC current and a collector voltage of the first transistor;
The output of the voltage comparison circuit is supplied to the base of the first transistor, and is also supplied to the base of the second transistor to change exponentially with respect to the AGC voltage from the collector of the second transistor. Take out the control current,
An AGC circuit in which the gain of the variable attenuator circuit is controlled by this control current. A conversion circuit that converts an input voltage into an input current proportional to the input voltage;
A resistor to which the input current is supplied;
Grounded first and second transistors;
A voltage comparison circuit that compares the voltage generated in the resistor by the input current with the collector voltage of the first transistor is formed into a one-chip IC.
The output of the voltage comparison circuit is supplied to the base of the first transistor, and is also supplied to the base of the second transistor to change exponentially with respect to the input voltage from the collector of the second transistor. An integrated circuit designed to obtain output current. The integrated circuit of claim 6, wherein
A variable gain amplifier whose gain varies linearly with respect to the control current,
The input voltage is an AGC voltage,
An integrated circuit configured to perform AGC by supplying the output current varying exponentially as a control current to the variable gain amplifier.

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