JP2005269033A - Ip network terminal - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To adjust reception throughput adaptively to temporary increase in received load without lowering the throughput of CPU with simple circuit configuration. <P>SOLUTION: A receiving buffer management circuit 103 stores received packet data in a receiving buffer 104 and informs a first level representing the residual capacity of the receiving buffer 104 stepwise to a receiving load operating circuit 106. Upon reading out the received packet data from the receiving buffer 104, a CPU 105 informs the data capacity of the packet data thus read out to the receiving buffer management circuit 103 and informs the information of the number of packet data thus read out, as the number of processing the received packet, to the receiving load operating circuit 106. The receiving load operating circuit 106 determines the state of received load by obtaining multiplication results of the first level and a second level representing the number of unprocessed received packet data stored in the receiving buffer 104 stepwise and controlling the transmission timing of a transmission timing generating circuit 107. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an IP network terminal device that includes an IP (Internet Protocol) interface and receives data from a network such as the Internet and transmits data to the network.

  A conventional IP network terminal device will be described with reference to FIG. As shown in FIG. 11, the conventional IP network terminal apparatus includes an ETHER reception I / F 302, an IP reception I / F 303, a reception buffer 304, a CPU 305, a transmission buffer 306, an IP transmission I / F 307, , ETHER transmission I / F 308.

  The ETHER reception I / F 302 has a termination function of Ethernet (registered trademark) as a physical interface for network line reception. The ETHER reception I / F 302 transfers the received packet data determined to be a MAC (Media Access Control) address to be received by the terminal device to the IP reception I / F 303.

  The IP reception I / F 303 has an IP termination function, and stores received packet data, which is determined to be an IP address to be received by its own terminal device, in the reception buffer 304.

  The CPU 305 reads unprocessed received packet data from the reception buffer 304 and performs processing according to the upper protocol. On the other hand, the CPU 305 stores the transmission packet data generated by the upper protocol in the transmission buffer 306.

  The IP transmission I / F 307 reads transmission packet data from the transmission buffer 306, generates IP packet data with the destination IP address and the source terminal device as the source IP address, and transfers the IP packet data to the ETHER transmission I / F 308.

  The ETHER transmission I / F 308 performs a physical interface for network line transmission, and transmits IP packet data as Ethernet packet data. The CPU 305 performs these reception processing and transmission processing independently and asynchronously.

  In such a conventional IP network terminal device, when reception and transmission processing for an IP network line is performed by a single CPU, reception processing and transmission processing are independently performed asynchronously. In an IP network, the data arrival time at the receiving terminal device may fluctuate due to the characteristics of the transmitting terminal device and the network, and a large amount of data may be received in a short time. In such a case, the conventional IP network terminal has the following problems.

  In a conventional IP network terminal device, transmission processing is performed regardless of the state of reception processing. Therefore, when a large amount of data is received in a short time and the transmission processing is accidentally concentrated, the CPU temporarily processes. It can happen that there is a shortage. In this case, reception processing is not in time, the reception buffer overflows, and reception data is lost. If the CPU detects a lack of received data before it recovers from a lack of processing power and a retransmission request is immediately sent by the higher-level protocol, a large amount of retransmission data arrives, and the state of insufficient processing power is chained. It can happen.

  In order to prevent such a problem, a network terminal apparatus having a function of determining a reception load state and ensuring a reception processing capability by suppressing transmission processing has been proposed (for example, see Patent Documents 1, 2, and 3). ). However, in such a network terminal device, the CPU supports functions for determining the reception load state and ensuring the reception processing capability by suppressing the transmission processing, so that complicated software processing is required. As a result, the overall processing capacity is reduced.

  Further, when a large-capacity reception buffer is used to increase the reception processing time, in a protocol that places importance on the immediacy of data, the delay time is exceeded before the corresponding data is processed, and data can be discarded.

From the above, in a network environment in which a large amount of data is received in a short time, communication quality may deteriorate in a conventional IP network device.
JP-A-2-16840 Japanese Patent Laid-Open No. 10-49344 JP 2000-17479 A

The above-described conventional IP network terminal device has the following problems.
(1) Since the transmission process is performed regardless of the state of the reception process, a large amount of data is received in a short time, and at the same time, if the transmission process is accidentally concentrated, the CPU temporarily becomes insufficient in processing capacity. Happen, and stable reception is not possible.
(2) In order to determine the reception load and to secure the reception processing capacity, a complicated software process is required in which the CPU determines the reception load state and the transmission load state and determines the distribution of the processing capacity. For this reason, the overall processing capacity is reduced.

  An object of the present invention is to provide an IP network terminal device that adjusts reception processing capacity in response to a temporary increase in reception load without causing a reduction in PU processing capacity with a simple circuit configuration.

In order to achieve the above object, the present invention provides an IP network terminal device that includes an IP interface and receives data from a network and transmits data to the network.
A receive buffer for storing received packet data;
A multiplication result of a first level value that represents the remaining capacity of the reception buffer stepwise and a second level value that represents the number of unprocessed received packet data stored in the reception buffer stepwise. A receiving load calculation circuit for determining a receiving load state by
And a transmission timing generation circuit for controlling the transmission timing so that the transmission interval becomes longer when the reception load is high based on the determination result of the reception load state in the reception load arithmetic circuit.

  According to the present invention, the reception load operation circuit determines the reception load state in consideration of the state of the number of unprocessed packets and the state of the remaining buffer capacity by multiplying the first level value and the second level value. In the transmission timing generation circuit, the reception processing capability is ensured by controlling the transmission timing according to the reception load state and suppressing the transmission load of the CPU. Accordingly, stable data reception can be performed in response to a temporary increase in reception load. Further, since the transmission interval is generated by the transmission timing generation circuit, the CPU can control the suppression of the transmission process without performing complicated software processing.

  As described above, according to the present invention, the following effects can be obtained.

  (1) The number of unprocessed packets stored in the reception buffer and the remaining capacity of the reception buffer are converted into level values, respectively, and the reception load state is determined based on a calculation result obtained by multiplying the level values. Therefore, it is possible to simultaneously determine the excessive number of unprocessed packets and the shortage of the buffer remaining capacity, and adjust the reception processing capacity to adapt to the temporary increase in reception load.

  (2) Since the transmission interval is generated by the transmission timing generation circuit, the CPU can control the suppression of the transmission process without performing complicated software processing.

  Next, embodiments of the present invention will be described in detail with reference to the drawings.

(First embodiment)
According to the present invention, in a terminal device having an IP network interface function by a CPU, even if a temporary load occurs on the receiving side, the processing on the transmitting side is suppressed by suppressing the processing on the transmitting side according to the load state on the receiving side. It is characterized by ensuring reception processing capability and enabling stable reception. FIG. 1 shows the configuration of the IP network terminal device 1 according to the first embodiment of the present invention.

  As shown in FIG. 1, the IP network terminal device 1 of the present embodiment includes an ETHER reception I / F 101, an IP reception I / F 102, a reception buffer management circuit 103, and reception for storing received packet data. A buffer 104, a CPU 105, a reception load calculation circuit 106, a transmission timing generation circuit 107, a transmission buffer 108 for storing packet data to be transmitted, an IP transmission I / F 109, an ETHER transmission I / F 110, It has.

  The ETHER reception I / F 101 has an Ethernet termination function as a physical interface for network line reception. The ETHER reception I / F 101 receives the Ether packet data from the network line, and transfers the reception packet data determined to be a MAC (Media Access Control) address to be received by the terminal device to the IP reception I / F 102.

  The IP reception I / F 102 has an IP termination function. When it is determined that the IP address of the packet data transferred from the ETHER reception I / F 101 is an IP address to be received by the terminal device, The reception packet data is transferred to the reception buffer management circuit 103. The IP reception I / F 102 notifies the reception load calculation circuit 106 every time that the received packet data has been transferred to the reception buffer management circuit 103.

  The ETHER reception I / F 101 and the IP reception I / F 102 constitute a packet data reception unit that receives packet data addressed to its own terminal.

  The reception buffer management circuit 103 stores the reception packet data of the IP reception I / F 102 in the reception buffer 104 and subtracts the data capacity of the stored packet data from the data capacity of the reception buffer 104 as the remaining capacity of the reception buffer 104. to manage. Upon receiving notification from the CPU 105 that the packet data stored in the reception buffer 104 has been processed, the reception buffer management circuit 103 adds the data capacity of the processed packet data to the remaining capacity, The received load calculation circuit 106 is notified as a first level value that represents the remaining capacity in stages.

  The CPU 105 reads the received packet data stored in the reception buffer 104 at any time, and performs upper protocol processing. When the CPU 105 reads the received packet data from the reception buffer 104, the CPU 105 notifies the reception buffer management circuit 103 of the data capacity of the read packet data, and sends the information of the read packet data number to the reception load calculation circuit 106 as the received packet processing number. Notice. Further, when a transmission timing is input from the transmission timing generation circuit 107 as a transmission process, the CPU 105 performs an operation of storing packet data to be transmitted in the transmission buffer 108 based on the input transmission timing. The transmission timing is input as an interrupt signal, and the number of transmission packets within a specified number is stored in the transmission buffer 108 by one interrupt input.

  The reception load calculation circuit 106 has a first level value that represents the remaining capacity of the reception buffer 104 stepwise and a second level that represents the number of unprocessed received packet data stored in the reception buffer 104 stepwise. By determining the multiplication result with the level value, the reception load state is determined, and the transmission timing of the transmission timing generation circuit 107 is controlled. The number of unprocessed received packets is incremented by one packet upon receiving a notification from the IP reception I / F 102, and the number of processed packets when receiving a notification of the number of packets processed by collecting data stored in the reception buffer 104 from the CPU 105. Only managed by subtracting. Therefore, the number of packet data received by the IP reception I / F 102 minus the number of received packet processes notified by the CPU 105 is the number of unprocessed received packet data. Here, the second level value is determined such that the value increases as the number of unprocessed received packets increases.

  The multiplication result output from the reception load calculation circuit 106 becomes a large value when the reception load is high, that is, when the remaining capacity of the reception buffer 104 is small and the number of unprocessed packets is large. When the remaining capacity is large and the reception load is low, the value is small.

  The transmission timing generation circuit 107 generates transmission processing start timings at regular intervals and outputs them to the CPU 105. If the reception load is high based on the reception load state determination result in the reception load calculation circuit 106, the transmission interval is generated. The transmission timing is controlled so that becomes longer. Specifically, the transmission timing generation circuit 107 divides the clock for generating the transmission timing by the value of the calculation result output from the reception load calculation circuit 106. The larger the output value of the reception load calculation circuit 106 is, the larger the frequency division value becomes, so that the cycle of the transmission timing becomes longer, and the transmission output process of the CPU 105 is suppressed.

  The IP transmission I / F 109 reads packet data from the transmission buffer 108 as needed, generates IP packet data with the destination IP address and the source terminal device as the source IP address, and transfers the IP packet data to the ETHER transmission I / F 110.

  The ETHER transmission I / F 110 performs a physical interface for network line transmission, and transmits IP packet data as Ethernet packet data.

  The ETHER transmission I / F 110 and the IP transmission I / F 109 constitute a packet data transmission unit that transmits packet data stored in the transmission buffer 108.

  Next, the configuration of the reception load calculation circuit 106 and the transmission timing generation circuit 107 will be described with reference to FIG. The reception load calculation circuit 106 includes an up / down counter 201, a level determination circuit 202, and a multiplier 203.

  The up / down counter 201 counts the number of unprocessed received packets stored in the reception buffer 104. The up / down counter 201 counts up every time there is a packet reception notification from the IP reception I / F 102, and counts down the number of processings every time there is a notification of the received packet processing count from the CPU 105. By this repeated operation, the count value of the up / down counter 201 becomes the number of unprocessed packets.

  The level determination circuit 202 determines several levels of state levels based on the magnitude of the count value of the up / down counter 201, and inputs the determination result to the multiplier 203 as a second level value. The multiplier 203 calculates a value obtained by multiplying the first level value based on the remaining capacity input from the reception buffer management circuit 103 and the second level value based on the number of unprocessed packets input from the level determination circuit 202. The first level value based on the remaining capacity increases as the remaining capacity of the buffer 104 decreases. The second level value based on the number of unprocessed packets increases as the number of unprocessed packets increases. That is, the calculation result of the multiplier 203 takes the largest value when there is no remaining capacity of the buffer 104 and the number of unprocessed packets is the maximum.

  Further, as shown in FIG. 2, the transmission timing generation circuit 107 includes an oscillator 206, a dividing period 205, and a variable frequency divider 204.

  The frequency divider 205 divides the clock output from the oscillator 206 at a fixed frequency division ratio, and determines the shortest interval of the transmission timing input to the CPU 105. The variable frequency divider 204 further divides the frequency-divided clock output from the frequency divider 205 according to the calculation result output from the multiplier 203 of the reception load calculation circuit 106. The smaller the remaining capacity of the buffer 104 and the larger the number of unprocessed packets, the larger the frequency division ratio of the variable frequency divider 204 and the longer the transmission timing interval to the CPU 105.

  Next, the operation of the IP network terminal device 1 of this embodiment will be described in detail with reference to the drawings.

  In the IP network terminal apparatus 1 shown in FIG. 1, the operation of increasing the reception of IP packet data and reducing the transmission rate to suppress the transmission processing load will be described using the flowchart of FIG.

  In FIG. 1, when the IP network terminal device 1 receives Ethernet packet data from the network line, the ETHER reception I / F 101 confirms the MAC address and CRC (Cyclic Redundancy Check) code of the received packet data, and The normal reception packet data is transferred to the IP reception I / F 102. The IP reception I / F 102 terminates the IP protocol, and transfers the received packet data of the IP address to be received by the terminal device to the reception buffer management circuit 103. At the same time, the reception load calculation circuit 106 is notified by the pulse signal that the received packet data has been transferred (step 401).

  The reception buffer management circuit 103 stores the reception packet data in the reception buffer 104. The reception buffer management circuit 103 knows the total capacity of the reception buffer 104 in advance, and calculates the remaining capacity of the buffer 104 by subtracting from the total buffer capacity according to the data size every time reception packet data is stored. To do. The reception buffer management circuit 103 outputs the remaining capacity of the reception buffer 104 to the reception load calculation circuit 106 as a first level value divided into several stages (step 402).

  An example of the remaining capacity of the reception buffer and the first level value is shown in FIG. The remaining capacity 100% to 0% of the reception buffer 104 is divided into four levels. As the remaining capacity decreases, the first level value changes to 1, 2, 4, and 8 to the reception load calculation circuit 106. Entered.

  On the other hand, the reception arithmetic circuit 106 to which the pulse signal is input from the IP reception I / F 102 counts the number of unprocessed packets stored in the reception buffer 104 (step 403). The counting is performed by the up / down counter 201 in FIG. The maximum count value of the up / down counter 201 is obtained when the IP reception packet having the minimum size is stored in the entire capacity of the reception buffer 104. The level determination circuit 202 in FIG. 2 determines the second level value divided into several stages based on the count value of the up / down counter 201.

  An example of the count value and the second level value is shown in FIG. The number of packets that can be stored in the reception buffer 104, that is, the maximum count value of the up / down counter 201 is set to 1024, and is equally divided into four stages. As the count value increases, the second level value is 1, 2, 4 , 8 changes.

  When the remaining capacity of the reception buffer 104 changes from 55% to 45% and the number of unprocessed packets changes from 250 to 300, the reception load calculation circuit 106 operates as follows. In FIG. 2, the value of the up / down counter 201 increases from 250 to 300, and the level determination circuit 202 updates the second level value from 1 to 2 from the relationship of FIG. Since the remaining capacity has decreased from 55% to 45%, the reception buffer management circuit 103 updates the first level value from 2 to 4 from the relationship of FIG. As a result, the calculation result of the multiplier 203 in FIG. 2 changes from 2 to 8. The reception load calculation circuit 106 updates the calculation result from 2 to 8, and outputs it to the transmission timing generation circuit 107 (step 404).

  The transmission timing generation circuit 107 divides the maximum transmission rate timing output from the oscillator 206 and the frequency divider 205 shown in FIG. The timing is changed to the rounded timing and output to the CPU 105 (step 405). The transmission processing timing of the CPU 105 is reduced to 1/8 of the maximum rate. As a result, the transmission processing load is suppressed, and the reception processing is increased accordingly.

  Next, an operation in which the suppression of transmission processing is alleviated by the progress of packet processing in the reception buffer 104 of the CPU 105 will be described using the flowchart of FIG. When the CPU 105 processes the packet data in the reception buffer 104, the remaining capacity of the reception buffer 104 changes from 45% to 50% and the number of unprocessed packets changes from 300 to 260 (step 501). The circuit 106 operates as follows.

  The reception buffer management circuit 103 updates the first level value from 4 to 2 and inputs it to the reception load calculation circuit 106 based on the relationship of FIG. 4 (step 502). In the reception load calculation circuit 106, the count value of the up / down counter 201 is down-counted (step 503), but the second level value is maintained at 2 from the relationship of FIG. From these level value changes, the operation result of the multiplier 203 changes from 8 to 4. The reception load calculation circuit 106 updates the calculation result from 8 to 4, and outputs it to the transmission timing generation circuit 107 (step 504). The transmission timing generation circuit 107 changes the maximum transmission rate timing from the timing divided by 1/8 by the variable frequency divider 204 to the timing divided by 1/4, and outputs it to the CPU 105 (step 505). The transmission processing timing of the CPU 105 increases from 1/8 to 1/4 of the maximum rate. As a result, transmission processing suppression is alleviated and the reception processing enhancement effect is reduced.

  The CPU 105 inputs the transmission timing as an interrupt signal, but interrupt processing becomes excessive for one packet transmission by one interrupt. Therefore, as shown in the flowchart of FIG. 7, the CPU 105 stores the number of transmission packets up to a predetermined number in the transmission buffer by one interrupt input. If the specified number is 20 packets and there are 30 packets to be transmitted, the CPU 105 receives an upper limit of 20 packets to the transmission buffer 108 when an interrupt is input as the transmission timing from the transmission timing generation circuit 107 (step 601). Store. Next, when the transmission timing is input, the CPU 105 stores the remaining 10 packets in the transmission buffer 108 (step 602). The IP transmission I / F 109 reads packet data from the transmission buffer 108 at any time, and generates IP packet data with the destination IP address and the source terminal device as the source IP address (step 603). The ETHER transmission I / F 110 performs a physical interface for network line transmission, and transmits IP packet data as Ethernet packet data.

  As described above, in the IP network terminal device 1 of the present embodiment, the number of unprocessed received packets stored in the reception buffer 104 and the remaining reception buffer by the reception buffer management circuit 103 and the reception load calculation circuit 106. Manage capacity. Even if there is a remaining capacity of the reception buffer, the size of the stored packet is small and the number is large, the reception load is high. Even when the number of received packets is small, the reception load is high even when the packet size is large and the remaining buffer capacity is small. Therefore, in the IP network terminal device 1 of the present embodiment, the number of unprocessed packets in the reception buffer 104 and the reception buffer are obtained by multiplying the state of the number of unprocessed packets and the state of the buffer remaining capacity by the reception load arithmetic circuit 106. The reception load state is determined by simultaneously evaluating the remaining capacity of 104, and the reception load state is determined. In a state where the reception load is high, the transmission timing interval of the transmission timing generation circuit 107 is lengthened, and the transmission load of the CPU 105 is suppressed, so that the reception processing capability is ensured. Therefore, stable data reception can be performed in response to a temporary increase in reception load. In this embodiment, since the transmission interval is generated by the transmission timing generation circuit 107, the CPU 105 can control the suppression of the transmission process without performing complicated software processing.

(Second Embodiment)
Next, an IP network terminal apparatus according to the second embodiment of the present invention will be described.

  An IP network terminal apparatus according to the second embodiment of the present invention is shown in FIG. In FIG. 8, the same components as those in FIG. 1 are denoted by the same reference numerals, and the description thereof is omitted.

  As shown in FIG. 8, the IP network terminal apparatus 8 of the present embodiment deletes the transmission timing generation circuit 107 from the IP network terminal apparatus 1 of the first embodiment shown in FIG. The reception load calculation circuit 106 is replaced with a CPU 803 and a reception load calculation circuit 801, respectively.

  Next, FIG. 9 shows the configuration of the reception load calculation circuit 801 in FIG. In FIG. 9, the same components as those in FIG. 2 are denoted by the same reference numerals, and description thereof is omitted. As shown in FIG. 9, the reception load calculation circuit 801 in this embodiment has a configuration in which a level determination circuit 802 is added after the multiplier 203 to the reception load calculation circuit 106 shown in FIG. 2. Yes.

  The level determination circuit 802 determines the transmission priority based on the multiplication result from the multiplier 203, and generates and outputs a transmission permission signal based on the transmission priority.

  In this embodiment, instead of inputting the transmission timing to the CPU 803, a transmission permission signal corresponding to the transmission priority is directly input from the reception load calculation circuit 801, so that the configuration shown in FIG. The transmission timing generation circuit 107 that has been used becomes unnecessary.

  The transmission processing on the CPU 803 side is classified into four priority levels in advance according to the service type and transmission destination of the transmission packet. The highest priority, priority (1), priority (2), and priority (3) are in this order. The highest-priority packet can be transmitted at an arbitrary timing regardless of the load state on the receiving side, but the minimum packet transmission is limited so as not to occupy the CPU processing. Packet transmissions with priorities (1) to (3) are transmitted according to the transmission permission signal output from the reception load calculation circuit 801. The transmission permission signal of the reception load calculation circuit 801 is output from the level determination circuit 802 in FIG.

  FIG. 10 shows the relationship between the operation value of the multiplier 203 indicating the reception load state and the level determination circuit 802. The range of arithmetic values 0 to 64 of the multiplier 203 is equally divided into four stages, and between 0 and 15 indicating a low reception load state, the level determination circuit 802 has all the priorities (1) to (3). The transmission permission signal is output. As the reception load increases, the transmission permission signal is stopped in ascending order of priority. When the multiplier 203 has a high reception load of 48 to 64, all transmission permission signals are stopped. In accordance with the transmission permission signal output in this way, the CPU 803 stores transmission packets with priority in the permitted state in the transmission buffer 108.

It is a block diagram which shows the structure of the IP network terminal device of the 1st Embodiment of this invention. FIG. 2 is a block diagram illustrating configurations of a reception load calculation circuit 106 and a transmission timing generation circuit 107 in FIG. 1. It is a flowchart which shows operation | movement of the IP network terminal device of FIG. 6 is a flowchart showing an operation of suppressing transmission processing load by reducing the transmission rate by increasing reception of IP packet data in the IP network terminal apparatus 1 shown in FIG. 1. It is a figure which shows the example of receiving buffer remaining capacity and a level value. It is a figure which shows the example of a count value and a level value. It is a flowchart for demonstrating the operation | movement by which suppression of a transmission process is eased because the packet process in the reception buffer of CPU105 progresses. It is a flowchart for demonstrating the operation | movement which CPU105 stores the transmission packet number to a predetermined number to a transmission buffer by one interruption input. It is a block diagram which shows the structure of the IP network terminal device of the 2nd Embodiment of this invention. It is a block diagram which shows the structure of the receiving load calculating circuit 801 in FIG. 6 is a diagram illustrating a relationship between a calculated value of a multiplier 203 indicating a reception load state and a level determination circuit 802. FIG. It is a block diagram which shows the structure of the conventional IP network terminal device.

Explanation of symbols

1 IP network terminal device 8 IP network terminal device 101 ETHER reception I / F
102 IP reception I / F
103 reception buffer management circuit 104 reception buffer 105 CPU
106 reception load calculation circuit 107 transmission timing generation circuit 108 transmission buffer 109 IP transmission I / F
110 ETHER transmission I / F
201 Up / Down Counter 202 Level Determination Circuit 203 Multiplier 204 Variable Divider 205 Divider 206 Oscillator 301 IP Network Terminal 302 ETHER Reception I / F
303 IP reception I / F
304 Reception buffer 305 CPU
306 Transmission buffer 307 IP transmission I / F
308 ETHER transmission I / F
401 to 405 Step 501 to 505 Step 601 to 603 Step 801 Reception load calculation circuit 802 Level determination circuit 803 CPU

Claims (6)

An IP network terminal device comprising an IP interface and receiving data from a network and transmitting data to the network,
A receive buffer for storing received packet data;
A multiplication result of a first level value that represents the remaining capacity of the reception buffer stepwise and a second level value that represents the number of unprocessed received packet data stored in the reception buffer stepwise. A receiving load calculation circuit for determining a receiving load state by
An IP network terminal apparatus comprising: a transmission timing generation circuit that controls transmission timing so that a transmission interval is lengthened when a reception load is high based on a determination result of a reception load state in the reception load calculation circuit. An IP network terminal device comprising an IP interface and receiving data from a network and transmitting data to the network,
A packet data receiving unit for receiving packet data addressed to the own terminal;
A receive buffer for storing received packet data;
A transmission buffer for storing packet data to be transmitted;
A packet data transmitter for transmitting packet data stored in the transmission buffer;
The packet data received by the packet data receiving unit is stored in the reception buffer, a value obtained by subtracting the data capacity of the stored packet data from the data capacity of the reception buffer is managed as the remaining capacity of the reception buffer, and the reception When a notification that the packet data stored in the buffer has been processed is received, a data level of the processed packet data is added to the remaining capacity, and a first level value that represents the current remaining capacity stepwise A receive buffer management circuit that outputs as
When the received packet data stored in the reception buffer is read and the processing in the upper protocol is performed and the received packet data is read from the reception buffer, the data capacity of the read packet data is notified to the reception buffer management circuit. A CPU that outputs information on the number of read packet data as a received packet processing number and stores packet data to be transmitted based on the input transmission timing in the transmission buffer;
A number obtained by subtracting the number of received packet processes notified by the CPU from the number of packet data received by the packet data receiving unit is defined as the number of unprocessed received packet data, and the number of unprocessed received packets is represented stepwise. A reception load calculation circuit that outputs a result of multiplying the level value of 2 by the first level value notified from the reception buffer management circuit;
An IP network terminal apparatus comprising: a transmission timing generation circuit that divides a clock having a constant frequency according to a value of a multiplication result output from the reception load calculation circuit and outputs the divided clock to the CPU as the transmission timing. The reception load calculation circuit is
An up-down counter that counts up each time packet data is received by the packet data receiving unit, and counts down the number of processes each time there is a notification of the number of received packet processes from the CPU;
A level determination circuit that determines a plurality of state levels based on the magnitude of the count value of the up / down counter and outputs the state level as the second level value;
3. The IP network terminal device according to claim 2, further comprising: a multiplier that multiplies the first level value by a second level value from the level determination circuit and outputs the multiplication result. 4. The transmission timing generation circuit is
An oscillator that generates and outputs a clock with a constant frequency;
A frequency divider that divides and outputs a clock output from the oscillator by a fixed frequency division ratio;
A variable frequency divider configured to further divide the frequency-divided clock output from the frequency divider according to a multiplication result output from the multiplier and output the divided clock as a transmission timing to the CPU. 3. The IP network terminal device according to 3. An IP network terminal device comprising an IP interface and receiving data from a network and transmitting data to the network,
A packet data receiving unit for receiving packet data addressed to the own terminal;
A receive buffer for storing received packet data;
A transmission buffer for storing packet data to be transmitted;
A packet data transmitter for transmitting packet data stored in the transmission buffer;
The packet data received by the packet data receiving unit is stored in the reception buffer, a value obtained by subtracting the data capacity of the stored packet data from the data capacity of the reception buffer is managed as the remaining capacity of the reception buffer, and the reception When a notification that the packet data stored in the buffer has been processed is received, a data level of the processed packet data is added to the remaining capacity, and a first level value that represents the current remaining capacity stepwise A receive buffer management circuit that outputs as
When the received packet data stored in the reception buffer is read and the processing in the upper protocol is performed and the received packet data is read from the reception buffer, the data capacity of the read packet data is notified to the reception buffer management circuit. A CPU that outputs information on the number of read packet data as a received packet processing number, and stores packet data to be transmitted based on the input transmission permission signal in the transmission buffer;
A number obtained by subtracting the number of received packet processes notified by the CPU from the number of packet data received by the packet data receiving unit is defined as the number of unprocessed received packet data, and the number of unprocessed received packets is represented stepwise. 2 and a first level value notified from the reception buffer management circuit, a transmission priority is determined, and the transmission permission signal based on the transmission priority is sent to the CPU. An IP network terminal device comprising: a reception load calculation circuit for outputting. The reception load calculation circuit is
An up-down counter that counts up each time packet data is received by the packet data receiving unit, and counts down the number of processes each time there is a notification of the number of received packet processes from the CPU;
A first level determination circuit that determines a plurality of state levels based on the count value of the up / down counter and outputs the state level as the second level value;
A multiplier that multiplies the first level value by a second level value from the first level determination circuit and outputs the multiplication result;
6. A second level determination circuit that determines a transmission priority based on the multiplication result, generates the transmission permission signal based on the transmission priority, and outputs the signal to the CPU. IP network terminal device.

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