JP2005267254A - Interfacing device, image processor, and image forming device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize a power consumption saving mode even when the power consumption saving mode is not realized by a function of an interface. <P>SOLUTION: An I/F controller issues a power-on indication to an electric power source part (S2), when detecting negotiation from a host computer (PC hereinafter)(S1), and a CPU starts booting (S3). The I/F controller processes concurrently the negotiation from the PC, starts reception of a data from the PC (S5), when finishing the processing (S4), and accumulates the data in an FIFO circuit (S6). Transfer from the FIFO circuit is set to disable, during the power consumption saving mode, and an electric power source interruption is enabled. When booted by the CPU (S7), the CPU starts transfer in a DMA controller (S8). A memory controller transfers therein the reception data to a RAM, using the DMA controller, while receiving a control signal from a timer/transfer control part, since a large volume of data is accumulated in the FIFO circuit. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an interface device with a peripheral device connected to a host PC through a parallel interface, an image processing device including the interface device, and an image forming apparatus including the image processing device.

  Conventionally, for example, an IEEE1284 standard interface is known as a parallel interface. This interface is used as an interface on the printer side when connecting the printer and the host computer as a Centronics I / F controller. An example of this is shown in FIG. In the figure, a host computer 100 is connected to a printer via a Centronics I / F controller 111. The Centronics I / F controller 111 is connected to a DMA (Direct Memory Access) controller 112 and a power supply control unit 113.

  The image processing unit 120 basically includes a memory controller 121, a CPU 122, a RAM 123, and a ROM 124, a power control unit 113 is connected to the CPU 122, and a DMA controller 112 is connected to the memory controller 121. With this configuration, the image data sent from the host computer 100 is stored in the RAM 113 and further stored in a large capacity storage means such as an HDD (not shown), and an image is output from a printer engine (not shown) based on the image data. It is like that.

As a related technique, for example, the invention disclosed in the following Patent Document 1 or 2 is known.
JP 2000-187578 A Japanese Patent Application Laid-Open No. 2002-244834

  By the way, in the conventional products that support IEEE1284 I / F, since it is not known when negotiation and data transfer start, the CPU cannot be turned off, and the sleep mode is used to monitor the 1284 I / F controller periodically. It was impossible even to enter. Therefore, a low power consumption mode (energy saving mode) cannot be realized by using a conventional Centronics I / F controller. The same can be said for those having the same characteristics as IEEE 1284 I / F.

  The present invention has been made in view of the actual situation of the prior art, and an object thereof is to realize the power saving mode even when the power saving mode cannot be realized by the function of the interface. Is to be able to.

  In order to achieve the above object, the first means shuts off the power supply of each part of the processing apparatus in the subsequent stage in the low power consumption mode, and the return from the low power consumption mode is performed when the interface controller and the host computer start negotiation. In the interface device for supplying power to the power controller, the FIFO circuit and the DMA controller provided between the interface controller and the processing device, and the data transfer from the interface controller to the FIFO circuit in the low power consumption mode And a control means for preventing transfer from the FIFO circuit to the DMA controller.

  The second means is an interface device that shuts off the power supply of each part of the processing device at the subsequent stage in the low power consumption mode, and supplies power to the power supply control unit when the interface controller detects the negotiation phase, thereby returning from the low power consumption mode. In the low power consumption mode, data is transferred from the interface controller to the FIFO circuit and transferred from the FIFO circuit to the DMA controller. And a control means for preventing it.

  A third means is the first or second means, wherein the control means adjusts a transfer interval from the interface controller to the FIFO circuit when returning from the low power consumption mode to the normal mode. And

  The fourth means is characterized in that, in the third means, the drive interval of the busy signal on the interface changes according to the change of the transfer interval from the interface controller to the FIFO circuit.

  A fifth means is characterized in that, in the third means, the data transferred from the interface controller is transferred from the FIFO circuit to the DMA controller after returning from the low power consumption mode to the normal mode. And

  A sixth means is characterized in that, in the fifth means, the data transfer interval between the interface controller and the FIFO circuit is set to an interval at which the host computer does not time out at least.

  A seventh means is the sixth means, wherein the number of stages of the FIFO circuit is equal to or longer than a time when the value of the timer set by the control means is multiplied by the number of stages to return from the low power consumption mode to the normal mode. It is set to time.

  The eighth means is the transfer time between the interface controller and the FIFO circuit after returning from the low power consumption mode to the normal mode and starting data transfer from the FIFO circuit to the DMA controller in the fifth to seventh means. The timer value for setting is changed between data transfers.

  According to a ninth means, in the second to eighth means, the interface controller comprises a Centronics interface controller.

  The tenth means is the first to ninth means, further comprising a CPU for controlling the operation of the power supply controller in accordance with an instruction from the interface controller.

  The eleventh means is the image processing apparatus according to any one of the first to tenth means, wherein the subsequent processing apparatus executes processing for performing image processing.

  A twelfth means includes an interface device according to the second to tenth means, wherein the subsequent processing device is an image processing device, and each of the units is controlled by a CPU that controls the respective units of the image processing device, and a transfer And a RAM that stores the image data, a ROM that functions as a work area of the CPU, and a memory controller that communicates with the DMA controller and performs storage control on the RAM and the ROM. .

  A thirteenth means is the twelfth means, further comprising a mass storage device that is controlled by the memory controller and accumulates image information stored in the RAM.

  The fourteenth means includes the image processing apparatus according to the twelfth or thirteenth means, and image forming means for forming a visible image on a recording medium based on the image data output from the memory controller. Features.

  In the following embodiments, the interface controller is the Centronics I / F controller 111, the host computer is the reference numeral 111, the power supply control unit is the reference numeral 113, the FIFO circuit is the reference numeral 115, the DMA controller is the reference numeral 112, and the control means Is the timer / transfer control circuit 114, the CPU is the second CPU 116, the memory controller is the reference numeral 121, the CPU is the reference numeral 122, the RAM is the reference numeral 123, the ROM is the reference numeral 124, the mass storage means is the HDD 300, The image forming means corresponds to the printer engine 200, the interface device corresponds to reference numeral 110, and the image processing apparatus corresponds to reference numeral 120.

  According to the present invention, the power saving mode can be realized even when the power saving mode cannot be realized by the function of the interface.

Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a block diagram showing a schematic configuration of an image processing apparatus according to an embodiment of the present invention. Although partially overlapping with the prior art shown in FIG. 8, it will be described in detail. In FIG. 1, the image processing apparatus according to this embodiment includes an interface unit 110 and an image processing unit 120. The interface unit 110 includes a Centronics I / F controller 111, a timer / transfer control circuit 114, a FIFO circuit 115, a DMA controller 112, and a power supply control unit 113. The image processing unit 120 includes a memory controller 121, a CPU 122, a RAM 123, and a ROM 124. Has been.

  A transfer time control timer (circuit) / transfer control circuit 114 and FIFO circuit 115 are provided in parallel between the Centronics I / F controller 111 and the DMA controller 112, respectively, and the power controller 113 includes a Centronics I A control signal is output from the / F controller 111. The timer / transfer control circuit 114 receives the Req signal from the Centronics I / F controller 111 and returns an Ack signal. The timer / transfer control circuit 111 outputs the Req_a signal to the DMA controller 112, and the Ack_a signal from the DMA controller 112. The FIFO 115 has a function of outputting the data received from the Centronics I / F controller 111 to the DMA controller 112 as Data_a. Further, the timer / transfer control circuit 111 and the power supply control unit 113, and the timer / transfer control circuit 111 and the FIFO circuit 115 are connected so as to communicate with each other.

  The image processing unit 120 includes a CPU 122 connected to the power supply control unit 113, a DMA controller 112, a memory controller 112 connected to the CPU 122, and a RAM 123 and ROM 124 connected to the memory controller 112.

  The low power consumption mode of the image processing unit according to this embodiment is set by the CPU 122. When the CPU 122 instructs the power control unit 113 to shift to the low power consumption mode, the CPU 122, the memory controller 121, the RAM 123, and the ROM 122 of the image processing unit 120, which are surrounded by a dotted line, are in a power-off state. In this embodiment, this state is referred to as a low power consumption mode state.

  In the case where complicated processing is required in the low power consumption mode as shown in FIG. 2, a configuration in which another CPU 116 is added like a second CPU (shown as CPU 2 in the figure) can be considered. In this case, the second CPU 116 is in an operating state with power supplied even in the low power consumption mode. In the example of FIG. 1, the Centronics I / F controller 111 takes charge of power control and negotiation. Although necessary, in the configuration of FIG. 2, negotiation and power control may be performed by the second CPU 116. These two processes are not necessarily performed by one resource, and there is no problem even if different resources control.

FIG. 3 is a flowchart showing an operation procedure when the system configuration of FIG.
As can be seen from the figure, first, when the Centronics I / F controller 111 detects a negotiation from the host computer 100 (negotiation start-step S1), it issues a power-on instruction to the power control unit 113 (power-on-step). S2), CPU122 starts Boot (step S3).

  At the same time (in parallel), the Centronics I / F controller 111 processes the negotiation from the host computer 100. When the processing is completed (negotiation complete-step S4), the timer / transfer control circuit 111 is preset. Data reception from the host computer 100 is started using a value that does not cause the host computer 100 to time out (step S5), and the data is stored in the FIFO circuit 115 (step S6).

  In the low power consumption mode, a register is set in advance so as not to transfer data from the FIFO circuit 115 to the DMA controller 112. As a result, data transferred from the IEEE 1284 I / F (Centronics I / F controller 111) is not transferred to the RAM 123, so that the power of the RAM 123 can be shut off.

  When the CPU 122 boots (step S7), the CPU 122 starts the transfer of the DMA controller 112 (step S8). At this time, since a large amount of data is still accumulated in the FIFO circuit 115, the memory controller 121 receives the control signal from the timer / transfer control unit 111 and uses the DMA controller 112 to transfer the received data to the RAM 123. I will forward it.

  When the timer control reception is performed, the data transfer rate from the host computer 100 to the FIFO circuit 115 is very slow. On the other hand, since the data transfer rate from the FIFO circuit 115 to the RAM 123 via the DMA controller 112 is very high, the CPU 122 sets the timer value for the timer / transfer control circuit 114 to a very small value and sets the IEEE1284 I / O. The processing capability (performance) of F is increased (step S9). This changed timer value is used when the next data is transferred from the Centronics I / F controller 111 to the FIFO circuit 115, and thereafter enters a normal reception state (step S10). As a result, the timer value can be changed while the operation is continued between data transfers. If the CPU 122 determines that it is not necessary to use the function of the timer / transfer control circuit 114, the CPU 122 may stop the operation of the timer / transfer control circuit 114 itself instead of changing the timer value.

  In the processing procedure of FIG. 3, the processing from step S1 to step S7 corresponds to the low power consumption mode. In this mode, the reception interval of the timer control data is delayed, and the received data is stored in the FIFO circuit 115. is there. The processing from step S7 to step S9 is a step of shifting to the normal mode, and the memory controller 121 receives the control signal from the timer / transfer control unit 111 and transfers the data accumulated in the FIFO circuit 115 to the DMA controller 121. Start transferring. The processes in step S9 and step S10 are processes in the normal mode. The timer value of the timer / transfer control unit 111 is changed, the communication speed is increased to the normal process speed, and the data is transferred to the RAM 123 side.

FIG. 4 is a timing chart showing operation timings of the Centronics I / F controller 111 and the FIFO circuit 115 during the low power consumption mode.
The Req signal is a Request signal indicating that there is data to be transferred by the Centronics I / F controller 111, the Ack signal is an Acknowledge signal indicating that the FIFO circuit 115 has received data, and the Data signal is transferred to the FIFO circuit 115. Req_a, Ack_a, and Data_a received from the CPU are signals between the FIFO circuit 115 and the DMA controller 112, respectively, and are the same as the transmission / reception of signals between the Centronics I / F controller 111 and the FIFO circuit 115. The BUSY signal is shown.

  In the low power consumption mode, the Req_a signal is never activated to stop the function of the DMA controller 112. When the Centronics I / F controller 111 activates the Req signal, the timer / transfer control circuit 114 activates the Ack signal according to the preset timer value, and the FIFO circuit 115 activates the Centronics I when the timer value is reached. Data (Data) is received from the / F controller 111. By inactivating the BUSY signal in conjunction with the Ack signal, the speed of data transfer from the host computer 100 is adjusted and a timeout is prevented. This timing corresponds to the processing from step S4 to step S6 in FIG.

  FIG. 5 is a timing chart showing timing when the transfer circuit of the DMA controller 111 and the FIFO circuit 115 is operated when the low power consumption mode is shifted to the normal mode. In this state, timer control reception is still active. When the Centronics I / F controller 111 activates the Req signal, the timer / transfer control circuit 114 activates the Ack signal according to the preset timer value, and the FIFO circuit 115 activates the Centronics I when the timer value is reached. Data (Data) is received from the / F controller 111. By inactivating the BUSY signal in conjunction with the Ack signal, the speed of data transfer from the host computer 100 is adjusted and a timeout is prevented.

  When the CPU 122 recovers from the power saving consumption mode and the power supply control unit 113 starts up, the timer / transfer control circuit 114 activates the Req_a signal, the DMA controller 112 receives the Data_a signal from the FIFO circuit 115, and sends the Ack_a signal to the timer Return to the transfer control circuit 114. The transfer speed between the FIFO circuit 115 and the DMA controller 112 is high because the timing is not limited by the timer / transfer control circuit 114. This timing corresponds to the processing from step S8 to step S10.

  FIG. 6 is a timing chart showing the timing when the timer value of the timer / transfer control circuit 114 is set to Zero and the timer function of the timer / transfer control circuit 114 is killed. At this timing, since the timer value of the timer / transfer control circuit 114 is set to “0”, when the Centronics I / F controller 111 activates the Req signal, the FIFO circuit 114 receives the Data signal, The transfer control circuit 114 returns an Ack signal to the Centronics I / F controller 111. Next, the timer / transfer control unit 114 activates the Req_a signal, the DMA controller 112 receives the Data_a signal from the FIFO circuit 115, and returns the Ack_a signal to the timer / transfer control circuit 114. This is executed each time the Centronics I / F controller 111 activates the Req signal. During this time, the timing is not limited by the timer / transfer control unit 114, so the processing is performed at high speed. As a result, the transfer rate of 1284 I / F is also increased. This timing corresponds to the processing after step S10.

FIG. 7 is a diagram showing a schematic configuration of an image forming apparatus provided with such an image processing apparatus.
As shown in the figure, the memory controller 121 is mounted on the ASIC 130, and the output of the memory controller 121 is supplied to the printer engine 200. The printer engine 200 forms and discharges a visible image on a recording medium such as recording paper based on the image data sent from the memory controller 121.

  When the hard disk device (HDD) 300 is used for storing image data, the image data is transmitted to and received from the RAM 123 via the memory controller 121 connected to the ASIC 130.

  As described above, according to the present embodiment, the Centronics I / F controller 111 responds to the negotiation of the host controller 111 until the CPU 122 that has been powered off by the timer / transfer control circuit 114 and the FIFO circuit 115 boots. By receiving data, even products that support IEEE 1284 can shift to a low power consumption mode in which the power of devices such as the CPU 122, ROM 124, RAM 123, etc. is cut off, and power consumption can be kept low. In addition, during the boot of the CPU 122, the data transfer interval from the transfer centrotonic I / F controller 111 to the FIFO circuit 115 is controlled by the timer / transfer control circuit 114, so that during the return from the power saving consumption mode to the normal mode. No data will be lost.

  In this embodiment, an I / F controller that supports IEEE 1284 is targeted. However, an I / F controller having similar characteristics can be adapted to the power saving consumption mode with the same configuration. Needless to say.

1 is a block diagram illustrating a schematic configuration of an image processing apparatus according to an embodiment of the present invention. It is a block diagram which shows schematic structure of the image processing apparatus which concerns on the modification of embodiment of this invention. 2 is a flowchart illustrating an operation procedure when shifting from a low power consumption mode to a normal mode in the system configuration of FIG. 1. It is a timing chart which shows the operation timing of the Centronics I / F controller and the FIFO circuit during the low power consumption mode. 6 is a timing chart showing timing when the DMA controller and the transfer circuit of the FIFO circuit operate when shifting from the low power consumption mode to the normal mode. 6 is a timing chart showing the timing of a state in which the timer function of the timer / transfer control circuit is killed by setting the timer value of the timer / transfer control circuit to Zero. It is a figure which shows schematic structure of the image forming apparatus provided with the image processing apparatus shown in FIG. It is a figure which shows schematic structure of the image processing apparatus which concerns on a prior art example.

Explanation of symbols

100 Host Computer 110 Interface Device 111 Centronics I / F Controller 112 DMA Controller 113 Power Supply Control Unit 114 Timer / Transfer Control Circuit 115 FIFO Circuit 116 Second CPU
120 Image Processing Device 121 Memory Controller 122 CPU
123 RAM
124 ROM
200 Printer engine 300 HDD

Claims (14)

In the low power consumption mode, the power supply of each part of the subsequent processing device is cut off, and the return from the low power consumption mode is the interface device that supplies power to the power control unit when the interface controller and the host computer start negotiation.
A FIFO circuit and a DMA controller provided between the interface controller and the processing device;
In the low power consumption mode, control means for transferring data from the interface controller to the FIFO circuit and preventing transfer from the FIFO circuit to the DMA controller;
An interface device characterized by comprising: In the low power consumption mode, in the interface device that cuts off the power supply of each part of the processing device in the subsequent stage and supplies power to the power control unit when the interface controller detects the negotiation phase, and returns from the low power consumption mode,
A FIFO circuit and a DMA controller provided between the interface controller and the processing device;
In the low power consumption mode, control means for transferring data from the interface controller to the FIFO circuit and preventing transfer from the FIFO circuit to the DMA controller;
An interface device comprising:   The interface apparatus according to claim 1, wherein the control unit adjusts a transfer interval from the interface controller to the FIFO circuit when returning from the low power consumption mode to the normal mode.   4. The interface apparatus according to claim 3, wherein a drive interval of the busy signal on the interface changes according to a change in a transfer interval from the interface controller to the FIFO circuit.   4. The interface apparatus according to claim 3, wherein the data transferred from the interface controller is transferred from the FIFO circuit to the DMA controller after returning from the low power consumption mode to the normal mode.   6. The interface apparatus according to claim 5, wherein a data transfer interval between the interface controller and the FIFO circuit is set to an interval at which the host computer does not time out at least.   The number of stages of the FIFO circuit is set to a time equal to or longer than a time required for returning from the low power consumption mode to the normal mode by multiplying the value of the timer set by the control means by the number of stages. Item 7. The interface device according to Item 6.   After returning from the low power consumption mode to the normal mode and starting data transfer from the FIFO circuit to the DMA controller, the timer value for setting the transfer time between the interface controller and the FIFO circuit is changed between the data transfer intervals. 8. The interface device according to claim 5, wherein the interface device is characterized in that:   9. The interface device according to claim 2, wherein the interface controller is a Centronics interface controller.   The interface device according to claim 1, further comprising a CPU that controls an operation of the power supply control unit in accordance with an instruction from the interface controller.   The interface apparatus according to claim 1, wherein the subsequent processing apparatus is an image processing apparatus that executes processing for performing image processing. An interface device according to any one of claims 2 to 10, comprising:
The subsequent processing device is an image processing device,
The respective units communicate with the CPU that controls the respective units of the image processing apparatus, the RAM that stores the transferred image data, the ROM that functions as a work area of the CPU, the DMA controller, the RAM, An image processing apparatus comprising: a memory controller that performs storage control with a ROM.   The image processing apparatus according to claim 12, further comprising a mass storage device that is controlled by the memory controller and stores image information stored in the RAM. An image processing apparatus according to claim 12 or 13,
Image forming means for forming a visible image on a recording medium based on image data output from the memory controller;
An image forming apparatus comprising:

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