JP2005266460A - Driving substrate and semiconductor power module mounted on the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a driving substrate which makes a wiring pattern thereon simplified while suppressing a bad influence of spurious radiation noise, and also to provide a semiconductor power module having the driving substrate mounted thereon. <P>SOLUTION: A semiconductor power module 9 mounted on a Y electrode-side driving substrate 1 includes a separation circuit 4 being a main circuit where a sustain pulse current flows, a sustain circuit 5, and a power recovery circuit 6, so that a wiring pattern on the Y electrode-side driving substrate 1 is simplified, and the substrate area is reduced. Since a circuit pattern and a terminal arrangement in the semiconductor power module 9 are laid out so that a sustain pulse current path is the shortest path, an inductance parasitic on the internal circuit pattern and a voltage drop resulting from passing-round of the circuit pattern are reduced. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a drive substrate that supplies a sustain pulse voltage to a scan driver circuit that applies a selection voltage to scan electrodes of a plasma display panel (hereinafter referred to as “PDP”), and a semiconductor power module mounted on the drive substrate. In particular, the present invention relates to a technique for simplifying a wiring pattern while suppressing an adverse effect of unnecessary radiation noise.

Currently, PDPs are widely used as display elements for thin large-screen televisions.
Since the PDP uses a discharge phenomenon for light-emitting display, a display device equipped with a PDP (hereinafter referred to as a “PDP device”) includes a drive substrate for supplying high-speed, high-current pulses. .
By the way, as conventionally considered as a problem, unnecessary radiation noise is generated when high-speed, large-current pulses flow on the wiring pattern, which may adversely affect the control system circuit such as malfunction.

In order to suppress this adverse effect, conventionally, it is possible to reduce the unnecessary radiation noise by widening the pattern width of the wiring pattern through which a high-speed, high-current pulse flows, or to avoid the adverse effect on the control system circuit due to the unnecessary radiation noise. Measures such as routing the wiring pattern were taken.
In addition, a semiconductor module disclosed in the following patent document is an integrated circuit mounted on a driving substrate, and a sustain discharge circuit (hereinafter referred to as a “sustain circuit”) is used to reduce unnecessary radiation noise generated in the semiconductor module. The power system circuit is separated into a plurality of blocks.

As a result, the high-speed and large-current pulses flowing in the semiconductor module are distributed to a plurality of blocks, and therefore there is an effect of reducing unnecessary radiation noise generated inside the blocks.
Here, a conventional PDP apparatus will be briefly described with reference to FIG.
A PDP apparatus 1000 shown in FIG. 8 includes a PDP 101, an address driver circuit 102, a waveform control circuit 103, an electrode X side drive substrate 104, a scan driver circuit 117, and an electrode Y side drive substrate 118.

As shown in FIG. 8, in the PDP 101, the sustain electrodes X1 to Xn and the scan electrodes Y1 to Yn are paired and arranged in parallel with each other, and the address electrodes A1 to Am are arranged orthogonal to these, and m × n Pixels are formed in a matrix.
Hereinafter, the address electrodes A1 to Am, the sustain electrodes X1 to Xn, and the scan electrodes Y1 to Yn are referred to as an electrode A, an electrode X, and an electrode Y, respectively.

The electrode X side drive substrate 104 is connected to the electrode X of the PDP 101, and the semiconductor power module 126, the coil 115, and the recovery capacitor 116 are disposed on the substrate.
The semiconductor power module 126 is an integrated circuit, and includes a sustain circuit 105 and a power recovery circuit 106.

The electrode Y side drive substrate 118 is connected to a scan driver circuit 117 connected to the electrode Y of the PDP 101, and a scan voltage generation circuit 119, a reset voltage generation circuit 120, a separation circuit 121, and a semiconductor power module are provided on the substrate. 127, a coil 124 and a recovery capacitor 125 are arranged.
The scan voltage generation circuit 119 has a function of outputting the scan voltage VSCN to the scan driver circuit 117.

The reset voltage generation circuit 120 has a function of outputting the reset voltage VSET to the scan driver circuit 117 via the separation circuit 121.
The semiconductor power module 127 is an integrated circuit, and includes a sustain circuit 122 and a power recovery circuit 123.
The sustain circuit 122 has a function of outputting a sustain pulse voltage VSUS to the separation circuit 121 based on a signal from the waveform control circuit 103.

The separation circuit 121 includes a plurality of switch elements connected in parallel, performs on / off control of each switch element based on a signal from the waveform control circuit 103, and performs a scan voltage generation circuit 119 and a reset in addition to the sustain discharge period. The voltage generation circuit 120 has a function of separating each circuit so that the voltage applied from the voltage generation circuit 120 is not output to the sustain circuit 122 side.
The waveform control circuit 103 has a function of generating a signal for controlling the address driver circuit 102, the scan driver circuit 117, the separation circuit 121, and the semiconductor power modules 126 and 127.
JP 2000-89724 A

  By the way, the PDP is actually discharged during a period in which the sustain pulse voltage VSUS, which is alternately inverted between the electrodes X and Y, is applied by the sustain circuits 105 and 122 and the power recovery circuits 106 and 123 and the sustain discharge is performed. Due to this period, the power supplied to the panel is the largest, and a large current having a peak current of about 200 A flows through the wiring through which the sustain pulse voltage VSUS flows.

The voltage waveform of the sustain pulse voltage VSUS has a voltage of 170 V, one cycle is about 5 μs, and the sustain pulse current has a large di / dt, so that radiation noise is generated due to induction caused by the pulse current.
The conventional electrode Y-side drive substrate 118 has a wide wiring pattern width for the separation circuit 121 or a wiring line in order to suppress the adverse effect of unnecessary radiation noise caused by the sustain pulse current flowing from the semiconductor power module 127 to the separation circuit 121. I was running around.

As a result, the substrate area of the electrode Y-side drive substrate 118 is increased, leading to a problem that the wiring pattern is complicated.
The present invention has been made to solve such a problem, and is mounted on a driving board capable of simplifying a wiring pattern on the driving board while suppressing the adverse effect of unnecessary radiation noise, and mounted on the driving board. An object is to provide a semiconductor power module.

  To achieve the above object, a drive substrate according to the present invention is a drive substrate that supplies a pulse voltage to a scan driver circuit that applies a selection voltage to a scan electrode of a plasma display panel, and includes a semiconductor power module, The semiconductor power module includes: a sustain circuit that supplies a pulse voltage; a power recovery circuit that is electrically connected to the sustain circuit and recovers power from the display panel; and a current between the sustain circuit and the scan driver circuit And a separation circuit that selectively separates paths.

  The drive substrate includes a reset voltage generation circuit that supplies a reset voltage to the scan driver circuit, and a scan voltage generation circuit that supplies a scan voltage to the scan driver circuit, and the separation circuit includes the sustain circuit And a first separation switch for separating a current path between the reset voltage generation circuit and a second separation switch for separating a current path between the sustain circuit and the scan voltage generation circuit.

  Furthermore, the sustain circuit includes a push-pull circuit, a first end of the push-pull circuit is electrically connected to the sustain power supply terminal, and a second end is electrically connected to the main output terminal, A third end is electrically connected to the power ground terminal, an upper arm switch is electrically connected between the first end and the second end, and a lower arm switch is connected between the second end and the third end. Are electrically connected, and the first output terminal of the first separation switch and the first output terminal of the second separation switch are both electrically connected to the reset voltage generation circuit, and the second terminal The second output terminal of the first separation switch may be electrically connected, and the second output terminal of the second separation switch may be electrically connected to the scan voltage generation circuit and the scan driver circuit. .

Each switch in the sustain circuit, the power recovery circuit, and the separation circuit may be configured by a power MOSFET.
Further, a power supply capacitor may be mounted in the immediate vicinity of the sustain power supply terminal of the semiconductor module, and a connector for connecting to the scan driver circuit may be provided in the immediate vicinity of the main output terminal of the semiconductor module.

  The drive board may be a multilayer board having an earth pattern layer, and a power ground terminal of the semiconductor power module may be electrically connected to the earth pattern layer.

If the drive board having the above configuration is used as the electrode Y side drive board of the PDP, all the paths through which the sustain pulse current flows are accommodated in the semiconductor power module, so that the drive board is used to suppress the adverse effects of unnecessary radiation noise. There is no need to route the upper wiring pattern, the wiring pattern can be simplified, and the area of the drive substrate can be reduced.
The semiconductor power module includes a sustain power terminal for electrically connecting the sustain circuit to a sustain power source, and a main output terminal for electrically connecting the separation circuit to the scan driver circuit. The large current pulse path in the semiconductor power module from the sustain power supply terminal to the main output terminal may be formed linearly, and the semiconductor power module further includes a power for grounding the sustain circuit. A ground current terminal may be provided, and a large current pulse path in the semiconductor power module from the main output terminal to the power ground terminal may be formed linearly.

With this configuration, the semiconductor power module is configured so that the internal high-current pulse path becomes the shortest path, and therefore, inductance reduction parasitic on the wiring pattern and voltage drop can be suppressed as much as possible.
In addition, each switch in the sustain circuit, the power recovery circuit, and the separation circuit may be made of a wide band gap semiconductor.

With this configuration, the on-resistance and switching time can be reduced, and it can be used under conditions where the junction temperature exceeds 150 ° C, the upper limit of conventional silicon semiconductors, greatly reducing the number of switch elements connected in parallel. The circuit size can be reduced.
Moreover, each switch in the sustain circuit, the power recovery circuit, and the separation circuit may be a single switch.

  With this configuration, when discrete components are used as conventional switch elements, the size of the semiconductor chip is limited by the size of the package, but each switch can be configured with a single switch element by arranging the switch elements in the semiconductor power module. Thus, the problem of current concentration due to the characteristics between the switch elements and the wiring impedance difference can be solved, and the current capability of the switch elements can be reduced more efficiently.

  The drive board is a multilayer board having an earth pattern layer, and the semiconductor power module is a metal base print in which an electrically insulating layer is formed on a main surface of a metal board and a circuit pattern is formed thereon. A high-side driver IC for driving each switch and the switch is disposed on the circuit pattern, and the upper electrode of each switch and the circuit pattern are electrically connected by a metal wire; The metal substrate and a ground terminal on the circuit pattern may be electrically connected, and the metal substrate and the ground pattern layer may be electrically connected.

With this configuration, a ground current can flow through the metal substrate in the same manner as the ground pattern layer of the drive substrate, the ground current flowing on the drive substrate can be reduced, and radiation noise generated on the drive substrate can be reduced. It is.
Moreover, a heat sink may be attached to the back surface of the metal substrate, and the heat sink may be electrically connected to the metal substrate.

  With this configuration, a ground current can flow through the metal substrate and the heat radiating plate in the same manner as the ground pattern layer of the drive substrate, the ground current flowing on the drive substrate is reduced, and radiation noise generated on the drive substrate is reduced. It is possible.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
<1 PDP device 100>
FIG. 1 is a diagram illustrating a functional configuration of the PDP apparatus according to the present embodiment.
The PDP device 100 includes a PDP 101, an address driver circuit 102, a waveform control circuit 103, an electrode X side drive substrate 104, a scan driver circuit 117, and an electrode Y side drive substrate 1.

The difference from the prior art is the electrode Y-side drive substrate 1 and the semiconductor power module 9 disposed on the electrode Y-side drive substrate 1, and each configuration is a feature of the present invention. Before describing these in detail, The functional units of the PDP device 100 and the light emission display operation of the PDP device 100 will be described.
In addition, the same code | symbol is provided about the same thing as the function part of the PDP apparatus 1000 demonstrated in background art.

<1.1 PDP101>
As shown in FIG. 1, in the PDP 101, sustain electrodes X1 to Xn and scan electrodes Y1 to Yn are paired and arranged in parallel, and address electrodes A1 to Am are arranged orthogonally to them, and m × n pieces. The pixels are formed in a matrix.
<1.2 Address Driver Circuit 102>
The address driver circuit 102 is connected to the electrode A and has a function of applying a predetermined address voltage VAD to the electrode A based on a signal from the waveform control circuit 103.

<1.3 Electrode X Side Drive Substrate 104>
The electrode X side drive substrate 104 is connected to the electrode X and includes a semiconductor power module 126, a coil 115, and a recovery capacitor 116.
<1.3.1 Semiconductor Power Module 126>
The semiconductor power module 126 includes a sustain circuit 105 and a power recovery circuit 106.

The sustain circuit 105 includes switch elements 107 and 108 and a high-side driver IC 113, and the switch elements 107 and 108 form a push-pull circuit. The high-side driver IC 113 controls on / off of the switch element.
The common output part of the push-pull circuit is connected to the electrode X, and the sustain pulse voltage VSUS for sustain discharge for causing the PDP 101 to emit light is applied to the other output terminal of the upper arm side switch element 107, and the lower arm side switch element The other output terminal 108 is grounded.

The high side driver IC 113 is driven based on a signal from the waveform control circuit 103 and performs control to apply the sustain pulse voltage VSUS to the electrode X.
The power recovery circuit 106 includes switch elements 109 and 110, diodes 111 and 112, and a high side driver IC 114.
One end of the output of the switch element 109 and one end of the output of the switch element 110 are connected to the recovery capacitor 116 grounded to the ground, and the other end of the output of the switch element 109 is connected to the input end of the diode 111. The other end of the output of 110 is connected to the output end of the diode 112, and the on / off of the switch element is controlled by the high side driver IC 114.

The output end of the diode 111 and the input end of the diode 112 are connected in common and connected to one end of the coil 115 and serve as an output unit of the power recovery circuit 106.
The other end of the coil 115 is connected to the output part of the sustain circuit 105.
The high side driver IC 114 is driven based on the signal from the waveform control circuit 103, supplies the charge accumulated in the recovery capacitor 116 to the electrode X via the coil 115 and the output portion of the sustain circuit 105, and outputs from the electrode X. Control for accumulating the charge in the recovery capacitor 116 is performed.

<1.4 Scan Driver Circuit 117>
The scan driver circuit 117 is connected to the electrode Y, and has a function of selectively outputting the voltage applied from the electrode Y side drive substrate 118 to the electrodes Y1 to Yn based on a signal from the waveform control circuit 103.
<1.5 Waveform Control Circuit 103>
The waveform control circuit 103 has a function of generating signals for controlling the address driver circuit 102, the scan driver circuit 117, and the semiconductor power modules 9 and 126.

<1.6 Electrode Y Side Drive Substrate 1>
The electrode Y side drive substrate 1 is connected to the scan driver circuit 117 and includes a scan voltage generation circuit 2, a reset voltage generation circuit 3, a coil 7, a recovery capacitor 8, and a semiconductor power module 9.
The scan voltage generation circuit 2 has a function of outputting the scan voltage VSCN to the scan driver circuit 117.

The reset voltage generation circuit 3 has a function of outputting the reset voltage VSET to the scan driver circuit 117 via the separation circuit 4.
The semiconductor power module 9 is an integrated circuit and includes a separation circuit 4, a sustain circuit 5, and a power recovery circuit 6, and is connected to the reset voltage generation circuit 3, the scan voltage generation circuit 2, the waveform control circuit 103, and the scan driver circuit 117. Has been.

<1.7 Light emission display operation>
Here, the light emission display operation of the PDP device 100 under the control of the waveform control circuit 103 will be described.
FIG. 2 is a timing chart used to explain the light emitting display operation of the PDP device 100.

First, the reset voltage VSET generated by the reset voltage generation circuit 3 is applied to the electrode Y during the reset period, and the entire surface is discharged between the electrode X and the electrode Y.
Next, the scan voltage VSCN generated by the scan voltage generation circuit 2 in the address period is applied to the selection electrode of the electrode Y via the scan driver circuit 118, and the address driver circuit 102 applies the address voltage VAD to the selection electrode of the electrode A. And an address discharge is performed between the electrode Y and the electrode A to select a discharge cell.

Thereafter, during the sustain discharge period, the sustain circuits 5 and 105 apply the sustain pulse voltage VSUS that is alternately inverted between the electrodes X and Y to perform the sustain discharge, whereby the light emission display of the PDP 101 is performed. In the next erasing period, the erasing voltage Ve is applied to the electrode X to extinguish the sustain discharge.
A subfield consisting of the reset period, address period, sustain discharge period, and erase period as described above is combined multiple times to form one field, and the number of sustain discharges in each subfield is changed to weight the luminance. The key is displayed.
<2 Equivalent Circuit of Semiconductor Power Module 9>
Next, the semiconductor power module 9 will be described using an equivalent circuit.

FIG. 3 is a diagram illustrating an example of an equivalent circuit of the semiconductor power module 9.
A portion surrounded by a broken line 4 is a separation circuit, a portion surrounded by a broken line 5 is a sustain circuit, and a portion surrounded by a broken line 6 is a power recovery circuit.
FIG. 3 shows only main components of each circuit.
The power MOSFETs 10, 11, 12, 13, 16, and 17 and the diodes 14 and 15 are connected in parallel to each other according to their current ratings. Illustration of each element is omitted.

<2.1 Sustain circuit 5>
The power MOSFETs 10 and 11 included in the sustain circuit 5 form a push-pull circuit.
A drain terminal of the power MOSFET 10 serving as an upper arm switch is connected to a sustain power supply terminal SUS to which a sustain pulse voltage VSUS is applied.

A source terminal of the power MOSFET 11 serving as a lower arm switch is connected to a power ground terminal PGND to which a ground potential is applied.
The source terminal of the power MOSFET 10 and the drain terminal of the power MOSFET 11 are connected in common and connected to a terminal OUT (S1) connected to one terminal of the coil 7 outside the module.

The gate terminals of the power MOSFETs 10 and 11 are connected to the high side driver IC 18 respectively.
The high side driver IC 18 performs on / off control of the power MOSFETs 10 and 11 based on a signal from the waveform control circuit 103 (not shown).
<2.2 Separation circuit 4>
The drain terminals of the power MOSFETs 16 and 17 included in the separation circuit 4 are connected in common and connected to a terminal SET (S2) which is a sub output terminal to which the reset voltage VSET from the reset voltage generation circuit 3 is applied.

The source terminal of the power MOSFET 16 is connected to the terminal OUT (S1).
A source terminal of the power MOSFET 17 is connected to a terminal SCN (S3) which is a main output terminal. Although not shown, the terminal SCN is commonly connected to the scan voltage generation circuit 2 and the scan driver circuit 117 outside the semiconductor power module 9.
The gate terminal of the power MOSFET 16 is connected to the high side driver IC 19, and the gate terminal of the power MOSFET 17 is connected to the high side driver IC 20.

  The high side driver ICs 19 and 20 perform on / off control of the power MOSFETs 16 and 17 (not shown) based on the signal from the waveform control circuit 103, and the power MOSFETs 16 and 17 include the reset voltage generation circuit 3 and the sustain circuit 5. And a switch for separating the current paths of the scan voltage generation circuit 2 and the reset voltage generation circuit 3.

<2.3 Power recovery circuit 6>
The drain terminal of the power MOSFET 12 included in the power recovery circuit 6 is connected to the terminal PC1 (S4), the source terminal of the power MOSFET 13 is connected to the terminal PC2 (S5), and the terminals PC1 and PC2 are commonly connected outside the module and are recovered. 8 is connected.

The source terminal of the power MOSFET 12 is connected to the anode terminal of the diode 14, and the cathode terminal of the diode 14 is connected to the terminal PL1 (S6).
The drain terminal of the power MOSFET 13 is connected to the cathode terminal of the diode 15, and the anode terminal of the diode 15 is connected to the terminal PL2.
Terminals PL1 and PL2 are commonly connected outside the module and connected to the coil 7.

The gate terminals of the power MOSFETs 12 and 13 are connected to the high side driver IC 21.
The high side driver IC 21 performs on / off control of the power MOSFETs 12 and 13 based on the signal from the waveform control circuit 103 (not shown).
With the configuration of each circuit described above, the sustain pulse current applied from the terminal SUS during the sustain discharge period is output from the terminal SCN through the power MOSFETs 10, 16, and 17 and output to the scan driver circuit.

That is, since all paths through which the sustain pulse current flows on the electrode Y side drive substrate 1 are formed in the semiconductor power module 9, the current wiring pattern on the electrode Y side drive substrate 1 can be made extremely simple.
The same applies even when the high-side driver ICs 18, 19, 20, and 21 are arranged outside the semiconductor power module 9 and the power MOSFETs 10, 11, 12, 13, 16, and 17 are controlled on / off from the outside of the module. The effect of can be obtained.
<3 Internal layout of the semiconductor power module 9>
Next, the internal layout of the semiconductor power module 9 will be described.

FIG. 4 is a plan transparent view of the semiconductor power module 9. As shown in FIG. 4, the semiconductor power module 9 has various circuit components (the power MOSFETs 10, 11, 12, 13, 16, 17, and the diode 14 described above) on the main surface of the metal base printed board 22 on which the circuit pattern is disposed. 15) is surface-mounted.
Various circuit components are fixed and electrically connected to predetermined positions with solder or the like, and the power MOSFET and the upper electrode of the diode are electrically connected to the circuit pattern with a plurality of metal wires, respectively.

Although omitted in the figure, a heat spreader (heat dissipating metal base) may be inserted between the power MOSFET and the circuit pattern for the purpose of improving heat dissipation.
In FIG. 4, various external connection terminals are arranged on the left and right sides of the metal base printed board 22. For example, the terminal SUS and the terminal PGND are arranged on the left side, and the terminal SET and the terminal SCN are arranged on the right side.

The terminal arrangements such as the input / output terminals of the control circuit and the output terminals of the power recovery circuit are not described because there are no arrangement restrictions.
A plurality of power MOSFETs 10 are arranged in a row on the circuit pattern 23 electrically connected to the terminal SUS, and the source wire of each power MOSFET 10 is electrically connected to the circuit pattern 24.

On the circuit pattern 25 electrically connected to the terminal SET, a plurality of power MOSFETs 16 and 17 are arranged vertically in a row, and the source wire of each power MOSFET 16 is electrically connected to the circuit pattern 24. It is connected.
The source wire of each power MOSFET 17 is connected to a circuit pattern 26 that is electrically connected to the terminal SCN.

The power MOSFETs 10, 16, and 17 are arranged substantially in parallel on the circuit pattern.
The plurality of power MOSFETs 11 are arranged in a row near the position where the source wires of the power MOSFET 16 are connected, below the position where the source wires of the power MOSFET 10 are connected on the circuit pattern 24 in FIG. Has been.

The source wire of each power MOSFET 11 is connected to a circuit pattern 27 that is electrically connected to the terminal PGND. The power MOSFETs 11, 16, and 17 are arranged substantially in parallel on the circuit pattern.
Since a high voltage is applied to the circuit patterns 23, 24, 25, 26, and 27, the insulation distance between the patterns is set to 1 mm to 10 mm.

  Further, in order to reduce inductance, a plurality of terminals are arranged for the terminals SUS, PGND, SET, and SCN, and the circuit patterns 23, 24, 25, 26, and 27 ensure a minimum space in which each power MOSFET and source wire can be arranged. However, the circuit pattern 23, 26, 27 is arranged in the vicinity of each electrically connected terminal.

In the semiconductor power module 9 described above, the current path I1 from the sustain power supply terminal SUS to the main output terminal SCN through which the sustain pulse current flows in the module and the current path I2 from the main output terminal SCN to the power ground terminal PGND are straight lines. Therefore, the parasitic inductance in the module can be reduced, and the voltage drop due to the circuit pattern routing can be reduced.
<4 Layout on Electrode Y Side Drive Substrate 1>
Next, the layout on the electrode Y-side drive substrate 1 will be described with reference to FIG.

FIG. 5 is a plan view of the electrode Y side drive substrate 1.
The connection connector 28 shown in the figure is a connector for supplying a reset voltage, a sustain pulse voltage, a scan voltage, etc. generated by the electrode Y side drive substrate to the scan driver circuit 117, and a plurality of connectors 28 are arranged to reduce wiring resistance. Yes.
The output wiring pattern 29 is a wiring pattern for electrically connecting the sustain pulse voltage VSUS to the connection connector 28 from the main output terminal SCN of the semiconductor power module 9.

Although not shown, the electrode Y-side drive board 1 is a multilayer wiring board having a plurality of wiring layers, and in this embodiment, an output wiring pattern 29 is arranged on the first layer.
The semiconductor power module 9 is arranged close to each other so that the linear distance t1 between the main output terminal SCN and the connection connector 28 is the shortest.
The sustain power supply capacitor 30 is a capacitor for supplying a sustain pulse voltage to the sustain power supply terminal SUS of the semiconductor power module 9, and is disposed close to the sustain power supply terminal SUS in order to minimize the inductance of the wiring pattern. The

The power supply wiring pattern 31 is a wiring pattern for electrically connecting the plus terminal of the sustain power supply capacitor 30 and the sustain power supply terminal SUS, and is arranged in the first layer, like the output wiring pattern 29.
The power ground terminal PGND of the semiconductor power module 9 is electrically connected to a ground pattern layer (not shown) provided in the lower layer of the electrode Y-side drive substrate 1, and the negative terminal of the sustain power supply capacitor 30 is also connected. Similarly, it is electrically connected to the ground pattern layer.

The ground pattern layer is preferably provided in a layer different from a layer through which a large current such as an input / output current flows and a layer through which a fine current such as a control signal flows.
In the electrode Y side driving substrate 1 described above, since the large current path is almost formed in the module, the large current wiring pattern arranged on the electrode Y side driving substrate 1 can be greatly simplified. The ground current wiring pattern can also be formed in a large area.

Therefore, voltage drop fluctuations generated in the semiconductor power module 9 and on the electrode Y-side drive substrate 1 due to high-speed and large-current pulses can be suppressed, and unnecessary radiation noise can be reduced.
<5 Supplement>
In addition, the above-mentioned embodiment is one Embodiment of this invention, Of course, it is not limited to this. That is,
(1) As switching elements such as the power MOSFETs 10, 11, 12, 13, 16, 17 and the diodes 14 and 15 shown in FIGS. 3 and 4, switching elements made of a wide band gap semiconductor such as gallium nitride are used. May be.

FIG. 6 is a partially transparent plan view of a semiconductor power module 9A using a wide band gap semiconductor switch element.
It is known that a switch element made of a gallium nitride semiconductor has many advantages over a silicon semiconductor, such as high breakdown voltage, high current density, low on-resistance, high speed operation, and high temperature operation.
Therefore, when the power MOSFETs 10, 11, 12, 13, 16, and 17 shown in FIGS. 3 and 4 are replaced with power MOSFETs 10A, 11A, 12A, 16A, and 17A having a low on-resistance and a short switching time, It can be used under conditions that exceed the upper limit of the junction temperature of 150 ° C., and for example, it can be used at a high temperature of the junction temperature of 400 ° C. or higher. That is, since the junction temperature restriction is almost eliminated, the entire switch element and circuit can be reduced, the number of parallel connections can be greatly reduced, and the heat dissipation mechanism of the switch element can be greatly simplified.

For example, in FIG. 4, the power MOSFET 10 is composed of three elements, but in FIG. 6, it can be replaced with one power MOSFET 10A. However, the parallel connection number reduction ratio of each power MOSFET is not limited to the above.
Further, the diodes 14 and 15 shown in FIG. 4 can be replaced with diodes 14A and 15A having a small forward voltage, recovery current, and recovery time.

  Furthermore, if a switch element made of a gallium nitride semiconductor is used as an element in a semiconductor power module, each switch can be configured with a single switch element. Therefore, conventionally, a sustain circuit, a power recovery circuit, a separation circuit, etc. When the power system circuit is composed of discrete components, it is possible to solve the problems that limit the size of the semiconductor chip due to the package size of each discrete component and the current concentration due to the characteristics between the switch elements and the wiring impedance difference. The current capacity of the switch element can be made more efficient. Moreover, the chip shape of each switch element 10A-17A can be made into the optimal shape for the circuit pattern shape of a module, and it becomes possible to form each switch with a single switch element.

Further, by combining the semiconductor power module 9A and the above-described electrode Y side drive substrate 1, it is possible to suppress voltage drop fluctuations generated in the semiconductor power module 9A and on the electrode Y side drive substrate 1 due to high-speed and large current pulses. Unnecessary radiation noise can be reduced.
(2) The connection relationship between the drive substrate and the semiconductor power module according to the present invention may be as described below.

FIG. 7 is a schematic cross-sectional view used to explain the connection relationship between the drive substrate 41, the semiconductor power module 9B, and the heat sink 42.
The metal base printed board 36 of the semiconductor power module 9 </ b> B includes a metal layer 33, an electrically insulating layer 34, and a circuit pattern 35.
The high side driver IC 37 is an IC for driving the power MOSFET 38, and is disposed at a desired position of the circuit pattern 35 and is electrically connected to the circuit pattern 35 by a metal wire 39.

The power ground terminal 40 and the ground terminals 44 arranged at the four ends of the metal base printed board 36 are terminals that are electrically connected to the semiconductor power module 9B and the ground pattern layer 41b of the drive board 41.
The heat radiating plate 42 is a heat radiating plate for efficiently releasing heat generated in the semiconductor power module 9 </ b> B, and is electrically connected to the metal substrate 33 of the metal printed circuit board 36.

The bolt 43 is a bolt for bonding and fixing the semiconductor power module 9B and the heat radiating plate 42, and is electrically connected to the ground terminal 44 via the circuit pattern 35 of the semiconductor power module 9B.
The power ground terminal 40, the ground terminal 44 and the metal substrate 33 are electrically connected by bolts 43. However, a part of the electrical insulating layer 34 is opened to connect the desired circuit pattern and the metal substrate 33 to the metal wire. You may connect with.

  With the above configuration, since the metal substrate 33 and the heat radiating plate 42 are electrically connected to the ground pattern layer 41b of the drive substrate 41, a ground current can flow through the ground pattern layer 41b. The flowing earth current can be reduced, and the radiation noise generated on the drive substrate can be reduced.

  INDUSTRIAL APPLICABILITY The present invention is useful as a drive substrate for a PDP device that requires high speed and large current pulses and a semiconductor power module mounted on the drive substrate.

2 is a diagram showing a functional configuration of a PDP device 100. FIG. 4 is a timing chart for explaining a light emission display operation of a drive circuit of the PDP device 100. 3 is a diagram showing an example of an equivalent circuit of a semiconductor power module 9. FIG. 2 is a plan transparent view of a semiconductor power module 9. FIG. 2 is a plan view of an electrode Y-side drive substrate 1. FIG. It is an example of the local plane transparent view of 9A of semiconductor power modules. It is an example of typical sectional drawing of the semiconductor power module 9B. It is a figure which shows the function structure of the conventional PDP apparatus.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1,118 Electrode Y side drive board | substrate 2,119 Scan voltage generation circuit 3,120 Reset voltage generation circuit 4,121 Separation circuit 5,105,122 Sustain circuit 6,106,123 Power recovery circuit 7,115,124 Coil 8, 32, 116, 125, 126, 127 Recovery capacitor 9, 9A, 9B Semiconductor power module 10, 11, 12, 13, 16, 17, 10A, 11A, 12A, 13A, 16A, 17A, 38, 107, 108, 109 110 Power MOSFET
14, 15, 14A, 15A, 111, 112 Diode 18, 19, 20, 21, 37, 113, 114 High side driver IC
22 Metal base printed circuit board 23, 24, 25, 26, 27 Circuit pattern 28 Connector 29 Output wiring pattern 30 Sustain power supply capacitor 31 Power wiring pattern 33 Metal substrate 34 Electrical insulating layer 35 Circuit pattern 36 Metal base printed circuit board 39 Metal Wire 40 Power ground terminal 44 Ground terminal 41 Drive board 42 Heat sink 43 Bolt 101 PDP
102 address driver circuit 103 waveform control circuit 104 electrode X side drive substrate 117 scan driver circuit

Claims (13)

A drive substrate that supplies a pulse voltage to a scan driver circuit that applies a selection voltage to a scan electrode of a plasma display panel,
Equipped with semiconductor power module,
The semiconductor power module is
A sustain circuit for supplying a pulse voltage;
A power recovery circuit that is electrically connected to the sustain circuit and recovers power from the display panel;
A drive substrate comprising: a separation circuit that selectively separates a current path between the sustain circuit and the scan driver circuit. The drive substrate is
A reset voltage generation circuit for supplying a reset voltage to the scan driver circuit;
A scan voltage generation circuit for supplying a scan voltage to the scan driver circuit,
The separation circuit is
A first separation switch for separating a current path between the sustain circuit and the reset voltage generation circuit;
The drive substrate according to claim 1, further comprising: a second separation switch that separates a current path between the sustain circuit and the scan voltage generation circuit. The semiconductor power module is
A sustain power supply terminal for electrically connecting the sustain circuit to a sustain power supply;
A main output terminal for electrically connecting the separation circuit to the scan driver circuit;
The drive substrate according to claim 2, wherein a large current pulse path in the semiconductor power module from the sustain power supply terminal to the main output terminal is formed linearly. The semiconductor power module is
A power ground terminal for grounding the sustain circuit;
The drive substrate according to claim 3, wherein a large current pulse path in the semiconductor power module from the main output terminal to the power ground terminal is formed linearly. The sustain circuit includes a push-pull circuit, the first end of the push-pull circuit is electrically connected to the sustain power supply terminal, the second end is electrically connected to the main output terminal, and the third end One end is electrically connected to the power ground terminal, an upper arm switch is electrically connected between the first end and the second end, and a lower arm switch is electrically connected between the second end and the third end. Connected,
A first output terminal of the first separation switch and a first output terminal of the second separation switch are both electrically connected to the reset voltage generation circuit;
The second end and a second output terminal of the first separation switch are electrically connected, and a second output terminal of the second separation switch is electrically connected to the scan voltage generation circuit and the scan driver circuit. The drive board according to claim 4, wherein the drive board is provided. The drive according to any one of claims 1 to 5, wherein the first separation switch, the second separation switch, the upper arm switch, and the lower arm switch are configured by power MOSFETs. substrate. The drive board according to any one of claims 1 to 6, wherein each of the switches in the sustain circuit, the power recovery circuit, and the separation circuit is made of a wide band gap semiconductor.   The drive board according to any one of claims 1 to 7, wherein each switch in the sustain circuit, the power recovery circuit, and the separation circuit is a single switch. The drive substrate is a multi-layer substrate having an earth pattern layer,
The semiconductor power module has a metal base printed board on which a circuit pattern is formed on an electrically insulating layer on a main surface of the metal board,
A high-side driver IC for driving each switch and the switch is disposed on the circuit pattern,
The upper electrode of each switch and the circuit pattern are electrically connected with a metal wire,
The metal substrate and a ground terminal on the circuit pattern are electrically connected,
The drive substrate according to claim 2, wherein the metal substrate and the ground pattern layer are electrically connected.   The drive board according to claim 9, wherein a heat radiating plate is attached to a back surface of the metal substrate of the semiconductor power module, and the heat radiating plate is electrically connected to the metal substrate.   4. The drive according to claim 3, wherein a power supply capacitor is mounted in the vicinity of a sustain power supply terminal of the semiconductor module, and a connector for connecting to a scan driver circuit is provided in the vicinity of the main output terminal of the semiconductor module. substrate. The drive substrate is a multi-layer substrate having an earth pattern layer,
The drive substrate according to claim 4, wherein a power ground terminal of the semiconductor power module is electrically connected to the ground pattern layer. A semiconductor power module mounted on a drive substrate that supplies a pulse voltage to a scan driver circuit that applies a selection voltage to a scan electrode of a plasma display panel,
A sustain circuit for supplying a pulse voltage;
A power recovery circuit that is electrically connected to the sustain circuit and recovers power from the display panel;
A semiconductor power module comprising: a separation circuit that selectively separates a current path between the sustain circuit and the scan driver circuit.

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