JP4408835B2 - Semiconductor integrated circuit device - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit comprising a plurality of output transistors and an output pad connected to an output signal line from each output transistor, and a multi-channel semiconductor in which a plurality of semiconductor integrated circuits are arranged as basic cells. The present invention relates to an integrated circuit, and more particularly to a layout of a binary output or ternary output semiconductor integrated circuit and a multichannel semiconductor integrated circuit.

  Conventionally, a circuit shown in FIG. 7 is known as a ternary output circuit. The ternary output circuit of FIG. 1 includes a first high-side transistor 4 for first high-level output, a second high-side transistor 5 for middle-level output, a diode 8 for backflow prevention, and a low-level output circuit. A low-side transistor 10, a first level shift circuit 6 that outputs a high-level output control signal, a second level shift circuit 7 that outputs a middle-level output control signal, and first, second level shift circuits, and a low-side transistor 10 A predriver 9 to be controlled, a first high voltage power supply terminal 12 to which a high level power supply voltage is applied from the outside, a second high voltage power supply terminal 13 to which a middle level power supply voltage is applied from the outside, and an output terminal 18 And an input terminal 19 for giving a trigger signal to the pre-driver 9.

  FIG. 8 is a block diagram showing a configuration of a multi-channel semiconductor integrated circuit using the ternary output circuit shown in FIG. 7 as a standard cell. As shown in the figure, the multi-channel semiconductor integrated circuit includes a plurality of standard cells and a control logic for controlling them. The control logic controls the pre-driver 9 of each standard cell in order to control the sequential output of a plurality of standard cells.

  FIG. 5 is a diagram showing a layout on the semiconductor chip of the ternary output circuit shown in FIG. As shown in the figure, the layout of the ternary output circuit is such that the low-side transistor 10, the first high-side transistor 4, the first level shift circuit 6, and the pre-driver 9 are arranged in the first column, and the output in the second column. A bonding pad 11, a second high side transistor 5, a diode 8, and a second level shift circuit 7 are arranged and wired. The reason why they are arranged in two rows in this way is to make the lengths of the respective wirings, which are the flow of signals from high-level, middle-level, and low-level input to output, the same length.

  FIG. 6 is a layout diagram on the semiconductor chip of the multi-channel semiconductor integrated circuit shown in FIG. In this figure, the ternary output circuit shown in FIG. 7 is a standard cell. The layout on the semiconductor chip of the multi-channel semiconductor integrated circuit is as shown in FIG. As shown in the figure, a plurality of standard cells 26 are arranged in two rows with the output bonding pad 11 side for bonding facing the outside of the semiconductor chip 21. A timing generation block 15 is arranged between the two columns. The timing generation block 15 includes the same number of timing generating unit cells 16 as the standard cells 26, one by one.

The timing generation block 15 functions as one shift register for controlling the timing of the trigger signal to each pre-driver 9 and the standard cell output, for example, according to the control signal from the input control terminal 20. The output of each timing generating unit cell 16 is connected to the input terminal 19 in the corresponding standard cell 26 via the bus wiring 36. In this case, the plurality of standard cells 26 output the pulse waveforms in order using the shift operation of the timing generation block 15 as a trigger. The input control terminal 20 is provided with a surge protection element 37 that forms a path for escaping surges and electrostatic noise to protect the internal circuit.
Japanese Patent Laid-Open No. 3-195045 (FIG. 3A)

  Incidentally, according to the layout of the ternary output circuit shown in FIG. 5, the low-side transistor 10, the first high-side transistor 4, the first level shift circuit 6, and the pre-driver 9 are arranged in the first column, and the second column. The output bonding pad 11, the second high-side transistor 5, the diode 8, and the second level shift circuit 7 are arranged in a two-row configuration. Therefore, when high withstand voltage and large current are required as output characteristics of the ternary output circuit, the area of the basic cell unit including each output transistor and level shift circuit becomes large, and the area under the pre-driver 9 in the ternary output circuit As a result, there is a problem in that the empty space 38 that can be reduced is increased and the degree of integration of the ternary output circuit is lowered.

  In addition, with regard to the multi-channel semiconductor integrated circuit shown in FIG. 6, in recent years, it has been required to improve the degree of integration so that one semiconductor chip can have more output channels. When the ternary output circuit shown in FIG. 5 is used as the standard cell 26, the area of the semiconductor chip increases in the vertical direction as the number of standard cells 26 arranged in one semiconductor chip increases. End up. However, the cell width of the timing generation unit cell 16 in the timing generation block for driving the standard cell 26 is smaller than the cell width of the standard cell 26. Therefore, when the standard cell 26 and the timing generation block 15 in the multi-channel semiconductor integrated circuit are laid out as shown in FIG. 6 of the prior art, an unnecessarily large empty space 38 is created below the timing generation block 15 of the semiconductor integrated circuit. As a result, there is a problem that the degree of integration is reduced.

  Further, in FIG. 6, there is a difference in the length of the bus wiring 36 from the timing generating unit cell 16 to the pre-driver 9 in each standard cell 26. Accordingly, there is a problem that the wiring capacity increases and the signal delay time increases. As a result, there is a problem that the output characteristics (particularly the delay time) of the respective ternary output circuits are greatly imbalanced between the portions where the timing generation unit cell 16 and the bus wiring 36 of the pre-driver 9 are short and long.

  In view of the above problems, the present invention improves the integration degree of the output circuit and the multi-channel semiconductor integrated circuit even as a standard cell, and reduces the unbalance of the output characteristics between the output circuits and the semiconductor integrated circuit and the multi-layout optimally laid out. An object is to provide a channel semiconductor integrated circuit.

  In order to solve the above problems, a semiconductor integrated circuit according to the present invention includes a first source electrode formed on a semiconductor substrate and located on a first metal layer, and a first drain electrode located on the first metal layer, and includes a first source. A first output transistor in which one of the electrode and the first drain electrode includes one or more linear partial electrodes and the other surrounds the partial electrodes; and a first output transistor formed on the semiconductor substrate and positioned on the first metal layer Two source electrodes and a second drain electrode located on the first metal layer, one of the second source electrode and the second drain electrode including one or more linear partial electrodes, and the other surrounding the partial electrode The second output transistor, the output pad arranged in a row with the second output transistor across the first output transistor, and the second metal layer on a different layer from the first metal layer. Dray A first connection wiring that is electrically connected to the electrode, and an electrical connection between the first drain electrode of the first output transistor and the second drain electrode of the second output transistor, which is located in the second metal layer. Second connection wiring connected to each other.

According to this configuration, it is possible to remove the empty space in the semiconductor integrated circuit as compared with the case where two rows are arranged, so that the degree of integration can be improved. In addition, since the first drain electrode is used as an output jumper line for the second output transistor, the signal path from the second drain electrode of the second output transistor to the output pad can be minimized. That is, the path of the output signal from the second drain electrode to the output pad is, in order, the second drain electrode, the second connection wiring, the first drain electrode, the first connection wiring, and the output pad of the second output transistor. As described above, since the first drain electrode is used as a jumper line for transmitting the output signal of the second output transistor, it is not necessary to form an independent wiring from the second drain electrode to the output pad. The signal path from the drain electrode to the output pad can be minimized. Further, since one of the first and second source electrodes and the first and second drain electrodes is linear, the current driving capability of the first and second output transistors can be increased. Further, the current drive capability of the first and second output transistors can be increased by the linear electrodes. In addition, the first and second connection wirings can each be formed wide so as to cover the two linear drain electrodes, and the wiring resistance can be reduced. Here, the semiconductor integrated circuit further includes the first source A first power supply wiring for supplying a first power supply voltage to a first source electrode electrically connected to the first source electrode, which is wired by a second metal layer so as to intersect the electrode and the first drain electrode, and a part of the second source electrode And a second power supply wiring that supplies a second power supply voltage to the second source electrode that is wired by the second metal layer so as to intersect a part of the second drain electrode and is electrically connected. Good.

  According to this configuration, the first power supply wiring can be further disposed on a part of the first drain electrode, and the first power supply is composed of at least two metal layers including the first metal layer and the second metal layer. A voltage can be supplied to the first source electrode. Similarly, the second power supply wiring can be disposed on a part of the second drain electrode, and the second power supply voltage is supplied to the second source in at least two metal layers including the first metal layer and the second metal layer. The electrode can be supplied. As a result, the metal wiring can be efficiently arranged while minimizing the wiring space by the second metal layer.

  Here, the semiconductor integrated circuit is further arranged on the opposite side of the first output transistor across the output pad, and a third source electrode located in the first metal layer and a third drain electrode located in the first metal layer A third output transistor in which one of the third source electrode and the third drain electrode includes one or more linear partial electrodes and the other surrounds the partial electrodes, and is located in the second metal layer A third connection wiring for electrically connecting the output pad and the third drain electrode may be provided.

  According to this configuration, the first to third output transistors can be arranged in a line, and the path of the output signal from each output transistor can be minimized. In addition, the metal wiring can be efficiently arranged while minimizing the wiring space by the second metal layer.

  Here, the layout width of the semiconductor integrated circuit may correspond to the width of the first and second output transistors.

According to this configuration, the empty space in the width direction in the layout of the semiconductor integrated circuit can be minimized. Here, the first output transistor includes a high side transistor for outputting a high level signal and a low level transistor. One of the low-side transistors for outputting a signal may be used, and the second output transistor may be the other of them.

  Here, the semiconductor integrated circuit further includes a first control circuit unit that generates a gate control signal to the first output transistor, a second control circuit unit that generates a gate control signal to the second output transistor, And a pre-driver section that drives the second control circuit section, and the widths of the first and second control circuit sections and the pre-driver section are equivalent to the widths of the first and second output transistors, respectively. The first control circuit unit, the pre-driver unit, the first and second output transistors, and the output pad may be arranged in a line.

  According to this configuration, since the width of each cell is equivalent to the width of the output transistor, the empty space in the semiconductor integrated circuit can be further reduced. Furthermore, when a plurality of semiconductor integrated circuits are arranged as cells, the effect of reducing free space is accumulated, so that the degree of integration can be further improved.

  Here, the withstand voltage of the first and second output transistors may be 100V or more.

  According to this configuration, the semiconductor integrated circuit can be used as a so-called power transistor having high current driving capability and high breakdown voltage.

  The multi-channel semiconductor integrated circuit of the present invention includes a multi-channel cell array that is an array of a plurality of basic cells, a timing generation block that is disposed in the center of the semiconductor chip and outputs a timing signal to each basic cell, A plurality of basic cells and a plurality of wirings for transmitting the timing signal between the timing generation blocks are provided, and the plurality of basic cells are symmetrically arranged on both sides of the circuit block. The basic cell is formed on the semiconductor substrate and includes a first source electrode located on the first metal layer and a first drain electrode located on the first metal layer, the first source electrode and the first drain electrode being A first output transistor including one or more linear partial electrodes and the other surrounding the partial electrodes; a second source electrode formed on a semiconductor substrate and positioned in a first metal layer; and a first metal A second output transistor including a second drain electrode located in a layer, wherein one of the second source electrode and the second drain electrode includes one or more linear partial electrodes, and the other surrounds the partial electrodes; An output pad arranged in a row with the second output transistor across the first output transistor, and a second metal layer in a different layer from the first metal layer, and an electrical connection is made between the output pad and the first drain electrode. Contact A second connection line located on the second metal layer and electrically connected between the first drain electrode of the first output transistor and the second drain electrode of the second output transistor. Connection wiring.

  According to this configuration, since a multi-channel cell array is formed from semiconductor integrated circuits (basic cells) formed in a single column arrangement, the unnecessary large empty space that appears below the conventional circuit block can be significantly reduced. And the degree of integration of the multi-channel semiconductor integrated circuit can be improved. In addition, since the plurality of basic cells are arranged symmetrically on both sides of the circuit block, it is possible to minimize the unbalance of the length of each wiring that transmits the timing signal from the circuit block to the basic cell. Thus, variation in delay characteristics can be reduced.

  Here, each basic cell is further wired by the second metal layer so as to intersect the first source electrode and the first drain electrode, and supplies the first power supply voltage to the electrically connected first source electrode. The second power supply voltage is applied to the first power supply wiring and the second source electrode, which is wired by the second metal layer so as to intersect with a part of the second source electrode and a part of the second drain electrode. A second power supply wiring to be supplied, and the first power supply wiring and the second power supply wiring may be arranged in a straight line.

  According to this configuration, the first and second power supply wirings can be connected to a plurality of basic cells with a straight line, that is, the shortest wiring.

  Here, the multi-channel semiconductor integrated circuit may further include at least two ground potential wirings for transmitting a ground potential along at least two sides of the timing generation block.

  According to this configuration, the influence of crosstalk and noise from the circuit block to the basic cell can be suppressed by the ground potential wiring.

  Here, the multi-channel semiconductor integrated circuit is further disposed at one end in the semiconductor chip and has a first pad that is at a ground potential, and a second pad that is disposed at the other end in the semiconductor chip and has a ground potential. And one of the first power supply wiring and the second power supply wiring is at a ground potential and may be connected to the first pad and the second pad.

  According to this configuration, since the impedance of the wiring of the ground potential that determines the low level of the output transistor for outputting the low level signal in each basic cell is reduced, the influence from noise is further prevented, and the output characteristics are reduced. Can be stabilized.

  As described above, according to the semiconductor integrated circuit of the present invention, the empty space in the semiconductor integrated circuit can be removed, so that the degree of integration can be improved. In addition, since variations in the length of the output signal line from each output transistor to the output pad are minimized, variations in the delay time of the output signal in the semiconductor integrated circuit can be minimized.

  Further, according to the multi-channel semiconductor integrated circuit of the present invention, the effect of reducing the vacant space is accumulated by arranging a plurality of semiconductor integrated circuits arranged in one column as cells, so that the degree of integration can be further improved. Can do. In addition, it is possible to minimize the unbalance of the lengths of the wirings that transmit the timing signal from the timing generation block to the basic cell, and to reduce variations in delay characteristics. Further, the influence of the crosstalk and noise from the timing generation block to the basic cell can be suppressed by the ground potential wiring. In addition, the impedance of the wiring of the ground potential that determines the low level of the output transistor for outputting the low level signal in each basic cell can be reduced, the influence from noise can be further prevented, and the output characteristics can be stabilized. it can.

  FIG. 1 is a plan view showing a layout configuration of a ternary output circuit as a semiconductor integrated circuit according to an embodiment of the present invention. The ternary output circuit shown in the figure corresponds to the circuit diagram shown in FIG. Further, the ternary output circuit cell shown in the layout of FIG. 1 can be used as one standard cell. The ternary output circuit in FIG. 1 includes a first high-side transistor 4 for high-level output, a second high-side transistor 5 for middle-level output, a diode 8 for backflow prevention, and a low-side transistor for low-level output. 10, a first level shift circuit 6 that outputs a high level output control signal, a second level shift circuit 7 that outputs a middle level output control signal, and the first and second level shift circuits and the low-side transistor 10. A pre-driver 9, an output bonding pad 11, and an input terminal 19 for giving a trigger signal to the pre-driver 9 are provided. The first high-side transistor 4, the second high-side transistor 5, and the low-side transistor 10 are power transistors having a DMOS structure and have a current drive capability of 100 mA or more. Further, as the power transistor for driving the PDP, a transistor having a withstand voltage of 100 V or more is adopted.

  In the layout shown in the figure, each circuit element is arranged in a line as a cell. With such a single row arrangement, the empty space 38 in the semiconductor integrated circuit can be removed. The layout width of the semiconductor integrated circuit corresponds to the cell width of output transistors such as the first high-side transistor 4, the second high-side transistor 5, and the low-side transistor 10. That is, the layout width of the semiconductor integrated circuit is substantially the same as the width of the output transistor, and more precisely, the width obtained by adding a slight wiring area to the width of the output transistor is the layout width of the semiconductor integrated circuit. It has become.

  Further, the layout of the ternary output circuit is such that the second high-side transistor 5, the diode 8, and the second level shift circuit 7 are sequentially arranged on the left side with the output bonding pad 11 as the center, and the low-side transistor 10 and the first high-side transistor are arranged on the right side. The side transistor 4, the first level shift circuit 6, and the pre-driver 9 are arranged in order. With this arrangement, variations in the length of the output signal line from each transistor to the output pad can be minimized, and variations in the delay time of the output signal in the semiconductor integrated circuit can also be minimized.

  Further, the first level shift circuit 6, the second level shift circuit 7 and the pre-driver 9 are designed in accordance with the cell width of the low side transistor 10 having the largest cell width. As a result, in the prior art, the cell arrangement in the standard cell 26 is configured in two rows as shown in FIG. 5, and in the present invention, a wasteful empty space 38 is formed below the cells of the pre-driver 9 in the present invention. Since it is composed of one column, useless empty space 38 can be excluded and the degree of integration can be improved.

  FIG. 2 is an enlarged plan view of the periphery of the low-side transistor 10 of the ternary output circuit shown in FIG. FIG. 3 is an enlarged plan view of the periphery of the second high-side transistor 5 of the ternary output circuit shown in FIG. 2 and 3, the hatched portion indicates the first metal layer 25. The first metal layer 25 is electrically insulated from the second metal layer 24, which is a different layer, by an insulating film (not shown), and electrically connected to the second metal layer 24 by a through hole (also referred to as a contact) 27. Connected. The second metal layer 24L above the low-side transistor 10 is a ground potential wiring, the second metal layer 24H above the first high-side transistor 4 is a first high-voltage power supply wiring corresponding to the high level, and the diode 8 The upper second metal layer 24M is a second high voltage power supply wiring corresponding to the middle level. Reference numeral 24 denotes a second metal layer, and reference numeral 25 denotes a first metal layer. First subscripts L, M, and H of reference numerals 24 and 25 correspond to a low level, a middle level, and a high level. The second subscripts s and d of reference numerals 24 and 25 correspond to the source and drain.

  In the figure, the low-side transistor 10 is formed on a semiconductor substrate. The source electrode 25Ls is located on the first metal layer on the source region 29 of the low-side transistor 10. The drain electrode 25Ld is located on the first metal layer on the drain region 28 of the low-side transistor 10. The drain electrode 25Ld is surrounded by the source electrode 25Ls on the surface of the semiconductor substrate. The drain region 28 of the low side transistor 10 is surrounded by the source region 29 of the low side transistor 10 on the semiconductor substrate. In the figure, the drain electrode 25Ld is composed of two linear partial electrodes. Each of the partial electrodes is surrounded by the source electrode 25Ls on the surface of the semiconductor substrate. In addition, the drain electrode 25L is an electrode that originally outputs a low level signal, and is also used as a path (jumper line) for transmitting a high level signal in this embodiment.

  The first high side transistor 4 is formed on a semiconductor substrate. The source electrode 25 </ b> Hs is located on the first metal layer on the source region 31 of the first high-side transistor 4. The drain electrode 25Hd is located on the first metal layer above the drain region 30 of the first high-side transistor 4. The drain electrode 25Hd is surrounded by the source electrode 25Hs on the surface of the semiconductor substrate. The drain region 30 of the first high side transistor 4 is surrounded by the source region 31 of the first high side transistor 4. In the figure, the drain electrode 25Hd is composed of two linear partial electrodes. Each of the partial electrodes is surrounded by the source electrode 25Hs on the surface of the semiconductor substrate.

  The output bonding pad 11 is usually located in the first metal layer and the second metal layer, and is formed by a metal layer that is at least the uppermost layer of the semiconductor integrated circuit. The output bonding pad 11 is arranged in line with the first high-side transistor 4 with the second low-side transistor 10 interposed therebetween.

  The connection wiring 24A is located in the second metal layer and extends from the output bonding pad 11 to the end of the drain electrode 25Ld on the output bonding pad 11 side. The second metal layer is different from the first metal layer and is insulated from the first metal layer. The connection wiring 24A is electrically connected to the end of the drain electrode 25Ld on the output bonding pad 11 side through a contact. The connection wiring 24A not only transmits a high level signal to the output bonding pad 11, but also serves to transmit a low level signal.

  The connection wiring 24B is located in the second metal layer and extends from the end of the drain electrode 25Ld on the first high-side transistor 4 side to the end of the drain electrode 25Hd on the low-side transistor 10 side. The connection wiring 24B is electrically connected to the end of the drain electrode 25Ld on the first high side transistor 4 side through a contact, and is electrically connected to the end of the drain electrode 25Hd on the side of the low side transistor 10 through a contact.

  The power supply wiring 24L is wired by the second metal layer so as to intersect the longitudinal direction of the source electrode 25Ls and the drain electrode 25Ld. The power supply wiring 24L is electrically connected to the source electrode 25Ls through a contact in order to supply the first power supply voltage (low level) to the source electrode 25Ls.

  The power supply wiring 24H is wired by the second metal layer so as to intersect the longitudinal direction of the source electrode 25Hs and the drain electrode 25Hd. The power supply wiring 24H is electrically connected to the source electrode 25Hs through a contact in order to supply the second power supply voltage (high level) to the source electrode 25Hs.

  The second high side transistor 5 is disposed on the opposite side of the low side transistor 10 with the output bonding pad 11 interposed therebetween.

  The source electrode 25Ms is formed of the first metal layer on the source region 35 of the second high side transistor 5. The drain electrode 25Md is located in the first metal layer on the drain region 34 of the second high-side transistor 5, and the third drain electrode is surrounded by the third source electrode on the surface of the semiconductor substrate. The drain region 34 of the second high side transistor 5 is surrounded by the source region 35 of the second high side transistor 5 on the semiconductor substrate. In the figure, the drain electrode 25Md is composed of two linear partial electrodes. Each of the partial electrodes is surrounded by a source electrode 25Ms formed on the semiconductor substrate.

  The connection wiring 24C is wired by a second metal layer extending from the output bonding pad 11 to the end of the drain electrode 25Md on the output bonding pad 11 side, and the connection wiring 24C is connected to the end of the drain electrode 25Md on the output bonding pad 11 side. Electrically connected by contact.

  2, the source electrode 25Ls of the low-side transistor 10 is connected to the power supply wiring 24L that is the ground potential wiring, and the drain electrode 25Ld of the low-side transistor 10 is output by the connection wiring 24A that is the output signal line. Connected to the bonding pad 11. A control signal line from the pre-driver 9 is connected to the gate region.

  In the first high-side transistor 4, the source electrode 25Hs of the first high-side transistor 4 is connected to the power supply wiring 24H that is the first high-voltage power supply wiring, and the drain electrode 25Hd of the first high-side transistor 4 is connected to the output signal line. Is connected to the drain electrode 25Ld of the low-side transistor 10 through the connection wiring 24B. As a result, the output signal from the drain electrode 25Hd of the first high-side transistor 4 is transmitted to the output bonding pad 11 via the two drain electrodes 25Ld immediately below the power supply wiring 24L wired by the second metal layer. Is done. In other words, when the first high-side transistor 4 is on, the high-level output signal from the first high-side transistor 4 is the drain electrode 25Hd of the first high-side transistor 4, the connection wiring 24B, and the drain electrode 25Ld of the low-side transistor 10. Then, the signal is output from the output bonding pad 11 through the connection wiring 24A in order. As described above, the drain electrode 25Ld of the low-side transistor 10 is also used as a jumper line for transmitting not only a low level signal output but also a high level output signal. As a result, the number of output signal lines to the output bonding pad 11 can be reduced, and the degree of integration can be improved.

  In the second high-side transistor 5 of FIG. 3, the source electrode 25Ms of the second high-side transistor 5 is connected to the power supply wiring 24M, which is the second high-voltage power supply wiring, via the diode 8, and the second high-side transistor The drain electrode 25Md of 5 is connected to the output bonding pad 11 by a connection wiring 24D which is an output signal line.

  In the circuit configuration shown in FIG. 7, the ternary output circuit operates normally even if the series circuit of the diode 8 and the second high-side transistor 5 is implemented with another circuit configuration in which they are replaced. The arrangement of the diode 8 and the second high-side transistor 5 in FIGS. 1 and 3 may be interchanged according to the circuit configuration.

  FIG. 4A is a plan view showing a layout configuration of the ternary output multi-channel semiconductor integrated circuit according to the embodiment of the present invention. The ternary output multi-channel semiconductor integrated circuit includes a first high-voltage power supply wiring 1, a second high-voltage power supply wiring 2, a ground potential wiring 3, a first high-voltage power supply terminal 12, and a second high voltage on a semiconductor chip 21. A power supply terminal 13, a ground terminal 14, a timing generation block 15, a timing generation unit cell 16, an input control terminal 20, a surge protection element, an array of standard cells 26, and the like are formed.

  Here, in the layout of the ternary output multi-channel semiconductor integrated circuit, the ternary output circuit shown in FIG. A timing generation block 15 is arranged at the center of the semiconductor chip 21. The timing generation block 15 is a set of timing generation unit cells 16 including an input control circuit, a shift register for controlling output timing, and a latch circuit for holding the output. The same number of timing generating unit cells 16 as standard cells 26 are arranged. The timing generation block 15 functions as one shift register for controlling the timing of the trigger signal to each pre-driver 6 and the standard cell output according to the control signal from the input control terminal 20, for example. The output of each timing generating unit cell 16 is connected to the input terminal 19 in the corresponding standard cell 26 as shown in FIG. In this case, the plurality of standard cells 26 sequentially output pulse waveforms triggered by the shift operation of the timing generation block 15, and operate as a control circuit for a display device such as a plasma display panel (PDP). The pulse waveform output from the ternary output circuit is, for example, normally a high level output in the case of negative logic, and is output at a low level for t1 time under the control of the pre-driver 9 receiving the trigger signal, and further at a middle level for t2 time Return to high level after output.

  In FIG. 4A, a plurality of standard cells 26 are arranged symmetrically so that the pre-driver 9 and the timing generating unit cell 16 are adjacent to each other at the left and right ends of the timing generating block 15, and the timing generating unit cell 16 and the pre-driver 9 are connected by bus wiring. 36 is connected. In addition, two ground terminals (bonding pads) 14 are arranged one above the other, and the ground potential wiring 3 (power supply wiring 24L in FIG. 2) is passed over the low-side transistor 10 in the standard cell 26, and above the semiconductor chip 21. The two ground terminals 14 arranged are connected to the two ground terminals 14 arranged below the semiconductor chip 21.

  In the embodiment of the present invention, the internal configuration of the standard cell 26 (ternary output circuit) arranged in the semiconductor chip is not a two-row arrangement as shown in FIG. 5 in the prior art but a one-row arrangement as shown in FIG. It has become. Therefore, even when the number of standard cells 26 to be arranged increases, an increase in the vertical direction of the semiconductor chip area as shown in FIG. 6 in the conventional example is suppressed, and an unnecessary empty space 38 that appears below the timing generation block 15 is formed. Minimization can be achieved, and improvement in the degree of integration of the multi-channel semiconductor integrated circuit is realized. Further, since there is almost no increase in the vertical direction of the semiconductor chip 21, it is possible to suppress variations in the length of the bus wiring 36 between the pre-driver 9 and the timing generation unit cell 16, and therefore, variations in delay time are also suppressed, and each output channel is suppressed. It can be reduced that the output characteristics become unbalanced due to the difference in delay time generated between them.

  Furthermore, in the present invention, the ground terminals 14 are arranged above and below the semiconductor chip 21, and the ground potential wiring 3 is passed over the low-side transistor 10 in the standard cell 26, and the ground terminals 14 arranged above the semiconductor chip 21 The ground terminal 14 disposed below the semiconductor chip 21 is connected. Further, since the upper and lower ground terminals 14 in the semiconductor chip 21 are wire-bonded from the package, the potential of the ground terminal 14 is stable. Therefore, the wiring impedance of the ground potential wiring 3 can be reduced, and even when the output of each channel becomes a large current, the ground potential of each standard cell 26 is stabilized and uniform output characteristics can be obtained.

  As shown in FIG. 4B, the timing generation block 15 may be configured so that the ground potential wiring 3 surrounds three directions other than the direction in contact with the input control terminal 20. Further, the ground potential wiring 3 may surround two directions (both sides) of the timing generation block 15. That is, the timing generation block 15 is surrounded by the ground potential wiring 3 in three directions other than the direction in contact with the input control terminal 20. The ground potential wiring 3 serves as a shield to prevent external noise entering from the output bonding pad 11 from passing through the standard cell 26 and being transmitted to the timing generation block 15. As a result, the signal input to the pre-driver 9 from the timing generation block 15 is stabilized, and the output characteristics are also stabilized.

  In the above embodiment, the ternary output circuit has been described. However, the present invention can be applied to a binary output circuit in exactly the same manner. In such a case, the circuit elements of the second high voltage power supply terminal 13, the diode 8, the second high side transistor 5, and the second level shift circuit 7 may be omitted in FIG. In FIG. 1, cells corresponding to these circuit elements may be deleted, and the output bonding pad 11 may be disposed between the first high-side transistor 4 and the low-side transistor 10.

  The layout of each output transistor shown in FIGS. 1 to 3 shows an example in which the drain electrode is composed of two linear partial electrodes. However, the number of linear partial electrodes is one, or three or more. Also good. The number of partial electrodes may be determined according to the driving capability required for each output transistor.

  Further, in the layout of each output transistor shown in FIGS. 1 to 3, an example in which the drain electrode is linear and is surrounded by the source electrode is shown, but this may be reversed. That is, the source electrode may be linear and surrounded by the drain electrode. Also in this case, the number of linear partial electrodes may be one or more.

  Moreover, in the layout of FIGS. 1-3, although the 1st metal layer 25 and the 2nd metal layer 24 are shown as a wiring layer, the number of wiring layers may be not only two layers but the multilayer of three or more layers, The first metal layer 25 and the second metal layer 24 may be swapped in the vertical relationship. Moreover, the 1st metal layer 25 and the 2nd metal layer 24 should just be a different layer, and may be any hierarchy in each of several wiring layers.

  In the above embodiment, the first metal layer 25 and the second metal layer 24 are not limited to aluminum wiring, and may be aluminum alloy, copper, copper alloy, or the like.

  The present invention relates to a semiconductor integrated circuit comprising a plurality of output transistors and an output pad connected to an output signal line from each output transistor, and a multi-channel semiconductor in which a plurality of semiconductor integrated circuits are arranged as basic cells. It is suitable for an integrated circuit, for example, a binary output circuit, a ternary output circuit, and a drive circuit for a display device such as a plasma display panel (PDP).

It is a top view which shows the structure of the ternary output circuit in embodiment of this invention. It is a low side transistor part enlarged plan view of a ternary output circuit. It is a 2nd high side transistor part enlarged plan view of a ternary output circuit. It is a top view which shows the structure of a ternary output multichannel semiconductor integrated circuit. It is a top view which shows the other structure of a ternary output multichannel semiconductor integrated circuit. It is a top view which shows the structure of the conventional semiconductor integrated circuit. It is a top view which shows the structure of the conventional ternary output multichannel semiconductor integrated circuit. It is a circuit diagram which shows the structure of a ternary output semiconductor integrated circuit. It is a block diagram of a ternary output multi-channel semiconductor integrated circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 1st high voltage power supply wiring 2 2nd high voltage power supply wiring 3 Ground potential wiring 4 1st high side transistor 5 2nd high side transistor 6 1st level shift circuit 7 2nd level shift circuit 8 Diode 9 Pre-driver 10 Low side transistor DESCRIPTION OF SYMBOLS 11 Output bonding pad 12 1st high voltage power supply terminal 13 2nd high voltage power supply terminal 14 Ground terminal 15 Timing generation block 16 Timing generation unit cell 17 Tri-level output circuit 18 Output terminal 19 Input terminal 20 Input control terminal 21 Semiconductor integrated circuit Chip 24 Second metal layer 24A to 24C Connection wiring 24L, 24M, 24H Power supply wiring 25 First metal layer 25Ld Low side transistor drain electrode 25Ls Low side transistor source electrode 25Hd First high side transistor drain Electrode 25Hs Source electrode of first high-side transistor 25Md Drain electrode of second high-side transistor 25Ms Source electrode of second high-side transistor 26 Standard cell 27 Through hole 28 Drain region of low-side transistor 29 Source region of low-side transistor 30 First high Side transistor drain region 31 Source region of first high side transistor 32 Diode anode portion 33 Diode cathode portion 34 Drain region of second high side transistor 35 Source region of second high side transistor 36 Bus wiring 37 Surge protection element 38 Free space

Claims (17)

A first source electrode located on the first metal layer and a first drain electrode located on the first metal layer are formed on the semiconductor substrate, and one of the first source electrode and the first drain electrode is one or more straight lines A first output transistor including a partial electrode having a shape and the other surrounding the partial electrode;
A second source electrode formed on the semiconductor substrate and positioned on the first metal layer and a second drain electrode positioned on the first metal layer, wherein one of the second source electrode and the second drain electrode is one or more straight lines A second output transistor including a partial electrode, the other surrounding the partial electrode;
An output pad arranged in a row with the second output transistor across the first output transistor;
A first connection wiring located in a second metal layer of a different layer from the first metal layer and electrically connecting the output pad and the first drain electrode;
A second connection wiring located in the second metal layer and electrically connecting between the first drain electrode of the first output transistor and the second drain electrode of the second output transistor;
A semiconductor integrated circuit comprising: The semiconductor integrated circuit according to claim 1, further comprising:
A first power supply wiring for supplying a first power supply voltage to the first source electrode, which is wired by the second metal layer so as to intersect the first source electrode and the first drain electrode and electrically connected;
Second power supply wiring for supplying a second power supply voltage to the second source electrode that is wired by the second metal layer so as to intersect with a part of the second source electrode and a part of the second drain electrode and electrically connected A semiconductor integrated circuit comprising: The semiconductor integrated circuit according to claim 1, further comprising:
A third source electrode disposed on the opposite side of the first output transistor across the output pad and positioned on the first metal layer; and a third drain electrode positioned on the first metal layer; A third output transistor in which one of the drain electrodes includes one or more linear partial electrodes and the other surrounds the partial electrodes;
A semiconductor integrated circuit, comprising: a third connection wiring located in the second metal layer and electrically connecting the output pad and the third drain electrode. The semiconductor integrated circuit according to claim 2, further comprising:
A third source electrode disposed on the opposite side of the first output transistor across the output pad and positioned on the first metal layer; and a third drain electrode positioned on the first metal layer; A third output transistor in which one of the drain electrodes includes one or more linear partial electrodes and the other surrounds the partial electrodes;
A semiconductor integrated circuit, comprising: a third connection wiring located by the second metal layer and electrically connecting the output pad and the third drain electrode. A semiconductor integrated circuit according to claim 1,
A semiconductor integrated circuit characterized in that the layout width of the semiconductor integrated circuit corresponds to the width of the first and second output transistors. A semiconductor integrated circuit according to claim 1,
The first output transistor is one of a high side transistor for outputting a high level signal and a low side transistor for outputting a low level signal,
The second output transistor is the other of them. A semiconductor integrated circuit, wherein: The semiconductor integrated circuit of claim 1, further comprising:
A first control circuit unit for generating a gate control signal to the first output transistor;
A second control circuit unit for generating a gate control signal to the second output transistor;
A pre-driver unit that drives the first and second control circuit units,
The widths of the first and second control circuit units and the pre-driver unit are equivalent to the widths of the first and second output transistors,
The first and second control circuit units, the pre-driver unit, the first and second output transistors, and the output pad are arranged in a line.
A semiconductor integrated circuit. The semiconductor integrated circuit according to claim 3, further comprising:
A first control circuit unit for generating a gate control signal to the first output transistor;
A second control circuit unit for generating a gate control signal to the second output transistor;
A third control circuit unit for generating a gate control signal to the third output transistor;
A pre-driver section for driving the first, second and third control circuit sections,
The widths of the first, second, and third control circuit units and the pre-driver unit are equivalent to the widths of the first, second, and third output transistors, respectively.
The semiconductor integrated circuit, wherein the first, second and third control circuit units, the pre-driver unit, the first, second and third output transistors and the output pad are arranged in a line. The semiconductor integrated circuit according to claim 1, comprising:
A semiconductor integrated circuit, wherein the first and second output transistors have a withstand voltage of 100 V or more. A multi-channel semiconductor integrated circuit,
A multi-channel cell array that is an array of a plurality of basic cells;
A timing generation block that is arranged in the center of the semiconductor chip and outputs a timing signal to each basic cell;
A plurality of wirings for transmitting the timing signal between a plurality of basic cells and a timing generation block;
The plurality of basic cells are symmetrically arranged on both sides of a circuit block,
The basic cell is
A first source electrode located on the first metal layer and a first drain electrode located on the first metal layer are formed on the semiconductor substrate, and one of the first source electrode and the first drain electrode is one or more straight lines A first output transistor including a partial electrode having a shape and the other surrounding the partial electrode;
A second source electrode formed on the semiconductor substrate and positioned on the first metal layer and a second drain electrode positioned on the first metal layer, wherein one of the second source electrode and the second drain electrode is one or more straight lines A second output transistor including a partial electrode, the other surrounding the partial electrode;
An output pad arranged in a row with the second output transistor across the first output transistor;
A first connection wiring located in a second metal layer of a different layer from the first metal layer and electrically connecting the output pad and the first drain electrode;
A second connection wiring located in the second metal layer and electrically connecting the first drain electrode of the first output transistor and the second drain electrode of the second output transistor;
A multi-channel semiconductor integrated circuit comprising: The multi-channel semiconductor integrated circuit according to claim 10,
Each basic cell
A first power supply wiring for supplying a first power supply voltage to the first source electrode, which is wired by the second metal layer so as to intersect the first source electrode and the first drain electrode and electrically connected;
Second power supply wiring for supplying a second power supply voltage to the second source electrode that is wired by the second metal layer so as to intersect with a part of the second source electrode and a part of the second drain electrode and electrically connected And
The multichannel semiconductor integrated circuit, wherein the first power supply wiring and the second power supply wiring are arranged in a straight line. The multi-channel semiconductor integrated circuit according to claim 10, further comprising:
A multichannel semiconductor integrated circuit comprising: at least two ground potential wirings for transmitting a ground potential along at least two sides of the timing generation block. The multi-channel semiconductor integrated circuit of claim 11, further comprising:
A first pad disposed at one end of the semiconductor chip and having a ground potential;
A second pad disposed at the other end of the semiconductor chip and having a ground potential;
One of the first power supply wiring and the second power supply wiring is at a ground potential, and is connected to the first pad and the second pad. The multi-channel semiconductor integrated circuit according to claim 10,
Each basic cell further includes:
A third source electrode disposed on the opposite side of the first output transistor across the output pad and positioned on the first metal layer; and a third drain electrode positioned on the first metal layer; A third output transistor in which one of the drain electrodes includes one or more linear partial electrodes and the other surrounds the partial electrodes;
A multi-channel semiconductor integrated circuit, comprising: a third connection wiring located in the second metal layer and electrically connecting the output pad and the third drain electrode. The multi-channel semiconductor integrated circuit according to claim 14,
The first, second, and third output transistors are combined into a first high-side transistor that outputs a high-level signal, a second high-side transistor that outputs a middle-level signal, and a low-side transistor that outputs a low-level signal. A multi-channel semiconductor integrated circuit characterized by that. The multi-channel semiconductor integrated circuit according to claim 10,
The multi-channel cell array generates a scanning signal for a display device. The multi-channel semiconductor integrated circuit according to claim 10,
A multi-channel semiconductor integrated circuit, wherein the first and second output transistors have a withstand voltage of 100 V or more.

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