JP2005261776A - Game machine - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To surely receive a control signal indicating the number of prize balls in a constitution quickly granting the prize balls at a low cost without being affected by characteristics of a microcomputer. <P>SOLUTION: When a power supply to the game machine is started, a putout control CPU becomes an operable state, after executing initialization, starts an putout control signal receiving processing, turns on a third connection confirming signal and executes a monitor processing monitoring first and second connection confirming signals from the main board. A CPU of the main board becomes an operable state, after executing the initialization, executes the monitor processing monitoring the third connection confirming signal, confirms the on state of the third connection confirming signal, and then turns on the first and the second connection confirming signals to start the game control processing. The putout control CPU confirms the on states of the first and the second connection confirming signals in the monitor processing and starts the putout control processing. The putout control processing starts almost simultaneously with the start of the game control processing. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention enables a player to play a predetermined game using a game medium, such as a pachinko game machine or a slot machine that pays out a prize game medium as a prize based on the fact that a payout condition is established by the game. It relates to gaming machines.

  As a gaming machine, a game medium such as a game ball is launched into a game area by a launching device, and when a game medium is won in a prize area such as a prize opening provided in the game area, a predetermined number of prize balls are paid out to the player. There is something to be done. Furthermore, there is provided a variable display unit capable of changing the display state, and configured to give a predetermined game value to the player when the display result of the variable display unit is in a predetermined specific display mode. is there.

  Note that the game value is the right that the state of the variable winning ball device provided in the gaming area of the gaming machine is advantageous for a player who is likely to win a ball, or the advantageous state for a player. Or a condition that the conditions for paying out a prize ball are easily established.

  In a pachinko gaming machine, a combination of a predetermined display mode with a display result of a variable display unit that displays a special symbol is usually referred to as “big hit”. When the big hit occurs, for example, the big winning opening is opened a predetermined number of times, and the game shifts to a big hit gaming state where the hit ball is easy to win.

  Game progress in the gaming machine is controlled by game control means such as a microcomputer. When the payout control means for controlling the prize ball payout is mounted on a payout control board different from the main board on which the game control means is mounted, the progress of the game is performed by the game control means mounted on the main board. Since it is controlled, the number of winning balls based on the winning is determined by the game control means, and a control signal indicating the number of winning balls is transmitted to the payout control board. Then, the payout control means performs a process of paying out the number of prize balls based on the winning based on the control signal from the game control means.

  In such a gaming machine, as described in Patent Document 1, a control signal indicating the number of winning balls is transmitted from the main board to the payout control board by unidirectional communication, and the payout control means is sent from the game control means. In accordance with the control signal, there has been a process of paying out a number of prize balls based on winning.

  In addition, as described in Patent Document 1, the game control unit receives a detection signal from a detection switch that detects a prize ball that has been paid out by the payout control unit. There was something that subtracted the number of winning balls.

  Further, as described in Patent Document 2, there is a delay between the initial reset circuit and the main board so that the control signal from the main board can be properly received by the sub-board such as the payout control board. By interposing a circuit, the input timing of the reset signal to the game control microcomputer mounted on the main board is delayed from the timing at which the reset signal is input to the electric component control microcomputer mounted on the other board. There was something to do.

JP 2001-314610 A JP 2001-300013 A (paragraphs 0107 to 0125, FIGS. 12 to 13)

  In the gaming machine described in Patent Document 1, the winning ball is paid out only by transmitting a control signal indicating the number of winning balls by unidirectional communication. Therefore, after the gaming ball is won, the winning ball is paid out. However, in order for the game control means to manage the number of unpaid prize balls, it is necessary to input a detection signal from the detection switch for detecting the paid-out prize balls to the game control means. Will occur. For this reason, the signal wiring in the gaming machine becomes complicated, and there is a problem that it is necessary to secure a wiring space, which may increase the cost.

  In addition, in the gaming machine described in Patent Document 2, a control signal from the main board can be properly received by the sub board even in unidirectional communication, but between the initial reset circuit and the main board. Since it was necessary to provide the delay circuit, there was a problem that the mounting area of the board on which the delay circuit was mounted increased and the component cost increased.

  Furthermore, when providing a delay circuit between the initial reset circuit and the main board, it is necessary to set the delay time in consideration of the operation timing of each electric component control microcomputer. When the specifications are changed or the microcomputer for controlling the electric parts is replaced with another type, there is a problem that the circuit configuration of the delay circuit has to be changed.

  Therefore, the present invention provides a game machine in which a game control means and a payout control means are provided separately, and can quickly give a game medium when a winning occurs, and the game control means has not paid out. The number of game media can be managed at low cost, and the control signal indicating the number of award balls is reliably received with a configuration that is low-cost and independent of the characteristics of the microcomputer without securing a large board mounting area. An object is to provide a gaming machine that can be used.

  The gaming machine according to the present invention allows a player to play a predetermined game using a game medium (for example, a game ball such as a pachinko ball), and a payout condition is established by the game (for example, the game ball is placed in the winning area). A game machine that pays out a prize game medium as a prize based on the winning), and game control means (for example, CPU 56, etc.) that executes game control for controlling the progress of the game (for example, control in steps S20 to S34). A payout means (for example, a ball payout device 97) for paying out premium game media; and a payout control means (for example, a payout control CPU 371) for executing payout control (eg, control in steps S750 to S760) including control of the payout means ) And signal line connecting means (for example, a connector) for connecting together a plurality of signal lines of signals transmitted between the game control means and the payout control means 9A and a cable provided with a connector 376A), and the game control means stores game control storage means (stores data on the number of prize game media to be paid out based on the establishment of the payout condition). For example, a payout number signal transmitting means for transmitting a payout number signal (for example, a prize ball number signal) for designating a payout number of a predetermined number of prize game media to the payout control means based on the prize game medium number data. (For example, the portion of the game control means that executes the processing of Step S255, Step S256, and Step S203) A prize game medium number data subtraction means (for example, a step in the game control means) for performing a subtraction process for subtracting a value corresponding to the designated payout number. The payout control means starts control signal reception control (for example, step S717) for receiving a control signal from the game control means based on the supply of power to the gaming machine. After that, payout side connection confirmation signal output means for turning on the payout side connection confirmation signal (for example, third connection confirmation signal) with respect to the game control means (for example, processing of steps S717 and S718 in the payout control means is executed. Portion) and unpaid number data indicating the number of unpaid premium game media that have not been paid out of the number of payouts of premium game media specified by the payout number signal transmitted by the payout number signal transmission means (for example, Payout control storage means (for example, award ball unpaid-out count counter) that stores variation data that fluctuates according to payout control including the value of the award ball unpaid-out counter. On the basis of the unpaid number data stored in the payout control storage means and the payout control means to pay out the prize game medium. A prize game medium payout control means (for example, a portion of the payout control means for executing the process of step S756) for executing the payout process, and the game control means controls the game based on the supply of power to the gaming machine. On the condition that the payout side connection confirmation signal is turned on by the payout side connection confirmation signal output means (for example, Y in step S96). The game side connection confirmation signal output means (for example, the scan in the game control means) that turns on the signals (for example, the first connection confirmation signal and the second connection confirmation signal) to the payout control means. And after the game side connection confirmation signal output means turns on the game side connection confirmation signal by the game side connection confirmation signal output means, the execution of the game control is started (for example, an interrupt permitted state). As shown in FIG. 14, the payout number signal, the game side connection confirmation signal, and the payout side connection confirmation signal are transmitted by a signal line connected by the signal line connection means (for example, After the payout connection confirmation signal is turned on by the payout side connection confirmation signal output means (for example, step S718), the payout control means outputs the game side connection confirmation signal within a predetermined monitoring period. On the condition that the game side connection confirmation signal is confirmed to be turned on by the means (for example, Y in step S719), the execution of the payout control is started (for example, the Tsu as interrupt enable state at flops S720 starts execution of the payout control processing shown in FIG. 32) that is characterized.

  The payout control means shifts the execution state of the payout control to an error state in response to the game side connection confirmation signal output from the game side connection confirmation signal output means being turned off after the execution of the payout control is started. The payout by the prize game medium payout control means when the payout side error state setting means (for example, the portion of the payout control means that executes the processing of steps S815 and S816) and the payout side error state setting means shifts to an error state. Dispensing stop means for stopping the execution of processing (for example, processing for setting the main control unconnected error bit in step S816 so that a new payout process is not executed so as to be determined as Y in step S621 in the payout control means) And a portion for executing the above.

  The payout control means shifts the execution state of the payout control to an error state in response to the game side connection confirmation signal output from the game side connection confirmation signal output means being turned off after the execution of the payout control is started. A payout-side error state setting means (for example, a portion of the payout control means that executes the processes of steps S815 and S816) and a take-in means for executing a take-in process for taking in the payout number signal transmitted by the payout number signal transmitting means ( For example, the portion for executing the process of receiving the award ball number signal in step S545 in the payout control means) and the payout control storage means for the number of prize game media specified by the payout number signal taken in by the take-in means Unpaid-out number data adding means for adding to the unpaid-out number data stored in (for example, the number of unpaid prize balls in step S545 in the payout control means) A portion that executes processing to be added to the counter) and when the payout side error state setting means shifts to an error state (for example, N in step S543, Y in step S815, step S816), Capture stop means (for example, when it is determined as N in step S543 in the payout control means, the error bit is set in step S816 without executing the processing from step S544 onward, and thereafter, step S541 is executed). And a portion for executing a process for determining Y in the above).

  The game control means shifts the execution state of the game control to the error state in response to the payout side connection confirmation signal output from the payout side connection confirmation signal output means being turned off after the execution of the game control is started. The number of payouts by the payout number signal transmission means when the game side error state setting means (for example, the portion of the game control means that executes the processing of steps S254 and S274) and the game side error state setting means shifts to an error state. Transmission stopping means for stopping signal transmission (for example, a part that executes the process of ending the award ball process without performing the process of step S202 when it is determined as Y in step S204 and step S205 in the game control means). You may have.

  The payout control means shifts the execution state of the payout control to an error state in response to the game side connection confirmation signal output from the game side connection confirmation signal output means being turned off after the execution of the payout control is started. When the payout side error confirmation setting means includes the payout side error state setting means (for example, the portion of the payout control means that executes the processing of steps S815 and S816), and the payout side error confirmation setting means outputs the error state In addition, the payout-side connection confirmation signal is turned off (for example, a part for executing processing for turning off the third connection confirmation signal when it is determined as Y in step S815 in the payout control means). May be.

  A payout detection means (for example, a payout count switch 301) that detects payout of a prize game medium and outputs a payout detection signal is provided, and the payout control means outputs a game side connection confirmation signal output means after starting the execution of payout control. In response to the game side connection confirmation signal from the player being turned off, payout side error state setting means for shifting the execution state of the payout control to an error state (for example, executing the processing of steps S815 and S816 in the payout control means) Each time the payout detection means detects the payout of the prize game medium, and subtracts the unpaid number data subtraction means (for example, a step in the payout control means) that subtracts the unpaid number data stored in the payout control storage means. The portion for executing the processing of S601 to S603), and the unpaid-out number data subtracting means -Even if the state is shifted to the state, every time the payout detecting means detects the payout of the prize game medium, the unpaid number data is subtracted (for example, the status of the error bit is confirmed in the prize ball lending control processing shown in FIG. 41). (The processing of steps S601 to S603 is performed without the above).

  A payout detection means (for example, a payout count switch 301) that detects payout of a prize game medium and outputs a payout detection signal is provided, and the payout control means outputs a game side connection confirmation signal output means after starting the execution of payout control. In response to the game side connection confirmation signal from the player being turned off, payout side error state setting means for shifting the execution state of the payout control to an error state (for example, the processing of steps S815 and S816 in the payout control means is executed. And a prize game medium signal output means (for example, a step in the payout control means) that outputs a prize game medium signal to the outside of the gaming machine each time the payout detection means detects payout of a predetermined number of prize game media. And the prize game medium signal output means is provided by the payout-side error state setting means. Even if the payout detection means detects the payout of a predetermined number of prize game media, it outputs a prize game medium signal (for example, confirms the state of an error bit in the information output process shown in FIG. 50). (Can perform each process without)

  The payout control means shifts the execution state of the payout control to an error state in response to the game side connection confirmation signal output from the game side connection confirmation signal output means being turned off after the execution of the payout control is started. A game-side connection confirmation signal is output when the payout-side error state setting means (for example, the portion of the payout control means that executes the processes of steps S815 and S816) and the payout-side error state setting means And an error state canceling means for canceling the error state in response to the game side connection confirmation signal from the means being turned on (for example, a part for executing the processing of steps S815 and S817 in the payout control means). It may be said.

  A gaming machine that pays out rental game media based on the establishment of a payout condition based on a loan request (for example, a ball rental request), and the payout control means starts from the game side connection confirmation signal output means after starting the execution of the payout control. In response to the game side connection confirmation signal being turned off, payout side error state setting means for shifting the execution state of the payout control to an error state (for example, the processing of steps S815 and S816 in the payout control means is executed) Part) and a lending game medium payout control means (for example, step S625 in the payout control means) for executing payout processing for controlling the payout means and paying out the loaned game media based on the fact that the payout condition by the loan request is satisfied. The portion for executing processing such as S627), and the rental game medium payout control means is based on the establishment of the payout condition by the loan request. Even when the error state is shifted to the error state setting means, the payout process is executed (for example, ball lending control is performed without determining whether or not there is a main control unconnected error in step S621). It may be configured.

  According to the first aspect of the present invention, the game control means stores the game control storage means for storing the number of prize game media that can specify the number of prize game media to be paid out based on the establishment of the payout condition, and the prize game. Based on the medium number data, a payout number signal transmitting means for transmitting a payout number signal for designating the number of payouts of a predetermined number of prize game media to the payout control means, and the payout number signal transmitting means transmitted the payout number signal. Accordingly, a prize game medium number data subtracting means for performing a subtraction process for subtracting a value corresponding to the number of payouts specified by the payout number signal from the prize game medium number data, wherein the payout control means is connected to the gaming machine. A payout side connection for turning on the payout side connection confirmation signal with respect to the game control means after starting control signal acceptance control for accepting a control signal from the game control means based on the supply of power Unpaid number data indicating the number of unpaid premium game media that have not been paid out of the number of payouts of premium game media designated by the payout number signal transmitted by the approval signal output means and the payout number signal transmission means Based on the payout control storage means for storing the fluctuation data that fluctuates depending on the payout control including the unpaid number data stored in the payout control storage means, the payout means is controlled to pay out the premium game medium. A prize-side connection confirmation signal after the game control means has entered a state in which game control can be executed based on the supply of power to the gaming machine. On the condition that the payout side connection confirmation signal is turned on by the output means, the game side connection confirmation signal that turns the game side connection confirmation signal on to the payout control means is turned on. After the game side connection confirmation signal output means is turned on by the game side connection confirmation signal output means, the execution of the game control is started, the payout number signal, the game side connection confirmation signal, and the payout side connection confirmation. The signal is transmitted by the signal line connected by the signal line connection means, and the payout control means turns on the payout side connection confirmation signal by the payout side connection confirmation signal output means and then within a predetermined monitoring period. In addition, since the game side connection confirmation signal output means confirms that the game side connection confirmation signal is turned on, the execution of the payout control is started. Sometimes it is possible to quickly give away prize game media and to manage the number of game media that have not been paid out by the game control means at a low cost. Furthermore, it is possible to reliably receive the payout number signal at a low cost and with a configuration that does not depend on the characteristics of the microcomputer used in the gaming machine without securing a large board mounting area.

  In the invention according to claim 2, the payout control means performs the payout control in response to the game side connection confirmation signal output from the game side connection confirmation signal output means being turned off after the execution of the payout control is started. A payout side error state setting means for shifting the execution state to an error state, and a payout stop means for stopping execution of the payout process by the prize game medium payout control means when the payout side error state setting means shifts to the error state. Therefore, the payout process can be stopped when there is a possibility that the communication between the game control means and the payout control means may not be accurately executed.

  In the invention according to claim 3, the payout control means performs the payout control in response to the game side connection confirmation signal output from the game side connection confirmation signal output means being turned off after the execution of the payout control is started. The payout side error state setting means for shifting the execution state to the error state, the take-in means for executing the take-in process for taking in the pay-out number signal transmitted by the pay-out number signal transmitting means, and the number of payouts taken in by the take-in means When an unpaid number data adding means for adding the number of payouts of the premium game medium designated by the signal to the unpaid number data stored in the payout control storage means and the payout side error state setting means shifts to an error state In addition, there is a capture stop unit that stops the execution of the capture process by the capture unit, and therefore communication between the game control unit and the payout control unit may not be performed accurately. To come, the number of prize game media specified by the payout number signal can be prevented that the payout control means misrecognition can be avoided that would adversely detrimental to the player.

  In the invention according to claim 4, the game control means performs the game control in response to the payout side connection confirmation signal output means from the payout side connection confirmation signal output means being turned off after the execution of the game control is started. A game side error state setting means for shifting the execution state to an error state, and a transmission stop means for stopping transmission of the payout number signal by the payout number signal transmitting means when the game side error state setting means shifts to the error state; Therefore, the payout process can be stopped when there is a possibility that the communication between the game control means and the payout control means may not be accurately executed.

  In the invention according to claim 5, the payout control means performs the payout control in response to the game side connection confirmation signal output from the game side connection confirmation signal output means being turned off after the execution of the payout control is started. It includes a payout side error state setting means for shifting the execution state to an error state, and the payout side connection confirmation signal output means turns off the payout side connection confirmation signal when it is shifted to the error state by the payout side error state setting means. The game control means side can be shifted to an error state in response to the payout control means side shifting to an error state, and the number of prize game media specified by the payout number signal Can be prevented from being misrecognized by the payout control means, and the recognition of the number of unpaid premium game media between the game control means and the payout control means can be prevented from being different. It is possible.

  According to the sixth aspect of the present invention, there is provided a payout detecting means for detecting payout of the prize game medium and outputting a payout detection signal. The payout control means outputs the game side connection confirmation signal output means after starting the execution of the payout control. Each time the game side connection confirmation signal from the player turns off, the payout side error state setting means for shifting the execution state of the payout control to the error state, and the payout detection means detect the payout of the prize game medium. And an unpaid-out number data subtracting means for subtracting unpaid-out number data stored in the payout control storage means, and the unpaid-out number data subtracting means has been shifted to an error state by the payout-side error state setting means. However, since the payout detecting means subtracts the unpaid number data every time the payout of the prize game medium is detected, the payout of the prize game medium is not performed even in an error state. It is possible to reliably manage.

  According to the seventh aspect of the present invention, there is provided payout detection means for detecting payout of the prize game medium and outputting a payout detection signal, and the payout control means is a game side connection confirmation signal output means after starting execution of the payout control. In response to the game side connection confirmation signal from the player being turned off, the payout side error state setting means for shifting the execution state of the payout control to the error state, and the payout detecting means pays out a predetermined number of prize game media. A prize game medium signal output means for outputting a prize game medium signal to the outside of the gaming machine each time it is detected, and the prize game medium signal output means is shifted to an error state by the payout side error state setting means. However, the payout detection means outputs the prize game medium signal every time it detects the payout of a predetermined number of prize game media. Out is the number of detected prize game media, winning balls signals can allow aggregation by fillable management device or the like, can allow perceive the payout of game media based on fraud.

  In the invention described in claim 8, the payout control means performs the payout control in response to the game side connection confirmation signal output from the game side connection confirmation signal output means being turned off after the execution of the payout control is started. The game-side connection confirmation signal from the game-side connection confirmation signal output means is in an ON state when the game-side connection confirmation signal output means is shifted to the error state by the payout-side error state setting means for shifting the execution state to the error state. Accordingly, the control state can be automatically restored when the error state is resolved because the error state canceling means for canceling the error state is included.

  According to the ninth aspect of the present invention, the gaming machine pays out the rented game medium based on the establishment of the payout condition by the loan request, and the payout control means outputs the game side connection confirmation signal after starting the execution of the payout control. Based on the fact that the payout side error state setting means for shifting the execution state of the payout control to the error state in response to the game side connection confirmation signal from the means being turned off, and that the payout condition by the lending request is satisfied A lending game medium payout control means for executing a payout process for controlling the payout means to pay out the rented game medium. Even if the setting means has shifted to an error state, the payout process is executed, so control related to gaming media lending that does not involve game control means. It can be continued, it is possible to smoothly proceed the game.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
First, the overall configuration of a pachinko gaming machine that is an example of a gaming machine will be described. FIG. 1 is a front view of a pachinko gaming machine as viewed from the front. In the following embodiments, a pachinko gaming machine will be described as an example. However, the gaming machine according to the present invention is not limited to a pachinko gaming machine, and can be applied to other gaming machines such as a slot machine.

  The pachinko gaming machine 1 includes an outer frame (not shown) formed in a vertically long rectangular shape, and a game frame attached to the inside of the outer frame so as to be opened and closed. Further, the pachinko gaming machine 1 has a glass door frame 2 formed in a frame shape that is provided in the game frame so as to be opened and closed. The game frame includes a front frame (not shown) installed to be openable and closable with respect to the outer frame, a mechanism plate to which mechanism parts and the like are attached, and various parts attached to them (excluding game boards described later). Is a structure including

  As shown in FIG. 1, the pachinko gaming machine 1 has a glass door frame 2 formed in a frame shape. On the lower surface of the glass door frame 2 is a hitting ball supply tray (upper plate) 3. Under the hitting ball supply tray 3, there are provided an extra ball receiving tray 4 for storing game balls that cannot be accommodated in the hitting ball supply tray 3 and a hitting operation handle (operation knob) 5 for firing the game balls. A game board 6 is detachably attached to the back surface of the glass door frame 2. The game board 6 is a structure including a plate-like body constituting the game board 6 and various components attached to the plate-like body. A game area 7 is formed on the front surface of the game board 6.

  Near the center of the game area 7, there is provided a variable display device (special symbol display device) 9 including a plurality of variable display portions each variably displaying a symbol as identification information. The variable display device 9 has, for example, three variable display portions (symbol display areas) of “left”, “middle”, and “right”. In addition, the variable display device 9 is provided with four special symbol start memory display areas (start memory display areas) 18 for displaying the number of effective winning balls that have entered the start winning opening 14, that is, the start memory number. Each time there is a valid start prize, the display color changes (for example, changes from blue display to red display), and the start storage display area is increased by one. Each time the variable display of the variable display device 9 is started, the start memory number display area where the display color is changed is reduced by 1 (that is, the display color is returned to the original). In this example, the symbol display area and the start memory display area are provided separately, so that the start memory number can be displayed even during variable display. The start memory display area may be provided in a part of the symbol display area. Further, the display of the starting memory number may be interrupted during variable display. In this example, the start memory display area is provided in the variable display device 9, but a display (special symbol start memory display) for displaying the start memory number may be provided separately from the variable display device 9. Good.

  Below the variable display device 9, a variable winning ball device 15 is provided as a start winning port 14. The winning ball that has entered the start winning opening 14 is guided to the back of the game board 6 and detected by the start opening switch 14a. A variable winning ball device 15 that opens and closes is provided below the start winning opening 14. The variable winning ball device 15 is opened by a solenoid 16.

  An opening / closing plate 20 that is opened by a solenoid 21 in a specific gaming state (big hit state) is provided below the variable winning ball device 15. The opening / closing plate 20 is a means for opening and closing a large winning opening (variable winning ball apparatus). Of the winning balls guided from the opening / closing plate 20 to the back of the game board 6, the winning ball entering one (V winning area: special area) is detected by the V count switch 22, and the winning ball from the opening / closing board 20 is counted. 23. On the back of the game board 6, a solenoid 21A for switching the route in the special winning opening is also provided.

  When a game ball wins the gate 32 and is detected by the gate switch 32a, variable display of the normal symbol display 10 is started. In this embodiment, variable display is performed by alternately lighting the left and right lamps (the symbols can be visually recognized when the lamp is lit). When the stop symbol in the normal symbol display 10 is a predetermined symbol (winning symbol), the variable winning ball device 15 is opened for a predetermined number of times for a predetermined time. In the vicinity of the normal symbol display 10, a normal symbol start memory display 41 having a display unit with four LEDs for displaying the number of winning balls entered into the gate 32 is provided. Each time there is a prize at the gate 32, the normal symbol start memory display 41 increments the LED to be turned on by one. Then, every time variable display on the normal symbol display 10 is started, the number of LEDs to be lit is reduced by one.

  The game board 6 is provided with a plurality of winning holes 29, 30, 33, 39, and winning of game balls to the winning holes 29, 30, 33, 39 is performed by winning hole switches 29a, 30a, 33a, 39a, respectively. Detected. Each winning opening 29, 30, 33, 39 constitutes a winning area provided in the game board 6 as an area for accepting game media and allowing winning. The start winning opening 14 and the big winning opening also constitute a winning area that accepts game media and allows winning. Decorative lamps 25 blinking and displayed during the game are provided around the left and right sides of the game area 7, and an outlet 26 for absorbing a game ball that has not won a prize is provided at the bottom. Two speakers 27 that emit sound effects are provided on the left and right upper portions outside the game area 7. On the outer periphery of the game area 7, a top frame lamp 28a, a left frame lamp 28b, and a right frame lamp 28c are provided. Further, a decoration LED is installed around each structure (such as a big prize opening) in the game area 7. The top frame lamp 28a, the left frame lamp 28b, the right frame lamp 28c, and the decorative LED are examples of a decorative light emitter provided in the gaming machine.

  In this example, a prize ball LED 51 that is lit during award ball payout is provided in the vicinity of the left frame lamp 28b, and a ball break LED 52 that is lit when the supply ball is cut is provided in the vicinity of the top frame lamp 28a. It has been. As described above, the pachinko gaming machine 1 of this embodiment is provided with lamps and LEDs as light emitters in various places. Further, a prepaid card unit (hereinafter referred to as “card unit”) that enables lending of a ball by inserting a prepaid card is installed adjacent to the pachinko gaming machine 1 (not shown).

  The card unit includes, for example, a use indicator lamp that indicates whether or not the card unit is in a usable state, a connection table direction indicator that indicates which side of the pachinko gaming machine 1 corresponds to the card unit, When checking the card insertion indicator lamp that indicates that a card has been inserted, the card insertion slot into which a card as a recording medium is inserted, and the card reader / writer mechanism provided on the back of the card insertion slot A card unit lock is provided to release the unit.

  The game balls launched from the hit ball launching device enter the game area 7 through the hit ball rail, and then descend the game area 7. When the game ball enters the start winning port 14 and is detected by the start port switch 14a, the special symbol starts variable display (fluctuation) in the variable display device 9 if the variable display of the symbol can be started. If the variable display of the symbol cannot be started, the start memory number is increased by one.

  The variable display of the special symbol on the variable display device 9 stops when a certain time has elapsed. If the combination of special symbols at the time of stoppage is a jackpot symbol (specific display result), the game shifts to a jackpot gaming state. That is, the opening / closing plate 20 is opened until a predetermined time elapses or a predetermined number (for example, 10) of game balls wins. When a game ball wins the V winning area while the opening / closing plate 20 is opened and is detected by the V count switch 22, a continuation right is generated and the opening / closing plate 20 is opened again. The generation of the continuation right is allowed a predetermined number of times (for example, 15 rounds).

  When the combination of special symbols in the variable display device 9 at the time of stoppage is a combination of jackpot symbols (probability variation symbols) with probability fluctuations, the probability of the next jackpot increases. That is, it becomes a more advantageous state for the player in the probability variation state.

  When the game ball wins the gate 32, the normal symbol display unit 10 is in a state where the normal symbol is variably displayed. Further, when the stop symbol on the normal symbol display 10 is a predetermined symbol (winning symbol), the variable winning ball device 15 is opened for a predetermined time. Further, in the probability variation state, the probability that the stop symbol on the normal symbol display 10 becomes a winning symbol is increased, and the opening time and the number of times of opening of the variable winning ball device 15 are increased. That is, the opening time and the number of times of opening of the variable winning ball device 15 are increased when the stop symbol of the normal symbol is a winning symbol, or when the stop symbol of the special symbol is a probabilistic symbol. It changes to an advantageous state. Note that increasing the number of times of opening is a concept including changing from a closed state to an open state.

  Next, the structure of the back surface of the pachinko gaming machine 1 will be described with reference to FIG. FIG. 2 is a rear view of the gaming machine as seen from the back side.

  As shown in FIG. 2, on the back side of the gaming machine, a game in which a variable display control unit 49 including an effect control board 80 on which an effect control means for controlling the variable display device 9 is mounted, a game control microcomputer, and the like are mounted. A control board (main board) 31 is installed. In addition, a payout control board 37 on which a payout control microcomputer that performs ball payout control is mounted is installed. The production control means includes a variable display device 9 provided on the game board 6, various decoration LEDs, a normal symbol start memory display 41, a decoration lamp 25, a top frame lamp 28a provided on the frame side, and a left frame. The lamp 28b and the right frame lamp 28c are controlled to be turned on, and sound generation from the speaker 27 is controlled.

  The effect control means is realized by one effect control microcomputer mounted on the effect control board 80, but various decoration LEDs, normal symbol start memory display 41, and decoration lamp 25 provided on the game board 6. The drive circuit for driving the top frame lamp 28a, the left frame lamp 28b and the right frame lamp 28c provided on the frame side is mounted on a lamp driver board electrically connected to the effect control board 80. Yes. The drive circuit for driving the speaker 27 is mounted on a sound control board that is electrically connected to the effect control board 80.

  Further, a power supply substrate 910 and a touch sensor substrate 91 on which a power supply circuit for generating DC30V, DC21V, DC12V, and DC5V is mounted are provided. Most of the power supply substrate 910 overlaps with the main substrate 31, but there is an exposed portion that is exposed so as not to overlap with the main substrate 31. In the exposed portion, power supply to the main board 31 and each electric component control board (the effect control board 80 and the payout control board 37) in the gaming machine 1 and each electric component provided in the gaming machine is executed or cut off. Data stored in a power switch as a power supply permitting unit and a storage content holding unit included in the main board 31 and the payout control board 37 (for example, a backup RAM capable of holding the contents even when power supply is stopped) And a clear switch as an operation means for clearing. Furthermore, a replaceable fuse is provided inside the power switch at the exposed portion (inside the substrate).

  An electrical component control means including an electrical component control microcomputer is mounted on the electrical component control board. The electrical component control means is an electrical component provided in the gaming machine according to a command signal (control signal) from the game control means (game device: ball payout device 97, variable display device 9, light emitter such as a lamp or LED, The speaker 27 and the like are controlled. Hereinafter, description may be made by including the main board 31 in the electric component control board. In that case, the electric component control means mounted on the electric component control board indicates each of the game control means and the means for controlling the electric components provided in the gaming machine in accordance with a command signal from the game control means. . A substrate on which a microcomputer other than the main substrate 31 is mounted may be referred to as a sub-substrate.

  On the back side of the gaming machine, a terminal board 160 provided with terminals for outputting various information to the outside of the gaming machine is installed above. The terminal board 160 includes at least a ball break terminal for introducing the output of the ball break detection switch 167 and outputting it externally, a prize ball terminal for outputting prize ball information (prize ball number signal) and a ball. A ball lending terminal for externally outputting lending information (ball lending number signal) is provided. Near the center, an information terminal board (information output board) 34 having terminals for outputting various information from the main board 31 to the outside of the gaming machine is installed.

  The game balls stored in the storage tank 38 pass through the guide rail 39 and reach the ball payout device covered with the payout case 40A through the curve rod. Above the ball payout device, a ball break switch 187 is provided as a game medium break detection means. When the ball break switch 187 detects a ball break, the payout operation of the ball payout device stops. The ball break switch 187 is a switch that detects the presence or absence of a game ball in the game ball passage. In the vicinity of the head). When the ball break detection switch 167 detects a shortage of game balls, the game machine is replenished to the game machine from the supply mechanism provided on the gaming machine installation island.

  When a large number of game balls as prizes based on winning a prize and game balls based on a ball lending request are paid out and the hitting ball supply tray 3 is full, the game balls are guided to the surplus ball receiving tray 4 through the surplus ball passage. When the game ball is further paid out, a sensing lever (not shown) presses a full tank switch (not shown) as a storage state detection means, and the full tank switch as a storage state detection means is turned on. In this state, the rotation of the payout motor in the ball payout device stops, the operation of the ball payout device stops, and the driving of the hitting ball launching device also stops.

  In this example, the power supply board 910 and the payout control board 37 are installed in the game frame, and the main board 31 and the like are installed in the game board 6.

  FIG. 3 is a front view (FIG. 3 (A)) and a cross-sectional view (FIG. 3 (B)) showing the ball dispensing device 97 covered with the dispensing case 40A. The ball payout device 97 is fixed to the lower part of the passage body installed between the ball break switch 187 and the ball payout device 97. The passage body has a ball passage for flowing down two rows of game balls whose flow-down direction is converted into the left-right direction by a curve saddle. A ball break switch 187 is installed on the upstream side of the ball passage. In practice, a ball break switch is installed in each ball passage. The ball break switch 187 detects the presence or absence of a game ball in the ball passage. When the ball break switch 187 stops detecting a game ball, the ball discharge device 97 has a payout motor (not shown in FIG. 3). Rotation is stopped and game ball payout is immobilized.

  The ball break switch 187 is locked by a locking piece at a position where it can be detected that 27 to 28 game balls are present in the ball path.

  In the ball payout device 97, a payout motor (not shown) using a stepping motor rotates, for example, a cam, thereby paying out one winning ball or one game ball based on a ball lending request. Also, below the ball payout device 97, for example, a payout number count switch 301 using a proximity switch is provided. Each time one game ball falls from the ball payout device 97, the payout number count switch 301 is turned on. That is, the payout number count switch 301 detects a game ball actually paid out from the ball payout device 97. Therefore, the payout control means can count the number of game balls actually paid out by the detection signal of the payout number count switch 301. In this example, the payout number count switch 301 detects both the paid-out prize balls and lending balls. That is, the payout of prize balls and the payout of lending balls are detected by the same detection means. Therefore, the number of parts can be reduced, and the cost of the gaming machine can be reduced. However, the payout of prize balls and the payout of rental balls may be detected by separate detection means.

  In this embodiment, the ball payout device 97 is configured to perform both prize ball payout and ball lending. However, a ball payout device for paying out a prize ball and a ball payout device for lending a ball may be provided separately. When separately provided, the payout means is composed of a ball payout device for paying out a prize ball and a ball payout device for lending a ball. Further, for example, the configuration may be such that the winning ball payout and the ball lending are separated by changing the rotation direction of the cam or the sprocket, or the ball paying device 97 exemplified in the present embodiment (the cam is rotated by the motor). The present invention can be applied to any structure other than the structure).

  FIG. 4 is a block diagram illustrating an example of a circuit configuration in the main board 31. FIG. 4 also shows a payout control board 37, an effect control board 80, and the like. The main board 31 includes a basic circuit (corresponding to a game control microcomputer: game control means) 53 for controlling the pachinko gaming machine 1 according to a program, a gate switch 32a, a start port switch 14a, a V count switch 22, and a count switch 23. , And an input driver circuit 58 for giving signals from the winning opening switches 29a, 30a, 33a, 39a to the basic circuit 53, a solenoid 16 for opening / closing the variable winning ball apparatus 15, a solenoid 21 for opening / closing the opening / closing plate 20, and the inside of the big winning opening And a solenoid circuit 59 for driving the solenoid 21A for switching the path according to a command from the basic circuit 53.

  The gate switch 32a, the start port switch 14a, the V count switch 22, the count switch 23, the winning port switches 29a, 30a, 33a, 39a, and other switches may be referred to as sensors. That is, the name of the game medium detection means (game ball detection means in this example) that can detect a game ball is not limited. Each of the start port switch 14a, the V count switch 22, the count switch 23, and the winning port switches 29a, 30a, 33a, and 39a for performing the winning detection is also a winning detection means. Note that the winning detection means may be configured to collectively detect the respective game balls that have been won separately at the plurality of winning openings. In addition, even if a passing gate such as the gate switch 32a is used, if a prize ball is to be paid out, a game ball entering the passing gate becomes a win, and a switch ( For example, the gate switch 32a) becomes a winning detection means. Further, in this embodiment, since the game balls won in the V winning area are detected only by the V count switch 22, the number of game balls won in the big winning opening is the number detected by the V count switch 22 and the count switch 23. It becomes the sum with the detection number by. However, the game ball that has won the V winning area may be detected by the V count switch 22 and also by the count switch 23. In this case, the number of game balls won in the big winning opening corresponds to the number detected by the count switch 23.

  A switch common voltage (for example, + 12V) is supplied to each of the start port switch 14a, the count switch 23, and the winning port switches 29a, 30a, 33a, and 39a. A switch common monitoring circuit 71 for monitoring the voltage is mounted. When the switch common monitoring circuit 71 detects that the switch common voltage has dropped to a predetermined value, the switch common monitoring signal input to the basic circuit 53 is turned off.

  Further, according to the data given from the basic circuit 53, the jackpot information indicating the occurrence of the jackpot, the effective starting information indicating the number of starting winning balls used for starting the variable display of the symbols in the variable display device 9, the probability variation has occurred. An information output circuit 64 for outputting an information output signal such as probability variation information indicating the above to an external device such as a hall computer is mounted.

  A basic circuit 53 realized by a game control microcomputer includes a ROM 54 for storing a game control (game control) program and the like, and storage means used as a work memory (variable data storage means for storing variable data). A RAM 55, a CPU 56 that performs control operations according to a program, and an I / O port unit 57 are included. In this embodiment, the ROM 54 and the RAM 55 are built in the CPU 56. That is, the CPU 56 is a one-chip microcomputer. The one-chip microcomputer only needs to have at least the RAM 55 built in, and the ROM 54 and the I / O port unit 57 may be externally attached or built in. Since the CPU 56 executes control according to the program stored in the ROM 54, the CPU 56 executes (or performs processing) hereinafter, specifically, the CPU 56 executes control according to the program. is there. The same applies to CPUs mounted on substrates other than the main substrate 31. The game control means is realized by a basic circuit 53 realized by a game control microcomputer, but is mainly realized by a CPU 56 that executes control according to a program in the game control microcomputer.

  The RAM 55 is a backup RAM as a non-volatile storage means that is partly backed up by a backup power source created on the power supply substrate 910. In other words, even if the power supply to the gaming machine is stopped, a part of the contents of the RAM 55 is stored for a predetermined period (until the power supply of the backup power supply is disabled). In this example, at least data corresponding to the game state, that is, the control state of the game control means (special symbol process flag, etc.) is stored in the backup RAM area (area where power is backed up in the RAM 55: an example of storage means for game control backup). Saved in. The data corresponding to the control state of the game control means is data necessary for restoring the control state before the occurrence of a power failure or the like based on the data when the power is restored after a power failure or the like. In this example, the data indicating the number of unpaid winning balls is stored in a non-backup RAM area (an area in the RAM 55 where power is not backed up: an example of a game control storage means). Note that data indicating the number of unpaid prize balls may be stored in the backup RAM.

  In addition, a reset confirmation signal, a power-off confirmation signal, and a clear signal output from the payout control board 37 are input to the basic circuit 53 (specifically, an input port). In this example, the reset terminal of the CPU 56 is not used.

  The hitting ball launching device for hitting and launching the game ball includes a launch motor 94 controlled by a circuit on the payout control board 37, and the game ball is launched toward the game area 7 by the rotation of the launch motor 94. A drive signal for driving the firing motor 94 is transmitted to the firing motor 94 via the touch sensor substrate 91. The touch sensor detects that the player is touching the operation knob (hitting ball handle) 5 and a signal from the touch sensor is mounted on the touch sensor substrate 91 (the player touches the operation knob 5). Is transmitted to the payout control board 37 via a circuit including a detection circuit for detecting whether or not it is touched. The circuit on the payout control board 37 stops the driving of the firing motor 94 when the signal from the touch sensor circuit indicates an off state. Note that the operation knob 5 is provided with a touch ring that adjusts the resilience and is a part that the player contacts. In the gaming machine, the touch sensor substrate 91 is disposed between the touch ring and the payout control substrate 37, and is disposed in the vicinity of the touch ring. Specifically, the wiring length between the touch ring and the touch sensor substrate 91 is shorter than the wiring length between the touch sensor substrate 91 and the payout control substrate 37.

  In this embodiment, the effect control means mounted on the effect control board 80 performs display control of the normal symbol start memory display 41 and the decoration lamp 25 provided on the game board 6, and the frame side Display control of the top frame lamp 28a, the left frame lamp 28b, and the right frame lamp 28c. The effect control means mounted on the effect control board 80 also performs display control of the variable display device 9 that variably displays special symbols and the normal symbol display 10 that variably displays normal symbols.

  In addition, the CPU 56 used in this embodiment includes a non-maskable interrupt terminal (NMI terminal) used for generating a non-maskable interrupt (NMI) that cannot be set to interrupt prohibition by software, And an interrupt terminal (INT terminal) used for generating an external interrupt (external interrupt; maskable interrupt that can be disabled by software). However, this embodiment does not use non-maskable interrupts and external interrupts. Therefore, the NMI terminal and the INT terminal are pulled up to Vcc (+5 V) through resistors. Therefore, the input levels of the NMI terminal and the INT terminal are always at a high level, and there is a possibility that the input level of the NMI terminal and the INT terminal falls due to noise or the like, and an interrupt is generated, as compared with the terminal open state. Reduce.

  In this example, an error display lamp 44 that is controlled to be turned on / off by the CPU 56 is provided. The error display lamp 44 is installed, for example, at a position where it can be seen by a player or a game store clerk on the front side of the gaming machine. The error display lamp 44 is turned on when either the first connection confirmation signal or the second connection confirmation signal from the payout control board 37 is turned off, and the first connection confirmation signal and the second connection confirmation signal are displayed. When both signals are on, the light is turned off. That is, the error display lamp 44 is an example of a communication abnormality notifying means for notifying a game store clerk or the like that an abnormality relating to communication of signals between the game control means and the payout control means has been detected. Note that the communication abnormality notifying means is a display for displaying characters or figures for notifying abnormality even if it is another light emitter such as an LED or a sound output device for notifying abnormality by sound. It may be a device.

  FIG. 5 is a block diagram showing components related to payout, such as the payout control board 37 and the ball payout device 97. As shown in FIG. 5, the payout control board 37 is equipped with a payout control microcomputer (an example of an electric component control microcomputer) including a payout control CPU 371. In this embodiment, the payout control microcomputer is a one-chip microcomputer and has at least a built-in RAM. Further, the RAM is backed up in the same manner as the RAM 55 in the main board 31. The payout control CPU 371, the RAM, the ROM (not shown) storing the payout control program, the I / O port, etc. constitute payout control means. Accordingly, the payout control means is realized by a payout control CPU 371, a payout control microcomputer including a RAM, a ROM, and an I / O port, but is mainly realized by a payout control CPU 371 that executes control according to a program.

  Detection signals from the full tank switch 48 and the payout number count switch 301 are input to the I / O port 372 f of the payout control board 37 via the relay board 72. Detection signals from the ball break switch 187 and the payout motor position sensor 295 are input to the I / O port 372e of the payout control board 37 via the relay board 72. The payout motor position sensor 295 is a sensor composed of a light emitting element (LED) and a light receiving element for detecting the rotational position of the payout motor 289, and is used for detecting that the game ball is clogged, that is, so-called ball biting. . The payout control CPU 371 of the payout control board 37 performs a ball payout process when the detection signal from the ball shortage switch 187 indicates a ball full state or when the detection signal from the full tank switch 48 indicates a full tank state. Stop. Furthermore, when the detection signal from the full tank switch 48 indicates a full tank state, the ball launching from the ball striking device is stopped.

  When a prize ball to be paid out is generated by winning, a prize ball REQ signal (prize ball request signal) for making a prize ball payout request and a prize ball to be paid out as a payout control signal from the output circuit 67 of the main board 31. A prize ball number signal indicating the number is output (turned on). The award ball number signal is composed of 4-bit data (binary 4-digit data) and is output by four signal lines. Note that the ON state of the signal, that is, the output state is a state where the signal is significant, and turning ON means that the signal receiving side is instructed to start some processing based on the signal. To do. For example, turning on the prize ball REQ signal means instructing the payout control means to recognize the payout number indicated by the prize ball number signal. The prize ball REQ signal and the prize ball number signal are input to the I / O port 372e via the input circuit 373A. When the winning ball REQ signal and the winning ball number signal are input via the I / O port 372e, the payout control CPU 371 drives the ball paying device 97 to pay out the number of game balls indicated by the winning ball number signal. Control. The output circuit 67 of the main board 31 also outputs two power supply confirmation signals (a first connection confirmation signal and a second connection confirmation signal) indicating that the main board 31 is connected.

  The payout control means outputs a power-off confirmation signal to the main board 31 in response to the input of the power-off signal from the power board 910. Also, the payout control means starts outputting the clear signal to the main board 31 in response to the input of the clear switch signal from the clear switch 921 mounted on the power supply board 910, and turns on the clear signal. . The power-off confirmation signal and the clear signal are output to the main board 31 via the output port 372b of the payout control board 37 and the output circuit 373B. Then, in the main board 31, the data is input to the CPU 56 via the input circuit 68 and the I / O port 57.

  The payout control CPU 371 receives a prize ball information signal indicating the number of prize balls to be paid out and a ball lending number signal indicating the number of balls to be rented via the output port 372b as a terminal board (the frame external terminal board and the board external terminal board). Output) 160. A driver circuit is provided outside the output port 372b, but is not shown in FIG. Further, door opening information switches 161A and 161B are connected to the terminal board 160 (frame external terminal board).

  Further, the payout control CPU 371 outputs an error signal to the error display LED 374 using a 7-segment LED via the output port 372c. Further, a signal for instructing lighting / extinguishing is output to the winning ball LED 51 and the ball running out LED 52 via the output port 372b. A detection signal from an error release switch 375 for releasing the error state is input to the input port 372f of the payout control board 37. The error cancel switch 375 is used to cancel the error state by software reset.

  Further, a drive signal from the payout control board 37 to the payout motor 289 is transmitted to the payout motor 289 in the payout mechanism portion of the ball payout device 97 via the output port 372a and the relay board 72. A driver circuit (motor drive circuit) is installed outside the output port 372a, but is not shown in FIG. A drive signal from the payout control board 37 to the firing motor 94 is transmitted to the firing motor 94 via the output port 372 a and the touch sensor board 91.

  A card unit control microcomputer is mounted on the card unit 50 installed adjacent to the gaming machine. In addition, the card unit 50 is provided with a usable display lamp 151, a connecting table direction indicator 153, a card insertion display lamp 154, and a card insertion slot 155. The interface board (relay board) 66 is connected to a frequency display LED 60, a ball lending LED 61, a ball lending switch 62 and a return switch 63 provided in the vicinity of the hitting ball supply tray 3.

  A card lending switch signal indicating that the ball lending switch 62 has been operated and a return switch signal indicating that the return switch 63 has been operated are given to the card unit 50 from the interface board 66 in accordance with the player's operation. . Further, a card balance display signal indicating a prepaid card balance and a ball lending display signal are given from the card unit 50 to the interface board 66. Between the card unit 50 and the payout control board 37, a connection signal (VL signal), a unit operation signal (BRDY signal), a ball lending request signal (BRQ signal), a ball lending completion signal (EXS signal), and a pachinko machine operation signal ( PRDY signal) is transmitted / received via the input port 372f and the output port 372d. An interface board 66 is interposed between the card unit 50 and the payout control board 37. Therefore, a signal such as a connection signal (VL signal) is transmitted and received between the card unit 50 and the payout control board 37 via the interface board 66 as shown in FIG.

  When the power of the pachinko gaming machine 1 is turned on, the payout control CPU 371 of the payout control board 37 outputs a PRDY signal to the card unit 50. The card unit control microcomputer outputs a VL signal when the power is turned on. The payout control CPU 371 determines the connected / unconnected state of the card unit 50 based on the input state of the VL signal. When a card is received in the card unit 50, the ball lending switch is operated and a ball lending switch signal is input, the card unit control microcomputer outputs a BRDY signal to the payout control board 37. When a predetermined delay time elapses from this point, the card unit control microcomputer outputs a BRQ signal to the payout control board 37.

  Then, the payout control CPU 371 of the payout control board 37 raises the EXS signal to the card unit 50 and, when detecting the fall of the BRQ signal from the card unit 50, drives the payout motor 289 to draw a predetermined number of rental balls. Pay to the player. When the payout is completed, the payout control CPU 371 causes the EXS signal to the card unit 50 to fall. Thereafter, on the condition that the BRDY signal from the card unit 50 is not in the ON state, a prize ball payout control is executed when a payout control signal is received from the game control means. The power supply voltage AC24V used in the card unit 50 is supplied from the payout control board 37.

  Power supply from the power supply board 910 to the card unit 50 is performed via the payout control board 37 and the interface board 66. In this example, a fuse for protecting the card unit 50 is provided in a 24 V AC power supply line for the card unit 50 arranged in the interface board 66, and a voltage higher than a predetermined voltage is supplied to the card unit 50. It is prevented.

  The payout control CPU 371 used in this embodiment generates a non-maskable interrupt terminal (NMI terminal) used for generating a non-maskable interrupt (NMI) and a maskable interrupt. And an interrupt terminal (INT terminal) used for the purpose. However, this embodiment does not use non-maskable interrupts and external interrupts. Therefore, the NMI terminal and the INT terminal are pulled up to Vcc (+5 V) through resistors.

  In this embodiment, the case where the card unit 50 is installed adjacent to the gaming machine as a separate body from the gaming machine is taken as an example, but the card unit 50 may be integrated with the gaming machine. . Further, the present invention can be applied even when a game ball corresponding to the amount of money is lent out in accordance with coin insertion.

  FIG. 6 is a block diagram illustrating a circuit configuration example of the effect control board 80, the lamp driver board 35, and the sound control board 70. The lamp driver board 35 and the sound control board 70 are not equipped with a microcomputer. In the effect control board 80, the effect control CPU 101 in the effect control microcomputer (an example of the electric component control microcomputer) operates in accordance with a program stored in a ROM (not shown), and a strobe signal from the main board 31. In response to (symbol control INT signal), a symbol control command is received via the input driver 102 and the input port 103. Further, the effect control CPU 101 causes the VDP (video display processor) 109 to perform display control of the variable display device 9 using the LCD, based on the symbol control command. The VDP 109 is sometimes called a GCL (graphic controller LSI).

  Further, the production control CPU 101 outputs sound number data to the sound control board 70 via the output port 104 and the output driver 110. A bus (including an address bus, a data bus, and a control signal line such as a write / read signal) that is input / output to / from the effect control CPU 101 is extended to the lamp driver board 35 via the bus driver 105.

  In the lamp driver board 35, a bus that is input to and output from the effect control CPU 101 is connected to the output port 352 and the expansion port 353 via the bus receiver 351. A signal for driving each lamp output from the output port 352 is amplified by a lamp driver 354 and supplied to each lamp. A signal for driving each LED output from the output port 352 is amplified by the LED drive circuit 355 and supplied to each LED.

  In this embodiment, lamps / LEDs and effect driving means provided in the gaming machine are controlled by effect control means including effect CPU 101 mounted on effect control board 80. Further, data for controlling the variable display device 9, the normal symbol display 10, the lamp / LED, and the like are stored in the ROM. The effect CPU 101 controls the variable display device 9, the normal symbol display 10, the lamp / LED, and the like based on the data stored in the ROM. Then, the lamp / LED and the effect driving means are driven via the output port 352 and each drive circuit mounted on the lamp driver board 35. Therefore, when changing the model, it is necessary to make a design change such as changing the number of ports for the lamp driver board 35, but for the production control board 80, it is only necessary to replace the ROM storing the program. There is no need to make design changes.

  In the voice control board 70, the sound number data from the effect control board 80 is input to the voice synthesis IC 703 by a digital signal processor, for example, via the input driver 702. The voice synthesis IC 703 reads data corresponding to the sound number data from the voice data ROM 704 mounted on the voice data board 70 </ b> A, generates voice and sound effects corresponding to the read data, and outputs them to the amplifier circuit 705. The amplification circuit 705 outputs an audio signal obtained by amplifying the output level of the speech synthesis IC 703 to a level corresponding to the volume set by the volume 706 to the speaker 27.

  The data corresponding to the sound number data stored in the sound data ROM 704 is a collection of data indicating the sound effect or sound output mode in a time series in a predetermined period (for example, a special symbol fluctuation period). When the voice number IC 703 receives the sound number data, the voice synthesis IC 703 performs sound output control according to the corresponding data in the voice data ROM 704. The sound output control according to the corresponding data is continued until the next sound number data is input. When the next sound number data is input, the speech synthesis IC 703 performs sound output control according to the data in the sound data ROM 704 corresponding to the newly input sound number data.

  In this embodiment, the sound and sound output from the speaker 27 are controlled by the effect control means including the effect control CPU 101, but the effect control means outputs the sound number data to the sound control board 70. . In the voice control board 70, the voice data ROM 704 stores a large amount of data for realizing voice and sound effects that can appear as the game progresses, and these data are associated with the sound number data. . Therefore, the production control means can realize sound output control only by outputting the sound number data. Note that the sound number data is, for example, 1-byte data and is transferred to the sound control board 70 via a serial signal line or a parallel signal line.

  Next, the configuration of the power supply substrate 910 will be described with reference to the block diagram of FIG. The power supply board 910 is provided with a power switch 914 for executing or shutting off power supply to each electrical component control board and mechanism component in the gaming machine. Note that the power switch 914 may be provided outside the power supply board 910 in the gaming machine. When the power switch 914 is in a closed state (on state), an AC power supply (AC 24 V) is applied to the input side (primary side) of the transformer 911. The transformer 911 is for electrically insulating the AC power supply (AC24V) and the inside of the power supply board 910, and its output voltage is also AC24V. A varistor 918 as an overvoltage protection circuit is installed on the input side of the transformer 911.

  The power supply board 910 is installed independently of the electrical component control board (the main board 31, the payout control board 37, and the effect control board 80), and generates a voltage used by each board and mechanism component in the gaming machine. In this example, AC24V, VSL (DC + 30V), VLP (DC + 24V), VDD (DC + 12V) and VCC (DC + 5V) are generated. Further, a capacitor 916 serving as a storage holding means for holding the stored contents in the backup power supply (VBB), that is, the backup RAM, is charged from DC + 5V (VCC), that is, a power supply line for driving an IC or the like on each substrate. Further, a backflow prevention diode 917 is inserted between the +5 V line and the backup +5 V (VBB) line. Note that VSL is generated by rectifying and boosting AC 24 V with a rectifying element in the rectifying and smoothing circuit 915. VSL is a solenoid driving power source. VLP is a lamp lighting voltage, and is generated by rectifying AC24V with a rectifier element in the rectifier circuit 912.

  The DC-DC converter 913 serving as a power supply voltage generation unit has one or a plurality of regulator ICs (two regulator ICs 924A and 924B are shown in FIG. 7), and generates VDD and VCC based on VSL. Relatively large capacitors 923A and 923B are connected to the input sides of the regulator ICs (switching regulators) 924A and 924B. Accordingly, when the power supply to the gaming machine from the outside is stopped, the DC voltages such as VSL, VDD, VCC, etc., decrease relatively slowly.

  As shown in FIG. 7, AC24V output from the transformer 911 is supplied to the connector 922B as it is. The VLP is supplied to the connector 922C. VCC, VDD and VSL are supplied to connectors 922A, 922B and 922C.

  The cable connected to the connector 922A is connected to the main board 31. The cable connected to the connector 922B is connected to the payout control board 37. Therefore, VBB is also supplied to the connectors 922A and 922B. The cable connected to the connector 922C is connected to the lamp driver board 35. Each voltage is supplied to the effect control board 80 via the lamp driver board 35.

  In addition, a clear switch 921 having a push button structure is mounted on the power supply board 910. When the clear switch 921 is pressed, a low level (on state) clear switch signal is output and transmitted to the payout control board 37 via the connector 922B. If the clear switch 921 is not pressed, a high level (off state) signal is output. The clear switch 921 may have a configuration other than the push button structure. Further, the clear switch 921 may be provided in a board other than the power supply board 910 such as the payout control board 37 or other places in the gaming machine.

  Further, the power supply board 910 generates a reset signal for a microcomputer such as a payout control microcomputer mounted on a sub-board such as the payout control board 37, and outputs a power cut-off signal. An output driver circuit 925 that amplifies the reset signal from the power supply monitoring circuit 920 and outputs it to the connectors 922B and 922C, and amplifies the power-off signal and outputs it to the connector 922B is mounted. The reset signal for the effect control microcomputer is transmitted to the effect control board 80 via the lamp driver board 35.

  The power supply monitoring circuit 920 is a circuit that realizes power supply monitoring means for outputting a power-off signal and reset signal generation means for generating a reset signal. As the power supply monitoring circuit 920, a commercially available power failure monitoring reset module IC should be used. Can do. The power supply monitoring circuit 920 outputs a power-off signal when a period during which a predetermined voltage (for example, + 24V) used in the gaming machine becomes equal to or lower than a predetermined value (for example, + 17V) continues for a predetermined time (for example, 56 ms). . Specifically, the power-off signal is turned on (low level). Further, the power supply monitoring circuit 920 enters a state in which the reset signal can be set to a low level when, for example, VCC becomes +4.5 V or less.

  When the power supply to the gaming machine is stopped, the power supply monitoring circuit 920 sets the reset signal to a low level when a predetermined period has elapsed since the power-off signal was output (set to a low level). . This predetermined period is sufficient time for the microcomputer mounted on the main board 31 and the payout control board 37 to execute a power-off process described later. In addition, when the power supply to the gaming machine is started and Vcc exceeds +4.5 V, for example, the reset signal is set to high level. ) The reset signal is set to high level on condition that a predetermined period has elapsed. Therefore, when the microcomputer mounted on each electrical component control board (including the main board 31) starts the control operation according to the program in response to the reset signal becoming high level, the power-off signal is always turned off. It is in a state.

  The reset signal from the power supply monitoring circuit 920 is input to the reset terminal of the payout control CPU 371 mounted on the payout control board 37 (see FIG. 5). Therefore, the payout control CPU 371 can check the timing of setting the payout control operation execution state and the timing of the payout control operation stop state by monitoring the input state of the reset terminal.

  The reset confirmation signal output from the payout control board 37 in response to the input of the reset signal from the power supply monitoring circuit 920 is input to the CPU 56 via the input port 57 in the main board 31. Therefore, the CPU 56 can confirm the timing for setting the game control operation to be executed and the timing for setting the game control operation to be stopped by monitoring the input signal of the input port 57.

  The power-off signal from the power monitoring circuit 920 is input to the payout control CPU 371 via the input port 372g in the payout control board 37 (see FIG. 5). Therefore, the payout control CPU 371 can confirm the occurrence of the stop of the power supply to the gaming machine by monitoring the input signal of the input port 372g.

  Note that the power-off confirmation signal output from the payout control board 37 in response to the input of the power-off signal from the power supply monitoring circuit 920 is input to the CPU 56 via the input port 57 in the main board 31. Therefore, the CPU 56 can confirm the occurrence of the stop of the power supply to the gaming machine by monitoring the input signal of the input port 57.

  In this embodiment, the power supply monitoring means monitors the output of the power supply of a predetermined potential, and the voltage from the outside of the gaming machine (this implementation) is used as a detection condition related to the stop of the supply of power supplied to the gaming machine from the outside. However, the detection condition is not limited to this, and other conditions can be used as long as it is possible to detect that power from the outside has been cut off. These conditions may be used. For example, the AC wave itself may be monitored and the AC wave may be detected as a detection condition, or the signal obtained by digitizing the AC wave may be monitored and the AC signal may be stopped when the digital signal becomes flat. May be used as a detection condition.

  8 and 9 are explanatory diagrams showing examples of output port assignment in the game control means. 8 and 9, “logic” is “1” and “state” is “on” means that the signal is on when the signal is at a high level, and “logic” is “0”. The “state” of “on” means that the signal is on when the signal is at a low level. As shown in FIG. 8, the output port 0 is an output port for a payout control signal transmitted to the payout control board 37. Further, 8-bit data of the symbol control command transmitted to the effect control board 80 is output from the output port 1.

  Further, from the output port 2, a solenoid (large winning opening door solenoid) 21 for opening and closing the opening / closing plate 2 of the large winning opening, a solenoid (large winning opening guide plate solenoid) 21A for switching the path in the large winning opening and a variable A drive signal for a solenoid (normal electric accessory solenoid) 16 for opening and closing the winning ball apparatus 15 is output. Further, a symbol control INT signal (strobe signal) for the symbol control command transmitted to the effect control board 80 is also output. The symbol control INT signal is a signal for instructing the effect control means to capture 8-bit data of the symbol control command.

  Then, various information output signals from the output ports 3 and 4 to the information terminal board 34 and the terminal board 160 through the information output circuit 64, that is, output data of information related to control are output.

  FIG. 10 is an explanatory diagram showing an example of bit assignment of input ports in the game control means. As shown in FIG. 10, bits 0 to 7 of the input port 0 are detected by the V count switch 22, the count switch 23, the gate switch 32a, the winning port switches 33a, 39a, 29a and 30a, and the start port switch 14a, respectively. A signal is input. In addition, the power-off confirmation signal, the clear signal, the reset confirmation signal, and the third connection confirmation signal from the payout control board 37 are input to bits 0 to 2 and 4 of the input port 1, respectively. Is supplied with a switch common monitoring signal. The detection signal from each switch is logically inverted in the input driver circuit 58.

  Next, the operation of the gaming machine will be described. 11 and 12 are flowcharts showing main processing executed by the game control means on the main board 31. When the gaming machine is turned on and the input level of the reset terminal to which a reset signal is input becomes high, the CPU 56 performs a security check process that is a process for confirming whether the contents of the program are valid. After execution, the main processing after step S1 is started. In the main process, the CPU 56 first performs necessary initial settings.

  In the initial setting process, the CPU 56 first sets the interrupt prohibition (step S1). Next, the interrupt mode is set to interrupt mode 2 (step S2), and a stack pointer designation address is set to the stack pointer (step S3). Then, the built-in device register is initialized (step S4).

  Next, the CPU 56 initializes the CTC (counter / timer) and PIO (parallel input / output port), which are built-in devices (built-in peripheral circuits) (step S5), and then sets the RAM 55 to an accessible state (step S5). S6).

  The CPU 56 used in this embodiment also incorporates an I / O port (PIO) and a timer / counter circuit (CTC). The CTC also includes two external clock / timer trigger inputs CLK / TRG2, 3 and two timer outputs ZC / TO0,1.

  In the CPU 56 used in this embodiment, the following three types of modes are prepared as maskable interrupt modes. When a maskable interrupt occurs, the CPU 56 automatically sets the interrupt disabled state and saves the contents of the program counter in the stack.

  Interrupt mode 0: The built-in device that issued the interrupt request sends an RST instruction (1 byte) or a CALL instruction (3 bytes) onto the internal data bus of the CPU. Therefore, the CPU 56 executes the instruction at the address corresponding to the RST instruction or the address specified by the CALL instruction. At reset, the CPU 56 automatically enters interrupt mode 0. Therefore, when setting to interrupt mode 1 or interrupt mode 2, it is necessary to perform processing for setting to interrupt mode 1 or interrupt mode 2 in the initial setting process.

  Interrupt mode 1: In this mode, when an interrupt is accepted, the mode always jumps to address 0038 (h).

  Interrupt mode 2: A mode in which the address synthesized from the value (1 byte) of the specific register (I register) of the CPU 56 and the interrupt vector (1 byte: least significant bit 0) output from the built-in device indicates the interrupt address It is. That is, the interrupt address is an address indicated by 2 bytes in which the upper address is the value of the specific register and the lower address is the interrupt vector. Therefore, an interrupt process can be set at an arbitrary address (although it is skipped). Each built-in device has a function of sending an interrupt vector when making an interrupt request.

  Therefore, when the interrupt mode 2 is set, it is possible to easily process an interrupt request from each built-in device, and it is possible to install an interrupt process at an arbitrary position in the program. . Further, unlike the interrupt mode 1, it is easy to prepare each interrupt process for each interrupt generation factor. As described above, in this embodiment, the CPU 56 is set to the interrupt mode 2 in step S2 of the initial setting process.

  Next, the CPU 56 confirms the state of the clear signal input via the input port 1 only once (step S7). When the on-state is detected in the confirmation, the CPU 56 executes a normal initialization process (steps S10 to S15). A predetermined period after the clear switch signal from the clear switch 921 is in the on state (when the clear switch 921 is pressed) and after the switch from the on state to the off state (after the press of the clear switch 921 is finished) The low level clear signal is output from the payout control board 37. Note that in the input port 1, the clear switch signal is in the high level.

  For example, the game store clerk can turn on the clear switch signal and the clear signal by starting power supply to the gaming machine (for example, turning on the power switch 914) while the clear switch 921 is turned on. Can execute initialization processing. That is, RAM clear or the like can be performed.

  If the clear signal is not on, check whether data protection processing of the backup RAM area (for example, power supply stop processing such as addition of parity data) has been performed when power supply to the gaming machine is stopped (Step S8). In this embodiment, when power supply is stopped, a process for protecting data in the backup RAM area is performed. If it is confirmed that such protection processing has been performed, the CPU 56 determines that there is a backup. When it is confirmed that such protection processing is not performed, the CPU 56 executes initialization processing.

  Whether or not the protection process has been performed depends on the value of the backup monitoring timer stored in the backup RAM area in the power supply stop process described later according to the execution of the data protection process in the backup RAM area (for example, It is confirmed by whether or not 2). Note that such a confirmation method is merely an example. For example, a flag indicating that the data protection process has been executed is set in the backup flag area in the power supply stop process, and the flag is set in step S8. If it is confirmed that there is a backup, it may be determined that there is backup.

  If it is determined that there is a backup, the CPU 56 performs a data check of the backup RAM area (parity check in this example) (step S9). In this embodiment, clear data (00) is set in the checksum data area, and the checksum calculation start address is set in the pointer. Also, the number of checksum calculations corresponding to the number of data to be checksum is set. Then, the exclusive OR of the contents of the checksum data area and the contents of the RAM area pointed to by the pointer is calculated. The calculation result is stored in the checksum data area, the pointer value is incremented by 1, and the checksum calculation count value is decremented by 1. The above processing is repeated until the value of the checksum calculation count becomes zero. When the value of the checksum calculation count becomes 0, the CPU 56 inverts the value of each bit of the contents of the checksum data area and uses the inverted data as the checksum.

  In the power supply stop process, a checksum is calculated by the same process as described above, and the checksum is stored in the backup RAM area. In step S9, the calculated checksum is compared with the stored checksum. When the power supply is stopped after an unexpected power outage or the like, the data in the backup RAM area should be saved, so the check result (comparison result) is normal (matched). That the check result is not normal means that the data in the backup RAM area is different from the data when the power supply is stopped. In such a case, since the internal state cannot be returned to the state when the power supply is stopped, the initialization process (the process of steps S10 to S15) executed when the power is turned on, not when the power supply is stopped is stopped. Execute.

  If the check result is normal, the CPU 56 performs a game state restoration process for returning the internal state of the game control means and the control state of the electric component control means such as the display control means to the state when the power supply is stopped. Specifically, the start address of the backup setting table stored in the ROM 54 is set as a pointer (step S91), and the contents of the backup setting table are sequentially set in the work area (area in the RAM 55) (step S92). ). The work area is backed up by a backup power source. In the backup setting table, initialization data for an area that may be initialized in the work area is set. As a result of the processing in steps S91 and S92, the saved contents of the work area that should not be initialized remain. The portion that should not be initialized is, for example, a portion in which data (such as a special symbol process flag) indicating a gaming state before stopping power supply is set.

  Further, the CPU 56 sets the start address of the backup command transmission table stored in the ROM 54 as a pointer (step S93), and power is supplied to the sub-boards (the payout control board 37 and the effect control board 80) according to the contents. Control is performed such that a control command (recovery command) indicating the recovery is transmitted (step S94). Then, the process proceeds to step S15.

  In the initialization process, the CPU 56 first performs a RAM clear process (step S10). The entire area of the RAM 55 may not be initialized, and predetermined data (for example, count value data of a counter for generating a big hit determination random number) may be left as it is. For example, if the count value data of the counter for generating the big hit determination random number is left as it is, the big hit determination random number is generated even if the initialization process is executed by an unauthorized means. Therefore, it is difficult to aim at a timing at which the count value of the counter for matching the jackpot determination value. Further, the start address of the initialization setting table stored in the ROM 54 is set as a pointer (step S11), and the contents of the initialization setting table are sequentially set in the work area (step S12). Through the processing of steps S11 and S12, for example, a normal symbol determination random number counter, a normal symbol determination buffer, a special symbol left middle right symbol buffer, a total prize ball number storage buffer, a special symbol process flag, an award ball flag, a ball break An initial value is set to a flag for selectively performing processing according to the control state, such as a flag or a payout stop flag.

  Further, the CPU 56 sets the head address of the initialization command transmission table stored in the ROM 54 as a pointer (step S13), and transmits an initialization command for initializing the sub board according to the contents to the sub board. Processing is executed (step S14). Examples of the initialization command include a command indicating an initial symbol displayed on the variable display device 9.

  In step S15, the CPU 56 sets a CTC register built in the CPU 56 so that a timer interrupt is periodically generated every predetermined time (for example, 4 ms) (step S15). That is, a value corresponding to, for example, 4 ms is set as an initial value in a predetermined register (time constant register). In this embodiment, it is assumed that a timer interrupt is periodically taken every 4 ms.

  When the execution of the initialization process (steps S10 to S15) is completed, the CPU 56 enters a control state in which game control can be executed, and repeatedly monitors the state of the third connection confirmation signal from the payout control board 37 (step S96). Then, when confirming that the third connection confirmation signal is turned on, the CPU 56 turns on the first connection confirmation signal and the second connection confirmation signal (step S97). When step S96 and step S97 are executed, the interrupt is prohibited, and control is performed so that a timer interrupt process, which will be described later, is not executed during the processes of step S96 and step S97. And CPU56 will be in an interruption permission state, after step S97 is complete | finished (step S98). Execution of game control is started by setting the interrupt permitted state in step S98. In other words, the control state allows the execution of the periodically executed game control process.

  When the first connection confirmation signal and the second connection confirmation signal are turned on, the CPU 56 allows execution of a timer interrupt process described later as an interrupt permission state. That is, execution of game control is started. If the third connection confirmation signal does not turn on even after a predetermined period has elapsed since the start of the monitoring process in step S96, for example, an error state is set, and error notification is performed by, for example, a lamp or a display. You can do it.

  Next, the CPU 56 repeatedly executes the display random number update process (step S17) and the initial value random number update process (step S18). The CPU 56 disables the interrupt when the display random number update process and the initial value random number update process are executed (step S16), and interrupts when the display random number update process and the initial value random number update process are finished. The permitted state is set (step S19). The display random number is a random number for determining a symbol displayed on the variable display device 9, and the display random number update process is a process for updating the count value of the counter for generating the display random number. It is. The initial value random number update process is a process for updating the count value of the counter for generating the initial value random number. The initial value random number is a random number for determining an initial value of a count value such as a counter for generating a random number for determining whether or not to make a big hit (a big hit determination random number generation counter). A game control process described later (a process in which a game control microcomputer controls itself a game device such as a variable display device 9, a variable winning ball device 15, a ball payout device 97 provided in the game machine, or In a process of transmitting a command signal for causing another microcomputer to control, also referred to as a gaming machine control process), when the count value of the jackpot determination random number generation counter makes one round, an initial value is set in the counter.

  Note that when the display random number update process and the initial value random number update process are executed, the interrupt disabled state is set even when the display random number update process and the initial value random number update process are performed by the timer interrupt process described later. This is to avoid conflict with the processing in the timer interrupt processing. That is, if a timer interrupt is generated during the processing of steps S17 and S18 and the count value of the counter for generating the display random number and the initial value random number is updated during the timer interrupt processing, The continuity of values may be impaired. However, such an inconvenience does not occur if the interrupt disabled state is set during the processes of steps S17 and S18.

  FIG. 13 is a timing diagram showing how the microcomputer operates when power supply to the gaming machine is started and when power supply is stopped. When power supply to the gaming machine is started and the voltage of the DC + 24V power supply exceeds a predetermined value, the power-off signal is turned off. When the value of VCC exceeds a predetermined value, the reset signal becomes high level. Note that, as described above, the power monitoring circuit 920 sets the reset signal to a high level off state after turning off the power off signal. The reset signal is input to the payout control board 37 and input to the effect control board 80 via the lamp driver board 35. Then, it is input to the reset terminal of the payout control CPU 371 mounted on the payout control board 37 and the effect control CPU 101 mounted on the effect control board 80. The payout control CPU 371 and the effect control CPU 101 become operable when the reset signal becomes high level. When the payout control CPU 371 enters an operable state, it first performs initialization processing, then sets the reset confirmation signal to a high level off state, starts payout control signal acceptance processing, and turns on the third connection confirmation signal. After that, a monitoring process for monitoring the input states of the first connection confirmation signal and the second connection confirmation signal from the main board 31 is performed. The effect control CPU 101 first executes an initialization process, and then starts the effect control process.

  A reset confirmation signal from the payout control CPU 371 is input to the main board 31. The main board 31 becomes operable in response to the reset confirmation signal being turned off at a high level. Therefore, the time when the CPU 56 becomes operable is later than the time when the CPU of the sub-board becomes operable. When the CPU 56 becomes operable, the CPU 56 executes security check processing based on the security check program. When the security check process is completed, an initialization process is executed, and then a monitoring process for monitoring the input state of the third connection confirmation signal from the payout control board 37 is performed. Then, when confirming that the third connection confirmation signal is turned on, the CPU 56 turns on the first connection confirmation signal and the second connection confirmation signal, and then starts the game control process.

  On the other hand, when the payout control CPU 371 confirms that the first connection confirmation signal and the second connection confirmation signal are turned on in the monitoring process, the payout control CPU 371 starts the payout control process. Accordingly, almost simultaneously with the start of the game control process by the CPU 56, the payout control CPU 371 starts the payout control process.

  As described above, the CPU 56 performs a process of transmitting a command (command signal) to the CPU of the sub board in the initialization process. Due to the time difference between when the reset signal is turned off and when the reset confirmation signal is turned off, the time when the CPU 56 starts the initialization process is later than the time when the CPU of the sub-board completes the initialization process. Yes. That is, the payout control CPU 371 turns off the reset confirmation signal after completing the initialization process, and when the CPU 56 starts the initialization process, the CPU of the sub board has completed the initialization process.

  In this embodiment, the security check process based on the security check program is executed before the CPU 56 starts the initialization process. Therefore, it is more certain that the time point when the CPU 56 starts the initialization process is later than the time point when all the CPUs of the sub-boards complete the initialization process. Therefore, when the power supply of the gaming machine is started, the CPU of the sub board can receive the control command from the CPU 56 more reliably.

  When the power supply to the gaming machine is stopped, the voltage of the DC + 24V power supply also gradually decreases. However, when the voltage of the DC + 24V power supply falls below a predetermined value, the power supply monitoring circuit 920 outputs a power-off signal (set to a low level). ). The power-off signal is input to the payout control board 37. The payout control means mounted on the payout control board 37 outputs a power-off confirmation signal in response to the input of the power-off signal, and thereafter a payout control signal (award ball) for designating a prize ball until a predetermined period elapses. After monitoring the input state of the REQ signal and prize ball number signal, a power supply stop process (also referred to as a power-off control process) is executed.

  A power-off confirmation signal from the payout control board 37 is input to the main board 31. The game control means mounted on the main board 31 executes a power supply stop process (also referred to as a power-off control process) in response to the power-off confirmation signal being output.

  The power supply monitoring circuit 920 sets the reset signal to a low level when VCC falls below a predetermined value. The payout control means mounted on the payout control board 37 sets the reset confirmation signal to low level in response to the reset signal becoming low level, and then the system is reset. That is, the payout control CPU 371 is not operated. Note that the power supply monitoring circuit 920 sets the reset signal to a low level when a predetermined time elapses from the time when the power supply cutoff signal is output when the power supply voltage decreases.

  Further, the game control means mounted on the main board 31 is system-reset in response to the reset confirmation signal becoming low level. That is, the CPU 56 enters a state where it does not operate.

  Next, the game control process will be described. FIG. 14 is a flowchart showing the timer interrupt process. When a timer interrupt occurs during execution of the main process, specifically, during the execution of the loop process of steps S16 to S19, the CPU 56 performs a timer interrupt process that is activated in response to the occurrence of the timer interrupt. A game control process is executed. In the timer interrupt process, the CPU 56 first executes a power-off process (power-off detection process) for detecting whether or not a power-off confirmation signal is output (whether the power-off confirmation signal is turned on) (step S20).

  Next, the CPU 56 inputs detection signals of switches such as the gate switch 32a, the start port switch 14a, the count switch 23, and the winning port switches 29a, 30a, 33a, and 39a via the switch circuit 58, and determines their state. Performed (switch processing: step S21). Specifically, if the state of the input port for inputting the detection signal of each switch is ON, the value of the switch timer provided corresponding to each switch is incremented by one.

  In this embodiment, the continuation time (specifically, the number of confirmations every 4 ms) in which the ON state of the detection signal of each switch related to winning detection or gate passing is confirmed in the switch processing (step S21) is set. If it continues for a predetermined period of time, it is determined that the switch has been turned on, and processing corresponding to the switch on is started.

  Moreover, the short circuit alerting | reporting process which performs a predetermined alerting | reporting process based on a switch common monitoring signal is performed (step S22).

  Next, a process of updating the count value of each counter for generating each determination random number such as a big hit determination random number used for game control is performed (step S23). The CPU 56 further performs a process of updating the count value of the counter for generating the display random number and the initial value random number (steps S24 and S25).

  Further, the CPU 56 performs special symbol process processing (step S26). In the special symbol process control, corresponding processing is selected and executed according to a special symbol process flag for controlling the pachinko gaming machine 1 in a predetermined order according to the gaming state. The value of the special symbol process flag is updated during each process according to the gaming state. Further, normal symbol process processing is performed (step S27). In the normal symbol process, the corresponding process is selected and executed according to the normal symbol process flag for controlling the display state of the normal symbol display 10 in a predetermined order. The value of the normal symbol process flag is updated during each process according to the gaming state.

  Next, the CPU 56 performs a process of setting a symbol control command related to the special symbol in a predetermined area of the RAM 55 and sending the symbol control command (special symbol command control process: step S28). Further, the symbol control command related to the normal symbol is set in a predetermined area of the RAM 55, and the symbol control command is transmitted (normal symbol command control processing: step S29).

  Further, the CPU 56 performs information output processing for outputting data such as jackpot information, starting information, probability variation information supplied to the hall management computer, for example (step S30).

  Further, the CPU 56 executes prize ball processing for setting the number of prize balls based on the detection signals from the prize opening switches 29a, 30a, 33a, 39a, etc. (step S31). Specifically, a payout control signal such as a prize ball number signal indicating the number of prize balls is output to the payout control board 37 in response to winning detection based on the fact that the prize opening switches 29a, 30a, 33a, 39a, etc. are turned on. . The payout control CPU 371 mounted on the payout control board 37 drives the ball payout device 97 in accordance with a payout control signal such as a prize ball number signal indicating the number of prize balls.

  And CPU56 performs the memory | storage process which checks the increase / decrease in the number-of-start winning memory | storage number (step S32). In addition, a test terminal process, which is a process for outputting a test signal for enabling the control state of the gaming machine to be confirmed outside the gaming machine, is executed (step S33). In this embodiment, a RAM area (output port buffer) corresponding to the output state of the output port is provided, but the CPU 56 relates to the solenoid in the RAM area of the output port 3 (see FIG. 8). Is output to the output port (step S34: solenoid output processing). Thereafter, the interrupt permission state is set (step S35), and the process is terminated.

  With the above control, in this embodiment, the game control process is started periodically (for example, every 4 ms). In this embodiment, the game control process is executed by the timer interrupt process. However, in the timer interrupt process, for example, only a flag indicating that an interrupt has occurred is set, and the game control process is performed by the main process. May be executed. Further, the processing of steps S21 to S34 (except for steps S30 and S33) corresponds to a game control process for controlling the progress of the game.

  15 and 16 are flowcharts illustrating an example of the power-off process in step S20. In the power-off process, the CPU 56 first checks whether or not a power-off confirmation signal is output (whether it is in an on state) (step S450). If not on, the value of the backup monitoring timer formed in the RAM 55 is cleared to 0 (step S451). If it is on, the value of the backup monitoring timer formed in the RAM 55 is incremented by 1 (step S452). If the value of the backup monitoring timer matches the determination value (for example, 2) (step S453), the power supply stop process after step S454, that is, the preparation process for stopping the power supply is executed. That is, the state shifts from a state in which the progress of the game is controlled to a state in which a power supply stop process (a power-off control process) for saving the game state is executed.

  In this example, although not shown, it is necessary for restoring the game control state, for example, processing for saving the value of the stack pointer to the stack pointer saving buffer in the power backup area of the RAM in the power supply stop processing. A data saving process for saving the data in the power backup area of the RAM 55 is executed.

  By using the backup monitoring timer and the determination value, when the power-off confirmation signal is kept on for a time corresponding to the determination value, the power supply stop process is started. That is, even if the power-off confirmation signal is turned on for a moment due to noise or the like, the power supply stop process is not erroneously started. Note that the value of the backup monitoring timer formed in the RAM 55 is stored by the backup power source for a predetermined period even when power supply to the gaming machine is stopped. Therefore, in step S8 in the main process, it can be confirmed that the process result of the power supply stop process is stored because the value of the backup monitoring timer is the same as the determination value.

  In the power supply stop process, the CPU 56 creates parity data (steps S454 to S463). That is, first, clear data (00) is set in the checksum data area (step S454), and the checksum calculation start address corresponding to the start address of the RAM area in which the contents are to be stored even when power supply is stopped is set in the pointer. (Step S455). Further, the number of checksum calculations corresponding to the final address of the RAM area where the contents are to be stored even when the power supply is stopped is set (step S456).

  Next, an exclusive OR of the contents of the checksum data area and the contents of the RAM area pointed to by the pointer is calculated (step S457). The calculation result is stored in the checksum data area (step S458), the pointer value is incremented by 1 (step S459), and the checksum calculation count value is decremented by 1 (step S460). Then, the processes in steps S457 to S460 are repeated until the value of the checksum calculation count becomes 0 (step S461).

  When the value of the checksum calculation count becomes 0, the CPU 56 inverts the value of each bit of the contents of the checksum data area (step S462). Then, the inverted data is stored in the checksum data area (step S463). This data becomes parity data to be checked when the power is turned on. Next, an access prohibition value is set in the RAM access register (step S471). Thereafter, the built-in RAM 55 cannot be accessed.

  Further, the CPU 56 sets the head address of the port clear setting table stored in the ROM 54 as a pointer (step S472). In the port clear setting table, the number of processes (the number of output ports to be cleared) is set to the head address, and then the output port address and output value data (clear data: the value of the off state of each bit of the output port) However, the number of output ports corresponding to the number of processes is sequentially set.

  The CPU 56 loads data at the address pointed to by the pointer (that is, the number of processes) (step S473). Further, the value of the pointer is incremented by 1 (step S474), and the data of the address pointed to by the pointer (that is, the address of the output port) is loaded (step S475). Further, the value of the pointer is incremented by 1 (step S476), and the data of the address pointed to by the pointer (that is, output value data) is loaded (step S477). Then, the output value data is output to the output port (step S478). Thereafter, the number of processes is reduced by 1 (step S479). If the number of processes is not 0 (N in step S480), the process returns to step S474. If the number of processes is 0 (Y in step S480), that is, if all output ports to be cleared are cleared, the timer interrupt is stopped (step S481), and the loop process is entered.

  In the loop processing, it is monitored whether or not the power-off confirmation signal is turned off (step S482). When the power-off confirmation signal is turned off, an execution address at power-on (address in step S1) is set as a return address and a return command is executed (step S483). That is, the process returns to the main process. Specifically, a state in which a gaming device provided in the gaming machine is controlled (concept including both controlling by itself and transmitting a command signal to cause another microcomputer to control). Return.

  Further, in the loop processing, it is monitored whether or not the reset confirmation signal is in a low level ON state (step S484). When the reset confirmation signal is turned on, the payout control CPU 371 enters a system reset state (system reset). That is, the payout control CPU 371 is returned to the operation stop state, which is the start state (step S485). In this example, detection for turning on the reset signal so that the payout control CPU 371 is actively stopped when a voltage higher than its drive voltage (for example, 4 V) is still supplied. The voltage level of the voltage is set.

  When the power supply is stopped by the above process, the power supply stop process in steps S454 to S481 is executed, and data indicating that the power supply stop process has been executed (specified value with backup and checksum) Is stored in the backup RAM, the RAM access is disabled, the output port is cleared, and the timer interrupt for executing the game control process is disabled.

  In this embodiment, a part of the RAM 55 is backed up by a backup power source (the contents of the RAM 55 are preserved for a predetermined period even when the power supply to the gaming machine is stopped). In this example, the checksum based on the contents of the RAM 55 when the power-off confirmation signal is output is stored in the backup area of the RAM 55 together with the value of the backup monitoring timer by the processing of steps S452 to S480. After the power supply to the gaming machine is stopped, if the power supply is restored within a predetermined period, the game control means performs data stored in the RAM 55 (immediately before the power supply is stopped) by the processing of steps S91 to S94 described above. In accordance with the data indicating the game state that is the control state by the game control means (for example, including the process flag state, the big hit flag state, the probability change flag state, the output port output state, etc.) It is possible to return to the state immediately before the supply is stopped. If the power supply stop period exceeds the predetermined period, the value of the backup monitoring timer and the checksum should be different from the regular values. In this case, the initialization process of steps S10 to S14 is executed. The

  As described above, the power supply stop process (preparation process for stopping the power supply) ensures that the data for returning the gaming state to the state immediately before the power supply stopped is the fluctuation data storage means (in this example) Stored in a part of the RAM 55). Therefore, even if a power failure occurs due to a power failure or the like, if the power is restored within a predetermined period, the gaming state can be returned to the state immediately before the power supply is stopped.

  If the power-off confirmation signal is turned off, the process returns to step S1. In this case, since data indicating that the power supply stop process has been executed is set, the game state recovery process of steps S91 to S94 is executed. Therefore, when the power-off confirmation signal from the payout control board 37 is turned off after executing the power supply stop process, the process returns to the state of controlling the progress of the game. Therefore, even if a power interruption or the like occurs, the game control process does not stop, and the game control process is automatically continued.

  The first connection confirmation signal and the second connection confirmation signal transmitted to the payout control board 37 are set to an off state by the process of clearing the output port. In the setting of the work area in steps 82 and S12, the contents of the respective output port buffers corresponding to the first connection confirmation signal and the second connection confirmation signal indicate that the first connection confirmation signal and the second connection confirmation signal are on. Set to a value corresponding to the state. When the prize ball processing in step S31 is executed, the contents of the output port buffer are output to the output port, so that the first connection confirmation signal and the second connection confirmation signal to the payout control board 37 are turned on. . Therefore, the first connection confirmation signal and the second connection confirmation signal are output (turned on) when the main board 31 rises. Note that the first connection confirmation signal and the second connection confirmation signal are also output when the power supply is recovered from an instantaneous power interruption or the like.

  Next, payout control signals transmitted and received between the main board 31 and the payout control board 37 will be described. FIG. 17 is an explanatory diagram showing an example of the contents of a control signal output from the game control means to the payout control means and a payout control signal input from the payout control means to the game control means. In this embodiment, a plurality of types of control signals are transmitted and received between the main board 31 and the payout control board 37 in order to perform various controls relating to payout control and the like. As shown in FIG. 17, the first connection confirmation signal and the second connection confirmation signal are output when the main board 31 rises (when the game control means is ready to execute the game control process), and the payout control board. 37 is a signal for notifying that the main board 31 has been raised. The first connection confirmation signal and the second connection confirmation signal are signals indicating that the main board 31 is in a state in which the payout control signal can be normally transmitted, as will be described in detail later.

  The prize ball REQ signal is a signal that is in an output state (= ON state) when a prize ball payout request is made (that is, a trigger signal for a prize ball payout request). In addition, the prize ball REQ signal is in a stopped state (off state) when a predetermined period has elapsed. The award ball number signal is a signal (prize ball number command) output for designating the number of game balls (0 to 15) for which a payout request is made.

  The power-off confirmation signal is a signal that is turned on when the dispensing control means confirms the on-state of the power-off signal from the power monitoring circuit 920, and is turned off when the off-state of the power-off signal is confirmed. That is, it is used as a signal for notifying the main board 31 of the reception state of the power-off signal.

  The clear signal is turned on when the payout control means confirms the on state of the clear switch signal from the clear switch 921, and a predetermined period after the clear switch signal is turned off (clear signal output extension period: see FIG. 36). It is a signal that is turned off when it is confirmed that elapses. That is, it is used as a signal for notifying the main board 31 of the reception state of the clear switch signal (in this case, not the presence / absence of reception, but the state during reception or within a predetermined period from the end of reception). .

  The reset confirmation signal instructs the payout control means to stop the game control operation of the game control means from the off state to the on state based on the fact that the reset signal from the power supply monitoring circuit 920 has changed from the off state to the on state. It is a signal for. In addition, the reset confirmation signal indicates that the payout control means starts the game control operation of the game control means from the on state to the off state based on the fact that the reset signal from the power supply monitoring circuit 920 has changed from the on state to the off state. It is a signal for instructing. That is, it is used as a signal for notifying the main board 31 of a stop / start instruction for the control operation.

  The third connection confirmation signal is output when the payout control board 37 rises (when the payout control unit enters a state in which the payout control process can be executed), and indicates that the payout control board 37 has risen with respect to the main board 31. This is a signal for notification. In other words, the third connection confirmation signal is supplied to the payout control board 37 with respect to the main board 31 and the payout control CPU 371 mounted on the payout control board 37 can normally receive the payout control signal. It is a signal for notifying that it is in a state.

  FIG. 18 is a block diagram showing signal lines and the like used for transmission / reception of each control signal shown in FIG. As shown in FIG. 18, the first connection confirmation signal, the prize ball REQ signal, the prize ball number signal, and the second connection confirmation signal are output by the CPU 56 via the output circuit 67 and are paid out via the input circuit 373A. Is input to the CPU 371. Further, the power-off confirmation signal, the clear signal, the reset confirmation signal, and the third connection confirmation signal are output by the payout control CPU 371 via the output circuit 373B and input to the CPU 56 via the input circuit 68. The first connection confirmation signal, the second connection confirmation signal, the prize ball REQ signal, the power-off confirmation signal, the clear signal, the reset confirmation signal, and the third connection confirmation signal are each 1-bit data, and one signal line Sent by. The award ball number signal designates 0 to 15, and is composed of 4-bit data and transmitted through four signal lines.

  FIG. 19 shows a payout control signal (first connection confirmation signal, prize ball REQ signal, prize ball number signal, and second connection confirmation signal) transmitted from the main board 31 to the payout control board 37, and a payout control board. It is explanatory drawing which shows the example of the connection state of the signal wire | line which transmits the 3rd connection confirmation signal transmitted with respect to the main board | substrate 31 from 37. FIG.

  As shown in FIG. 19, the payout control signal output by the CPU 56 through the output circuit 67 is sent out via the connector 69B mounted on the main board 31 and the connector 69A connected to the connector 69B. 37 is transmitted. The payout control signal transmitted to the payout control board 37 side is input to the input circuit 373A via the connector 376A and the connector 376B mounted on the payout control board 37 connected to the connector 376A. Then, a payout control signal is input to the payout control CPU 371 via the input circuit 373A.

  That is, the payout control signal is a cable provided with a connector 69A connected to the main board 31, a connector 376A connected to the payout control board 37, and a signal line for transmitting a signal between the connector 69A and the connector 376A. (Signal line connecting means). In this example, each payout control signal is transmitted by a plurality of signal lines provided in the cable.

  The third connection confirmation signal output by the payout control CPU 371 via the output circuit 373B is sent to the main board via the connector 376B mounted on the payout control board 37 and the connector 376A connected to the connector 376B. It is transmitted to the 31 side. The third connection confirmation signal transmitted to the main board 31 side is input to the input circuit 68 via the connector 69A and the connector 69B mounted on the main board 31 connected to the connector 69A. Then, the third connection confirmation signal is input to the CPU 56 via the input circuit 68.

  That is, the third connection confirmation signal transmits a signal between the connector 69A connected to the main board 31, the connector 376A connected to the payout control board 37, and the connector 69A and the connector 376A, like the payout control signal. Is transmitted by a cable (signal line connecting means) having a signal line. In this example, the third connection confirmation signal is transmitted by one of the plurality of signal lines provided in the cable.

  Each of the connector 69A and the connector 376A includes a plurality of pins for transmitting a payout control signal from the main board 31 and a third connection confirmation signal to the payout control board 37. In this example, the connector 69A and the connector 376A each have at least one pin for a first connection confirmation signal, a prize ball REQ signal, a second connection confirmation signal, and a third connection confirmation signal, respectively, and a prize ball number signal. It has 4 pins for use. That is, the connector 69A and the connector 376A each have at least eight pins to which the payout control signal and the third connection confirmation signal are assigned.

  In this example, the plurality of pins provided in the connector 69A and the connector 376A include a prize ball REQ signal between a pin used for transmitting the first connection confirmation signal and a pin used for transmitting the second connection confirmation signal. The payout control signal is assigned so that five pins used for the transmission of the award ball number signal are located.

  That is, the arrangement of the plurality of pins provided in each of the connector 69A and the connector 376A may be any arrangement such as that arranged in a plurality of stages, but at least for the first connection confirmation signal. Each of the signals is assigned to the pin so that another payout control signal pin is located between the pin and the second connection confirmation signal pin.

  As described above, the connectors 69A and 376A are arranged so that the prize ball REQ signal pin and the prize ball number signal pin are arranged between the first connection confirmation signal pin and the second connection confirmation signal pin. Since the signal is assigned to the pins included in the pin, if there is an abnormality in the connection state of the pin for the prize ball REQ signal or the pin for the prize ball number signal, the pin for the first connection confirmation signal or the Since an abnormality occurs in the connection state of at least one of the two connection confirmation signal pins, an abnormality relating to communication can be accurately detected. Therefore, only by monitoring the states of the first connection confirmation signal and the second connection confirmation signal, it is possible to accurately grasp whether the winning ball REQ signal or the winning ball number signal can be normally transmitted. Since it is possible to prevent the prize ball REQ signal and the prize ball number signal from being missed, it is possible to more reliably manage the number of unpaid prize balls in the game control means.

  FIG. 20 is a timing chart showing an example of how to output the payout control signal, and FIG. 21 is a timing chart showing a part of FIG. 20 in an enlarged manner. As shown in FIG. 20, when the winning detection switch detects the winning of a game ball, the game control means changes the output state of the winning ball number signal to a state corresponding to the number of winning balls to be paid out in accordance with the winning, The sphere REQ signal is turned on. In this embodiment, when a game ball is detected by the start port switch 14a, four prize balls are paid out, and when a game ball is detected by any one of the prize port switches 33a, 39a, 29a, 30a. Seven prize balls are paid out. When a game ball is detected by the V count switch 22 or the count switch 23, 15 prize balls are paid out. Further, as described above, the prize ball number signal is composed of 4 bits, so the lower 4 bits of the prize ball number commands of 00 (H) to 0F (H) expressed in 8 bits are The signal is transmitted from the main board 31 to the payout control board 37 by the award ball number signal. Hereinafter, it may be expressed as “00 (H) to 0F (H) prize ball number signal”, but in reality, the prize ball number signal is represented by 8 bits. This corresponds to the lower 4 bits of 0F (H).

  When the payout control means confirms the reception of the prize ball REQ signal, the payout control means confirms the reception state of the prize ball number signal, and adds the prize ball number indicated by the prize ball number signal to the prize ball unpaid number counter.

  The game control means turns off the prize ball REQ signal and clears the output state of the prize ball number signal when the prize ball REQ signal off waiting time elapses after the prize ball REQ signal is turned on. Put it in a state. That is, a state in which the prize ball number signal indicates 0 (a state in which an invalid command is output) is set. Accordingly, since the prize ball number signal is in an invalid command output state when the prize ball REQ signal is in an on state, the on-state of the prize ball REQ signal is detected by noise or the like in the payout control means. However, there is no such thing as accidentally paying out a prize ball. The award ball REQ signal off waiting time is a time period during which the award ball REQ signal is turned on in advance, which is predetermined as a time during which the payout control board 37 can reliably recognize reception of the award ball REQ signal. Further, the waiting time for the prize ball REQ signal is different when the frequency of the clock signal supplied to the CPU 56 and the payout control CPU 371 is changed. That is, when the frequency of the clock signal supplied to the CPU 56 and the payout control CPU 371 changes, the value becomes different.

  As shown in FIG. 20, when a new winning is detected when the winning ball REQ signal is in the on state, the turning on of the winning ball REQ signal and the output of the winning ball number signal based on the winning are waited. Specifically, when a new winning is detected when the winning ball REQ signal is on, the number of winning balls to be paid out based on the winning is the content of the total winning ball buffer formed in the RAM 55. Is added to Then, when the game control means turns off the prize ball REQ signal, if the content of the total prize ball number buffer is not 0, the game control means sets the number of prize balls indicated by the content of the total prize ball number buffer to 15 as the upper limit. In order to instruct a prize ball payout, the prize ball REQ signal is turned on and a prize ball number signal is output.

  FIG. 22 is a timing chart showing an example of how to output the payout control signal. When either the first connection confirmation signal or the second connection confirmation signal is in the OFF state, the game control means is in a prize ball control signal transmission prohibited state in which the prize ball REQ signal and the prize ball number signal are not transmitted. Become. In the prize ball control signal transmission prohibited state, the game control means does not output a prize ball REQ signal even if a prize is generated, as shown in FIG. Therefore, the process in which the payout control means captures the winning ball number signal is not executed. Thereafter, when both the first connection confirmation signal and the second connection confirmation signal are turned on, the prize ball control signal transmission prohibition state is canceled, and the game control means outputs a prize ball number signal and a prize ball REQ signal. Turn on the.

  As described above, when either the first connection confirmation signal or the second connection confirmation signal is in the OFF state, the game control means determines that an abnormality has occurred in the transmission state of the prize ball control signal. Since the prize ball REQ signal is not transmitted, it is possible to inhibit the prize ball number signal from being taken in by the payout control means when there is a possibility that the prize ball control signal may not be normally transmitted. It is possible to prevent the payout control means from erroneously recognizing the number of winning balls, and to avoid adversely affecting the player.

  FIG. 23 is a flowchart showing an example of the prize ball processing in step S31. In the prize ball process, the CPU 56 executes the prize ball number addition process (step S201) and then checks the state of the payout signal stop flag (step S204). If the payout signal stop flag is off, that is, if the prize ball control signal transmission is not prohibited, the process proceeds to step S202.

  If the payout signal stop flag is on, that is, if the prize ball control signal transmission is prohibited, the CPU 56 checks the input states of the first connection confirmation signal and the second connection confirmation signal (step S205).

  If both the first connection confirmation signal and the second connection confirmation signal are on (N in step S205), the CPU 56 turns off the payout signal stop flag (step S206), and turns off the error display lamp 44. (Step S207), the process proceeds to step S202. That is, if both the first connection confirmation signal and the second connection confirmation signal are returned to the on state, processing for canceling the prize ball control signal transmission prohibited state is performed.

  If either the first connection confirmation signal or the second connection confirmation signal is in the off state (Y in step S205), the process is terminated without proceeding to step S202. That is, if both the first connection confirmation signal and the second connection confirmation signal are not returned to the on state, the process is terminated while the prize ball control signal transmission prohibited state is maintained.

  Next, in step S202, the CPU 56 executes a prize ball control process. Then, the contents of the port 0 buffer formed in the RAM 55 are output to port 0 (step S203). The contents of the port 0 buffer are updated in the prize ball control process.

  In the prize ball number adding process, if the detection signal of the winning detection switch to be inspected is in the ON state, the CPU 56 sets the prize ball number corresponding to the switch as the prize ball addition value, and the prize ball addition value is stored in the RAM 55. Is added to the contents of the 16-bit total award ball number storage buffer. The total winning ball number storage buffer is formed in the backup RAM. Note that “formed in the RAM” means an area in the RAM.

  FIG. 24 is a flowchart showing the prize ball control process in step S202. In the prize ball control process, the CPU 56 executes any one of steps S231 to S233 according to the value of the prize ball process code.

  FIG. 25 is a flowchart showing the winning ball waiting process 1 (step S231) executed when the value of the winning ball process code is zero. In the award ball waiting process 1, the CPU 56 sets the award ball waiting output value (20 (H)) in the port 0 buffer (step S241). When the prize ball waiting output value is set in the port 0 buffer, the prize ball REQ signal is turned off by outputting the contents of the port 0 buffer to port 0 in step S203 (see FIG. 8). . In addition, the award ball number signal enters an invalid command (00 (H)) output state.

  Next, the CPU 56 checks whether or not the prize ball timer is 0 (step S242). If the prize ball timer is not 0, the value of the prize ball timer is decreased by 1 (step S243), and the process is terminated. The prize ball timer is a timer for measuring the time required for prize ball processing. At this stage, if the value of the prize ball timer is not 0, the next prize ball after the previous payout process is completed. Waiting time until the REQ signal is turned on (time for providing an interval between ON periods of a plurality of prize ball REQ signals when prize ball payout is continuously executed, 00 (H ) During which the award ball number signal is output (for example, MAX49.391 ms)) is not completed. The prize ball timer is set in step S263 of the prize ball waiting process 2 described later. In addition, after the execution of the award ball waiting process 2 in step S234 is completed and the previous award ball control process is completed, the processes of steps S241 to S243 are performed with the award ball REQ signal turned off and the award ball number signal. As an invalid command (00 (H)).

  If the value of the prize ball timer is 0, the CPU 56 then checks the contents of the total prize ball number storage buffer (step S244). If the value is 0, the process ends. If not, the value of the prize ball process code is set to 1 (step S245), and the process ends.

  FIG. 26 is a flowchart showing a prize ball transmission process (step S232) executed when the value of the prize ball process code is 1. In the prize ball transmission process, the CPU 56 checks whether or not the content of the total prize ball number storage buffer is smaller than the prize ball command maximum value (“15” in this example) (step S251). If the content of the total prize ball number storage buffer is equal to or greater than the prize ball command maximum value, the prize ball command maximum value is set in the prize ball number buffer (step S252). If the content of the total prize ball number storage buffer is smaller than the maximum value of the prize ball command, the content of the total prize ball number storage buffer is set in the prize ball number buffer (step S253).

  When the winning ball number buffer is set, the CPU 56 checks the input states of the first connection confirmation signal and the second connection confirmation signal (step S254).

  If both the first connection confirmation signal and the second connection confirmation signal are on (N in step S254), the output value (81 (H)) in the prize ball REQ is set in the output port 0 buffer (step S255). When the output value in the prize ball REQ is set in the output port 0 buffer, the contents of the output port 0 buffer are outputted to the port 0 in step S203, so that the prize ball REQ signal is turned on (FIG. 8). reference). Further, the contents of the winning ball number buffer are set in bits 1 to 4 of the output port 0 buffer (step S256).

  In this embodiment, the maximum value of the prize ball command is “15”. Accordingly, a prize ball control signal designating the maximum number of payouts of “15” is transmitted to the payout control board 37.

  If one of the first connection confirmation signal and the second connection confirmation signal is in an off state (Y in step S254), the error display lamp 44 is turned on without proceeding to step S255 (step S255). S271), the payout signal stop flag is turned on (step S274). That is, the winning ball control signal transmission is prohibited. In this example, in the prize ball control signal transmission prohibited state in which the payout signal stop flag is on, the prize ball control process (step S202) and the subsequent output process of the contents of the port 0 buffer (step S203) are executed. It is prohibited and no prize ball control signal is transmitted. The prize ball number addition process (step S201) and other processes in the prize ball process in the game control process (see FIG. 14) are continued without being prohibited.

  When the prize ball control signal is transmitted, the CPU 56 subtracts the contents of the prize ball number buffer (the number of prize balls paid out to the payout control means) from the contents of the total prize ball number storage buffer (step S257). Then, a REQ end determination time value (for example, 3) is set in the prize ball timer (step S258). The REQ end determination time value is a value for creating the award ball REQ signal off waiting time shown in FIG. Thereafter, the value of the prize ball process code is set to 2 (step S259), and the process is terminated.

  In this example, after the prize ball control signal is transmitted, the subtraction process in step S257 is performed. Specifically, in step S255 and step S256, the output value in the prize ball REQ and the content of the prize ball number buffer are obtained. After being set in the output port 0 buffer, this is performed before the contents of the output port 0 buffer are output to port 0 in step S203. However, in step S255 and step S256, the output value in the prize ball REQ and the contents of the prize ball number buffer are set in the output port 0 buffer, and then in step S203, the contents of the output port 0 buffer are output to port 0. Subtraction processing for subtracting the contents of the prize ball number buffer from the contents of the total prize ball number storage buffer may be performed after the prize ball REQ signal is actually turned on.

  FIG. 27 is a flowchart showing the winning ball waiting process 2 (step S233) executed when the value of the winning ball process code is 2. In the award ball waiting process 2, the CPU 56 confirms the value of the award ball timer (step S261). If the value is not 0, the value of the award ball timer is decreased by 1 (step S262), and the process is terminated. When the value of the prize ball timer becomes 0, that is, when the prize ball REQ signal OFF waiting time shown in FIG. 21 has elapsed, the prize ball REQ waiting time is set in the prize ball timer (step S263). Then, the value of the prize ball process code is set to 0 (step S264), and the process is terminated. As described above, the award ball REQ waiting time is the waiting time until the next award ball REQ signal is turned on (when award ball payout is continuously performed, the on periods of a plurality of award ball REQ signals are Is a time for providing an interval).

  Through the above processing, the game control means stores the total number of game balls as prize balls to be paid out based on the establishment of the payout condition in the total prize ball number storage buffer so as to be specified. Further, the game control means transmits a payout command signal for designating a payout number of a predetermined number of prize balls to the payout control means based on the number of prize balls stored in the total prize ball number storage buffer. Here, the predetermined number is 15 if the number of prize balls stored in the total prize ball number storage buffer is 15 or more, and is stored in the total prize ball number storage buffer if it is less than 15. The number of prize balls. Then, when a prize ball control signal designating the prize ball payout is transmitted, a subtraction process is performed to subtract the number of payouts designated by the payout command signal from the number of prize balls stored in the total prize ball number storage buffer.

  As described above, by confirming the input state of the first connection confirmation signal and the second connection confirmation signal, the prize ball control signal is transmitted only when the transmission is normally performed, and the prize ball control signal is Since the number of payouts specified by the payout number signal is subtracted from the number of prize balls stored in the total prize ball number storage buffer in response to the transmission, the number of prize balls not paid out by the game control means Can be reliably managed. That is, when an abnormality relating to communication occurs, the prize ball control signal is not transmitted, so that the management of the number of unpaid prize balls by the game control means is ensured.

  In this embodiment, as the prize game medium number storage means for storing the total number of prize game media to be paid out in accordance with the establishment of the payout condition, a total prize ball number storage buffer for storing the total number itself is exemplified. However, the prize game medium number storage means for storing the total number of the prize game media in an identifiable manner stores the number of prizes received in each prize area, or the number of prizes for each prize area (for example, 6). The number of winning holes 14 corresponding to the number of winning balls, the number of winning holes 33, 39, 29, 30 corresponding to the number of 10 winning balls, and the number of winning prizes corresponding to the number of 15 winning balls, , The number of winning prizes for which the winning ball payout has not ended yet) may be stored.

  Next, the operation of the payout control means (the payout control CPU 371 and peripheral circuits such as ROM and RAM) will be described. FIG. 28 is an explanatory diagram showing an example of output port assignment in the payout control means. As shown in FIG. 28, the output port 0 is an output port for outputting each phase signal supplied to the firing motor 94 by the stepping motor and each phase signal supplied to the payout motor 289 by the stepping motor. It is. The output port 1 is an output port for outputting a ball break LED 52, a prize ball LED 51, a power cut confirmation signal, a third connection confirmation signal, a reset confirmation signal, and a clear signal. The output port 2 is an output port of each segment output of the error display LED 374 by 7 segment LED. The output port 3 is an output port for outputting an award ball signal, award ball information, ball lending information, and a gaming machine error status signal output to the outside of the gaming machine.

  Although not shown in FIG. 28, the payout control board 37 is also provided with an output port 4 for outputting an EXS signal and a PRDY signal to the card unit 50.

  FIG. 29 is an explanatory diagram showing an example of bit assignment of input ports in the payout control means. As shown in FIG. 29, the first connection confirmation signal from the main board 31 is input to bit 0 of the input port 0, and the 4-bit prize ball number signal from the main board 31 is input to bits 1 to 3. Bits 5 and 7 receive a prize ball REQ signal from the main board 31 and a second connection confirmation signal from the main board 31, respectively. Bits 0 to 3 of the input port 1 respectively include a touch sensor signal (launch control signal) from the touch sensor, a detection signal from the payout count switch 301, an operation signal from the error release switch 375, and a full switch 48. The detection signal is input. The VL signal, the BRDY signal, and the BRQ signal from the card unit 50 are input to bits 4 to 6 of the input port 1, respectively. To the input port 2, an output signal (clear switch signal) of the clear switch 921 from the power supply substrate 910, a power-off signal, a detection signal of the ball break switch 187, and a detection signal of the payout motor position sensor 295 are input.

  FIG. 30 is a timing chart for explaining the communication between the payout control means of the gaming machine and the card unit 50. The payout control means turns on the PRDY signal when power supply to the gaming machine is started and a payout operation is possible. When the power supply is started, the card unit 50 turns on the VL signal as a connection signal. When a card is received in the card unit 50, the ball lending switch is operated and a ball lending switch signal is input, the card unit 50 outputs a BRDY signal to the payout control means. That is, the BRDY signal is turned on. When a predetermined delay time elapses from this point, the card unit 50 outputs a BRQ signal to the payout control means. That is, the BRQ signal is turned on.

  Then, when the payout control means turns on the EXS signal for the card unit 50 and detects the falling (off) of the BRQ signal from the card unit 50, the payout motor 289 is driven to drive a predetermined number (for example, 25). Pay out the rental balls to the player. Then, when the payout is completed, the payout control means causes the EXS signal to the card unit 50 to fall. That is, the EXS signal is turned off.

  Next, the operation of the payout control means will be described. FIG. 31 is a flowchart showing main processing executed by the payout control means. In the main process, the payout control CPU 371 first performs necessary initial settings. That is, the payout control CPU 371 first sets the interruption prohibition (step S701). Next, the interrupt mode is set to interrupt mode 2 (step S702), and a stack pointer designation address is set to the stack pointer (step S703). The payout control CPU 371 initializes the built-in device register (step S704), initializes the CTC and PIO (step S705), and then sets the RAM in an accessible state (step S706). . Further, 0000 (H) is set as an initial value of the award ball unpaid number counter (step S707).

  In this embodiment, one channel of the built-in CTC is used in the timer mode. Accordingly, in the built-in device register setting process in step S704 and the process in step S705, register setting for setting the channel to be used to timer mode, register setting for permitting interrupt generation, and setting an interrupt vector. The register is set. The interrupt by the channel is used as a timer interrupt. For example, when it is desired to generate a timer interrupt every 0.7 ms, a value corresponding to 0.7 ms is set as an initial value in a predetermined register (time constant register).

  The interrupt vector set for the channel set to the timer mode (channel 3 in this embodiment) corresponds to the start address of the timer interrupt process. Specifically, the start address of the timer interrupt process is specified by the value set in the I register and the interrupt vector. In the timer interruption process, a payout control process for controlling the payout means (including at least a process of driving the ball payout device 97 in response to a command signal related to award ball payout from the main board, and a ball payout device 97 in response to a ball lending request. A process for driving the program may be included.

  In this embodiment, the interruption mode 2 is also set in the payout control CPU 371. Therefore, it is possible to use an interrupt process based on counting up the built-in CTC. Also, an interrupt processing start address can be set according to the interrupt vector sent by the CTC.

  The interrupt based on CTC channel 3 (CH3) count-up is an interrupt that occurs when the CPU internal clock (system clock) counts down and the register value becomes “0”, and is used as a timer interrupt. . Specifically, a clock obtained by dividing the operation clock of the CPU 371 is given to the CTC, the register value is subtracted by the input of the clock, and when the register value becomes 0, a timer interrupt occurs. For example, the register value of CH3 is subtracted at 1/256 period of the system clock. Since the subtraction is performed based on the divided clock, the initial value of the register does not increase.

  Next, the state of the clear switch signal from the clear switch 921 input via the input port 2 is confirmed only once (step S708). When ON is detected in the confirmation, the payout control CPU 371 sets a clear signal to the output port 1 and outputs a clear signal to the main board 31 (step S712). That is, the clear signal is turned on. Then, initialization processing is executed (steps S713 to S716). When the clear signal is turned on in step S712, the clear switch signal from the clear switch 921 is turned off thereafter for a predetermined period (clear signal output extension period: see FIG. 36B). Until the time elapses, the ON state of the clear signal is continued.

  When the clear switch signal from the clear switch 921 is not in the on state, the data protection processing of the backup RAM area (for example, power supply stop processing such as addition of parity data) is performed when power supply to the gaming machine is stopped. It is confirmed whether it has been received (step S709). Whether or not the protection process has been performed depends on the value of the backup monitoring timer stored in the backup RAM area in the power supply stop process described later according to the execution of the data protection process in the backup RAM area (for example, It is confirmed by whether or not 10). Note that such a confirmation method is merely an example. For example, a flag indicating that the data protection processing has been executed is set in the backup flag area in the power supply stop processing, and the flag is set in step S709. If it is confirmed that there is a backup, it may be determined that there is a backup.

  If it is determined that there is a backup, the payout control CPU 371 performs a data check (parity check in this example) in the backup RAM area (step S710). In this embodiment, clear data (00) is set in the checksum data area, and the checksum calculation start address is set in the pointer. Also, the number of checksum calculations corresponding to the number of data to be checksum is set. Then, the exclusive OR of the contents of the checksum data area and the contents of the RAM area pointed to by the pointer is calculated. The calculation result is stored in the checksum data area, the pointer value is incremented by 1, and the checksum calculation count value is decremented by 1. The above processing is repeated until the value of the checksum calculation count becomes zero. When the value of the checksum calculation count becomes 0, the CPU 56 inverts the value of each bit of the contents of the checksum data area and uses the inverted data as the checksum.

  In the power supply stop process described later, the checksum is calculated by the same process (the process shown in FIG. 34) as the above process, and the checksum is stored in the backup RAM area. In step S710, the calculated checksum is compared with the stored checksum. When the power supply is stopped after an unexpected power outage or the like, the data in the backup RAM area should be saved, so the check result (comparison result) is normal (matched). That the check result is not normal means that the data in the backup RAM area is different from the data when the power supply is stopped. In such a case, since the internal state cannot be returned to the state when the power supply is stopped, the payout control state restoration process is not executed, the clear signal is turned on (step S712), and the initialization process ( Steps S713 to S716) are executed.

  If the check result is normal, the payout control CPU 371 performs payout control state recovery processing. Specifically, the value of the award ball unpaid number counter formed in the backup RAM is set as the initial value of the award ball unpaid number counter (step S711). And the process after step S714 is performed.

  In the initialization process, the payout control CPU 371 first performs a RAM clear process (step S713). Also, initial values are set in the flags and counters of the RAM area (step S714). The process of step S714 includes a process of setting the initial value of the award ball unpaid number counter in the award ball unpaid number counter. Therefore, when the payout control state recovery process (step S711) is executed, the value of the unsold prize ball number counter stored in the backup RAM is set again in the unsold prize ball number counter. In other words, the value of the award ball unpaid number counter stored in the backup RAM is used as it is.

  Then, the CTC register provided in the payout control CPU 371 is set so that a timer interruption is periodically performed (step S715). That is, a value corresponding to the timer interrupt generation interval is set as an initial value in a predetermined register (time constant register).

  Further, when the initialization process is finished, the payout control CPU 371 switches the reset confirmation signal from the on state to the off state, and instructs the main board 31 to start the game control operation (step S716).

  Next, the payout control CPU 371 starts payout control signal reception processing (step S717). That is, the control state is such that the payout control signal from the game control means can be received. Since the payout control process has not yet started, when a payout control signal is received in the payout control signal reception process, information indicating the content of the received payout control signal is stored in the RAM provided in the payout control board 37. The processing according to the received payout control signal is executed after the payout control process is started.

  Then, the payout control CPU 371 sets the third connection confirmation signal to the on state (step S718), assuming that the payout control process can be executed, and then inputs the first connection confirmation signal and the second connection confirmation signal. A monitoring process for monitoring is performed (step S719).

  The monitoring process for monitoring the input states of the first connection confirmation signal and the second connection confirmation signal may be started after the third connection confirmation signal is turned on as described above. It may be started before the connection confirmation signal is turned on.

  When the monitoring process in step S719 confirms that the first connection confirmation signal and the second connection confirmation signal are in the ON state before the predetermined monitoring period elapses, the payout control CPU 371 starts executing the payout control. To do. That is, since interruption is prohibited in step S701 of the initial setting process, interruption is permitted in order to allow execution of the payout control process (step S720). Thereafter, a loop process for monitoring the occurrence of a timer interrupt is entered.

  Although not explicitly shown in FIG. 31, in this example, after the third connection confirmation signal is turned on, the first connection confirmation signal and the second connection confirmation signal are not turned on and are determined in advance. When the monitoring period elapses, the payout control CPU 371 determines that it is a main control non-connection error, for example, notifies the game store clerk or the like by a notification means such as a lamp, and turns off the third connection confirmation signal. Then, the control process is terminated.

  As described above, in this embodiment, the built-in CTC of the payout control CPU 371 is set to repeatedly generate a timer interrupt. When a timer interrupt occurs, the payout control CPU 371 executes a timer interrupt process.

  FIG. 32 is a flowchart showing an example of timer interrupt processing executed by the payout control means. In the timer interrupt process, the payout control CPU 371 executes a power-off process for monitoring whether or not a power-off signal is output (step S749). Thereafter, a payout control process after step S750 is executed. In the payout control process, the payout control CPU 371 first performs an excitation pattern output process for the firing motor 94 (output of the patterns of the firing motors φ1 to φ4 to the output port 0) (step S750). In the firing motor control process in step S752, the excitation pattern is stored in the excitation pattern buffer that is the RAM area. In step S750, the payout control CPU 371 outputs the contents of the excitation pattern buffer to the lower 4 bits of the output port 0. Perform the process.

  Next, the payout control CPU 371 performs input determination processing (step S751). The input determination process detects the states of bits 0, 4, and 7 of the input port 0, bits 3 to 6 of the input port 1, and bit 2 (see FIG. 29) of the input port 2, and the detection result is stored in a predetermined RAM This process is reflected in one byte (referred to as an input state flag). In the payout control process, when control is performed based on the state of each bit in each input port, the state of the input state flag is checked instead of directly checking the state of the input port.

  Next, the payout control CPU 371 executes a firing motor control process (step S752). In the firing motor control process, the patterns of the firing motors φ1 to φ4 are stored in the excitation pattern buffer. When the firing motor 94 should be disabled, the patterns of the firing motors φ1 to φ4 that do not rotate the firing motor 94 are stored in the excitation pattern buffer. Also, the payout control CPU 371 executes a payout motor control process (step S753). In the payout motor control process, when the payout motor 289 is to be driven, a process for outputting the patterns of the payout motors φ1 to φ4 to the output port 0 is performed.

  Also, the payout control CPU 371 executes a prepaid card unit control process for communicating with the card unit 50 (step S754). Next, the payout control CPU 371 executes main control communication processing for communicating with the game control means of the main board 31 (step S755). Further, a prize ball lending control process for performing a control for paying out a lending ball in response to a ball lending request from the card unit 50 and performing a control for paying out the number of award balls indicated by a prize ball number signal from the main board. Is executed (step S756).

  Then, the payout control CPU 371 executes error processing for detecting various errors (step S757). Further, an information output process for outputting prize ball information and ball lending information output to the outside of the gaming machine is executed (step S758). Further, a predetermined display is performed on the error display LED 374 according to the result of the error processing, and a display control process for lighting the prize ball LED 51 and the ball out LED 52 is executed (step S759). In the display control process, the payout control CPU 371 performs control for lighting the prize ball LED 51 when the prize ball REQ signal is on. Further, when the prize ball REQ signal is turned off, control for turning off the prize ball LED 51 is performed.

  In this embodiment, a RAM area (output port 0 buffer to output port 3 buffer) corresponding to the output state of the output port is provided. However, the payout control CPU 371 is configured to output the output port 0 buffer to output. The contents of the port 3 buffer are output to the output port (step S760: output processing). However, since the lower 4 bits (fire motors φ1 to φ4) of output port 0 are executed in step S750, the output of the lower 4 bits of output port 0 is not performed in the output process. The output port 0 buffer to output port 3 buffer are a payout motor control process (step S753), a prepaid card control process (step S754), a main control communication process (step S755), an information output process (step S758), and a display control process ( Updated in step S759).

  33 to 35 are flowcharts illustrating an example of the power-off process in step S749. In the power-off process, the payout control CPU 371 first checks whether or not a power-off signal is output (whether or not it is in an on state) (step S901). If not in the ON state, the value of the backup monitoring timer formed in the RAM provided in the payout control board 37 is cleared to 0 (step S902). If it is in the ON state, the value of the backup monitoring timer formed in the RAM provided in the payout control board 37 is increased by 1 (step S903). If the value of the backup monitoring timer matches the determination value (for example, 2) (step S904), the power supply stop process after step S905, that is, the preparation process for stopping the power supply is executed. That is, the process shifts from a state in which the payout control is executed to a state in which a power supply stop process (a power-off control process) for saving the payout control state is executed.

  By using the backup monitoring timer and the determination value, if the power-off signal is kept on for a time corresponding to the determination value, the power supply stop process is started. That is, even if the power-off signal is turned on for a moment due to noise or the like, the power supply stop process is not erroneously started. Note that the value of the backup monitoring timer formed in the RAM provided in the payout control board 37 is stored by the backup power source for a predetermined period even when the power supply to the gaming machine is stopped. Therefore, in step S709 in the main process, it can be confirmed that the process result of the power supply stop process is stored because the value of the backup monitoring timer is the same as the determination value.

  In this example, although not shown, in the power supply stop process, for example, the payout control state such as the process of saving the value of the stack pointer to the stack pointer save buffer in the RAM power backup area provided in the payout control board 37 is changed. Data saving processing for saving data necessary for recovery in the power backup area of the RAM is executed.

  In the power supply stop process, the payout control CPU 371 outputs a power-off confirmation signal (turns on) (step S905) and sets the power supply stop process standby time to the standby time timer (step S906). Then, a prize ball receiving process is performed during a standby time for receiving a prize ball control signal from the game control means for a predetermined period (process standby time when power supply is stopped) (steps S907 to S910). The standby time timer is stored in a RAM provided in the payout control board 37.

  The processing standby time at the time of power supply stop is determined in advance as a period from when the power-off confirmation signal is output until the processing at the time of power supply stop at the main board 31 is started according to the input of the power-off confirmation signal. It's time. The power supply stop process standby time is determined at least so that the power supply stop process on the main board 31 is started before the award ball acceptance process during the standby time is completed. This time may be determined, for example, by actually measuring the period from when the payout control means outputs the power-off confirmation signal until the game control means starts the process of stopping power supply. .

  In the award ball acceptance process during the waiting time, if the prize ball REQ signal is on (step S907), the payout control CPU 371 adds the number indicated by the prize ball number signal to the prize ball unpaid number counter (step S907). S908). Next, the payout control CPU 371 subtracts 1 from the standby time timer (step S909), and if the standby time timer is not 0, returns to the process of step S907 (step S910). That is, the prize ball acceptance process is executed during the standby time until the process standby time at the time of stopping power supply elapses, the reception state of the prize ball REQ signal is monitored, and the unpaid-out number counter is updated.

  If the waiting time timer is 0 (Y in step S910), the award ball acceptance process during the waiting time is terminated, and the process proceeds to step S911.

  In the waiting ball prize ball receiving process, for example, a predetermined delay period is provided after determining N in step S910, so that the loop period (cycle) of the waiting ball prize ball receiving process is the prize ball REQ. It is set to be surely longer than the signal ON period (prize ball REQ signal output time). That is, in the award ball acceptance process during the waiting time, the same award ball control command is processed so that it is not received repeatedly within the process.

  As described above, when a delay period is provided in the award ball acceptance process during the standby time, the time set in the standby time timer is a power supply stop process standby time that takes into account the delay period. In other words, the time set in the standby time timer does not coincide with the processing standby time when the power supply is stopped, and the product of the scheduled number of loop processing and the delay period per time in the waiting ball reception processing during the standby time The time added to the time set in the time timer is the processing standby time when the power supply is stopped.

  When the award ball acceptance process during the waiting time is completed, the payout control CPU 371 creates parity data (steps S911 to S920). That is, first, clear data (00) is set in the checksum data area (step S911), and the checksum calculation start address corresponding to the start address of the RAM area where the contents are to be stored even when power supply is stopped is set as a pointer. (Step S912). Also, the number of checksum calculations corresponding to the final address of the RAM area where the contents are to be stored even when the power supply is stopped is set (step S913).

  Next, an exclusive OR of the contents of the checksum data area and the contents of the RAM area pointed to by the pointer is calculated (step S914). The calculation result is stored in the checksum data area (step S915), the pointer value is incremented by 1 (step S916), and the value of the checksum calculation count is decremented by 1 (step S917). Then, the processes in steps S914 to S917 are repeated until the value of the checksum calculation count becomes 0 (step S918).

  When the value of the checksum calculation count becomes 0, the payout control CPU 371 inverts the value of each bit of the contents of the checksum data area (step S919). Then, the inverted data is stored in the checksum data area (step S920). This data becomes parity data to be checked when the power is turned on. Next, an access prohibition value is set in the RAM access register (step S921). Thereafter, the built-in RAM 55 cannot be accessed.

  Further, the payout control CPU 371 sets the start address of the port clear setting table stored in the ROM 54 as a pointer (step S922). In the port clear setting table, the number of processes (the number of output ports to be cleared) is set to the head address, and then the output port address and output value data (clear data: the value of the off state of each bit of the output port) However, the number of output ports corresponding to the number of processes is sequentially set.

  The payout control CPU 371 loads data at the address pointed to by the pointer (that is, the number of processes) (step S923). Further, the value of the pointer is incremented by 1 (step S924), and the data of the address pointed to by the pointer (that is, the output port address) is loaded (step S925). Further, the value of the pointer is incremented by 1 (step S926), and the data of the address pointed to by the pointer (that is, output value data) is loaded (step S927). Then, the output value data is output to the output port (step S928). Thereafter, the number of processes is reduced by 1 (step S929), and if the number of processes is not 0, the process returns to step S924 (step S930). If the number of processes is 0 (Y in step S930), that is, if all output ports to be cleared are cleared, the timer interrupt is stopped (step S931) and the loop process is started.

  In this example, it is assumed that at least an output port used for outputting a power-off confirmation signal or a reset confirmation signal is not included in the output ports to be cleared, and is not cleared in the processing of steps S922 to S930. . That is, in the port clear setting table, the address of the output port used for outputting the power-off confirmation signal and the reset confirmation signal is not set.

  In the loop processing, it is monitored whether or not the power-off signal is turned off (step S932). When the power-off signal is turned off, output of the power-off confirmation signal is stopped (turned off) (step S933), and the power-on execution address (address of step S701) is used as the return address. Set and execute a return instruction (step S934). That is, the process returns to the main process. Specifically, the state returns to a state in which a gaming device (such as a ball payout device 97) provided in the gaming machine is controlled.

  In the loop processing, it is monitored whether or not the reset signal is in a low level on state (step S935). When the reset signal is turned on, the reset confirmation signal is switched from the off state to the on state (step S936). Then, the payout control CPU 371 enters a system reset state (system reset). That is, the payout control CPU 371 is returned to the operation stop state that is the start state (step S937). In this example, detection for turning on the reset signal so that the payout control CPU 371 is actively stopped when a voltage higher than its drive voltage (for example, 4 V) is still supplied. The voltage level of the voltage is set.

  When the power supply is stopped by the above process, the process of outputting the power-off confirmation signal, the award ball acceptance process during the standby time, and the power supply stop time process of steps S911 to S931 are executed. Data indicating that processing at the time of stoppage (specified value with backup and checksum) is stored in the backup RAM, RAM access is disabled, the output port is cleared, and the payout control processing is executed The timer interrupt is disabled.

  In this embodiment, the entire RAM area of the payout control board 37 is backed up by a backup power source (the contents of the RAM are preserved for a predetermined period even when power supply to the gaming machine is stopped). Accordingly, by the processing in steps S905 to S931, the checksum based on the contents of the RAM when the power-off signal is output is also stored in the RAM together with the value of the backup monitoring timer. When the power supply is restored within a predetermined period after the power supply to the gaming machine is stopped, the payout control means performs the data stored in the RAM (the payout immediately before the power supply is stopped) by the process of step S711 described above. The payout state can be returned to the state immediately before the power supply is stopped according to the data indicating the payout state which is the control state by the control means (for example, including the value of the award ball non-payout number counter). If the power supply stop period exceeds the predetermined period, the value of the backup monitoring timer and the checksum should be different from the regular values. In this case, the initialization process in steps S712 to S714 is executed. The

  As described above, the data for returning the payout control state to the state immediately before the power supply is stopped by the power supply stop process (preparation process for power supply stop) is reliably changed data storage means (this example Then, it is stored in the entire RAM area of the payout control board 37. Therefore, even if the power is cut off due to a power failure or the like, if the power is restored within a predetermined period, the payout control state can be returned to the state immediately before the power supply is stopped. It should be noted that the entire RAM area of the payout control board 37 is not backed up by power, but only the area for storing data for returning the payout control state to the state immediately before the power supply is stopped is backed up by power. May be.

  Further, as described above, when the power-off signal is turned off, the power-off confirmation signal is turned off. Therefore, it is possible to instruct the main board 31 to execute the game state restoration process.

  If the power-off signal is turned off, the process returns to step S701. In this case, since data indicating that the power supply stop process has been executed is set, the payout control state recovery process in step S711 is executed. Therefore, when the detection signal from the power supply monitoring unit is turned off after executing the power supply stop process, the payout control process (at least in response to the command signal related to the prize ball payout from the main board 31) Including a process of driving, and may include a process of driving the ball dispensing device 97 in response to a ball lending request. Therefore, even if a power interruption or the like occurs, the payout control process does not stop, and the payout control process is automatically continued.

  Further, as described above, when the reset signal is turned on, the reset confirmation signal is turned on. Therefore, it is possible to instruct the main board 31 to stop the game control operation.

  FIG. 36A is a timing diagram illustrating an example of output timings of the power-off signal and the power-off confirmation signal. In this example, as shown in FIG. 36 (A), when the power supply voltage decreases and the monitoring voltage (VLP + 24V) decreases to a predetermined voltage (for example, + 17V), the power supply monitoring circuit 920 issues a low-level power-off signal. Output to the substrate 37. Upon receipt of the power-off signal from the power supply monitoring circuit 920, the payout control CPU 371 outputs a low-level power-off confirmation signal to the main board 31 and executes a waiting time thereafter (award ball acceptance processing during the waiting time). When the period of time elapses, the power supply stop process (steps S911 to S931) is executed.

  When the power-off confirmation signal is received from the payout control CPU 371, the CPU 56 executes power supply stop processing (steps S454 to S481).

  Since the waiting time elapses after the CPU 56 starts the power supply stop process, the payout control CPU 371 starts the power supply stop process after the CPU 56 starts the power supply stop process. Therefore, since the prize ball control signal is not output by the CPU 56 after the payout control CPU 371 starts the power supply stop process, it is possible to prevent the prize ball control signal from being missed.

  When the power supply voltage is further reduced and the power supply monitoring circuit 920 completes the power supply stop processing in the payout control CPUs 371 and 56, and the VCC monitored by the power supply monitoring circuit 920 becomes +4.5 V or less, the reset signal is set to the low level. The low-level reset signal is input to the payout control CPU 371 and the CPU, and the operation is stopped.

  FIG. 36B is a timing diagram illustrating an example of output timings of the clear switch signal and the clear signal. In this example, as shown in FIG. 36B, when the power is turned on while the clear switch 921 is pressed by a game clerk or the like, for example, the clear switch signal is turned on immediately after the power supply is started. Next, when the clear switch signal is turned on and the execution timing of the clear switch signal confirmation process (step S708) in the main process (see FIG. 31) comes, the payout control CPU 371 displays the clear switch signal. Is turned on, output of a low-level clear signal to the main board 31 is started (step S712), and initialization processing is executed (steps S713 to S716).

  When the clear signal from the payout control CPU 371 is in the ON state, when the execution timing of the clear signal confirmation process (step S7) in the main process (see FIG. 12) comes, the CPU 56 turns on the clear signal. After confirming that it is in a state, initialization processing is executed (steps S10 to S14).

  The clear signal remains on until a predetermined period (clear signal output extension period) elapses after the clear switch 921 is completely pressed and the clear switch signal is turned off. The clear signal output extension period is set to a period longer than the period (for example, it may be measured by actual measurement) from the execution of the process of step S708 to the execution of the process of step S7.

  Accordingly, a game clerk or the like who operates the clear switch 921 only needs to continue pressing the clear switch 921 at least until the execution timing of the clear switch signal confirmation process (step S708), and the clear signal confirmation process (step S7). It is not necessary to continue the pressing operation until the execution timing of). Even if the clear switch signal is turned off immediately after the execution timing of the clear switch signal confirmation process (step S708), the clear signal remains on until the execution timing of the clear signal confirmation process (step S7). This is because the initialization process is also reliably performed on the main board 31. Thus, the initialization process can be executed by the main board 31 and the payout control board 37 with a simple hardware configuration without requiring the long pressing operation of the clear switch 921.

  Note that in game machines that output operation signals from a conventional clear switch to a plurality of boards, when the lengths of the signal lines for transmitting the operation signals are different, the delay of the signal arrival time is determined by interposing a delay circuit. Although it is conceivable to match, in such a configuration, the delay time is set according to the slowest arrival, so it is necessary to press and hold the clear switch for a long time. End up. In the gaming machine of this example, the above problem is also solved.

  FIG. 37 is a flowchart showing the main control communication process of step S755. In the main control communication process, the payout control CPU 371 executes any one of steps S531 to S532 according to the value of the main control communication control code.

  FIG. 38 is an explanatory diagram showing conditions for inputting the award ball number signal through the input port in the main control communication normal process. As shown in FIG. 38, the main control non-connection error (OFF of the first connection confirmation signal or the second connection confirmation signal) in the 1-byte error flag formed in the RAM, the prize ball REQ signal error (prize ball REQ signal) Is turned on or off at incorrect timing) and the first connection confirmation signal and the second connection confirmation signal are both on when the error bit is not set and the BRDY signal from the card unit 50 is not on. When the prize ball REQ signal is turned on, the payout control means inputs the prize ball number signal via the input port. The error bit is a bit in an error flag that is set when it is detected that various errors have occurred.

  FIG. 39 is a flowchart showing main control communication normal processing (step S531) executed when the value of the main control communication control code is 0. In the main control communication normal processing, when the error bit (main control unconnected error bit or prize ball REQ signal error bit) is on, the payout control CPU 371 ends the processing without executing the subsequent processing. (Step S541). In step S541, if any one of the two bits in the error flag is set, it is determined that the error bit is set.

  If the BRDY signal is on, the payout control CPU 371 ends the process without executing the subsequent processes (step S542). That the BRDY signal is on means that a ball lending request is generated from the card unit 50. That is, when a ball lending request is generated, communication with the game control means of the main board 31 (communication relating to prize ball payout) does not proceed.

  When the conditions of steps S541 to S542 are not satisfied and both the first connection confirmation signal and the second connection confirmation signal are in the on state, the payout control CPU 371 determines whether or not the prize ball REQ signal is in the on state. (Steps S543, S544). The fact that both the first connection confirmation signal and the second connection confirmation signal are in the on state means that power is supplied and the game control means can control the progress of the game. The fact that either the signal or the second connection confirmation signal is in the off state means that the main board 31 and the payout control due to the state where the power supply is stopped and the game control means cannot advance the game, or the signal connection state is defective. This means that the signal cannot be normally transmitted to the substrate 37.

  If the prize ball REQ signal is on, the payout control CPU 371 adds the prize ball number indicated by the prize ball number signal to the content of the prize ball unpaid number counter (step S545) and main control. Processing for setting a prize ball REQ signal off monitoring time (a longest period during which the prize ball REQ signal can be kept on for a predetermined period: for example, “24” here) to the communication control timer is performed ( Step S547). The main control communication control timer is a timer used for monitoring the time related to communication with the game control means of the main board 31. At this stage, the main control communication control timer is a prize for monitoring the timing for turning off the prize ball REQ signal. The sphere REQ signal off monitoring time is set. Then, the value of the main control communication control code is set to 1 (step S548), and the process ends. The prize ball unpaid-out number counter is formed in a non-volatile (power-backed up in this example) RAM area.

  FIG. 40 is a flowchart showing main control communication end processing (step S532) executed when the value of the main control communication control code is 1. In the main control communication process, when the error bit (main control unconnected error bit or prize ball REQ signal error bit) is on, the payout control CPU 371 proceeds to step S567 (step S561). Moreover, also when the 1st connection confirmation signal or the 2nd connection confirmation signal is an OFF state, it transfers to step S567 (step S562). If both error bits are off and the first and second connection confirmation signals are both on, it is confirmed whether or not the prize ball REQ signal is off (step S563). If it is turned off, the process proceeds to step S567.

  If the prize ball REQ signal is not turned off, the value of the main control communication control timer is confirmed (step S564). If the value of the main control communication control timer is not 0, the value of the main control communication control timer is decremented by 1 (step S565). If the value of the main control communication control timer is 0, the prize ball REQ signal error bit is set in the error flag, assuming that the prize ball REQ signal is not turned off within the monitoring time (step S566), and the process goes to step S567. Transition.

  In step S567, the value of the main control communication control code is set to 0, and the process ends.

  FIG. 41 is a flowchart showing the winning ball lending control process in step S756. In the winning ball lending control process, the payout control CPU 371 confirms that the detection signal of the payout number count switch 301 is turned on (step S601). The value is decremented by 1 (steps S602 and S604), and if the ball is not being lent, the value of the unpaid prize ball counter is decremented by 1 (steps S602 and S603). Next, the payout ball detection bit of the payout control state flag formed in the RAM is set (step S605). The payout ball detection bit is a game regardless of whether the payout motor 289 is driven during one award ball payout process (maximum 15 balls) or one ball lending process (25 payouts) in the payout passing waiting process. This is used to detect that no sphere has passed through the payout number counting switch 301. Thereafter, one of steps S610 to S612 is executed according to the value of the payout control code.

  In the winning ball lending control process, when checking the detection signal of the payout number count switch 301 or subtracting the unpaid number counter, the error bit check is not executed. Therefore, even if an error state relating to payout of game balls is detected, every time a payout of game balls is detected by the payout count switch 301, if the payout game balls are loaned balls, a ball rental unpaid number counter 1 is subtracted, and if it is a prize ball, a process of subtracting 1 from the prize ball unpaid number counter value is executed. Therefore, even if an error related to payout occurs, the number of unpaid game balls can be managed accurately.

  FIG. 42 is a flowchart showing the payout start waiting process (step S610) executed when the payout control code is 0. In the payout start waiting process, the payout control CPU 371 does not execute the subsequent processes if the error bit is set (step S621). The error bit in the error flag includes a main control unconnected error bit. The main control non-connection error is set when the connection confirmation signal from the main board 31 is in the off state. Accordingly, the payout control means starts substantial control on condition that the connection confirmation signal is turned on after power supply to the gaming machine is started. The fact that the connection confirmation signal is on means that power is supplied and the game control means can control the progress of the game, so that the payout control of the prize ball according to the progress of the game can be executed. means. On the other hand, the fact that the connection confirmation signal is in the off state means that the power supply is stopped and the game control means cannot advance the game, so that the award ball payout control according to the progress of the game cannot be executed. It means that there is.

  On the other hand, if the BRDY signal is not in the ON state, the process for paying out a prize ball after step S631 is executed. If the BRDY signal is on and the BRQ signal, which is a ball lending request signal, is on, a ball lending operation flag is set (steps S623 and S624). Then, “25” is set in the unpaid ball lending number counter (step S625), and “25” is set in the payout motor rotation number buffer (step S626).

  The payout motor rotation frequency buffer is referred to in the payout motor control process (step S753). That is, in the payout motor control process, control is performed to rotate the payout motor 289 by the number of rotations corresponding to the value set in the payout motor rotation frequency buffer.

  Thereafter, the payout control CPU 371 sets a value (specifically “1”) corresponding to the payout motor activation preparation process (step S522) to the payout motor control code for selecting the process executed in the payout motor control process. It is set (step S627), the value of the payout control code is set to 1 (step S628), and the process is terminated.

  In step S631, the payout control CPU 371 checks whether or not the value of the award ball non-payout counter is 0 (step S631). If 0, the process ends. The award ball unpaid-out number counter has a non-zero value (the number indicated by the award ball number signal) when the prize ball REQ signal is received from the game control means of the main board 31 in step S546 in the main control communication normal process. ) Is added. If the value of the award ball unpaid number counter is not 0, it is confirmed whether it is 15 or more (step S632). If it is less than 15, the value of the award ball unpaid number counter is set in the payout motor rotation count buffer (step S633), and if it is 15 or more, “15” is set in the payout motor rotation count buffer. Then, a winning ball moving flag is set (step S635), and the process proceeds to step S627.

  FIG. 43 is a flowchart showing a payout motor stop waiting process (step S611) executed when the payout control code is 1. In the payout motor stop waiting process, the payout control CPU 371 checks whether or not the payout operation is completed (step S641). For example, the payout control CPU 371 sets a flag to that effect when the payout motor brake process (step S525) in the payout motor control process ends, and whether the payout operation is completed by checking the flag in step S641. You can check whether or not.

  When the payout operation is completed, the payout control CPU 371 sets the payout passing monitoring time in the payout control monitoring timer (step S642). The payout passing monitoring time is a time that has a margin in the time from when the last payout ball is paid out by the payout motor 289 until it passes through the payout number count switch 301. Then, the value of the payout control code is set to 2 (step S643), and the process ends.

  44 to 46 are flowcharts showing the payout passing waiting process (step S612) executed when the value of the payout control code is 2. In the payout passing waiting process, when a prize ball is being paid out, it is determined that the payout has been completed normally if the value of the prize ball unpaid number counter is zero. If the value of the award ball unpaid-out counter is not 0, if it is not in an error state, a re-payout operation of one game ball is tried up to 2 times. In the re-payout operation, when it is detected by the payout number count switch 301 that the game ball is actually paid out, it is determined that the payout has been completed normally. In this embodiment, the maximum number of game balls to be paid out in one prize ball payout operation is 15, and if the prize ball number signal is received during the prize ball payout, the value of the prize ball unpaid number counter is received. Therefore, even when the payout is completed normally, the value of the award ball non-payout number counter may not be 0.

  In addition, when the ball lending is being paid out, it is determined that the payout has been completed normally if the value of the unlending ball lending number counter is 0. If the value of the ball lending unpaid number counter is not 0, and if it is not in an error state, a re-payout operation of one game ball or the remaining number of ball lending (corresponding to the value of the ball lending unpaid number counter) Try. In this embodiment, the number of game balls to be paid out in one ball lending and payout operation is 25 (fixed value), and the payout motor 289 is rotated so that 25 game balls are paid out. Therefore, when the value of the unpaid ball lending counter is not 0, the payout has not been completed normally.

  In the payout waiting process, the payout control CPU 371 first checks the value of the payout control timer, and if the value is 0, the process proceeds to step S653 (step S650). If the value of the payout control timer is not 0, the value of the payout control timer is decremented by 1 (step S651). If the value of the payout control timer is not 0 (step S652), that is, if the payout control timer has not timed out, the process is terminated. Note that the process of step S650 is a process that takes into account when a game ball payout retry operation to be described later is started. When the process of step S807 described later is executed, a retry operation is started through a route that moves from step S650 to S653.

  If the payout control timer has timed out (step S652), it is confirmed whether or not the ball lending payout process (ball lending operation) has been executed (step S653). Whether or not the ball lending operation has been executed is confirmed by whether or not the ball lending operation in-progress flag set in the RAM is set. When the ball lending operation is not executed, that is, when the prize ball payout process (prize ball operation) is executed, the payout control CPU 371 checks the value of the award ball unpaid number counter (step S654). ). When the value of the winning ball unpaid number counter is 0, it is determined that the winning ball payout processing has been completed normally, and the payout ball detection bit in the payout control state flag, 1 bit during re-payout operation, and during re-payout operation 2 bits, the winning ball operating flag and the ball lending operating bit are reset (step S655), the payout control code is set to 0 (step S656), and the processing is terminated. This bit is set when the switch 301 is turned on, and indicates that the payout number counting switch 301 has detected at least one game ball during the payout operation. Further, 1 bit during the re-payout operation and 2 bits during the re-payout operation are control bits used when executing a re-payout process including two re-payout operations.

  The payout control CPU 371 determines that an error flag (specifically, a payout switch error error 1 bit, a payout switch error error 2 bit, and a payout case error bit when the value of the award ball unpaid number counter is not 0. (One or a plurality of bits) is not set (step S658), and if the payout ball detection bit is not set (step S661), the re-payout operation is executed. To do. If the error flag is set, the re-payout operation is not executed.

  As described above, in this embodiment, even when the payout is normally completed, the value of the award ball non-payout number counter may not be 0. Therefore, if the payout ball detection bit is set, that is, if the payout number count switch 301 detects the payout of at least one game ball during the prize ball payout process, it is assumed that the prize ball payout process is normally completed. The process proceeds to step S655. In addition, for example, when 15 game balls should be paid out in one prize ball payout process, when only 14 game balls are actually paid out (the payout number count switch 301 has 14 game balls). In the case where it is detected only), the payout ball detection bit is set, so that it is considered that the award ball payout processing is normally completed. It should not have been done, and the shortage will be paid out in the next prize ball payout process, so there will be no disadvantage to the player.

  In order to execute the re-payout process, the pay-out control CPU 371 first checks whether or not 2 bits during re-payout operation are set (step S662). If not set, it is confirmed whether or not 1 bit is set during the re-payout operation (step S663). If 1 bit is not set during the re-payout operation, 1 is set as the number of re-payout operations to execute the first re-payout operation (step S664), and 1 bit is set during the re-payout operation (step S665). ) The value of the re-payout operation number or ball lending unpaid-out number counter is set in the payout motor rotation number buffer (step S666). The payout motor rotation frequency buffer is referred to in the payout motor control process (step S753). That is, in the payout motor control process, control is performed to rotate the payout motor 289 by the number of rotations corresponding to the value set in the payout motor rotation frequency buffer. In step S666, the value of the unpaid ball lending number counter is also handled because step S666 is also used in the re-payout process in the ball lending payout process. That is, in step S666, the payout control CPU 371 sets the re-payout operation number in the re-payout process in the prize ball payout process, and sets the value of the ball lending unpaid-out number counter in the re-payout process in the ball lending payout process. . Thereafter, the payout control code is set to 1 (step S667), and the process is terminated.

  When it is confirmed in step S663 that 1 bit is being set during the re-payout operation, the payout control CPU 371 sets 1 as the re-payout operation number in order to execute the second re-payout (step S668). Then, 1 bit is reset during the re-payout operation (step S669), and 2 bits are set during the re-payout operation (step S670). Then, control goes to a step S666.

  When it is confirmed in step S662 that 2 bits are set during the re-payout operation, the payout control CPU 371 does not pay out the game ball even if the re-payout process is executed twice (payout number count switch). 301 does not detect a game ball), the payout case error bit in the error flag is set (step S672). At that time, 2 bits during the re-payout operation are reset (step S671). Then, the process ends.

  As described above, if no game balls are paid out even if two re-payout operations are performed in the re-payout process (corrected payout process), the payout number count switch has not been set as a game ball payout operation failure. A passing error bit (payout case error bit) is set.

  Therefore, in this embodiment, the prize game medium payout control means in the payout control means indicates that the prize game medium has not been paid out based on the detection signal from the payout number count switch 301 as the payout detection means. When it is detected, control is performed so that the payout means pays out one prize game medium up to a predetermined number of times (in this example, twice) as a limit. In this embodiment, if the prize game medium is not paid out even if the retry operation for paying out the prize game medium is performed twice, the payout case error bit is set and an error is being generated. (Step S672), the payout case error bit may be set when it is first detected that the premium game medium has not been paid out. The “retry operation (or“ retry ”,“ retry operation processing ”)” means that the actual payout number is the same as the normal payout process for executing the payout of a predetermined number of game balls. This is an operation to be executed when the number is small, and means an operation for executing the payout process again in order to pay out an unpaid game ball separately from the normal payout process.

  In the prize ball lending control process, the error bit is checked to determine whether or not to perform a payout operation (one prize ball payout or one ball lending). The payout start shown in FIG. Only in the waiting process. In the payout motor stop waiting process shown in FIG. 43 and the payout passing wait process shown in FIG. 44 and the like, the error bit is not checked. Note that the error bit is also checked in step S658 and the like in the payout passing waiting process, but this check is for determining whether or not to perform a payout operation again, and is a payout operation (single prize ball payout or 1 This is not to determine whether or not to start ball lending. Therefore, after the process of step S626, S633, or step S634 is performed and the game ball payout process is started, the payout process is not interrupted even if an error occurs. In other words, when an error occurs, the game ball payout process is continued until a point at which the game ball can be cut well (at the time when one prize ball payout or one ball lending ends). The error bits in the error flag checked in step S621 include an error bit indicating that the connection confirmation signal from the main board 31 has been turned off. Therefore, even when the connection confirmation signal is turned off, the game ball payout process is stopped at a time when it is best to turn it off.

  Upon confirming that the ball lending / dispensing process (ball lending operation) has been executed in step S653, the payout control CPU 371 confirms whether or not the value of the unlapped ball lending number counter is 0 (step S657). . If it is 0, it is determined that the ball lending / dispensing process is normally completed, and the process proceeds to step S655.

  If the value of the ball lending unpaid number counter is not 0, an error flag (specifically, any one bit of the payout switch abnormal error 1 bit, the payout switch abnormal error 2 bit, and the payout case error bit) On the condition that (multiple bits) is not set (step S675), the re-payout process is executed. If the error flag is set, the re-payout process is not executed.

  In order to execute the re-payout process, the pay-out control CPU 371 first checks whether or not 2 bits during re-payout operation are set (step S676). If not set, it is confirmed whether or not 1 bit is set during the re-payout operation (step S677). If 1 bit is not set during re-payout operation, 1 is set as the number of re-payout operations to execute the first re-payout operation (step S678), and 1 bit is set during re-payout operation (step S679). ) After further resetting the payout ball detection bit (step S680), the process proceeds to step S666.

  In step S677, when it is confirmed that 1 bit is set during the re-payout operation, the payout control CPU 371 performs a process for re-executing the re-payout operation. Specifically, 1 bit is reset during the re-payout operation (step S681). If the payout ball detection bit is set, that is, if the game ball is paid out in the first re-payout operation, the process proceeds to step S683. If the payout ball detection bit is not set, the process proceeds to step S684 to execute the second re-payout operation.

  In step S683, the payout ball detection bit is reset, and then the process proceeds to step S666. Therefore, in this case, since 1 bit remains set during the re-payout operation, the first (first) re-payout operation is performed again. In step S684, 1 is set as the number of re-payout operations (step S684), 2 bits during re-payout operation are set (step S685), and the process proceeds to step S666.

  In step S676, when it is confirmed that the 2 bits during re-payout operation are set, the payout control CPU 371 resets 2 bits during the re-payout operation (step S686), and if the payout ball detection bit is set, That is, if the game ball is paid out by the re-payout operation, the process proceeds to step S683 to try to eliminate the remaining unpaid out. If the payout ball detection bit is not set, it is determined that the game ball has not been paid out even if the re-payout process is executed twice (the payout number count switch 301 has not detected a game ball). A payout case error bit is set (step S688). Then, the process ends.

  As described above, if one game ball is not paid out even if two re-payout operations are continuously performed in the re-payout process (corrected payout process) related to the ball lending process, a game ball payout operation is performed. As a failure, a payout count switch non-passing error bit (payout case error bit) is set.

  Next, error processing will be described. FIG. 47 is an explanatory diagram showing the relationship between the type of error and the display of the LED 374 for error display. As shown in FIG. 47, when the first connection confirmation signal or the second connection confirmation signal from the main board 31 is turned off, the payout control CPU 371 indicates an error display LED 374 as a main control non-connection error. Control is performed to display “1”. Therefore, in this example, when the first connection confirmation signal or the second connection confirmation signal is turned off, “1” is displayed on the error display LED 374.

  When the disconnection of the payout count switch 301 or a ball clogging occurs at the payout count switch 301, the error display LED 374 is controlled to display “2” as the payout switch abnormality detection error 1. The disconnection of the payout number count switch 301 or the occurrence of ball clogging in the payout number count switch 301 is determined by the detection signal of the payout number count switch 301 not being turned off.

  When the detection signal of the payout number count switch 301 is turned on even though the game ball is not paying out, a control for displaying “3” on the error display LED 374 as a payout switch abnormality detection error 2 is performed. Do. If the detection signal of the payout count switch 301 does not turn on despite the rotation abnormality of the payout motor 289 or the game ball being paid out, “4” is displayed on the error display LED 374 as a payout case error. Control. The specific method for detecting that the detection signal of the payout number count switch 301 is not turned on is as described above. When the prize ball REQ signal is turned on at an improper timing or when the prize ball REQ signal is turned off at an improper timing, “5” is displayed in the error display LED 374 as a prize ball REQ signal error. Control to display. A specific method for detecting that the prize ball REQ signal is turned on or off at an incorrect timing is as described above.

  In addition, when the lower pan is full, that is, when the full switch 48 is turned on, control is performed to display “6” on the error display LED 374 as a full error. When the supply ball is insufficient, that is, when the ball break switch 187 is turned on, control is performed to display “7” on the error display LED 374 as a ball break error.

  Further, when the VL signal from the card unit 50 is turned off, control is performed to display “8” on the error display LED 374 as a prepaid card unit unconnected error. When communication with the card unit 50 is performed at an improper timing, control is performed to display “9” on the error display LED 374 as a prepaid card unit communication error. The prepaid card unit communication error is detected in the prepaid card unit control process (step S754).

  Among the above errors, after the occurrence of a payout switch abnormality detection error 2, a payout case error or a prize ball REQ signal error, the error release switch 375 is operated and an operation signal is output from the error release switch 375 (becomes turned on). The payout control means returns to the state before the error occurred.

  FIG. 48 is a flowchart showing the error processing in step S757. In the error processing, the payout control CPU 371 checks the error flag, and the set bits are only payout switch abnormality detection error 2, payout case error and prize ball REQ signal error (any one of the three). It is confirmed whether it is only a bit, or only two bits out of three, or only these three bits (step S801). If only those bits are set, it is confirmed whether or not the operation signal is turned on from the error release switch 375 (step S802). When the operation signal is turned on, the error recovery time is set in the pre-error recovery timer (step S803). The error recovery time is the time from when the error release switch 375 is operated until the actual return from the error state to the normal state.

  If the operation signal from the error release switch 375 is not on, the value of the timer before error recovery is confirmed (step S804). If the value of the timer before error recovery is 0, that is, if the timer before error recovery is not set, the process proceeds to step S808. If the pre-error recovery timer is set, the value of the pre-error recovery timer is decremented by -1 (step S805). If the pre-error recovery timer value becomes 0 (step S806), the payout switch of the error flag is set. The bits of the abnormality detection error 2, the payout case error and the prize ball REQ signal error are reset (step S807), and the process proceeds to step S808.

  When the processing of step S807 is executed, there may be an error bit that is not set among the bits of the payout switch abnormality detection error 2, the payout case error, and the prize ball REQ signal error. There is no problem resetting error bits that are not in the state. As described above, in this embodiment, when an error (see FIG. 47) that causes the setting of the payout switch abnormality detection error 2, the payout case error, or the winning ball REQ signal error bit occurs, an error occurs. The error is released when the release switch 375 is pressed.

  When the process of step S807 is executed and the payout case error bit is reset, the payout control code is “2” (corresponding to the execution of the payout passing waiting process shown in FIGS. 44 to 46), and the prize ball When the value of the unpaid-out number counter or the value of the ball-lending unpaid-out number counter is not 0, a retry operation for game ball payout is started. That is, when the award ball lending control process of step S756 is executed next, when the payout passing waiting process of step S612 is executed, the repayment process is performed again. For example, if a prize ball payout process has been performed and the value of the prize ball unpaid number counter is not 0, the process proceeds from step S654 to step S659, and it is confirmed in step S659 that the error bit is in a reset state. Therefore, the process for starting the re-payout process after step S662 is executed again, and the re-payout process is executed. Regarding the payout case error bit reset by pressing the error release switch 375, when the bit is set (when step S672 is executed), the payout control timer has already expired. Therefore, when the process in step S807 is executed and the payout case error bit is reset, the payout control timer = 0 is determined in the determination in step S652 when the payout passage waiting process is executed next. Further, when the payout case error bit is set, the payout ball detection bit is 0 (since step S672 is not executed unless the payout ball detection bit is 0 according to the determination in step S661). Therefore, step S662 is always executed whenever it is confirmed in step S659 that the error bit is in the reset state. That is, the re-payout process is always executed.

  As described above, the payout control means is used to pay out a game ball when the payout number count switch 301 detects no game ball even though the ball payout device 97 pays out a game ball. After performing the correct payout control for causing the ball payout device 97 to execute the retry operation for a predetermined number of times (for example, twice) as a limit, the payout number count switch 301 has detected no game balls. When it is detected (see step S661 and after in FIG. 45), the control state related to the payout is shifted to an error state, and corrected payout control is performed again on condition that an error release signal is output from the error release switch 375 in the error state. A correction payout control restart process for executing

  Further, even during re-payout processing in an error state (specifically, during re-payout processing before setting a payout case error and during re-payout processing after the error release switch 375 is pressed), steps S601 to S601 shown in FIG. The process of S604 is being executed. That is, even when an error relating to payout occurs, if the game ball passes the payout number count switch 301, the value of the award ball unpaid number counter or the ball lending unpaid number counter is subtracted. Therefore, the value of the award ball unpaid number counter or the ball lending unpaid number counter when returning from the error state is a value reflecting the number of game balls actually paid out. That is, even if an error related to payout occurs, the number of game balls actually paid out can be accurately managed.

  Also, in the payout passing waiting process shown in FIGS. 44 to 46, even when it is confirmed that the game ball has been paid out as a result of the re-payout process, the payout case error bit is not reset. The bit of the payout case error is reset only when the error release switch 375 is operated (specifically, when an error return time after operation has elapsed) (steps S802 and S807). That is, the state of the payout case error (payout shortage error) is not automatically canceled based on the fact that the game ball has passed the payout number count switch 301, etc. The error is not cleared. Therefore, the game store clerk and the like can surely recognize that a shortage of payout has occurred.

  When the error cancel switch 375 is operated so as to be reset in hardware (reset to the payout control CPU 371), the error cancel switch 375 is operated, for example, a prize ball has not been paid out. The value of the number counter is also cleared. However, in this embodiment, since the payout control means is configured to perform the re-payout operation again by operating the error release switch 375, the payout process is executed reliably, which is disadvantageous to the player. Can not be given.

  In step S808, the payout control CPU 371 checks the detection signal of the full tank switch 48. If the detection signal of the full tank switch 48 is output (if it is in the ON state), the full tank error bit in the error flag is set (step S809). If the detection signal of the full tank switch 48 is in the OFF state, the full tank error bit is reset (step S810).

  Also, the payout control CPU 371 checks the detection signal of the ball break switch 187 (step S811). If the detection signal of the ball break switch 187 is output (if it is on), the ball break error bit in the error flag is set (step S812). If the detection signal of the ball break switch 187 is OFF, the ball break error bit is reset (step S813). When the ball break error bit is set, the bit corresponding to the ball break LED 52 in the output port 1 buffer is set to a value corresponding to the lighting state in the display control process of step S759.

  Further, the payout control CPU 371 confirms the states of the first connection confirmation signal and the second connection confirmation signal from the main board 31 (step S815), and either the first connection confirmation signal or the second connection confirmation signal is detected. If it is not output (if it is off), the main control unconnected error bit is set (step S816). Also, if both the first connection confirmation signal and the second connection confirmation signal are output (if they are in the ON state), the main control unconnected error bit is reset (step S817).

  Further, the payout control CPU 371 checks the value of the switch timer corresponding to the payout number count switch 301 among the switch timers in which the state of the detection signal of each switch is set, and the value is the switch on maximum time (for example, “ 240 ") (step S818), the bit of the payout switch abnormality detection error 1 is set in the error flag (step S819). If the value of the switch timer corresponding to the payout number count switch 301 is less than the switch-on maximum time, the bit of the payout switch abnormality detection error 1 is reset (step S820). Note that the value of each switch timer is incremented by 1 when the state of the input port to which the detection signal of each switch is input is switched on in the input determination process of step S751, and cleared by 0 when it is off. Accordingly, the fact that the value of the switch timer corresponding to the payout number count switch 301 exceeds the switch on maximum time means that the payout number count switch 301 is in the on state exceeding the switch on maximum time. Then, it is determined that the game ball is clogged at the disconnection of the payout number count switch 301 or at the portion of the payout number count switch 301.

  Further, the payout control CPU 371, when the value of the switch timer corresponding to the payout number count switch 301 becomes a switch-on determination value (eg, “2”) (step S821), the ball lending operation flag and the winning ball operation If both the middle flags are in the reset state, the game ball has passed through the payout number count switch 301 even though the payout operation is not in progress, and the bit of the payout switch abnormality detection error 2 in the error flag is set (steps S822 and S823). . If the ball lending operation flag or the winning ball operation flag is set, the bit of the payout switch abnormality detection error 2 is reset (step S824).

  Further, the payout control CPU 371 checks the input state of the VL signal from the card unit 50 (step S825). If the VL signal is not input (if it is in the OFF state), the prepaid card unit not yet out of the error flags is displayed. A connection error bit is set (step S826). If the VL signal is input (if it is on), the prepaid card unit unconnected error bit is reset (step S827).

  In the display control process in step S759, notification by display (numerical value display) corresponding to the error bit in the error flag is performed by the error display LED 374. In this embodiment, the game control means mounted on the main board 31 and the payout control means mounted on the payout control board 37 perform bi-directional communication with respect to prize ball payout, but a communication error is indicated by an error display LED 374. Can be notified.

  Further, since the communication error is detected on the payout control means side, even if the game control means and the payout control means perform bi-directional communication with respect to the prize ball payout, the communication without increasing the burden on the game control means. Can detect errors.

  In this embodiment, the main control unconnected error is automatically cleared when the connection confirmation signal is turned on (see steps S815 and S817), but additionally, a condition that the error release switch 375 is operated is added. Thus, the error state may be eliminated.

  In this embodiment, a communication error is reported so as to be distinguishable from a communication error with the card unit 50 (a prepaid card unit unconnected error and a prepaid card unit communication error) and other errors (see FIG. 47). ). Therefore, a communication error between the game control unit and the payout control unit is easily identified.

  In this embodiment, the error display LED 374 mounted on the payout control board 37 installed on the back side of the gaming machine is informed that an error relating to the payout has occurred. You may mount an alerting | reporting means in other locations (For example, the payout unit in which the ball payout apparatus 97 etc. were concentratedly arranged). Furthermore, you may make it alert | report by the indicator (for example, prize ball LED51) installed in the front side of the gaming machine. In the display control process, the payout control CPU 371 performs control for turning on the prize ball LED 51 when the prize ball REQ signal is on. When the prize ball REQ signal is off, the prize ball LED 51 is displayed. Control for turning off the light is performed. When an error relating to payout occurs, for example, the prize ball LED 51 is blinked to notify that an error related to payout has occurred. If an error is notified by a display device installed on the front side of the gaming machine, the game shop clerk can more easily recognize the occurrence of the error. Moreover, you may use together the alerting | reporting by error display LED374, and the alerting | reporting by the indicator installed in the front side of the gaming machine.

  FIG. 50 is a flowchart showing a portion related to the output of prize ball information (prize ball signal) as a prize ball number signal in the information output process (step S770). The prize ball signal is output from the payout control board 37 to the outside of the gaming machine via the terminal board 160.

  In the information output process, the payout control CPU 371 checks whether or not the value of the signal output timer is 0 (step S831). The signal output timer is a timer for setting an ON period of one pulse prize ball signal. That is, that the value of the signal output timer is not 0 indicates that a prize ball signal is being output. When the value of the signal output timer is not 0, the value of the signal output timer is subtracted (step S841). When the value of the signal output timer becomes 0 (step S842), the prize ball signal is turned off (step S842). Step S843).

  If the value of the signal output timer is 0, it is confirmed whether or not the ball lending operation flag is set (step S832). When the ball lending operation flag is not set, if the payout number count switch 301 is turned on (if the game ball passes), the value of the prize ball payout number counter is incremented by 1 (steps S833 and S834). The prize ball payout number counter is a counter formed in the RAM.

  When the value of the prize ball payout number counter reaches 10 (step S835), the value of the prize ball payout quantity counter is cleared, the prize ball signal is turned on (step S837), and the signal output timer is set to the prize output timer. The on period value of the sphere signal is set (step S838). As a result of the above processing, one prize ball signal is output every time ten game balls as prize balls are paid out. As described above, when the payout control means detects that a predetermined number (10 in this example) of game balls have been paid out based on the detection signal of the payout count switch 301, the payout control means indicates the number. The prize ball signal is output to the outside of the gaming machine. In this embodiment, the predetermined number is 10. However, other numbers may be used as the predetermined number. Further, there may be a plurality of predetermined numbers. For example, when 10 game balls are instructed to be paid out and 10 game balls have been paid out, a first prize ball signal is output, and 15 game balls are instructed from the game control means. The predetermined number is 10 and 15 when the second prize ball signal is output when the game balls are paid out.

  In the information output process, error bit checking is not executed. Accordingly, even in an error state related to payout of game balls, a payout ball signal (prize game medium signal) is output every time ten game balls are detected by the payout number count switch 301 as prize balls. . Therefore, even if an error related to payout occurs, the number of game balls actually paid out can be accurately managed outside the gaming machine. In other words, even if an error related to payout has occurred, the number of prize game media in which payout is actually detected can be tabulated by a management device or the like that can input a prize ball signal, It is possible to detect the payout of game media based on cheating.

  In addition, when the error cancel switch 375 is operated and the hardware is reset (reset to the payout control CPU 371), the payout of the winning ball is performed by operating the error cancel switch 375. The value of the number counter is also cleared. However, in this embodiment, the payout control means is configured such that the error can be released by operating the error release switch 375, and the winning ball payout number counter is not cleared when the error is released. Therefore, the game ball actually paid out is accurately reflected in the prize ball signal. In addition, even in an error state related to payout, the number of game balls actually paid out can be ascertained outside the gaming machine, so that an illegal act that causes an error related to payout and illegally pays out game balls is performed. This is easily detected.

  Also, the prize ball payout number counter is incremented by 1 when the payout number count switch 301 detects a game ball in a state where the ball lending operation flag is not set. Therefore, not only when the winning ball operating flag is set (pending a winning ball), but also when the winning ball operating flag or the lending ball operating flag is not set (both winning or paying a ball) When the payout number count switch 301 detects a game ball, the value is incremented by one. In other words, when the payout number counting switch 301 detects a game ball when it is neither paying out a ball nor lending a ball, it is considered that a game ball has been paid out by paying out a prize ball, and is outside the gaming machine (for example, a hall computer). It is reflected in the output prize ball signal. In this way, the game balls actually paid out are always reflected in the signal output to the outside of the gaming machine, and are therefore always reflected in the total result of the number of payouts at the game store, for example. Note that when the payout number count switch 301 detects a game ball when it is neither paying out a prize ball nor lending a ball, it may be considered that a game ball has been paid out based on a lending ball request.

  As described above, the game control means transmits a prize ball number signal that designates the number of prize balls to be paid out based on a winning, and is designated by the prize ball number signal in response to the transmission of the prize ball number signal. The number of winning balls is subtracted from the total number of winning balls storage buffer, and the payout control means turns on the third connection confirmation signal after starting payout control signal acceptance processing based on the supply of power to the gaming machine. State, the number of unpaid out of the number of prize balls specified by the prize ball number signal is stored in the prize ball unpaid number counter, and the ball is paid out based on the number of unpaid numbers stored in the prize ball unpaid number counter. The device 97 is controlled to pay out a prize ball, and after the game control means becomes able to execute the game control based on the supply of power to the gaming machine, the third connection confirmation signal is turned on. On the condition that it was confirmed that The game control is started after the first and second connection confirmation signals are turned on, and the prize ball number signal, the first and second connection confirmation signals, and the third connection confirmation signal are the same connector (see FIG. 19), the first control signal is transmitted by the signal line connected between the game control means and the payout control means, and the payout control means turns on the third connection confirmation signal and then the first and Since the execution of the payout control is started on the condition that it has been confirmed that the second connection confirmation signal is turned on, the prize game medium can be quickly applied when the payout condition is satisfied. In addition, the management of the number of unpaid game media by the game control means is not affected by the characteristics of the microcomputer used in the game machine at a low cost without securing a large board mounting area. It can be reliably performed in the adult.

  That is, in the embodiment described above, the game control means manages the number of unpaid prize balls without inputting the detection signal from the payout quantity detection switch 301 to the game control means. Signal wiring can be simplified, and it is possible to eliminate the need to secure wiring space. Therefore, the game control means and the payout control means are not paid out at low cost without securing a large board mounting area. The number of prize balls can be managed. Also, since the game control means and the payout control means are configured to adjust the control start timing when the power is turned on by sending and receiving connection confirmation signals to each other, it is possible to prevent the payout control signal from being missed without providing a delay circuit. It is possible to reliably manage the number of unpaid game media in the game control means with a configuration that does not depend on the characteristics of the microcomputer.

  In the above-described embodiment, the game control process is not started in the game control means until the third connection confirmation signal from the payout control means is turned on. It is possible to prevent the payout control signal from being transmitted by the game control means when the signal is not normally transmitted, and to prevent the payout control means from receiving the payout control signal from the game control means. .

  In the embodiment described above, since the execution of the payout control process in the payout control means is not started until after the first and second connection confirmation signals from the game control means are turned on, the connector failure etc. Thus, it is possible to prevent a situation in which the payout control unit malfunctions due to an abnormal command being input.

  Further, as described above, when the payout control means detects an abnormality in the connection state of communication with the game control means (Y in step S815), the payout control means stops payout processing (determined as Y in step S621). Therefore, the payout process is not started), so that the payout process when an abnormality occurs in the connection state between the game control means and the payout control means can be restricted. Note that the payout process being executed may be immediately stopped when an abnormality in the connection state of communication with the game control means is detected.

  In addition, as described above, the payout control unit detects that the first connection confirmation signal or the second connection confirmation signal has been turned off as an abnormality related to communication, and the first connection confirmation signal or the second connection confirmation signal is detected. When the player enters the off state, the configuration is such that the prize ball control signal reception refusal state in which the reception of the prize ball control signal is refused. it can. In addition, the configuration is such that the prize ball control signal is received only when no abnormality relating to communication has occurred (this is a concept including taking in the prize ball number signal). It is possible to prevent the payout control means from erroneously recognizing, and to avoid adversely affecting the player.

  For example, when an abnormality relating to communication has occurred, the number of prize balls indicating 7 prize ball payouts, even though the game control means outputs a prize ball number signal indicating 15 prize ball payouts. If a signal is input, the payout control means may misrecognize. If such a misrecognition is made, the player will be disadvantaged. On the other hand, in the above-described embodiment, the prize ball control signal is received only when there is no abnormality related to communication, so that it is possible to prevent erroneous recognition as described above. It is possible to avoid adversely affecting the player.

  In the above-described embodiment, the payout control means determines that a communication abnormality has occurred when the first connection confirmation signal or the second connection confirmation signal is turned off (N in step S543). The first connection confirmation signal has been configured such that the confirmation of the state of the REQ signal (step S544) and the process of adding the number of prize balls indicated by the prize ball number signal (step S545) are not accepted. Alternatively, when the second connection confirmation signal is turned off, a transition may be made to a standby loop that monitors the input states of the first connection confirmation signal and the second connection confirmation signal. In this case, when it is determined as N in step S543, the process proceeds to a standby loop for monitoring the input states of the first connection confirmation signal and the second connection confirmation signal, and the first connection confirmation signal and the second connection confirmation signal are turned on. When it is confirmed that the state has been reached, the standby loop is exited to release the prize ball control signal non-acceptance state, and the process returns to step S543 to confirm the prize ball REQ signal status (step S544) and the prize ball. The process of adding the number of winning balls indicated by the number signal (step S545) may be resumed. Also in the case of such a configuration, the control state can be automatically restored when the communication abnormality is resolved.

  In the above-described embodiment, the game control means for subtracting the number of unpaid prize balls in response to the transmission of the prize ball control signal communicates that the third connection confirmation signal has been turned off. When the third connection confirmation signal is turned off, the prize ball control signal transmission prohibited state is set to prohibit the transmission of the prize ball control signal. It is possible to quickly pay out the balls, and it is possible to prevent the game control means and the payout control means from recognizing the difference in the number of award balls that have not been paid out. In addition, since the prize ball control signal is transmitted only when there is no abnormality related to communication, the payout control means prevents erroneous recognition of the number of prize balls specified by the prize ball control signal. It is possible to more reliably prevent the recognition of the number of unpaid prize balls between the game control means and the payout control means.

  In the above-described embodiment, the game control means detects that the first connection confirmation signal or the second connection confirmation signal has been turned off as an abnormality related to communication, and the first connection confirmation signal or the second connection confirmation. When the signal is turned off, a prize ball control signal transmission prohibition state prohibiting execution of the prize ball control process (step S202) and the subsequent output process of the contents of the port 0 buffer (step S203) is set. In response to confirming that both the first connection confirmation signal and the second connection confirmation signal are turned on by monitoring the input states of the first connection confirmation signal and the second connection confirmation signal during the control signal transmission prohibited state. Since the configuration is such that the prize ball control signal transmission prohibition state is canceled and the prize ball control processing is resumed, the control state can be automatically restored when the communication abnormality is resolved. That.

  In the embodiment described above, when the connection confirmation signal from the game control means is turned off, the payout control means stops receiving the payout control signal, and the connection confirmation signal from the payout control means is turned off. The game control means is configured to stop the payout control signal transmission process, but when the monitored connection confirmation signal is turned off, the connection confirmation signal output by itself May be turned off. With this configuration, when one of the connection confirmation signals is in an abnormal state, both the payout control signal transmission process and the reception process can be stopped, and the payout control signal such as a prize ball number signal can be set. Can be prevented, and malfunctions in the payout control means due to the input of an abnormal signal can be prevented.

  For example, the payout control means may turn off the third connection confirmation signal in response to the first or second connection confirmation signal from the game control means being turned off. Specifically, when the payout control unit determines Y in step S815, the process of turning off the third connection confirmation signal may be executed. If constituted in this way, for example, when a communication abnormality is detected on the payout control means side and the error control state is shifted, the game control means side can also be shifted to the error state. It is possible to more reliably prevent the recognition of the number of unpaid premium game media with the means.

  In the above-described embodiment, the payout control unit sets the payout control state to the error state (mainly in response to the first or second connection confirmation signal being turned off after the payout control is started. Control unconnected error), and when it is in an error state, it is configured to cancel the error state in response to the first or second connection confirmation signal being turned on. When it is resolved, the control state can be automatically restored.

  In the embodiment described above, when an error state (main control unconnected error) occurs, both the award ball payout control and the ball lending control are stopped, but this is when the error state occurs. However, the ball lending control may be continued. In this case, for example, in the payout start waiting process (see FIG. 42), in step S621, whether or not there is a main control unconnected error is not confirmed, and whether or not a main control unconnected error is confirmed before step S631. If there is an error state, the prize ball control may not be performed. In this way, even if it is in an error state, when it is configured to execute the lending ball payout process based on the establishment of the payout condition by the lending request, the control related to the lending of the game medium that does not involve the game control means is continued. And the game can proceed smoothly.

  In the above-described embodiment, the game control means outputs two connection confirmation signals and the payout control means outputs one connection confirmation signal. However, the game control means and the payout control means output the connection control signals. The number of connection confirmation signals may be one, two, or three or more.

  In this case, as shown in the example shown in FIG. 19 described above, a plurality of pins provided in the connector 69A and the connector 376A each have a prize ball REQ between two pins used for transmitting the connection confirmation signal. It is desirable that each signal is assigned so that five pins used for transmission of the signal and the number-of-award ball number signal are located.

  Specifically, for example, as shown in FIG. 51, the game control means outputs one connection confirmation signal (first connection confirmation signal), and the payout control means outputs two connection confirmation signals (third connection confirmation signal, first connection confirmation signal, 4 connection confirmation signal), a prize ball REQ signal and a prize ball number signal are provided between a pin used for transmission of the third connection confirmation signal and a pin used for transmission of the fourth connection confirmation signal. Each signal may be assigned such that five pins used for transmission of the signal are located.

  For example, as shown in FIG. 52, the game control means outputs one connection confirmation signal (first connection confirmation signal), and the payout control means outputs one connection confirmation signal (third connection confirmation signal). In this case, five pins used for the transmission of the prize ball REQ signal and the prize ball number signal between the pin used for transmission of the first connection confirmation signal and the pin used for transmission of the third connection confirmation signal. Each signal may be assigned so that is located. As described above, even if the configuration is such that the five pins used for transmitting the prize ball REQ signal and the prize ball number signal are sandwiched by the pins used for transmission of two connection confirmation signals having different transmission directions, If an abnormality occurs in the connection confirmation signal, the communication control relating to payout is stopped, so that the pin used for transmitting two connection confirmation signals with the same transmission direction is used for transmitting the prize ball REQ signal and the prize ball number signal. The same effect can be obtained as when five pins are sandwiched.

  Further, in the above-described embodiment, when the communication abnormality detecting means detects an abnormality (detects an off state of the connection confirmation signal to be monitored), this is notified (for example, notification is made by turning on the lamp). Since the communication abnormality notification means (for example, the error display lamp 44) is provided, it is possible to make the game store clerk recognize that the prize ball control signal transmission process is prohibited.

  Further, in the above-described embodiment, when the communication abnormality detecting means detects an abnormality, the communication abnormality notifying means (error notification LED 374) for notifying (for example, displaying “1”: see FIG. 47) is provided. Therefore, it is possible to make the game store clerk recognize that the receiving process of the prize ball control signal is stopped.

  In the above-described embodiment, when the payout control unit confirms the input of the clear switch signal (operation signal) from the clear switch 921, the stored contents held in the RAM that is backed up by the power supply are initialized. When executing the initialization process and outputting a clear signal indicating that the input of the clear switch signal is confirmed to the game control means, and when the payout control means confirms the input of the clear signal from the payout control means, Since the initialization process for initializing the storage contents held in the backup area of the RAM 55 is executed, the function for clearing the information (backup information) held in the backup area of the storage medium (the initialization process is performed) (Function to be executed) can be realized with a simple hardware configuration, and backup information for multiple boards can be assured with simple operations. It can be cleared.

  In the above embodiment, the payout control means determines whether the stored contents of the RAM are valid based on the check data stored in the RAM when the power supply to the gaming machine is restored. Is executed, and when it is determined that the stored contents are not valid, a clear signal is output to the game control means and an initialization process is executed, so that it is stored in the RAM provided in the payout control board 37. If the stored contents are not valid, both the game control means and the payout control means can execute initialization processing, and the RAM 55 provided in the main board 31 as well as the RAM provided in the payout control board 37 can be stored. The contents can be cleared easily.

  In the above embodiment, the payout control means stores the execution confirmation information (the value of the backup monitoring timer indicating that the protection process has been performed) in the RAM when the power supply to the gaming machine is restored. Is executed, and when it is determined that the execution confirmation information is not stored, a clear signal is output to the game control means and an initialization process is executed. Therefore, when the execution confirmation information is not stored in the RAM provided in the payout control board 37, both the game control means and the payout control means can execute the initialization process, and only the RAM provided in the payout control board 37. In addition, the stored contents of the RAM 55 provided in the main board 31 can be easily cleared.

  In the above embodiment, the clear switch 921 is mounted on the power supply board 910 on which the power switch 924 for supplying power to the gaming machine according to the operation is mounted. It is possible to simplify the wiring configuration of signals (clear switch signal, clear signal) output based on the original, and to shorten the wiring of signal lines. For this reason, it is possible to reduce the influence of noise and to reduce the cost. Furthermore, since the clear switch 921 and the power switch 924 are mounted on the same board and the clear switch 921 and the power switch 924 can be arranged close to each other, an operation for executing the initialization process is facilitated.

  In the above embodiment, when the payout control means receives the power-off signal (voltage drop detection signal) from the power supply monitoring means, the power-off confirmation signal (voltage drop detection confirmation signal) is sent to the game control means. The payout control side power supply stop processing (steps S906 to S931) for saving the payout control execution state from the state where the payout control is executed (the state where the payout control process is executed) is executed. When the game control means receives a power-off confirmation signal from the payout control means, the game progress state is saved from the state that controls the progress of the game (the state in which the game control process is executed). The game control side power supply stop process (steps S454 to S481) for executing the process is executed, and the payout control means is executing the payout control side power supply stop process. Even in such a case, since the number of prize balls paid out designated by the prize ball control signal is added to the prize ball unpaid number counter (steps S906 to S910), the backup function is realized with a simple hardware configuration. In addition, it is possible to prevent the disadvantage of the player due to the missing out amount data.

  In the above embodiment, the power-off signal from the power supply monitoring circuit 920 is input only to the payout control board 37. Therefore, a circuit configuration for providing a backup function for the main board 31 and the payout control board 37 as compared with the case where the power cut-off signal from the power supply monitoring circuit 920 is supplied to both the main board 31 and the payout control board 37. Can be simplified and the cost can be reduced.

  In the above embodiment, since the power supply monitoring circuit 920 is mounted on the power supply board 910 separate from the payout control board 37 and the main board 31, the detection signal wiring configuration based on the power supply voltage drop is provided. Since the wiring can be shortened, the influence of noise can be reduced.

  In the above embodiment, the payout control CPU 371 periodically changes the input state of the input port by the payout control side power supply confirmation process (step S901 in the power shutoff process) arranged at a predetermined location in the payout control process. After confirming and executing the payout control side power supply stop process in response to the input of the power cut-off signal from the power supply monitoring circuit 920 to the input port, executing the payout control side power supply stop process, the input port The process of confirming the input state (step S932 in the power-off process) is repeatedly executed, and when the power-off signal input to the input port is released, the process returns to the state of executing the payout control process. Therefore, in the event of a momentary power interruption or the like, if the power supply is restored, the original control state can be automatically restored.

  In the above embodiment, the CPU 56 periodically checks the input state of the input port by the game control side power supply confirmation process (step S450 in the power-off process) arranged at a predetermined location in the game control process. The game control side power supply stop process is executed in response to the power-off confirmation signal from the payout control means being input to the input port, and after the game control side power supply stop process is executed, the input state of the input port Is repeatedly executed (step S482 in the power-off process), and when the power-off confirmation signal input to the input port is canceled, the game control process is returned to the state. When power supply is interrupted, the original control state can be automatically restored if the power supply is restored.

  Further, as described above, when the payout control means receives a power-off signal (voltage drop detection signal) from the power supply monitoring means, it transmits a power-off confirmation signal (voltage drop detection confirmation signal) to the game control means. At the same time, the payout control side power supply stop process (steps S906 to S931) for saving the payout control execution state is executed from the state where the payout control is executed (state where the payout control process is executed). When the game control means receives the power-off confirmation signal from the payout control means, the game progress state is saved from the state in which the game progress is controlled (the state in which the game control process is executed). The game control side power supply stop process (steps S454 to S481) is executed, and the payout control means is executing the payout control side power supply stop process. In addition, since the configuration is such that the number of paid-out prize balls designated by the prize-ball control signal is added to the number-of-paid-out paid counter (steps S906 to S910), the backup function can be realized with a simple hardware configuration. In addition, it is possible to prevent the player from being disadvantaged due to the loss of the payout amount data.

  In the above embodiment, the payout request is made by the prize ball REQ signal and the payout number is specified by the prize ball number signal. However, the payout request and the payout number are designated by the prize ball number signal. May be. In this case, the payout control means may determine that a payout request is made at the same time when the prize ball number signal is output. According to such a configuration, it is not necessary to use the prize ball REQ signal.

  In the above embodiment, the payout control means determines that the prize ball payout has ended when it detects that the payout motor 289 has rotated by the planned payout number. However, the number of times detected by the payout motor position sensor is the expected payout number. If it reaches, it may be determined that the prize ball payout has ended. That is, the payout control means is configured to determine whether or not the payout has been completed by detecting the operation amount of the payout means (in this example, the rotation amount of the payout motor 289 or the number of detections by the payout motor position sensor). May be.

  Further, in the above embodiment, the payout control means confirms that the game ball has been paid out based on the detection signal of the payout count switch 301, but the game ball is based on the output signal of the payout motor position sensor. You may make it confirm that was paid out.

  Also, the payout control means detects the operation amount of the drive means (for example, payout motor 289, cam, etc.) of the payout means, and determines whether or not an abnormality related to payout (payout unit error) has occurred based on the detected amount. It may be configured to. With such a configuration, it is possible to reliably detect an abnormality relating to payout.

  In the above embodiment, the ball payout device 97 is configured to execute both ball lending and prize ball payout. However, even if the mechanism for lending the ball and the mechanism for paying the prize ball are independent, The invention can be applied.

  In the above-described embodiment, the payout is prohibited when the ball is out of the ball or the lower pan is full. However, when it is not preferable to perform another payout or when the payout cannot be performed, You may set it in a payout prohibition state. For example, the payout prohibition state may be set also when the glass door frame 2 is in an open state and a detection signal is output from a door opening switch for detecting this.

  In each of the above-described embodiments, the recording medium used in the recording medium processing apparatus (card unit 50) is a magnetic card (prepaid card). However, the recording medium is not limited to a magnetic card, and is a non-contact type or a contact type. An IC card may be used. In addition, when the recording medium processing device is configured to be able to identify the recording information based on the identification code, the recording medium can be read at least by the recording medium processing device such as an identification code that can identify the recording information It may be something that can be recorded on. Further, the recording medium may be a medium on which a predetermined information recording symbol such as a barcode is printed so as to be readable. The shape of the recording medium is not limited to a card shape, and may be any shape such as a disk shape, a spherical shape, or a chip shape.

  The pachinko gaming machine of each of the above embodiments mainly gives a player a predetermined game value when the stop symbol of the special symbol variably displayed on the variable display unit 9 based on the start winning is a combination of the predetermined symbols. It was a first type pachinko game machine that can be used, but if there is a prize in a predetermined area of an electric game that is released based on a start prize, a second type pachinko game that can give a predetermined game value to a player 3rd type pachinko game where a predetermined right is generated or continued when there is a prize for a predetermined electric game that is released when the stop symbol of the pattern variably displayed based on the machine or the start winning combination becomes a combination of the predetermined pattern The present invention can be applied even to a machine. Furthermore, the present invention is not limited to a pachinko gaming machine in which the game medium is a game ball, and the present invention is also provided in the case where the game medium is a slot machine such as a coin (medal) or the like and is provided with an electrical component for paying out the game medium. Can be applied.

  In the above-described embodiments, different expressions such as transmission / reception and output / input are used for the exchange of various signals, but transmission and output or reception and input are used in substantially the same meaning. It goes without saying that these expressions are interchangeable. In addition, the transmission / reception of signals having many meanings such as control commands is made transmission / reception, and the transmission / reception and output / input are made of transmission / reception of signals for transmitting information by switching on / off. There are also cases where they are used properly. Even in this case, these expressions are interchangeable.

  In the above-described embodiment, the on / off state of the signal may be a high level state / low level state, and conversely, may be a low level state / high level state.

In the embodiment described above, the configurations of the gaming machines (1) to (5) shown below are also shown.
(1) A gaming machine in which the game control means performs transmission control of the payout number signal by the payout number signal transmission means after the game side connection confirmation signal output means turns on the game side connection confirmation signal. With this configuration, it is possible to prevent the payout number signal from being missed.

  (2) The signal transmitted by the signal line connected by the signal line connection means includes a payout number signal, a game side connection confirmation signal, and a payout side connection confirmation signal, and outputs a payout side connection confirmation signal. The means is a gaming machine that maintains the on-state of the payout side connection confirmation signal after the payout control can be executed based on the supply of power to the gaming machine. Since it is configured in this way, the game control means can be immediately started up when the signal connection by the signal line connection means is established.

  (3) The payout control means shifts the payout control state to an error state in response to the game side connection confirmation signal output from the game side connection confirmation signal output means being turned off after the payout control is started. A payout-side error state setting means, and a payout-side error notification means (for example, an error display LED 374) for notifying that when the payout-side error state setting means shifts to an error state. A game-side error state setting means for shifting the control state of the game control to an error state in response to the payout-side connection confirmation signal output from the payout-side connection confirmation signal output means being turned off after starting the game control; And a game-side error notification means (for example, an error display lamp 44) for notifying that when the game-side error state setting means shifts to an error state. . As described above, since the error is notified by the separate notification means on the game control means side and the payout control means side, the cause of the error occurrence can be easily grasped.

  (4) When the game side connection confirmation signal is composed of a first connection confirmation signal and a second connection confirmation signal, and either the first connection confirmation signal or the second connection confirmation signal is in an off state. Means that the game side connection confirmation signal is in an off state, and when both the first connection confirmation signal and the second connection confirmation signal are in an on state, the game side connection confirmation signal is in an on state. The signal line connecting means includes a connector having a plurality of pins for connecting the signal line to the game control means and the payout control means, and the plurality of pins of the connector includes the first connection confirmation Each signal to be transmitted is assigned such that a pin used for transmission of a payout number signal is located between a pin used for signal transmission and a pin used for transmission of the second connection confirmation signal. Gaming machine (see FIG. 19). If comprised in this way, the abnormality regarding communication can be detected correctly, and management of the number of unpaid prize game media in a game control means can be performed more reliably.

  (5) The payout side connection confirmation signal is composed of a third connection confirmation signal and a fourth connection confirmation signal, and when either the third connection confirmation signal or the fourth connection confirmation signal is in an OFF state. Means that the payout side connection confirmation signal is in an off state, and when both the third connection confirmation signal and the fourth connection confirmation signal are in an on state, the payout side connection confirmation signal is in an on state. The signal line connecting means includes a connector having a plurality of pins for connecting the signal line to the game control means and the payout control means, and the plurality of pins of the connector includes the third connection confirmation Each signal to be transmitted is assigned such that a pin used for transmission of a payout number signal is located between a pin used for signal transmission and a pin used for transmission of the fourth connection confirmation signal. Gaming machine (see FIG. 51). If comprised in this way, the abnormality regarding communication can be detected correctly, and management of the number of unpaid prize game media in a game control means can be performed more reliably.

  The present invention is applicable to a game such as a pachinko gaming machine, and in particular, in a gaming machine in which a game control means and a payout control means are provided separately, when a winning occurs, a game medium is quickly given, This is useful for reliably managing the number of unpaid game media in the game control means with a low cost and a configuration that does not depend on the characteristics of the microcomputer without securing a large board mounting area.

It is the front view which looked at the pachinko game machine from the front. It is the rear view which looked at the gaming machine from the back. It is the front view and sectional drawing which show a ball dispensing apparatus. It is a block diagram which shows the circuit structural example of a game control board (main board). It is a block diagram which shows the circuit structural example of a payout control board. It is a block diagram showing a configuration example of an effect control board, a lamp driver board and a sound control board. It is a block diagram which shows the structural example of a power supply board. It is explanatory drawing which shows the example of bit allocation of the output port in a game control means. It is explanatory drawing which shows the example of bit allocation of the output port in a game control means. It is explanatory drawing which shows the bit allocation example of the input port in a game control means. It is a flowchart which shows the main process which CPU in a main board | substrate performs. It is a flowchart which shows the main process which CPU in a main board | substrate performs. FIG. 6 is a timing chart showing how the microcomputer operates when power supply to the gaming machine is started and when power supply is stopped. It is a flowchart which shows a timer interruption process. It is a flowchart which shows a power-off process. It is a flowchart which shows a power-off process. It is explanatory drawing which shows an example of the content of a control signal. It is a block diagram which shows the signal wire | line etc. which are used for transmission / reception of a control signal. It is a block diagram which shows the connection state between the boards of the signal wire | line used for transmission / reception of a control signal. It is a timing diagram which shows an example of how to output a payout control signal. It is a timing diagram which expands and shows a part in FIG. It is a timing chart showing an example of change of the payment permission / prohibition state depending on the output state of the connection confirmation signal. It is a flowchart which shows a prize ball process. It is a flowchart which shows a prize ball control process. It is a flowchart which shows prize ball waiting processing 1. It is a flowchart which shows a prize ball transmission process. It is a flowchart which shows the winning ball waiting process 2. FIG. It is explanatory drawing which shows the bit allocation example of the output port in a payout control means. It is explanatory drawing which shows the example of bit allocation of the input port in a payout control means. It is a timing diagram for demonstrating communication between a prepaid card unit and a game machine. It is a flowchart which shows the main process which CPU for payout control performs. It is a flowchart which shows the timer interruption process which CPU for payout control performs. It is a flowchart which shows the power-off process which CPU for payout control performs. It is a flowchart which shows the power-off process which CPU for payout control performs. It is a flowchart which shows the power-off process which CPU for payout control performs. It is a timing chart showing an example of output timing of a power-off signal and a power-off confirmation signal, and output timing of a clear switch signal and a clear signal. It is a flowchart which shows main control communication processing. It is explanatory drawing which shows the conditions for inputting a prize ball number signal via an input port in main control communication normal processing. It is a flowchart which shows main control communication normal processing. It is a flowchart which shows a main control communication end process. It is a flowchart which shows a prize ball lending control process. It is a flowchart which shows the payout start waiting process. It is a flowchart which shows a payout motor stop waiting process. It is a flowchart which shows payout passage waiting processing. It is a flowchart which shows payout passage waiting processing. It is a flowchart which shows payout passage waiting processing. It is explanatory drawing which shows the relationship between the kind of error, and the display of LED for an error display. It is a flowchart which shows an error process. It is a flowchart which shows an error process. It is a flowchart which shows the part in connection with the output of the prize ball signal of an information output process. It is a block diagram which shows the other example of the connection state between the boards of the signal wire | line used for transmission / reception of a control signal. It is a block diagram which shows the further another example of the connection state between the boards of the signal wire | line used for transmission / reception of a control signal.

Explanation of symbols

1 Pachinko machine 31 Game control board (main board)
37 Dispensing control board 56 CPU
69A, 376A connector (for cable)
69B connector (for main board mounting)
371 CPU for payout control
376B connector (for loading control board)

Claims (9)

A gaming machine in which a player can play a predetermined game using a game medium and pays out a prize game medium as a prize based on the fact that a payout condition is established by the game,
Game control means for executing game control for controlling the progress of the game;
A payout means for paying out the prize game medium;
Payout control means for executing payout control including control of the payout means;
Signal line connecting means for connecting together a plurality of signal lines of signals transmitted between the game control means and the payout control means;
The game control means includes
Game control storage means for storing premium game medium number data capable of specifying the number of premium game media to be paid out based on establishment of the payout condition;
Based on the prize game medium number data, a payout number signal transmitting means for transmitting a payout number signal designating a payout number of a predetermined number of prize game media to the payout control means;
The prize game medium number data for performing a subtraction process for subtracting a value corresponding to the number of payouts designated by the payout number signal from the prize game medium number data in response to the payout number signal transmitting means transmitting the payout number signal. Subtracting means,
The payout control means includes
After starting control signal reception control for receiving a control signal from the game control means based on the supply of power to the gaming machine, the payout side connection confirmation signal is turned on with respect to the game control means. A delivery side connection confirmation signal output means;
The payout control including unpaid number data indicating the number of unpaid premium game media that have not been paid out of the payout number of premium game media specified by the payout number signal transmitted by the payout number signal transmission means Payout control storage means for storing fluctuation data that fluctuates according to
A prize game medium payout control means for executing a payout process for controlling the payout means and paying out a prize game medium based on the unpaid number data stored in the payout control storage means;
The game control means includes
Based on the supply of power to the gaming machine, after the game control can be executed, it has been confirmed that the payout side connection confirmation signal is turned on by the payout side connection confirmation signal output means. On the condition, including a game side connection confirmation signal output means for turning on the game side connection confirmation signal with respect to the payout control means,
After turning on the game side connection confirmation signal by the game side connection confirmation signal output means, start execution of the game control,
The payout number signal, the game side connection confirmation signal, and the payout side connection confirmation signal are transmitted by a signal line connected by the signal line connection means,
The payout control means turns on the payout side connection confirmation signal by the payout side connection confirmation signal output means and then turns the game side connection confirmation signal output means into the game side connection confirmation signal within a predetermined monitoring period. A game machine characterized in that execution of payout control is started on the condition that it has been confirmed that is turned on. Withdrawal control means
A payout-side error state in which the execution state of the payout control is shifted to an error state in response to the game-side connection confirmation signal output from the game-side connection confirmation signal output means being turned off after execution of the payout control is started. Setting means;
The gaming machine according to claim 1, further comprising payout stopping means for stopping execution of the payout processing by the prize game medium payout control means when the payout side error state setting means shifts to an error state. Withdrawal control means
A payout-side error state in which the execution state of the payout control is shifted to an error state in response to the game-side connection confirmation signal output from the game-side connection confirmation signal output means being turned off after execution of the payout control is started. Setting means;
A take-in means for executing a take-in process for taking in the pay-out number signal transmitted by the pay-out number signal transmitting means;
Unpaid number data adding means for adding the number of payouts of the premium game medium designated by the payout number signal fetched by the fetching means to the unpaid number data stored in the payout control storage means;
The gaming machine according to claim 1, further comprising an acquisition stop unit that stops execution of an acquisition process by the acquisition unit when the payout side error state setting unit shifts to an error state. The game control means
A game-side error state that shifts the execution state of the game control to an error state in response to the payout-side connection confirmation signal output means from the payout-side connection confirmation signal output means being turned off after the execution of the game control is started. Setting means;
The transmission stop means for stopping transmission of the payout number signal by the payout number signal transmission means when the game side error state setting means shifts to an error state. The gaming machine described. Withdrawal control means
A payout-side error state in which the execution state of the payout control is shifted to an error state in response to the game-side connection confirmation signal output from the game-side connection confirmation signal output means being turned off after execution of the payout control is started. Including setting means,
The payout-side connection confirmation signal output means turns off the payout-side connection confirmation signal when the payout-side error state setting means shifts to an error state. Gaming machine. A payout detecting means for detecting payout of a prize game medium and outputting a payout detection signal;
Withdrawal control means
A payout-side error state in which the execution state of the payout control is shifted to an error state in response to the game-side connection confirmation signal output from the game-side connection confirmation signal output means being turned off after execution of the payout control is started. Setting means;
An unpaid-out number data subtracting means for subtracting unpaid-out number data stored in the payout control storage means each time the payout detecting means detects a payout of a prize game medium;
The unpaid-out number data subtracting means subtracts the unpaid-out number data every time the payout detecting means detects the payout of the prize game medium even when the payout-side error state setting means has shifted to an error state. The gaming machine according to any one of claims 1 to 5. A payout detecting means for detecting payout of a prize game medium and outputting a payout detection signal;
Withdrawal control means
A payout-side error state in which the execution state of the payout control is shifted to an error state in response to the game-side connection confirmation signal output from the game-side connection confirmation signal output means being turned off after execution of the payout control is started. Setting means;
A prize game medium signal output means for outputting a prize game medium signal to the outside of the gaming machine each time the payout detection means detects a payout of a predetermined number of prize game media;
The prize game medium signal output means outputs the prize game medium signal each time the payout detection means detects the payout of a predetermined number of prize game media, even if the payout error state setting means has shifted to an error state. The game machine according to any one of claims 1 to 6. Withdrawal control means
A payout-side error state in which the execution state of the payout control is shifted to an error state in response to the game-side connection confirmation signal output from the game-side connection confirmation signal output means being turned off after execution of the payout control is started. Setting means;
The error state is canceled when the game side connection confirmation signal output means from the game side connection confirmation signal output means is turned on when the payout side error state setting means has shifted to the error state. The game machine according to any one of claims 1 to 7, further comprising an error state canceling unit. A gaming machine that pays out rental game media based on the establishment of a payment condition according to a loan request,
Withdrawal control means
A payout-side error state in which the execution state of the payout control is shifted to an error state in response to the game-side connection confirmation signal output from the game-side connection confirmation signal output means being turned off after execution of the payout control is started. Setting means;
A rental game medium payout control means for executing a payout process for controlling the payout means and paying out the loaned game medium based on the fact that the payout condition by the loan request is satisfied;
The lending game medium payout control means executes a payout process based on establishment of a payout condition by the lending request even if the payout side error state setting means has shifted to an error state. A gaming machine according to any one of the above.

Images