JP2005260639A - Signal processor and signal processing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem of scaling up a circuit in the configuration which simply comprises a plurality of decoding parts when regenerating the signal which is compression coded at a high speed. <P>SOLUTION: In a variable length decoding process which requires serial processing when the signal processed for variable length coding is speeded up after arithmetic operation, the process is divided into desired process units, and a plurality of process units are simultaneously decoded at a plurality of variable length decoding parts. In an arithmetic operation process for next inverse operation, a process is performed in time series for each process unit. The arithmetic operation part assures process performance here by parallelizing a calculation circuit. Thus, the signal processor for high speed decoding process is provided while scaling up of a circuit is suppressed. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a signal processing method and a signal processing device for decoding an encoded signal.

  For compression encoding of moving images, the MPEG compression encoding method is widely used. In MPEG, variable length encoding is performed after conversion to a frequency space using discrete cosine transform. In recent years, digital television broadcasting of HDTV has progressed, and with the expansion of TV product specifications, the amount of data (processing amount) handled by the MPEG decoder is also increasing. For this reason, in order to reproduce the input signal in real time according to the required specifications, a method for speeding up the decoding process without increasing the operating frequency has been proposed.

  FIG. 18 shows an example of a conventional signal processing apparatus that has been proposed to realize high speed.

  A conventional signal processing apparatus divides an input signal into predetermined units, a preparser unit 901 that outputs a plurality of signals, and a signal output from the preparser unit 901 as an input, and a header recorded at a predetermined position in the input signal Header analysis units 902a and 902b that analyze information, variable length decoding units 903a and 903b that detect matching codes from a plurality of variable length coding tables, and output symbols that match the variable length coding tables as decoded data; The differential data output from each of the arithmetic operation units 904a and 904b and the arithmetic operation units 904a and 904b that perform arithmetic processing on the decoded data output from each of the variable length decoding units 903a and 903b and output difference data Is composed of a frame memory 905 for storing.

  Further, as shown in FIG. 19, each of the arithmetic operation units 904 a and 904 b includes a frequency conversion unit 9040 that performs reverse conversion (inverse frequency conversion) for restoring the frequency conversion performed in the process of encoding the input signal. The input signal includes a motion compensation unit 9041 that reproduces motion prediction (performs motion compensation) performed in the process of encoding.

  As described above, the conventional signal processing apparatus has a configuration having a plurality of decoding processing systems having the same function in order to divide an input signal into slice units and simultaneously perform decoding processing in slice units. Thus, by having a plurality of decoding processing systems, the input signal can be decoded at high speed.

For example, consider a case where two MP @ HL streams are decoded by a decoder capable of decoding one MP @ HL (1920 × 1080) per frame time. At this time, the processing performance required for the decoder is to decode two frames in one frame decoding time. When a conventional decoder is used, if two slice decoders are provided in parallel, a double speed performance can be ensured, and two frames can be decoded in one frame decoding time.
JP 10-178644 A

  However, if a double-speed signal processing apparatus is studied using such a method, the circuit scale is doubled. Further, considering the triple speed, the circuit scale is tripled. That is, the performance is improved and the circuit scale is also increased.

  Further, when such a method is not used and only one decoding processing system is provided, the operating frequency of the entire apparatus must be increased in order to obtain double speed and triple speed performance.

  In view of the above, the present invention proposes a signal processing device that suppresses an increase in circuit scale and performs decoding processing of an input signal at high speed.

  According to one aspect of the present invention, the signal processing device processes a signal encoded by a predetermined standard. The encoded signal includes a plurality of block data and a header. The header stores block information regarding the block data. The signal processing apparatus includes a header information acquisition unit, a preparser unit, a plurality of variable length decoding units, and an arithmetic operation unit. The header information acquisition unit acquires block information stored in the header from the encoded signal. The preparser unit associates one of the plurality of variable length decoding units with each of the plurality of block data with reference to the block information acquired by the header information acquisition unit. Each of the plurality of variable length decoding units generates decoded data by performing variable length decoding on the block data associated by the preparser unit. The arithmetic operation unit selects a plurality of variable length decoding units one by one in order, and generates reproduction data by performing an inverse arithmetic operation on the decoded data generated by the selected variable length decoding unit.

  In the signal processing apparatus, since the decoded signal in units of blocks is processed in parallel by the plurality of variable length decoding units, the encoded signal can be decoded at high speed. Further, when the operation speed of the arithmetic operation unit is increased, it is possible to perform an arithmetic operation on the decoded data generated by each of the plurality of variable length decoding units at high speed. Therefore, even if there is only one arithmetic operation unit, high-speed processing performance can be obtained by increasing only the operation speed of the arithmetic operation unit. In this way, it is possible to suppress an increase in circuit scale due to parallelization of the decoding processing system, and to obtain high-speed processing performance by increasing only the operating frequency of the arithmetic operation unit without increasing the operating frequency of the entire apparatus. Can do.

  Preferably, each of the plurality of block data is added with a termination code indicating the termination of the block data. The pre-parser unit includes a termination code detection unit, a block control unit, and a selection unit. The termination code detector detects a termination code from the block data. The block control unit associates one of the plurality of variable length decoding units with each of the plurality of blocks based on the block information acquired by the header information acquisition unit. When the termination code is detected by the termination code detection unit, the selection unit converts the block code in which the termination code is detected according to the association between the plurality of blocks and the plurality of variable length decoding units by the block control unit. Any one of the plurality of variable length decoding units is associated.

  In the signal processing device, each time a terminal code is detected, a variable-length code unit is associated with the block data to which the terminal code is added. In this way, block data can be associated with each of the plurality of variable length decoding units.

  Preferably, the arithmetic operation unit includes a frequency conversion unit and a motion compensation unit. The frequency transform unit selects the plurality of variable length decoding units one by one in order, and generates spatial data by performing inverse orthogonal transform on the decoded data generated by the selected variable length decoding unit. The motion compensation unit generates reproduction data by performing motion compensation on the spatial data generated by the frequency conversion unit.

  In the above signal processing apparatus, the frequency calculation unit simply calculates the input data, and therefore it is relatively easy to increase the operation speed. Further, since only one frame memory can be accessed, even if there is only one motion compensation unit, the same performance as when there are a plurality of motion compensation units can be obtained. As described above, even if there is only one frequency conversion unit and motion compensation unit, it is possible to suppress an increase in circuit scale due to parallelization of the decoding processing system, and an arithmetic operation unit without increasing the operating frequency of the entire apparatus. If only the operating frequency is increased, high-speed processing performance can be obtained.

  Preferably, the operation speed of the arithmetic operation unit is faster than the operation speed of the variable length decoding unit.

  Preferably, the signal encoded according to the predetermined standard is an MPEG stream.

  According to another aspect of the present invention, a signal processing method processes a signal encoded according to a predetermined standard. The encoded signal includes a plurality of block data and a header. The header stores block information regarding the block data. The signal processing method includes a header information acquisition step, a preparser step, a plurality of variable length decoding steps, and an arithmetic operation step. The header information acquisition step acquires block information stored in the header from the encoded signal. The preparser step associates any one of the plurality of variable length decoding steps with each of the plurality of block data with reference to the block information acquired by the header information acquisition step. Each of the plurality of variable length decoding steps generates decoded data by performing variable length decoding on the block data associated by the preparser step. In the arithmetic operation step, a plurality of variable length decoding steps are selected one by one in order, and reproduction data is generated by performing an inverse arithmetic operation on the decoded data generated by the selected variable length decoding step.

  In the above signal processing method, since the decoded signal in units of blocks is processed in parallel by a plurality of variable length decoding steps, the encoded signal can be decoded at high speed. Further, when the operation speed of the arithmetic operation step is increased, the arithmetic operation on the decoded data generated by each of the plurality of variable length decoding steps can be performed at high speed. Therefore, even if there is only one arithmetic operation step, high processing performance can be obtained by increasing only the operation speed of the arithmetic operation step. In this way, it is possible to suppress the increase in circuit scale due to parallelization of the decoding processing system, and to obtain high-speed processing performance by increasing only the operating frequency of the arithmetic operation step without increasing the operating frequency of the entire method. Can do.

  Preferably, each of the plurality of block data is added with a termination code indicating the termination of the block data. The preparser step includes a termination code detection step, a block control step, and a selection step. In the termination code detection step, a termination code is detected from the block data. The block control step associates any one of the plurality of variable length decoding steps with each of the plurality of blocks based on the block information acquired by the header information acquisition step. In the selection step, when the termination code is detected by the termination code detection step, the block data in which the termination code is detected is determined according to the association between the plurality of blocks and the plurality of variable length decoding steps in the block control step. Any one of the plurality of variable length decoding steps is associated.

  In the signal processing method, each time a terminal code is detected, a variable length code step is associated with the block data to which the terminal code is added. In this way, block data can be associated with each of a plurality of variable length decoding steps.

  Preferably, the arithmetic operation step includes a frequency conversion step and a motion compensation step. In the frequency transform step, the plurality of variable length decoding steps are selected one by one in order, and spatial data is generated by performing inverse orthogonal transform on the decoded data generated by the selected variable length decoding step. In the motion compensation step, reproduction data is generated by performing motion compensation on the spatial data generated in the frequency conversion step.

  In the signal processing method described above, the frequency calculation step simply calculates the input data, and therefore it is relatively easy to increase the operation speed. Further, since only one frame memory can be accessed, even if there is only one motion compensation step, the same performance as when there are a plurality of motion compensation steps can be obtained. Thus, even if there is only one frequency conversion step and motion compensation step, it is possible to suppress an increase in circuit scale accompanying parallelization of the decoding processing system, and to perform an arithmetic operation step without increasing the operating frequency of the entire method. If only the operating frequency is increased, high-speed processing performance can be obtained.

  Preferably, the operation speed of the arithmetic operation step is faster than the operation speed of the variable length decoding step.

  Preferably, the signal encoded according to the predetermined standard is an MPEG stream.

  As described above, since the decoded signal in block units is processed in parallel by the plurality of variable length decoding units, the encoded signal can be decoded at high speed. Further, when the operation speed of the arithmetic operation unit is increased, it is possible to perform an arithmetic operation on the decoded data generated by each of the plurality of variable length decoding units at high speed. Therefore, even if there is only one arithmetic operation unit, high-speed processing performance can be obtained by increasing only the operation speed of the arithmetic operation unit. In this way, it is possible to suppress an increase in circuit scale due to parallelization of the decoding processing system, and to obtain high-speed processing performance by increasing only the operating frequency of the arithmetic operation unit without increasing the operating frequency of the entire apparatus. Can do.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.

(First embodiment)
<overall structure>
FIG. 1 shows the overall configuration of the signal processing apparatus according to the first embodiment of the present invention. This apparatus includes a header analysis unit 101, a preparser unit 102, variable length decoding units 103a and 103b, an arithmetic operation unit 104, and a frame memory 105. The header analysis unit 101 obtains information SignalA used for motion compensation, information SignalB related to blocks, and information SignalC related to inverse discrete cosine transform by analyzing header information recorded at a predetermined position in the input signal. The preparser unit 102 refers to the information SignalB from the header information analysis unit 101 and outputs the input signal from the header information analysis unit 101 to the variable length decoding units 103a and 103b for each predetermined unit. Each of the variable length decoding units 103a and 103b detects a code that matches the input signal output from the preparser unit 102 from a plurality of variable length coding tables, and decodes the symbols that match the variable length coding table respectively. D103A and D103B are output (variable length decoding is performed). The arithmetic operation unit 104 refers to the information SignalA and SignalC from the header information analysis unit 101 and time-divisions the decoded data D103A output from the variable length decoding unit 103a and the decoded data D103B output from the variable length decoding unit 103b. The difference data is generated by arithmetic processing. The frame memory 105 stores the difference data generated by the arithmetic operation unit 104.

<input signal>
Here, the input signal will be described with reference to FIGS. 3 and 4. The input signal is an MPEG2 compressed bit stream and has a hierarchical structure including a sequence, a GOP, a picture, a slice, a macro block, and a block as shown in FIG. Here, only the blocks and macroblocks necessary for the description of the present embodiment will be described.

《Macro block》
A macroblock is a processing unit for motion prediction and has a data size of 16 × 16 pixels. The macro block includes four blocks (luminance blocks Y0, Y1, Y2, Y3) indicating luminance data of the macro block, two blocks (color difference blocks Cb, Cr) indicating color difference data of the macro block, and a macro block. Header. The luminance blocks Y0, Y1, Y2, Y3 and the color difference blocks Cb, Cr are recorded in the stream in the order of Y0, Y1, Y2, Y3, Cb, Cr. Information defined for each macroblock, such as a CBP (Coded Block Pattern), a quantization step value, and a motion vector, is recorded in the macroblock header. CBP is information indicating that there is no valid data in a specific block among blocks included in the macroblock. The motion vector is macroblock motion information acquired when motion prediction is performed, and is information used for motion compensation.

"block"
As shown in FIG. 4, the lowest layer block includes luminance blocks Y0, Y1, Y2, and Y3 indicating luminance components of 8 × 8 pixel sections in the macroblock (16 × 16 pixel section), and macroblocks. There are color difference blocks Cb and Cr indicating color difference components of (16 × 16 pixel section). These blocks are run-length encoded after being subjected to DCT processing. Also, an EOB (end of block) code is added to the end of each block.

<Internal configuration of pre-parser>
FIG. 5 shows an internal configuration of the preserver unit shown in FIG. The preparser unit 102 includes an EOB search unit 1020, a block information output unit 1023, a block control unit 1022, and a switch 1021. The EOB search unit 1020 and the block control unit 1022 operate while communicating using an EOB signal. Further, the block information output unit 1023 and the block control unit 1022 operate while communicating by a GET_DATA signal. The EOB search unit 1020 receives the run-length encoded block data after the macroblock header output from the header information analysis unit 101, and detects an EOB code indicating the end of the block, and sends an EOB signal to the block control unit 1022. Output. When the EOB signal is input from the EOB search unit, the block control unit 1022 outputs a GET_DATA signal to the block information output unit 1023. The block information output unit 1023 generates block selection information indicating one of the variable length decoding units 103a and 103b based on the CBP included in the macroblock header processed by the header analysis unit 101. The block information output unit 1023 outputs block selection information when a GET_DATA signal is input by the block control unit 1022. Further, the block control unit 1022 inputs the block data output from the EOB search unit to either the variable length decoding unit 103a or the variable length decoding unit 103b based on the block selection information output from the block information output unit 1023. Therefore, the switch 1021 is switched.

<Internal configuration of arithmetic unit>
FIG. 2 shows an internal configuration of the arithmetic operation unit 104 shown in FIG. The arithmetic operation unit 104 includes block buffers 10A, 11A, 10B, and 11B, a frequency conversion unit 1040, macroblock buffers 12MA and 12MB, and a motion compensation unit 1041. Each of the block buffers 10A and 11A has a data size of one block, and stores the decoded data D103A output from the variable length decoding unit 103a. Each of the block buffers 10B and 11B has a data size for one block, and stores the decoded data D103B output from the variable length decoding unit 103b. The frequency conversion unit 1040 performs inverse discrete cosine transform on the decoded data D103A and D103B stored in each of the block buffers 10A, 11A, 10B, and 11B using the information SignalC acquired by the header information analysis unit 101. To generate differential data. Each of the macroblock buffers 12MA and 12MB has a data size corresponding to two macroblocks, and stores differential data generated by the frequency conversion unit 1040. The motion compensation unit 1041 performs motion prediction on the difference data stored in each of the macroblock buffers 12MA and 12MB, using prediction data from the frame memory, and generates reproduction data.

  In the present embodiment, the frequency conversion unit 1040 and the motion compensation unit 1041 are assumed to have a processing performance that is twice the processing speed of the variable length decoding units 103a and 103b.

<Operation>
Next, the operation of the signal processing apparatus shown in FIG. 1 will be described with reference to FIG.

[Step ST101]
The header information analysis unit 101 inputs an MPEG2 compressed bit stream (a signal including a macroblock header and block data) in order from the top.

[Step ST102]
Next, the header information analysis unit 101 determines whether or not the input data is a macroblock header. If it is a macroblock header, the process proceeds to step ST103. Otherwise, the process proceeds to step ST104.

[Step ST103]
Next, the header information analysis unit 101 analyzes the input macroblock header, and acquires information SignalA used for motion compensation stored in the macroblock header, information SignalB regarding the block, and information SignalC regarding the inverse discrete cosine transform. . For example, the information SignalA is a motion vector and a coding mode, the information SignalB is a CBP, and the information SignalC is a quantization step value. The header information analysis unit 101 outputs information SignalA and SignalC to the arithmetic operation unit 104 and outputs information SignalB to the preparser unit 102. Next, the process proceeds to step ST101.

[Step ST104]
On the other hand, when it is determined in step ST102 that the input data is not a macroblock header (when it is determined that the data is block data), the header information analysis unit 101 outputs an input signal (block data) to the preparser unit 102.

[Step ST105]
Next, the preparser unit 102 refers to the information SignalB output from the header information analysis unit 101, selects one of the variable length decoding units 103a and 103b, and outputs the block data output from the header information analysis unit 101 Is output to the selected variable-length decoding unit.

[Step ST106]
Next, the variable length decoding unit 103a generates decoded data D103A by performing variable length decoding on the block data output from the preparser unit 102. On the other hand, the variable length decoding unit 103b generates decoded data D103B by variable length decoding the block data output from the preparser unit 102.

[Step ST107]
Next, the variable length decoding unit 103a stores the generated decoded data D103A in one of the block buffers 10A and 11A of the arithmetic operation unit 104. At this time, the variable length decoding unit 103a stores the data in the order of the block buffers 10A, 11A. On the other hand, the variable length decoding unit 103b stores the generated decoded data D103B in one of the block buffers 10B and 11B of the arithmetic operation unit 104. At this time, the variable length decoding unit 103b stores the data in the order of the block buffers 10B, 11B.

[Step ST108]
Next, the frequency conversion unit 1040 of the arithmetic operation unit 104 selects any one of the block buffers 10A, 11A, B, and 11B and decodes data (decoded data D103A or B103) stored in the selected block buffer. The difference data is generated by performing the inverse discrete cosine transform on. At this time, the frequency conversion unit 1040 processes the data in the order of the block buffers 10A, 10B, 11A, 11B, 10A, 10B.

[Step ST109]
Next, the frequency conversion unit 1040 stores the generated difference data in one of the macroblock buffers 12MA and 12MB. At this time, the frequency conversion unit 1040 stores the macroblock buffers 12MA, 12MB, 12MA, 12MB.

[Step ST110]
Next, the motion compensation unit 1041 determines whether or not difference data for one macroblock is stored in at least one of the macroblock buffers 12MA and 12MB. If it is determined that the difference data for one macroblock is stored, the process proceeds to step ST111.

[Step ST111]
Next, the motion compensation unit 1041 selects one of the macroblock buffers 12MA and 12MB, and selects the difference data stored in the selected buffer from the image data stored in the frame memory 105. Motion compensation is performed using the acquired prediction data. At this time, the motion compensation unit 1041 performs processing in the order of the macroblock buffers 12MA, 12MB, 12MA, 12MB. Next, the motion compensation unit 1041 stores the reproduction data generated by the motion compensation in the frame memory 105.

[Step ST112]
Next, when data to be processed remains, the process proceeds to step ST101. If not, the process ends.

<Operation of the pre-parser unit>
Next, the operation (step ST104) by the preparser unit 102 will be described in detail with reference to FIG.

[Step ST201]
First, the EOB search unit 1020 sequentially stores the input signals output from the header information analysis unit 101 until an EOB code is detected from the input signals output from the header information analysis unit 101.

[Step ST202]
On the other hand, the block information output unit 1023 refers to the information SignalB (CBP) output from the header information analysis unit 101, and generates block selection information indicating one of the variable length decoding units 103a and 103b.

[Step ST203]
Next, when an EOB code is detected by the EOB search unit, the block control unit 1022 acquires block selection information from the block information output unit 1023.

[Step ST204]
Next, the block control unit 1022 instructs the switch 1021 which of the variable length decoding units 103a and 103b is selected according to the block selection information acquired from the block information output unit 1023.

[Step ST205]
Next, the switch 1021 selects one of the variable length decoding units 103a and 103b in accordance with an instruction from the block control unit 1022, and selects the block data stored in the EOB search unit 1020. Output to.

<< Operation by EOB Search Unit 1020 >>
Next, the operation (step ST201) by the EOB search unit 1020 will be described in detail with reference to FIG.

[Step ST301]
First, the EOB search unit 1020 determines whether an EOB signal is output from itself to the block control unit. When the output value of the EOB signal becomes “0”, the process proceeds to step ST302.

[Step ST302]
Next, the EOB search unit 1020 stores the input signal (block data) output from the header information analysis unit.

[Step ST303]
Next, when the EOB search unit 1020 detects an EOB code included in the block data, the EOB search unit 1020 sets the output value of the EOB signal to the block control unit 1022 to “1”. Next, the process proceeds to step ST301.

<Operation by block information output unit>
Next, the operation (step ST202) by the block information output unit 1023 will be described in detail with reference to FIG.

[Step ST401]
The block information output unit 1023 receives the information SignalB (CBP) output from the header information analysis unit 101.

[Step ST402]
Next, the block information output unit 1023 calculates the total number K of block data including valid data among the block data included in the macroblock with reference to the input information SignalB (CBP).

[Step ST403]
Next, the block information output unit 1023 sets the block ID to “0” in order to generate block selection information. The block ID is a number indicating the number of the block from the top in one macroblock. For example, if the block ID is “2”, the block ID indicates the second block from the top.

[Step ST404]
Next, the block information output unit 1023 refers to the input CBP and determines whether or not the block data indicated by the block ID includes valid data. For example, assume that the CBP indicates that the second block from the beginning does not contain valid data. At this time, if the block ID is “2”, the block information output unit 1023 determines that the block data corresponding to the block ID does not include valid data. If the block data indicated by the block ID includes valid data, the process proceeds to step ST405. Otherwise, the process proceeds to step ST411.

[Step ST405]
Next, the block information output unit 1023 determines whether or not the block ID is an even number. If it is an even number, the process proceeds to step ST406. If it is an odd number, the process proceeds to step ST413.

[Step ST406]
Next, the block information output unit 1023 generates block selection information (SW1) indicating the variable length decoding unit 103a.

[Step ST407]
Next, the block information output unit 1023 determines whether or not the output value of the GET_DATA signal output from the block control unit 1022 is “1”. When the output value of the GET_DATA signal becomes “1”, the process proceeds to step ST408.

[Step ST408]
Next, the block information output unit 1023 writes the generated block selection information in the block control unit 1022.

[Step ST409]
Next, the block information output unit 1023 determines whether or not the writing of the block selection information to the block control unit 1022 has been completed. When the writing of the block selection information is completed, the process proceeds to step ST410. Otherwise, the process proceeds to step ST408.

[Step ST410]
Next, the block information output unit 1023 sets the output value of the GET_DATA signal output from the block control unit 1022 to “0”.

[Step ST411]
Next, the block information output unit 1023 adds 1 to the block ID. The block information output unit 1023 subtracts 1 from the total number K of effective blocks.

[Step ST412]
Next, the block information output unit 1023 determines whether or not the total number K of valid blocks is “0”. If it is determined that the total number K of valid blocks is “0”, the process proceeds to step 401. Otherwise, the process proceeds to step ST404.

[Step ST413]
On the other hand, when it is determined in step ST405 that the block ID is an odd number, the block information output unit 1023 generates block selection information (SW2) indicating the variable length decoding unit 103b. Next, the process proceeds to step ST407.

<Operation by block control unit>
Next, the operation (steps ST203 and ST204) by the block control unit 1022 will be described in detail with reference to FIG.

[Step 501]
First, the block control unit 1022 determines whether or not the output value of the EOB signal output from the EOB search unit 1020 is “1”. When the output value of the EOB signal becomes “1”, the process proceeds to step ST502.

[Step ST502]
Next, the block control unit 1022 sets the output value of the GET_DATA signal output to the block information output unit 1023 to “1”. When the output value of the GET_DATA signal becomes “1”, the block selection information generated by the block information output unit 1023 is written into the block control unit 1022.

[Step ST503]
Next, the block control unit 1022 determines whether or not the output value of the GET_DATA signal that it outputs to the block information output unit 1023 is “0”. When the output value of the GET_DATA signal becomes “0”, the process proceeds to step ST504.

[Step ST504]
Next, the block control unit 1022 reads the block selection information written by the block information output unit 1023.

[Step ST505]
Next, the block control unit 1022 determines whether or not the read block selection information indicates “SW1”. When the read block selection information indicates “SW1”, the process proceeds to step ST506. When the read block selection information indicates “SW2”, the process proceeds to step ST508.

[Step ST506]
Next, the block control unit 1022 instructs the switch 1021 to select the variable length decoding unit 103a.

[Step ST507]
Next, the block control unit 1022 sets the output value of the EOB signal output from the EOB search unit 1020 to “0”. Next, the process proceeds to step ST501.

[Step ST508]
On the other hand, when the block selection information read in step ST504 indicates “odd number”, the block control section 1022 instructs the switch 1021 to select the variable length decoding section 103b. Next, the process proceeds to step ST507.

<data flow>
FIG. 11 shows a data flow in the arithmetic operation unit 104.

  First, block data Y0, Y2, and Cb having an even block ID among block data included in one macroblock data are output from the variable length decoding unit 103a in order from the top. On the other hand, among the block data included in one macroblock data, block data Y1, Y3, and Cr having an odd block ID are output from the variable length decoding unit 103b in order from the top.

  Here, when the output of the block data from the variable length decoding unit 103a to the block buffer 10A is completed, the frequency calculation unit 1040 performs a difference by performing inverse discrete cosine transform on the block data Y0 stored in the block buffer 10A. Data Y0 is generated, and the generated difference data Y0 is output to the macroblock buffer 12MA. In parallel with this, the block buffer 10B stores the block data Y1 from the variable length decoding unit 103b.

  Next, when the inverse discrete cosine transform for the block data Y0 is completed, the frequency transform unit 1040 performs inverse discrete cosine transform on the block data Y1 stored in the block buffer 10B.

  In this way, the frequency conversion unit 1040 performs inverse discrete cosine transform in the order of the block data Y0, Y1, Y2, Y3, Cb, and Cr.

  When the luminance data (difference data Y0, Y1, Y2, Y3) for one macroblock is stored in the macroblock buffer 12MA, the motion compensation unit 1041 stores one macroblock stored in the macroblock buffer 12MA. Motion compensation is performed on the luminance data. When the color difference data (difference data Cb, Cr) for one macroblock is stored in the macroblock buffer 12MA, the motion compensation unit 1041 stores the color difference data for one macroblock stored in the macroblock buffer 12MA. Motion compensation for

  In this way, the motion compensation unit 1041 performs motion compensation on the luminance data and color difference data for one macroblock data.

  As shown in FIG. 2, since the frequency conversion unit 1040 has block buffers 10A, 11A, 10B, and 11B between the variable length decoding units 103a and 103b, due to the processing delay of the frequency conversion unit 1040, The variable length decoding units 103a and 103b are not delayed.

  In addition, since the frequency conversion unit 1040 includes the macroblock buffers 12MA and 12MB between the motion compensation unit 1041 and the frequency conversion unit 1040, the frequency conversion unit 1040 is not affected by the processing delay of the motion compensation unit 1041.

<effect>
As described above, the signal processing apparatus according to the present embodiment processes the decoded signal in block units in parallel by the plurality of variable length decoding units, so that the encoded signal can be decoded at high speed. In addition, by using one frequency calculation unit and one motion compensation unit and increasing their operating frequencies, it is possible to perform arithmetic operations on the decoded data generated by each of the plurality of variable length decoding units at high speed. Here, since the frequency calculation unit simply calculates the input data, it is relatively easy to raise the operating frequency. In addition, even if there are a plurality of motion compensation units, only one frame memory can be accessed, so even if there is only one motion compensation unit, the same performance as when there are a plurality of motion compensation units can be obtained. it can. In this way, it is possible to suppress an increase in circuit scale due to parallelization of the decoding processing system, and to obtain high-speed processing performance by increasing only the operating frequency of the arithmetic operation unit without increasing the operating frequency of the entire apparatus. Can do.

  In addition, although the frequency converter 1040 of the present embodiment is illustrated with one configuration, it may be configured with two.

  In the present embodiment, an example in which an MPEG2 compressed video signal is input as an input signal is shown, but the present invention is not limited to this. The same effect can be obtained if the arithmetic operation is performed and the variable-length encoding process is performed.

(Second Embodiment)
<overall structure>
FIG. 12 shows the overall configuration of a signal processing apparatus according to the second embodiment of the present invention. This apparatus includes a preparser unit 201, header information analysis units 202a and 202b, and an arithmetic operation unit 204 instead of the header information analysis unit 101 shown in FIG. Other configurations are the same as those in FIG. The preparser unit 201 divides an input signal into predetermined units and outputs a plurality of signals. Each of the header analysis units 202a and 202b receives the input signal output from the preparser unit 201, and obtains information SignalA, SignalB, and SignalC by analyzing the header information recorded at a predetermined position from the input signal. To do. The arithmetic operation unit 204 performs arithmetic processing on the decoded data D103A (or decoded data D103B) from each of the variable length decoding units 103a and 103b with reference to the information SignalA, SignalB, and SignalC from the header information analysis unit 202a or 202b. Thus, reproduction data D204A and D204B are generated. The frame memory 105 stores the reproduction data D204A and D204B from the arithmetic operation unit 204.

<Internal configuration of arithmetic unit>
FIG. 13 shows an internal configuration of the arithmetic operation unit 204 shown in FIG. The arithmetic operation unit 204 replaces the frequency conversion unit 1040, the motion compensation unit 1041, and the block buffers 10A, 11A, 10B, and 11B shown in FIG. 2 with a frequency conversion unit 2040, motion compensation units 2041a and 2041b, and a macroblock buffer. 13MA, 14MA, 13MB, 14MB are provided. Other configurations are the same as those in FIG. Each of the macroblock buffers 13MA and 14MA has a data size corresponding to one macroblock, and stores the decoded data D103A from the variable length decoding unit 103a. Each of the macroblock data 13MB and 14MB is macroblock data 1 The decoded data D103B from the variable length decoding unit 103b is stored. The frequency conversion unit 2040 refers to the information SignalB and SignalC from the header information analysis unit 202a or the information SignalB and SignalC from the header information analysis unit 202b, and is stored in each of the macroblock buffers 13MA, 14MA, 13MB, and 14MB. Difference data is generated by performing discrete cosine transform on the decoded data D103A or the decoded data D103B. The motion compensation unit 2041a refers to the information SignalA from the header information analysis unit 202a, performs motion compensation on the difference data stored in the macroblock buffer 12MA using the prediction data D105A from the frame memory 105, and reproduces the data. D204A is generated. The motion compensation unit 2041b refers to the information SignalA from the header information analysis unit 202b, performs motion compensation on the difference data stored in the buffer memory 12MB using the prediction data D105B from the frame memory 105, and reproduces the data D204B. Is generated.

  In the present embodiment, the frequency conversion unit 2040 has a processing performance that is twice the processing speed of the variable length decoding units 103a and 103b.

<Internal configuration of pre-parser unit 201>
FIG. 14 shows an internal configuration of the preparser unit 201 shown in FIG. The preparser unit 201 includes a buffer memory 2011, a header detection unit 2012, a memory 2013, and a slice control unit 2014. The buffer memory 2011 temporarily stores input signals. The header detection unit 2012 detects a slice header from the input signal stored in the buffer memory 2011, and when the slice header is detected, the slice number and the address in the buffer memory 2011 in which the slice is stored are stored in the memory 2013. To store. The slice control unit 2014 sequentially reads out the slice number stored in the memory 2013 and the address at which the slice is stored, and the slice data to be processed from the input signal stored in the buffer memory 2011 is converted into the header information analysis unit 202a, The data is output to either one of 202b.

<Operation>
The operation when the MPEG2 compressed bit stream (FIGS. 3 and 4) is input to the signal processing apparatus shown in FIG. 12 will be described below.

  First, the signal input to the preparser unit 201 is temporarily stored in the buffer memory 2011.

  Next, the header detection unit 2012 reads the input signal stored in the buffer memory 2011 and detects a slice header from the input signal. When detecting the slice header, the header detection unit 2012 records the slice number and the address in the buffer memory 2011 in which the slice is stored in the memory 2013.

  Next, the slice control unit 2014 sequentially reads the slice number recorded in the memory 2013 and the address where the slice is stored, reads the input signal stored in the buffer memory 2011 according to them, and reads the read input signal Is input to one of the header information analysis units 202a and 202b. For example, if the image shown in FIG. 15 is used, the slice control unit 2014 analyzes the slice 0 to the header information analysis unit 202a, the next slice 1 to the header information analysis unit 202b, and the slice 2 to the header information analysis. The output is controlled so as to be input to the unit 202a.

  Here, it is assumed that slice 0 is input to the header information analysis unit 202a and slice 1 is input to the header information analysis unit 202b.

  The header information analysis unit 202a acquires information SignalA, SignalB, and SignalC by analyzing data in the stream up to the input macro block header of slice 0. On the other hand, the header information analysis unit 202b obtains information SignalA, SignalB, and SignalC by analyzing the data in the stream up to the macroblock header in the input slice 1.

  Next, the data processed by the header information analysis unit 202a is input to the variable length decoding unit 103a and decoded. Further, the variable length decoding unit 103a performs inverse quantization processing and outputs decoded data D103A. On the other hand, the data processed by the second header information analysis unit 202b is input to the variable length decoding unit 103b and decoded. Further, the variable length decoding unit 103b performs inverse quantization processing and outputs decoded data D103B.

  Next, the variable length decoding unit 103a writes the decoded data D103A for one macro block in the order of the macro block buffers 13MA, 14MA... Into each of the macro block buffers 13MA, 14MA. On the other hand, the variable length decoding unit 103b writes the decoded data D103B for one macroblock in the order of the macroblock buffers 13MB, 14MB,... Into each of the macroblock buffers 13MB, 14MB.

  Next, the frequency conversion unit 2040 refers to the information SignalB and SignalC from the header information analysis unit 202a or the information SignalB and SignalC from the header information analysis unit 202b, and performs macroblock buffers 13MA, 13MB, 14MA, 14MB, 13MA, Difference data A or difference data B is generated by performing inverse discrete cosine transform on the decoded data D103A or decoded data D103B in the order of 13 MB.

  Next, when writing the difference data A to the macroblock buffer 12MA, the frequency conversion unit 2040 refers to the information SignalB from the header information analysis unit 202a to confirm the block position, and the generated difference data A is used as the macroblock buffer. Write to a predetermined position of 12MA. Further, when writing the difference data B to the buffer 12MB, the frequency conversion unit 2040 refers to the information SignalB from the header information analysis unit 202b to confirm the block position, and sets the generated difference data B to a predetermined position in the buffer 12MB. Write. Further, when there is no valid data in the block from the information SignalB (CBP), the frequency conversion 2040 outputs zero data for one block to the corresponding block position in the buffers 12MA and 12MB.

  Next, when the difference data A for one macroblock is stored in the macroblock buffer 12MA, the motion compensation unit 2041a starts motion compensation. The motion compensation unit 2041 reads the prediction data D105A from the reference frame stored in the frame memory 105 with reference to SignalA (motion vector information and encoding mode) acquired by the header information analysis unit 202a. Then, the prediction data D105A and the difference data A stored in the macroblock buffer 12MA are added to output reproduction data D204A. The reproduction data D204A is stored in the frame memory 105. On the other hand, the second motion compensation unit 2041b starts motion compensation when the difference data B for one macroblock is stored in the macroblock buffer 12MB. The motion compensation unit 2041b reads the prediction data D105B from the reference frame stored in the frame memory 105 with reference to SignalA (motion vector information and encoding mode) acquired by the header information analysis unit 202b. Then, the prediction data D105B and the difference data B stored in the macroblock buffer 12MB are added to output reproduction data D204B. The reproduction data D204B is stored in the frame memory 105.

<effect>
As described above, the signal processing apparatus according to the present embodiment processes the decoded signal in block units in parallel by the plurality of variable length decoding units, so that the encoded signal can be decoded at high speed. Also, by using one frequency calculation unit and increasing its operating frequency, inverse discrete cosine transform can be performed at high speed on the decoded data generated by each of the plurality of variable length decoding units. Here, since the frequency calculation unit simply calculates the input data, it is relatively easy to raise the operating frequency. In this way, it is possible to suppress an increase in circuit scale due to parallelization of the decoding processing system, and to obtain high-speed processing performance by increasing only the operating frequency of the frequency calculation unit without increasing the operating frequency of the entire apparatus. Can do.

  In the second embodiment of the present invention, an example in which an MPEG2-compressed video signal is input as an input signal has been described. However, the present invention is not limited to this. The same effect can be obtained if the arithmetic operation is performed and the variable-length encoding process is performed.

  In the present embodiment, a configuration having two motion compensation units (motion compensation units 2041a and 2041b) has been described. In this case, motion compensation is simultaneously performed in each of the two motion compensation units, and access to the frame memory 105 may occur at the same time.

  FIG. 16 shows a configuration example of the arithmetic operation unit 304 for avoiding this.

  As shown in FIG. 16, the arithmetic operation unit 304 includes a frequency conversion unit 3040 and a motion compensation unit 3041 instead of the frequency conversion unit 2040 and the motion compensation units 2041a and 2041b shown in FIG.

  The interface (IF) between the frequency conversion unit 3040 and the variable length decoding units 103a and 103b is the same as that of the frequency conversion unit 2040. The motion compensation unit 3041 refers to the information SignalA from the header information analysis unit 202a when reading the difference data from the macroblock buffer 12MA, and the header information analysis unit 202b when reading the difference data from the macroblock buffer 12MB. The prediction data D105A or the prediction data D105B is read from the frame memory 105, motion compensation is performed, and the reproduction data D304A or the reproduction data D304B is written in the frame memory 105.

  In this configuration, it is assumed that the frequency conversion unit 3040 and the motion compensation unit 3041 have a processing performance that is twice the processing speed of the variable length decoding units 103a and 103b.

  As described above, since the information SignalA can be appropriately referred to, the same processing as the arithmetic operation unit 204 can be performed.

(Third embodiment)
<Overall configuration>
The overall configuration of a signal processing apparatus according to the third embodiment of the present invention is shown in FIG. This apparatus has a configuration in which the pre-parser unit shown in FIG. 12 is omitted. Other configurations are the same as those in FIG. The header analysis unit 202a receives the input signal S1, and acquires information SignalA, SignalB, and SignalC by analyzing header information recorded at a predetermined position from the input signal S1. The variable length decoding unit 103a detects a code that matches the input signal S1 from a plurality of variable length coding tables, and outputs a symbol that matches the variable length coding table as decoded data D103A. The header analysis unit 202b receives the input signal S2, and acquires information SignalA, SignalB, and SignalC by analyzing header information recorded at a predetermined position from the input signal S2. The variable length decoding unit 103b detects a code that matches the input signal S2 from a plurality of variable length coding tables, and outputs a symbol that matches the variable length coding table as decoded data D103B.

<Operation>
The operation of the signal processing apparatus shown in FIG. 17 will be described.

  The input signal S1 is input to the header information analysis unit 202a. On the other hand, the input signal S2 is input to the header information analysis unit 202b.

  The header information analysis unit 202a analyzes the data in the stream up to the macroblock header in the input signal S1. On the other hand, the header information analysis unit 202b analyzes the data in the stream up to the macroblock header in the input signal S2.

  Next, the input signal S1 is input to the variable length decoding unit 103a, subjected to run length decoding processing, inverse quantization processing, and output. On the other hand, the input signal S2 is input to the variable length decoding unit 103b, subjected to run length decoding processing, inverse quantization processing, and output.

  Next, the decoded data D103A and D103B output from the variable length decoding units 103a and 103b are input to the arithmetic operation unit 204. The frequency transform unit 2040 generates difference data A and B by performing inverse discrete cosine transform on each of the decoded data D103A and D103B, and outputs each of them to the motion compensation unit 2041.

  Next, the motion compensation unit 2041 generates reproduction data D204A and D204B by performing motion compensation on the difference data A and B using the information SignalB (CBP information) from the header information analysis unit 202a or 202b. Each is stored in the frame memory.

<effect>
As described above, the signal processing apparatus according to the present embodiment processes the decoded signal in block units in parallel by the plurality of variable length decoding units, so that the encoded signal can be decoded at high speed. Also, by using one frequency calculation unit and increasing its operating frequency, inverse discrete cosine transform can be performed at high speed on the decoded data generated by each of the plurality of variable length decoding units. Here, since the frequency calculation unit simply calculates the input data, it is relatively easy to raise the operating frequency. In this way, it is possible to suppress an increase in circuit scale due to parallelization of the decoding processing system, and to obtain high-speed processing performance by increasing only the operating frequency of the frequency calculation unit without increasing the operating frequency of the entire apparatus. Can do. Therefore, a plurality of input signals can be reproduced in real time.

  In the present embodiment, the number of input signals is two, but the present invention is not limited to this.

  However, in the present embodiment, since there are two motion compensation units, memory access contention occurs in the motion compensation process.

  In that case, when the block configuration shown in FIG. 16 is adopted, this memory contention can be prevented.

  In addition, although the example which input the video signal by which MPEG2 compression was input was shown, it does not restrict to this. The same effect can be obtained if the arithmetic operation is performed and the variable-length encoding process is performed.

  As described above, the present invention is effective as a signal processing apparatus or the like that performs a decoding process on an input signal that has been subjected to a variable-length coding process after an arithmetic operation.

1 is a block diagram illustrating an overall configuration of a signal processing device according to a first embodiment of the present invention. It is a block diagram which shows the internal structure of the arithmetic operation part shown in FIG. It is a figure which shows an example of an input signal. It is a figure which shows the block contained in a macroblock. It is a block diagram which shows the internal structure of the pre-parser part shown in FIG. It is a flowchart which shows the operation | movement by the signal processing apparatus shown in FIG. It is a flowchart which shows the operation | movement by the preparser part shown in FIG. 6 is a flowchart showing an operation by the EOB detection unit shown in FIG. 5. It is a flowchart which shows the operation | movement by the block information output part shown in FIG. It is a flowchart which shows the operation | movement by the block control part shown in FIG. It is a timing chart which shows the operation | movement by the arithmetic operation part shown in FIG. It is a block diagram which shows the whole structure of the signal processing apparatus by 2nd Embodiment of this invention. It is a block diagram which shows the internal structure of the arithmetic operation part shown in FIG. It is a block diagram which shows the internal structure of the pre-parser part shown in FIG. It is a figure which shows an example of an image image. It is a block diagram which shows the modification of the internal structure of the arithmetic operation part shown in FIG. It is a block diagram which shows the whole structure of the signal processing apparatus by 3rd Embodiment of this invention. It is a block diagram which shows the whole structure of the conventional signal processing apparatus. It is a block diagram which shows the internal structure of the arithmetic operation part shown in FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 101 Header information analysis part 102 Preparser part 103a, 103b Variable length decoding part 104 Arithmetic operation part 105 Frame memory 10A, 11A, 10B, 11B Block buffer 1040 Frequency conversion part 12MA, 12MB Macroblock buffer 1041 Motion compensation part 1020 EOB search part 1021 Switch 1022 Block control unit 1023 Block information output unit

Claims (10)

An apparatus for processing a signal (encoded signal) encoded according to a predetermined standard,
The encoded signal includes a plurality of block data and a header that stores block information related to the block data,
The device is
A header information acquisition unit, a preparser unit, a plurality of variable length decoding units, and an arithmetic operation unit;
The header information acquisition unit
Obtaining block information stored in the header of the encoded signal;
The pre-parser part is
Referring to the block information acquired by the header information acquisition unit, each of the plurality of block data is associated with any one of the plurality of variable length decoding units,
Each of the plurality of variable length decoding units includes:
Generate decoded data by performing variable length decoding on the block data associated by the preparser unit,
The arithmetic operation unit is
Signal processing characterized in that the plurality of variable length decoding units are selected one by one in order and reproduction data is generated by performing inverse arithmetic operation on the decoded data generated by the selected variable length decoding unit apparatus In claim 1,
Each of the plurality of block data is
An end code indicating the end of the block data is added,
The pre-parser part is
A termination code detector for detecting a termination code from the block data;
A block control unit that associates any one of the plurality of variable length decoding units with each of the plurality of blocks based on the block information acquired by the header information acquisition unit;
When the termination code is detected by the termination code detection unit, the block control unit detects the plurality of blocks in the block data in which the termination code is detected according to the association between the plurality of blocks and the plurality of variable length decoding units by the block control unit. A signal processing apparatus comprising: a selection unit that associates any one of the variable length decoding units. In claim 1,
The arithmetic operation unit is
Selecting a plurality of variable length decoding units one by one in order, a frequency conversion unit for generating spatial data by performing inverse orthogonal transform on the decoded data generated by the selected variable length decoding unit;
A signal processing apparatus comprising: a motion compensation unit that generates reproduction data by performing motion compensation on the spatial data generated by the frequency conversion unit. In claim 1,
An operation speed of the arithmetic operation unit is faster than an operation speed of the variable length decoding unit. In claim 1,
The signal processing apparatus characterized in that the signal encoded by the predetermined standard is an MPEG stream. A method of processing a signal (encoded signal) encoded according to a predetermined standard,
The encoded signal includes a plurality of block data and a header that stores block information related to the block data,
The method
A header information acquisition step, a preparser step, a plurality of variable length decoding steps, and an arithmetic operation step;
The header information acquisition step includes:
Obtaining block information stored in the header of the encoded signal;
The pre-parser step includes
With reference to the block information acquired by the header information acquisition step, each of the plurality of block data is associated with any one of the plurality of variable length decoding steps,
Each of the plurality of variable length decoding steps includes:
Generating decoded data by performing variable length decoding on the block data associated by the preparser step;
The arithmetic operation step includes
Signal processing, wherein the plurality of variable length decoding steps are sequentially selected one by one, and reproduction data is generated by performing an inverse arithmetic operation on the decoded data generated by the selected variable length decoding step. Method In claim 6,
Each of the plurality of block data is
An end code indicating the end of the block data is added,
The pre-parser step includes
A terminal code detection step of detecting a terminal code from the block data;
A block control step of associating any one of the plurality of variable length decoding steps with each of the plurality of blocks based on the block information acquired by the header information acquisition step;
When the termination code is detected by the termination code detection step, the block data in which the termination code is detected is added to the block data in which the termination code is detected according to the association between the plurality of blocks and the plurality of variable length decoding steps by the block control step. And a selection step of associating any one of the variable length decoding steps. In claim 6,
The arithmetic operation step includes
A frequency conversion step of selecting the plurality of variable length decoding steps one by one in order and generating spatial data by performing inverse orthogonal transform on the decoded data generated by the selected variable length decoding step;
And a motion compensation step of generating reproduction data by performing motion compensation on the spatial data generated by the frequency conversion step. In claim 6,
An operation speed of the arithmetic operation step is faster than an operation speed of the variable length decoding step. In claim 6,
The signal processing method characterized in that the signal encoded according to the predetermined standard is an MPEG stream.

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