JP2005259223A - Memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a memory capable of suppressing the occurrence of an erroneous discrimination of data even when the amount of disturbance occurring in a storage means is changed. <P>SOLUTION: This memory is equipped with; a memory cell 1 including ferroelectric capacitors 3a and 3b holding either one of data "1" and data "0"; and sense amplifiers 11 for discriminating the data "1" or "0" in accordance with a differential signal of data signals read out from the memory cell 1. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a memory, and more particularly to a memory including storage means for holding data.

  Conventionally, as an example of a memory including storage means for holding data, a ferroelectric memory including storage means including a ferroelectric capacitor is known. FIG. 19 is an equivalent circuit diagram showing a configuration of a memory cell of a ferroelectric memory according to a conventional example. FIG. 19 shows a memory cell of a 1T type (one transistor type) ferroelectric memory which is an example of an FET type ferroelectric memory. Referring to FIG. 19, a memory cell 101 according to this conventional example has a configuration in which one ferroelectric capacitor 103 is connected to the gate of one field effect transistor (FET) 102. In the ferroelectric memory according to this conventional example, data “1” or data “0” is recorded according to the polarization direction generated by applying a voltage to the ferroelectric capacitor 103. In this ferroelectric memory, since the amount of charge induced in the gate of the field effect transistor 102 differs depending on the polarization direction of the ferroelectric capacitor 103, the field effect transistor depends on the polarization direction of the ferroelectric capacitor 103. A difference occurs in the current flowing through 102. Data “1” or “0” is discriminated by discriminating this current difference in the read operation.

  In the conventional ferroelectric memory shown in FIG. 19, after a positive voltage (positive voltage) is applied to the terminal 104 to polarize the ferroelectric capacitor 103 in the positive direction and write data. When holding the written data, the potential of the terminal 104 is set to 0V. In this case, since an electric field in the direction opposite to the polarization direction of the data to be held is applied to the ferroelectric capacitor 103, there is a disadvantage that the polarization amount of the ferroelectric capacitor 103 is reduced.

  Therefore, a 1T2C type ferroelectric memory that can eliminate the disadvantages of the above-described conventional 1T type ferroelectric memory has been conventionally proposed (for example, see Patent Document 1).

  FIG. 20 is an equivalent circuit diagram showing a configuration of a memory cell of a conventional 1T2C type ferroelectric memory. Referring to FIG. 20, a conventional proposed memory cell 111 of 1T2C type ferroelectric memory has two ferroelectric capacitors 113a and 113b connected to the gate of a single field effect transistor 112. Yes. In the conventional 1T2C type ferroelectric memory shown in FIG. 20, the charge of the ferroelectric capacitor 113a and the charge of the ferroelectric capacitor 113b having the opposite polarity to the ferroelectric capacitor 113a cancel each other in the write operation. As a result, no charge is induced at the gate of the field effect transistor 112. Thus, when the potentials of terminals 114a and 114b connected to each of ferroelectric capacitors 113a and 113b are set to 0 V when data is held, the polarization state of each of ferroelectric capacitors 113a and 113b is canceled. Is suppressed from being applied to the ferroelectric capacitors 113a and 113b. This suppresses a decrease in the amount of polarization of the ferroelectric capacitors 113a and 113b when holding data.

  FIG. 21 is a schematic diagram for explaining a polarization state during a write operation of a conventional 1T2C type memory cell. FIG. 22 is a schematic diagram for explaining a polarization state during a read operation of a conventional 1T2C type memory cell. FIG. 23 is a voltage waveform diagram for explaining a read operation of a conventionally proposed memory cell. Next, the operation of the 1T2C type ferroelectric memory will be described with reference to FIGS.

  When data “0” is written in the memory cell 111, as shown in FIG. 21, a write voltage Vw (> 0V) is applied to the terminal 114a connected to the ferroelectric capacitor 113a, and the ferroelectric capacitor 113b. A voltage of 0 V is applied to the terminal 114b connected to the. Thereby, the ferroelectric capacitors 113a and 113b are polarized by the same amount of polarization in the A direction and the B direction in FIG. 21, respectively. On the other hand, when data “1” is written in the memory cell 111, as shown in FIG. 21, a voltage of 0 V is applied to the terminal 114a connected to the ferroelectric capacitor 113a and connected to the ferroelectric capacitor 113b. A write voltage Vw is applied to the terminal 114b. Thereby, the ferroelectric capacitors 113a and 113b are polarized by the same amount of polarization in the C direction and the D direction in FIG. 21, respectively.

  During the write operation, a disturbance occurs in which the polarization amounts of the ferroelectric capacitors 113a and 113b decrease in the memory cells 111 other than the memory cell 111 to which data is written. That is, when an electric field in the direction opposite to the polarization direction of data originally held is applied to the ferroelectric capacitors 113a and 113b of the memory cells 111 other than the memory cell 111 to which data is written during the write operation, The amount of polarization of the ferroelectric capacitors 113a and 113b decreases. As a result, disturbance occurs in the memory cells 111 other than the memory cell 111 into which data is written during the write operation.

  Next, when reading data from the memory cell 111, as shown in FIG. 22, after applying a predetermined voltage to the source / drain of the field effect transistor 112, the read voltage Vr (> 0V) is applied to the terminal 114a. At the same time, the terminal 114b is brought into a floating state. As a result, an amount of positive charge corresponding to the data held in the ferroelectric capacitors 113 a and 113 b is induced at the gate of the field effect transistor 112. When the data “1” is held in the ferroelectric capacitors 113a and 113b, as shown in FIG. 22, a larger amount of positive charge is generated in the field effect than when the data “0” is held. Since it is induced at the gate of the type transistor 112, the field effect transistor 112 is turned on more strongly. For this reason, in the case of data “1”, the drain current flowing in the field effect transistor 112 becomes larger than in the case of data “0”.

  Further, the current of the data signal read during the read operation varies depending on the amount of disturbance during the write operation. That is, in the state of data “0” in FIG. 21, due to the disturbance, the amount of charge on the field effect transistor 112 side of the ferroelectric capacitor 113a decreases to −2, and the electric field of the ferroelectric capacitor 113b. When the charge amount on the effect transistor 112 side decreases to +2, during the read operation (see data “0” in FIG. 22), −5 is applied to the field effect transistor 112 side of the ferroelectric capacitor 113a. A negative charge is generated, and a positive charge of +2 is generated on the field effect transistor 112 side of the ferroelectric capacitor 113b. Note that an amount of charge corresponding to the read voltage Vr is generated on the field effect transistor 112 side of the ferroelectric capacitor 113a regardless of the amount of disturbance during the write operation. In this case, a positive charge of +3 is induced on the gate of the field effect transistor 112, which is larger than the charge (+2 positive charge) in the case where there is no influence of disturbance (see data “0” in FIG. 22). . Accordingly, when data “0” is held, the field effect transistor 112 is turned on more strongly when the disturb amount during the write operation is larger than when the disturb amount is small. The drain current flowing through the field effect transistor 112 increases. Therefore, in the data signal corresponding to the data “0”, as shown in FIG. 23, the voltage at the data determination timing is larger when the disturb amount is larger than when the disturb amount is small.

On the other hand, in the state of data “1” in FIG. 21, due to the disturbance, the charge amount on the field effect transistor 112 side of the ferroelectric capacitor 113a decreases to +2, and the field effect of the ferroelectric capacitor 113b. When the charge amount on the side of the type transistor 112 decreases to −2, during the read operation (see data “1” in FIG. 22), a value of −5 A negative charge is generated, and a negative charge of −2 is generated on the field effect transistor 112 side of the ferroelectric capacitor 113b. Note that an amount of charge corresponding to the read voltage Vr is generated on the field effect transistor 2 side of the ferroelectric capacitor 113a regardless of the amount of disturbance during the write operation. In this case, a positive charge of +7 is induced on the gate of the field effect transistor 112, which is smaller than the charge (+8 positive charge) in the case where there is no influence of disturbance (see data “1” in FIG. 22). . Accordingly, in the case of data “1”, the field effect transistor 112 is weaker when the disturb amount during the write operation is larger than when the disturb amount is small. The drain current flowing through the For this reason, in the data signal corresponding to the data “1”, as shown in FIG. 23, the voltage at the data determination timing is larger when the disturb amount during the write operation is larger than when the disturb amount is small. Get smaller.
Japanese Patent No. 3239109

  However, in the 1T2C type ferroelectric memory shown in FIG. 20, as shown in FIG. 23, the voltage of the data signal of data “0” and the voltage of the data signal of data “1” are determined at the data determination timing. The magnitude relationship may be reversed depending on whether the amount of disturbance generated in the ferroelectric capacitors 113a and 113b is small or large. In this case, there is a problem that erroneous determination of data occurs.

  The present invention has been made to solve the above-described problems, and one object of the present invention is to prevent erroneous determination of data even when the amount of disturbance generated in the storage means changes. It is to provide a memory that can be suppressed.

Means for Solving the Problems and Effects of the Invention

  In order to achieve the above object, a memory according to one aspect of the present invention includes a memory cell including storage means for holding one of first data and second data, and a data signal read from the memory cell. A first data discriminating circuit for discriminating between the first data and the second data based on the rate of change;

  In the memory according to this aspect, as described above, by determining the first data or the second data by the first data determination circuit based on the rate of change of the data signal read from the memory cell in the read operation, Even when the disturb amount generated in the memory means changes, the rate of change (rising slope) of the data signal read from the memory cell is less likely to change than the absolute value of the signal read from the memory cell. Even when the amount of disturbance that occurs changes, it is possible to suppress erroneous data discrimination.

  The memory according to the first aspect preferably further includes a differentiating circuit that is connected between the memory cell and the first data discriminating circuit and outputs a differential signal of the data signal read from the memory cell, and the first data discriminating circuit. Determines the first data or the second data based on the differential signal. With this configuration, the differential signal of the data signal read from the memory cell corresponds to the rate of change of the data signal read from the memory cell, so that the change in the data signal read from the memory cell can be easily performed in the read operation. Based on the rate, the first data or the second data can be determined.

  In the memory according to the above aspect, the storage unit preferably includes a capacitor that holds one of the first data and the second data, and the memory cell includes a gate to which the capacitor is connected and a pair of sources And a transistor for outputting a data signal corresponding to data held by the capacitor, and one of the source / drain of the transistor is connected to the first data discrimination circuit. With this configuration, in a memory including an FET-type memory cell including a capacitor and a transistor, it is possible to prevent erroneous data discrimination even when the amount of disturbance generated in the capacitor changes. be able to.

  In this case, the capacitor preferably includes a first capacitor that is polarized in a predetermined direction in the write operation, and a second capacitor that is polarized in a direction opposite to the predetermined direction in the write operation, and the first capacitor and the second capacitor Is connected to the gate of the transistor. According to this configuration, the charge of the first capacitor and the charge of the second capacitor having the opposite polarity to the first capacitor are canceled in the write operation, so that no charge is generated at the gate of the transistor. Accordingly, when the potential of the electrode on the opposite side to the side connected to the gate of each transistor of the first capacitor and the second capacitor is set to 0 V when data is held, each of the first capacitor and the second capacitor It is possible to suppress application of an electric field in a direction that cancels the polarization state of the first capacitor and the second capacitor, respectively. Thereby, it is possible to suppress a decrease in the polarization amounts of the first capacitor and the second capacitor when data is held.

  In this case, more preferably, the first data discriminating circuit is configured so that the output signal of one of the first data and the second data substantially rises and the other of the first data and the second data. The first data or the second data is discriminated at the timing when the output signal rises. With this configuration, the rate of change of the output signal after rising (the slope after rising) becomes smaller than the rate of change of the output signal during rising (the slope during rising). Based on the change rate of the output signal, the first data or the second data can be easily determined.

  In the memory according to the above aspect, it is preferable that the memory further includes an integration circuit that is connected between the differentiation circuit and the first data determination circuit, and that outputs an integration signal of the differentiation signal. Based on this, the first data or the second data is discriminated. With this configuration, the difference between the magnitude of the integrated signal of the differential signal corresponding to the first data and the magnitude of the integrated signal of the differential signal corresponding to the second data is equal to the magnitude of the differential signal corresponding to the first data. Since it is often larger than the difference from the magnitude of the differential signal corresponding to the two data, the first data or the second data can be easily determined.

  The memory according to the above aspect preferably further includes a second data discriminating circuit that discriminates the first data or the second data based on the change amount of the data signal read from the memory cell. According to this configuration, the amount of change in the data signal read from the memory cell by the second data determination circuit is determined while determining the data based on the rate of change of the data signal read from the memory cell by the first data determination circuit. Based on this, data can be determined. As a result, the data can be determined more reliably.

  In the memory according to the aforementioned aspect, the storage means includes a ferroelectric capacitor having a ferroelectric film. With this configuration, in a memory including a storage unit composed of a ferroelectric capacitor including a ferroelectric film, erroneous data discrimination occurs even when the amount of disturbance generated in the ferroelectric capacitor changes. Can be suppressed.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is an equivalent circuit diagram showing a configuration of a memory cell of a ferroelectric memory according to the first embodiment of the present invention. FIG. 2 is an equivalent circuit diagram showing a configuration of a ferroelectric memory using the memory cell according to the first embodiment shown in FIG. FIG. 3 is an equivalent circuit diagram showing the configuration of the differentiation circuit of the ferroelectric memory according to the first embodiment shown in FIG. FIG. 4 is an equivalent circuit diagram showing the configuration of the sense amplifier of the ferroelectric memory according to the first embodiment shown in FIG. First, the configuration of the ferroelectric memory according to the first embodiment of the present invention will be described with reference to FIGS.

  As shown in FIG. 1, the memory cell 1 of the ferroelectric memory according to the first embodiment has two ferroelectric capacitors 3a and 3 at the gate of one field effect transistor (FET) 2 composed of an n-channel MOS transistor. It has a 1T2C type configuration in which 3b is connected. The field effect transistor 2 is an example of the “transistor” of the present invention, and the ferroelectric capacitors 3a and 3b are examples of the “memory means” and the “capacitor” of the present invention. The two ferroelectric capacitors 3a and 3b are made of a ferroelectric film and are configured to have the same amount of polarization when a predetermined voltage is applied.

  In the ferroelectric memory according to the first embodiment, as shown in FIG. 2, a memory cell array 4 is configured by arranging a plurality of memory cells 1 having the above-described configuration. FIG. 2 shows a memory cell array 4 in which 2 × 2 memory cells 1 are arranged for simplification of the drawing. In the memory cell array 4, one electrode of the ferroelectric capacitor 3a is connected to the electrode line 5a. The other electrode of the ferroelectric capacitor 3b is connected to the electrode line 5b. One of the source / drain of the field effect transistor 2 is connected to the voltage supply line 6 and the other is connected to the signal output line 7. Further, a control line 8 for applying a voltage to the substrate on which the field effect transistor 2 is formed is provided. The signal output line 7 is connected to a resistor 9 having one end grounded. The resistor 9 has a function of converting a current corresponding to a data signal read out via the field effect transistor 2 into a voltage.

  Here, in the first embodiment, the differentiation circuit 10 is connected to the signal output line 7. The differentiating circuit 10 is configured to receive a data signal output from the memory cell 1 and to output a differential signal of the input data signal. Further, as shown in FIG. 3, the differentiating circuit 10 includes a capacitor 10a and a resistor 10b. One electrode of the capacitor 10 a is connected to the input terminal 10 c of the differentiation circuit 10, and the other electrode is connected to the output terminal 10 d of the differentiation circuit 10. Further, one end of the resistor 10b is connected to the output terminal 10d side of the capacitor 10a, and the other end is grounded.

  Further, a sense amplifier 11 is connected to the output terminal 10d of the differentiating circuit 10 as shown in FIGS. The sense amplifier 11 is an example of the “first data determination circuit” in the present invention. The sense amplifier 11 is a voltage sense amplifier, and compares the voltage corresponding to the differential signal output from the differentiating circuit 10 with the voltage (reference voltage) of the reference signal supplied from a reference circuit (not shown). Thus, it has a function of discriminating whether the data read from the memory cell 1 is data “1” or data “0”.

  The sense amplifier 11 has a cross-coupled configuration as shown in FIG. Specifically, the sense amplifier 11 is composed of two n-channel transistors 11a and 11b and two p-channel transistors 11c and 11d. Further, the input / output of the CMOS inverter composed of the n-channel transistor 11a and the p-channel transistor 11c and the CMOS inverter composed of the n-channel transistor 11b and the p-channel transistor 11d are cross-coupled to each other. The node ND1 is connected to a data line 11e to which a differential signal output from the differentiating circuit 9 is input. Further, a reference signal line 11f to which a reference signal is input from a reference circuit (not shown) is connected to the node ND2.

  The start signal SNL is input to the node ND3, and the start signal SPL is input to the node ND4. The start signals SNL and SPL are signals that are synchronized with the differential signal and that are slightly delayed in timing from the differential signal. Further, as the start signal SPL, a positive voltage VDD larger than the voltage of the differential signal is supplied, while as the start signal SNL, a negative voltage −VDD obtained by inverting the polarity of the start signal SPL is supplied. Further, when the differential signal voltage is larger than the reference signal voltage, the sense amplifier 11 outputs an H level (VDD) signal to the outside, while the differential signal voltage is smaller than the reference signal voltage. Is configured to output an L level (−VDD) signal to the outside. When the output signal from the sense amplifier 11 is H level, the data read from the memory cell is determined as data “1”, and when it is L level, the data is read from the memory cell. The data is determined as data “0”.

  FIG. 5 is a schematic diagram for explaining the polarization state during the write operation of the memory cell according to the first embodiment of the present invention. FIG. 6 is a schematic diagram for explaining a polarization state during a read operation of the memory cell according to the first embodiment of the present invention. FIG. 7 is a voltage waveform diagram for explaining a read operation of the memory cell according to the first embodiment of the present invention. 8 and 9 are voltage waveform diagrams corresponding to the data signal shown in FIG. Next, a write operation and a read operation of the ferroelectric memory according to the first embodiment will be described with reference to FIGS.

(Write operation)
When data “0” is written in the memory cell 1, as shown in FIG. 2, a write voltage Vw (> 0V) is applied to the electrode line 5a, and a voltage of 0V is applied to the electrode line 5b. Further, the control line 8 is held at a potential of 0V. As a result, the ferroelectric capacitor 3a is polarized in the A direction in FIG. 5, and the ferroelectric capacitor 3b is polarized in the B direction in FIG. In the first embodiment, this state is defined as a state in which data “0” is written. At this time, the polarization amounts of the ferroelectric capacitors 3a and 3b are equal. As a result, the charges caused by each of the ferroelectric capacitors 3a and 3b cancel each other, so that no charge is induced at the gate of the field effect transistor 2 connected to the ferroelectric capacitors 3a and 3b. Thereafter, the potentials of the electrode lines 5a and 5b (see FIG. 2) are both set to 0V. Thereby, the data “0” written in the ferroelectric capacitors 3a and 3b is held. At this time, since no charge is induced at the gate of the field effect transistor 2, an electric field in the direction opposite to the polarization direction of the ferroelectric capacitors 3a and 3b is not applied to the ferroelectric capacitors 3a and 3b. Thereby, it is suppressed that the amount of polarization of the ferroelectric capacitors 3a and 3b decreases.

  On the other hand, when data “1” is written in the memory cell 1, a voltage of 0 V is applied to the electrode line 5a and a write voltage Vw is applied to the electrode line 5b. As a result, the ferroelectric capacitor 3a is polarized in the C direction in FIG. 5, and the ferroelectric capacitor 3b is polarized in the D direction in FIG. In the first embodiment, this state is defined as a state in which data “1” is written. At this time, the polarization amounts of the ferroelectric capacitors 3a and 3b are equal. As a result, the charges caused by each of the ferroelectric capacitors 3a and 3b cancel each other, so that no charge is induced at the gate of the field effect transistor 2 connected to the ferroelectric capacitors 3a and 3b. Thereafter, the potentials of the electrode lines 5a and 5b (see FIG. 2) are both set to 0V. As a result, the data “1” written in the ferroelectric capacitors 3a and 3b is held. At this time, since no charge is induced at the gate of the field effect transistor 2, an electric field in the direction opposite to the polarization direction of the ferroelectric capacitors 3a and 3b is not applied to the ferroelectric capacitors 3a and 3b. Thereby, it is suppressed that the amount of polarization of the ferroelectric capacitors 3a and 3b decreases.

  As described above, when data is written to the ferroelectric capacitors 3a and 3b, a disturbance in which the polarization amount of the ferroelectric capacitors 3a and 3b decreases in the memory cell 1 other than the memory cell 1 to which the data is written occurs. . For example, when data “0” is written in a predetermined memory cell 1, the write voltage Vw is also applied to other memory cells 1 on the electrode line 5a to which the memory cell 1 is connected. At this time, if the data “1” is originally held in the ferroelectric capacitors 3 a and 3 b of the other memory cells 1, an electric field opposite to the polarization direction of the ferroelectric capacitors 3 a and 3 b is applied. Therefore, the polarization amounts of the ferroelectric capacitors 3a and 3b holding the data “1” are reduced. In this manner, disturbance is generated in the memory cells 1 other than the memory cell 1 to which data is written during the write operation, by applying a voltage in the direction opposite to the polarization direction of the data originally held.

(Read operation)
When data stored in the memory cell 1 is read, as shown in FIG. 2, a predetermined voltage is applied to the voltage supply line 6 and then a read voltage Vr (> 0 V) is applied to the electrode line 5a. The electrode line 5b is brought into a floating state. Further, the control line 8 is held at a potential of 0V. As a result, an electric field in the A direction in FIG. 6 is applied to the ferroelectric capacitor 3 a, whereby a predetermined amount of positive charge is induced at the gate of the field effect transistor 2. At this time, data “0” is held in the ferroelectric capacitors 3a and 3b (see data “0” in FIG. 5), and data “1” is held (data in FIG. 5). The amount of charge induced at the gate of the field effect transistor 2 is different from that of “1”.

  That is, as shown in FIG. 6, when data “1” is held, more positive charges are applied to the gate of the field effect transistor 2 than when data “0” is held. Induced. For example, in a state where data “0” is held (see FIG. 5), a negative charge of −3 exists on the field effect transistor 2 side of the ferroelectric capacitor 3a, and the field effect type of the ferroelectric capacitor 3b. When a positive charge of +3 is present on the transistor 2 side, as shown in FIG. 6, a negative charge of −5 generated on the field effect transistor 2 side of the ferroelectric capacitor 3a by applying the read voltage Vr. This cancels out the positive charge of +3 on the field effect transistor 2 side of the ferroelectric capacitor 3b. As a result, a positive charge of +2 is induced at the gate of the field effect transistor 2. On the other hand, a positive charge of +3 exists on the field effect transistor 2 side of the ferroelectric capacitor 3a in the state where the data “1” is held (see FIG. 5), and the field effect transistor of the ferroelectric capacitor 3b. When a negative charge of -3 exists on the second side, as shown in FIG. 6, a negative charge of -5 generated on the field effect transistor 2 side of the ferroelectric capacitor 3a by applying the read voltage Vr. -3 negative charges on the field effect transistor 2 side of the ferroelectric capacitor 3b are combined. As a result, a positive charge of +8 is induced at the gate of the field effect transistor 2. Therefore, when data “1” is held in the ferroelectric capacitors 3a and 3b, the field effect transistor 2 is turned on more strongly than when data “0” is held. For this reason, in the case of data “1”, the drain current flowing in the field effect transistor 2 becomes larger than in the case of data “0”. For this reason, in the case of data “1”, the current flowing through the signal output line 7 becomes larger than in the case of data “0”.

  The current flowing through the signal output line 7 during the read operation changes due to disturbance during the write operation. That is, when data “0” is held (refer to data “0” in FIG. 5), the charge amount on the field effect transistor 2 side of the ferroelectric capacitor 3a becomes −2 due to the disturbance. When the charge amount on the field effect transistor 2 side of the ferroelectric capacitor 3b decreases to +2, the read voltage Vr is applied during the read operation (see data “0” in FIG. 6). As a result, a negative charge of -5 is generated on the field effect transistor 2 side of the ferroelectric capacitor 3a, and a positive charge of +2 is generated on the field effect transistor 2 side of the ferroelectric capacitor 3b. Note that, on the field effect transistor 2 side of the ferroelectric capacitor 3a, an amount of electric charge corresponding to the read voltage Vr is generated regardless of the amount of disturbance during the write operation. In this case, a positive charge of +3 is induced on the gate of the field effect transistor 2 which is larger than the charge (+2 positive charge) in the case where there is no influence of disturbance (see data “0” in FIG. 6). . Thus, in the case of data “0”, the field effect transistor 2 is turned on more strongly when the disturb amount during the write operation is larger than when the disturb amount is small. The drain current flowing through 2 increases.

  On the other hand, when data “1” is held (see data “1” in FIG. 5), the charge amount on the field effect transistor 2 side of the ferroelectric capacitor 3a decreases to +2 due to the disturbance. At the same time, when the amount of charge on the field effect transistor 2 side of the ferroelectric capacitor 3b decreases to −2, the read operation (see data “1” in FIG. 6) of the ferroelectric capacitor 3a is performed. A negative charge of −5 is generated on the field effect transistor 2 side, and a negative charge of −2 is generated on the field effect transistor 2 side of the ferroelectric capacitor 3b. Note that, on the field effect transistor 2 side of the ferroelectric capacitor 3a, an amount of electric charge corresponding to the read voltage Vr is generated regardless of the amount of disturbance during the write operation. In this case, a positive charge of +7 is induced at the gate of the field effect transistor 2 which is smaller than the charge (+8 positive charge) when there is no influence of disturbance (see data “1” in FIG. 6). . Thus, in the case of data “1”, the field effect transistor 2 is weaker when the disturbance amount during the write operation is larger than when the disturbance amount is small. The drain current flowing through becomes smaller.

  The current corresponding to the data signal flowing through the signal output line 7 is converted into a voltage by the resistor 9 (see FIG. 2). The data signal thus converted into a voltage has a voltage waveform as shown in FIGS. That is, the voltage waveform of the data signal corresponding to the data “0” rises rapidly immediately after the read voltage Vr is applied, and hardly changes thereafter. On the other hand, the voltage waveform of the data signal corresponding to data “1” rises more slowly than the case of data “0”, and continuously increases until near the end of application of the read voltage Vr. Note that the voltage waveform of the data signal in the case of the data “0” and “1” described above shows the same tendency when the disturb amount during the write operation is small and when it is large.

  In the case of data “0”, the current corresponding to the data signal during the read operation increases as the disturb amount during the write operation increases. Therefore, the voltage that the data signal reaches when the disturb amount is large is When the amount of disturbance is small, it becomes larger than the voltage that the data signal reaches. In the case of data “1”, the current corresponding to the data signal during the read operation decreases as the disturb amount during the write operation increases. Therefore, the voltage that the data signal reaches when the disturb amount is large is When the amount of disturbance is small, it becomes smaller than the voltage that the data signal reaches. Accordingly, as shown in FIG. 7, the magnitude of the voltage reached by the data signal may be reversed depending on whether the disturb amount during the write operation is small or large. That is, when the disturb amount is small, the voltage reached by the data signal in the case of data “1” is larger than the voltage of the data signal in the case of data “0”, while when the disturb amount is large, the data “ The voltage reached by the data signal in the case of “0” may be smaller than the voltage reached by the data signal in the case of “1”.

  Next, the data signal converted into the voltage is input to the differentiating circuit 10. As a result, a differential signal obtained by differentiating the voltage waveform of the data signal is output from the differentiating circuit 10. The differential signal output from the differentiating circuit 10 is a voltage signal corresponding to the voltage change rate (voltage waveform slope) of the data signal. This differential signal has a voltage waveform as shown in FIG. That is, the differential signal corresponding to the data “0” rises rapidly and then immediately returns to the original voltage, while the differential signal corresponding to the data “1” becomes a differential signal corresponding to the data “0”. After starting up more slowly, it gradually returns to the original voltage. The tendency of the voltage waveform of the differential signal is the same when the amount of disturbance during the write operation is small and large.

  The differential signal output from the differentiation circuit 10 is input to one data line 11e of the sense amplifier 11 (see FIG. 4). Prior to the differential signal being input to the data line 11e, the reference signal generated by a reference circuit (not shown) is input to the other reference signal line 11f of the sense amplifier 11. Then, the start signals SNL and SPL are input to the sense amplifier 11 at a timing slightly delayed after being synchronized with the timing at which the differential signal is input to the sense amplifier 11. Then, the differential signal voltage and the reference signal voltage (reference voltage) are compared and amplified. Thereby, when the voltage of the differential signal is larger than the voltage of the reference signal, the n-channel transistor 11b and the p-channel transistor 11c are turned on, and the n-channel transistor 11a and the p-channel transistor 11d are turned off. Become. As a result, the potential of the node ND1 to which the H level (VDD) start signal SPL is supplied through the p-channel transistor 11c is increased, and the L level (−VDD) start signal SNL is supplied through the n-channel transistor 11b. The potential of the node ND2 to which is supplied is lowered. Therefore, since the p-channel transistor 11c and the n-channel transistor 11b are turned on more strongly, the potential of the node ND1 rises toward VDD (the voltage of the start signal SPL), and the potential of the node ND2 is −VDD It decreases toward (the voltage of the start signal SNL). As a result, an H level (VDD) signal is output from the data line 11 e of the sense amplifier 11. In this case, it is determined that the data read from the memory cell 1 is data “1”.

  On the other hand, when the voltage of the differential signal is smaller than the voltage of the reference signal, the n-channel transistor 11a and the p-channel transistor 11d are turned on, and the n-channel transistor 11b and the p-channel transistor 11c are turned off. . As a result, the potential of the node ND1 to which the L level (−VDD) start signal SNL is supplied via the n channel transistor 11a is lowered, and the H level (VDD) start signal SPL is supplied via the n channel transistor 11d. The potential of the node ND2 to which is supplied is raised. For this reason, since the n-channel transistor 11a and the p-channel transistor 11d are turned on more strongly, the potential of the node ND1 is lowered toward −VDD (the voltage of the start signal SNL), and the potential of the node ND2 is VDD The voltage rises toward (the voltage of the start signal SPL). As a result, an L level (−VDD) signal is output from the data line 11 e of the sense amplifier 11. In this case, it is determined that the data read from the memory cell 1 is data “0”.

  The data “1” or “0” in the read data is determined at a predetermined determination timing after the read voltage is applied to the ferroelectric capacitor 3a as shown in FIG. The determination timing is such that after the differential signal corresponding to the data “0” returns to the original voltage even after the peak, the differential signal corresponding to the data “1” returns to the original voltage before the read voltage application. Set the timing between. That is, after the data signal corresponding to the data “0” substantially rises, the determination is performed at a timing during the rise of the data signal corresponding to the data “1”. The voltage waveform of the differential signal corresponding to each of the data “1” and “0” shows the same tendency depending on whether the disturb amount during the write operation is small or large. At the determination timing, the voltage of the differential signal corresponding to the data “1” is always higher than the voltage of the differential signal corresponding to the data “0” regardless of whether the disturbance amount is small or large.

  As shown in FIG. 8, when the disturb amount during the write operation is small, in the conventional method for determining data by comparing the voltage of the data signal, the voltage of the data signal of data “1” is the data It is necessary to determine the data after time t1 when the value is equal to or higher than the voltage of the data signal “0”. On the other hand, in the data determination method according to the first embodiment, the slope (voltage change rate) of the data signal “1” is before the time t1 from the slope (voltage change rate) of the data signal “0”. Therefore, the voltage of the differential signal corresponding to the data “1” becomes larger than the voltage of the differential signal corresponding to the data “0” before the time t1. That is, if the voltage waveform of the data signal of data “0” shown in FIG. 8 substantially rises, the slope (differential value) of the voltage waveform of the data signal of data “1” is the data “ It becomes larger than the slope (differential value) of the voltage waveform of the data signal of “0”. Thereby, in the data determination method according to the first embodiment, since it is possible to determine data before time t1, compared with the conventional method of determining data by comparing the voltage of the data signal. It is possible to determine data earlier.

  In the first embodiment, as described above, the write operation is performed by determining the data “1” or “0” by the sense amplifier 11 based on the differential signal of the data signal read from the memory cell 1 in the read operation. Even when the disturbance amount generated in the ferroelectric capacitors 3a and 3b sometimes changes, the differential signal of the data signal read from the memory cell 1 is less likely to change than the voltage of the data signal read from the memory cell 1. Even when the amount of disturbance generated in the ferroelectric capacitors 3a and 3b changes, it is possible to suppress erroneous data discrimination.

  FIG. 10 is an equivalent circuit diagram showing a configuration of a ferroelectric memory according to a modification of the first embodiment of the present invention. The ferroelectric memory according to the modification of the first embodiment is different from the ferroelectric memory according to the first embodiment in that the data “1” or “0” is determined based on the differential signal of the data signal. In addition, the data “1” or “0” is determined based on the amount of change in the voltage of the data signal. Specifically, as shown in FIG. 10, the ferroelectric memory according to the modification of the first embodiment includes a sense amplifier for determining data “1” or “0” based on the voltage of the data signal. 12 is provided. The sense amplifier 12 is an example of the “second data determination circuit” in the present invention. The internal configuration of the sense amplifier 12 is the same as the configuration of the sense amplifier 11 (see FIG. 4) according to the first embodiment. The sense amplifier 12 compares the voltage of the data signal with the voltage of the reference signal to output an H level signal when the voltage of the data signal is larger than the voltage of the reference signal, and when it is small, the sense amplifier 12 outputs L. It is configured to output a level signal. The sense amplifier 12 is connected between the connection point of the resistor 9 of the signal output line 7 and the differentiation circuit 10. In the ferroelectric memory according to this modification, after the current of the data signal is converted into a voltage by the resistor 9, the converted voltage of the data signal is input to the sense amplifier 12 as it is and the differentiation circuit 10. Then, the signal is further converted into a differential signal and then input to the sense amplifier 11. The other configuration of the ferroelectric memory according to the modification of the first embodiment is the same as that of the ferroelectric memory according to the first embodiment.

  Next, the operation of the ferroelectric memory according to the modification of the first embodiment will be described with reference to FIG. In the ferroelectric memory according to the modification of the first embodiment, in the read operation, the current corresponding to the data signal read from the memory cell 1 is converted into a voltage by the resistor 9, and then the sense amplifier 12 and the differential Each is input to the circuit 10. As a result, the sense amplifier 12 compares the voltage of the data signal with the voltage of the reference signal. When the data signal voltage is higher than the reference signal voltage, an H level signal is output, and when the data signal voltage is lower than the reference signal voltage, an L level signal is output. . When the H level signal is output, it is determined that the data read from the memory cell 1 is data “1”, while when the L level signal is output, the memory cell 1 It is determined that the data read from 1 is data “0”. Further, the differential circuit 10 to which the data signal is input outputs a differential signal obtained by differentiating the voltage waveform of the data signal. The differential signal is input to the sense amplifier 11 and the voltage of the differential signal is compared with the voltage of the reference signal in the sense amplifier 11. Thereby, it is determined whether the data read from the memory cell is data “1” or “0”. The operation of the sense amplifier 11 at this time is the same as the operation of the sense amplifier 11 according to the first embodiment.

  In the ferroelectric memory according to the modification of the first embodiment, data “1” or “0” is determined based on the data determination result by the sense amplifier 11 and the data determination result by the sense amplifier 12. That is, when the disturb amount during the write operation is small, as shown in FIG. 7, the voltage of the data signal of data “1” becomes larger than the voltage of the data signal of data “0”, and the above-described determination The voltage of the differential signal corresponding to the data “1” at the timing is larger than the voltage of the differential signal corresponding to the data “0”. As described above, when the disturb amount during the write operation is small, the data discrimination results by the sense amplifiers 11 and 12 coincide with each other, so that the data discrimination can be performed more reliably. If the amount of disturbance is large, erroneous determination of data by the sense amplifier 12 that determines the data by comparing the absolute value of the voltage of the data signal with the absolute value of the reference voltage is likely to occur. The result of data discrimination by each of 12 is not necessarily consistent. Therefore, the modification of the first embodiment is effective when the amount of disturbance is small.

(Second Embodiment)
FIG. 11 is an equivalent circuit diagram showing a configuration of a ferroelectric memory according to the second embodiment of the present invention. FIG. 12 is an equivalent circuit diagram showing the configuration of the integrating circuit of the ferroelectric memory according to the second embodiment shown in FIG. The configuration of the ferroelectric memory according to the second embodiment of the present invention will be described with reference to FIGS.

  Unlike the ferroelectric memory according to the first embodiment, the ferroelectric memory according to the second embodiment converts the differential signal of the data signal into an integral signal, and then converts the data “1” or “1” based on the converted integral signal. It is configured to determine “0”. Specifically, in the ferroelectric memory according to the second embodiment, an integrating circuit 13 is connected between the differentiating circuit 10 and the sense amplifier 11 as shown in FIG. As shown in FIG. 12, the integration circuit 13 includes a resistor 13a and a capacitor 13b. The differential signal is input to one end of the resistor 13a, and the other electrode of the capacitor 13b having one electrode grounded is connected to the other end. An integration signal is output from the integration circuit 13 having such a configuration, and the output integration signal is input to the sense amplifier 11. The other configuration of the ferroelectric memory according to the second embodiment is the same as that of the ferroelectric memory according to the first embodiment.

  Next, the operation of the ferroelectric memory according to the second embodiment will be described with reference to FIGS. In the ferroelectric memory according to the second embodiment, in a read operation, a differential signal corresponding to the data in the memory cell 1 is input to the integration circuit 13, whereby an integrated signal obtained by integrating the voltage waveform of the input differential signal. Is output from the integrating circuit 13. The voltage waveform of the differential signal input to the integrating circuit 13 is the same as the voltage waveform of the differential signal according to the first embodiment (see FIG. 7). In addition, the voltage of the integrated value of the voltage waveform of the differential signal is a value corresponding to the area of the voltage waveform of the differential signal. Therefore, the area of the voltage waveform of the differential signal corresponding to data “1” is larger than the area of the voltage waveform of the differential signal corresponding to data “0” as shown in FIG. The voltage of the corresponding integration signal is larger than the voltage of the integration signal corresponding to the data “0”.

  The integral signal is input to the sense amplifier 11 and the sense amplifier 11 compares the voltage of the integral signal with the voltage of the reference signal, thereby determining data “1” or “0”. The operation of the sense amplifier 11 at this time is the same as the operation of the sense amplifier 11 according to the first embodiment. In other words, when the voltage of the integration signal is larger than the voltage of the reference signal, an H level signal is output from the sense amplifier 11, while when the voltage of the integration signal is smaller than the voltage of the reference signal, the sense amplifier 11 outputs an L level signal. When an H level signal is output from the sense amplifier 11, data “1” is determined. On the other hand, when an L level signal is output, data “0” is determined.

  In the second embodiment, the data determination timing is set to a predetermined timing after the voltage waveform of the differential signal corresponding to the data “1” has fallen through the peak. That is, the data is determined at a predetermined timing after the voltage waveform of the data signal corresponding to the data “1” completely rises. Thereby, the voltage of the integral signal at the data determination timing is fixed to a predetermined value obtained by integrating the voltage waveform from the start of the rising of the differential signal to the falling after the peak. For this reason, in the second embodiment, even when the data determination timing slightly shifts, the voltage of the integrated signal at the time of data determination is suppressed from changing. The other operations of the ferroelectric memory according to the second embodiment are the same as the operations of the ferroelectric memory according to the first embodiment.

  In the second embodiment, as described above, the integration circuit 13 that outputs the integration signal of the differential signal of the data signal is provided, and the sense amplifier 11 determines the data “1” or “0” based on the integration signal. As a result, the difference between the magnitude of the voltage of the integral signal corresponding to data “1” and the magnitude of the voltage of the integral signal corresponding to data “0” is equal to the magnitude of the voltage of the differential signal corresponding to data “1”. In many cases, the difference is larger than the difference between the voltage of the differential signal corresponding to the data “0”, and therefore the data “1” or “0” can be easily determined.

  FIG. 13 is an equivalent circuit diagram showing a configuration of an integration circuit of a ferroelectric memory according to a modification of the second embodiment of the present invention. In the ferroelectric memory according to the modification of the second embodiment, unlike the ferroelectric memory according to the second embodiment, the integrating circuit 23 integrates the voltage waveform of the differential signal and outputs an amplified integrated signal. It is configured as follows. Specifically, the integration circuit 23 includes resistors 23a, 23b, and 23c, a capacitor 23d, and operational amplifiers 23e and 23f. A differential signal is input from one end of the resistor 23a from the differentiating circuit 10 (see FIG. 11), and the other end is connected to the inverting input terminal of the operational amplifier 23e. A capacitor 23d is connected between the output of the operational amplifier 23e and the inverting input terminal. The non-inverting input terminal of the operational amplifier 23e is grounded. The output of the operational amplifier 23e is input to the inverting input terminal of the operational amplifier 23f via the resistor 23b. A resistor 23c is connected between the output of the operational amplifier 23f and the inverting input terminal. The resistor 23b and the resistor 23c have the same resistance value. Therefore, the amplification factor of the operational amplifier 23f is 1. Note that the non-inverting input terminal of the operational amplifier 23f is grounded. An integrated signal is output from the operational amplifier 23 f to the sense amplifier 11. Other configurations of the ferroelectric memory according to the modification of the second embodiment are the same as those of the ferroelectric memory according to the second embodiment.

  Next, with reference to FIGS. 11 and 13, the operation of the ferroelectric memory according to the modification of the second embodiment will be described. In the ferroelectric memory according to the modification of the second embodiment, a differential signal corresponding to the data in the memory cell 1 is input to the integration circuit 23 in the read operation. The differential signal input to the integration circuit 23 is input to the inverting input terminal of the operational amplifier 23e via the resistor 23a. Thereby, the voltage waveform of the differential signal is integrated and the amplified signal is output from the operational amplifier 23e. This signal is a signal having a polarity obtained by inverting the polarity of the differential signal. Then, the signal is input to the inverting input terminal of the operational amplifier 23f through the resistor 23b. As a result, a signal having a polarity obtained by inverting the polarity of the output signal of the operational amplifier 23e is output from the operational amplifier 23f. Therefore, the integrating circuit 23 integrates and amplifies the voltage waveform of the differential signal, and outputs an integrated signal having the same polarity as the differential signal. Then, the output integration signal is input to the sense amplifier 11. Then, the sense amplifier 11 compares the voltage of the integration signal with the voltage of the reference signal, thereby determining data “1” or “0”. The other operations of the ferroelectric memory according to the modification of the second embodiment are the same as the operations of the ferroelectric memory according to the second embodiment.

  In the ferroelectric memory according to the modification of the second embodiment, as described above, the amplified integration signal is output from the integration circuit 23, so that the integration signal corresponding to the data “1” at the time of data discrimination is output. Since the difference between the voltage and the voltage of the integration signal corresponding to the data “0” becomes large, the data “1” or “0” can be easily discriminated by the sense amplifier 11.

(Third embodiment)
FIG. 14 is an equivalent circuit diagram showing the configuration of the ferroelectric memory according to the third embodiment of the present invention. The configuration of the ferroelectric memory according to the third embodiment of the present invention will be described with reference to FIG. In the ferroelectric memory according to the third embodiment, unlike the ferroelectric memory according to the first embodiment, an example applied to a 1T type (one transistor type) ferroelectric memory will be described.

  As shown in FIG. 14, the memory cell 31 of the ferroelectric memory according to the third embodiment includes a field effect transistor 32 and a ferroelectric capacitor 33. The field effect transistor 32 is an example of the “transistor” of the present invention, and the ferroelectric capacitor 33 is an example of the “memory means” and the “capacitor” of the present invention. The field effect transistor 32 is composed of an n-channel MOS transistor. The ferroelectric capacitor 33 includes a ferroelectric film. Further, a memory cell array 34 is configured by arranging a plurality of memory cells 31 in a matrix. One electrode of the ferroelectric capacitor 33 is connected to the gate of the field effect transistor 32, and the other electrode is connected to the electrode line 35. One of the source / drain of the field effect transistor 32 is connected to the voltage supply line 36, and the other is connected to the signal output line 37. A control line 38 for applying a voltage to the substrate on which the field effect transistor 32 is formed is provided. The other configuration of the ferroelectric memory according to the third embodiment is the same as that of the ferroelectric memory according to the first embodiment.

  FIG. 15 is a voltage waveform diagram for explaining a read operation of the ferroelectric memory according to the third embodiment of the present invention. Next, the operation of the ferroelectric memory according to the third embodiment will be described with reference to FIGS. In the following description, the state in which the ferroelectric capacitor 33 is polarized in the E direction in FIG. 14 is defined as data “0”, and the state in which the ferroelectric capacitor 33 is polarized in the F direction in FIG. 1 ”.

(Write operation)
When data “0” is written to the ferroelectric capacitor 33, a voltage of 0 V is applied to the electrode line 35 and a write voltage Vw (> 0 V) is applied to the control line 38. As a result, the ferroelectric capacitor 33 is polarized in the E direction in FIG. 14, and thus data “0” is written. On the other hand, when data “1” is written to the ferroelectric capacitor 33, a write voltage Vw is applied to the electrode line 35 and a voltage of 0 V is applied to the control line 38. As a result, the ferroelectric capacitor 33 is polarized in the F direction in FIG. 14, and thus data “1” is written. Then, after the data is written, the potential of the electrode line 35 is set to 0V. At this time, a predetermined amount of positive charge remains at the gate of the field effect transistor 32 connected to the ferroelectric capacitor 33. The amount of remaining positive charges is larger when the ferroelectric capacitor 33 holds data “1” than when it holds data “0”.

  Note that during the write operation, disturbance occurs in the memory cells 31 other than the memory cell 31 to which data is written. That is, the write voltage Vw is also applied to the other memory cells 31 via the electrode lines 35 or the control lines 38 connected to the memory cells 31 into which data is written. As a result, when an electric field in the direction opposite to the polarization direction of the ferroelectric capacitor 33 of the other memory cell 31 is applied, the amount of polarization of the ferroelectric capacitor 33 is reduced, resulting in disturbance.

(Read operation)
First, the read voltage Vr (> 0 V) is applied to the voltage supply line 36. When the data of the ferroelectric capacitor 33 is “1”, more positive charges remain at the gate of the field effect transistor 32 than when the data is “0”. , The field effect transistor 32 is turned on more strongly than in the case of data “0”. As a result, the current of the data signal output to the signal output line 37 via the field effect transistor 32 in the case of data “1” is larger than the current of the data signal in the case of data “0”. The data signal is input to the differentiation circuit 10 after the current is changed to a voltage by the resistor 9.

  The data signal input to the differentiating circuit 10 has a voltage waveform as shown in FIG. That is, both the data signals of data “1” and data “0” tend to gradually rise immediately after the read voltage Vr is applied. In addition, the rising slope (voltage change rate) of the data signal in the case of data “1” is larger than the rising slope (voltage change rate) of the data signal in the case of data “0”. The tendency of the voltage waveform of the data signal is the same when the disturb amount during the write operation is small or large. Then, the data signal is input to the differentiation circuit 10. Thereby, the differentiation circuit 10 outputs a differential signal obtained by differentiating the voltage waveform of the data signal. This differential signal has a voltage waveform as shown in FIG. That is, the voltage waveform of the differential signal shows a larger voltage peak in the case of data “1” than in the case of data “0”. Note that the voltage waveform of this differential signal shows the same tendency when the disturb amount during the write operation is small and when it is large.

  Then, the differential signal is input to the sense amplifier 11. Then, the voltage of the differential signal is compared with the voltage of the reference signal at a predetermined timing (determination timing) when the differential signal corresponding to the data “1” and the differential signal corresponding to the data “0” reach the peak. The data “1” or “0” is discriminated. At this determination timing, the voltage of the differential signal of data “1” becomes larger than the voltage of the differential signal of data “0” as shown in FIG. This is the same when the disturb amount is large or small in the write operation. Therefore, as shown in FIG. 15, when the disturb amount during the write operation is large, the voltage of the data signal and the voltage of the reference signal are reduced because the voltage of the data signal of data “1” becomes smaller than the voltage of the reference signal. In the conventional discrimination method for comparing the data “1” and “0”, the data can be discriminated based on the differential signal even when the data “1” or “0” cannot be discriminated. Other operations of the ferroelectric memory according to the third embodiment are the same as those of the ferroelectric memory according to the first embodiment.

  In the third embodiment, with the above-described configuration, in the 1T type ferroelectric memory, even when the disturb amount of the ferroelectric capacitor 33 changes, erroneous determination of data occurs in the read operation. Can be suppressed.

(Fourth embodiment)
FIG. 16 is an equivalent circuit diagram showing the configuration of the memory cell of the ferroelectric memory according to the fourth embodiment of the present invention. FIG. 17 is an equivalent circuit diagram for explaining the configuration of the ferroelectric memory according to the fourth embodiment of the present invention. FIG. 18 is an equivalent circuit diagram showing a configuration of a ferroelectric memory using the memory cell according to the fourth embodiment shown in FIG. A configuration of the ferroelectric memory according to the fourth embodiment will be described with reference to FIGS. In the fourth embodiment, in a 1T1C type memory cell having a single field effect transistor and a single ferroelectric capacitor, data is rewritten after a read operation accompanied by data destruction. Will be described.

  As shown in FIGS. 16 to 18, the memory cell 41 of the ferroelectric memory according to the fourth embodiment includes a single field effect transistor 42, a single ferroelectric capacitor 43, and a gate control terminal 44. It has. The field effect transistor 42 is an example of the “transistor” in the present invention, and the ferroelectric capacitor 43 is an example of the “memory means” and the “capacitor” in the present invention. The gate control terminal 44 is an example of the “terminal” in the present invention. As shown in FIG. 18, one of the source / drain of the field effect transistor 42 is connected to the resistor 9 and the differentiation circuit 10 having one end grounded, and the other is connected to the voltage supply line 46. ing. A control line 48 for applying a voltage to the substrate on which the field effect transistor 42 is formed is provided. One electrode of the ferroelectric capacitor 43 is connected to the gate of the field effect transistor 42, and one of the source / drain of the selection transistor 49 is connected to the other electrode. The other of the source / drain of the selection transistor 49 is connected to the bit line 50 and the gate is connected to the word line 51.

  In the fourth embodiment, the gate control terminal 44 is provided between the ferroelectric capacitor 43 and the gate of the field effect transistor 42. The gate control terminal 44 is provided to apply a predetermined voltage to the ferroelectric capacitor 43 when data is written and rewritten. The gate control terminal 44 is connected to the gate control line 52. The gate control line 52 is connected to a ferroelectric capacitor 43 of another memory cell 41 provided along the gate control line 52. Thereby, the field effect transistor 42 is shared by a plurality of memory cells 41 provided along the gate control line 52. That is, the field effect transistor 42 is provided only in the output stage of the ferroelectric memory according to the fourth embodiment. The memory cells 41 other than the output stage have a one-transistor one-capacitor configuration including a single selection transistor 49 and a single ferroelectric capacitor 43. The remaining configuration of the ferroelectric memory according to the fourth embodiment is similar to that of the ferroelectric memory according to the aforementioned first embodiment.

  Next, the operation of the ferroelectric memory according to the fourth embodiment will be described with reference to FIG. In the following description of the operation, the state in which the ferroelectric capacitor is polarized in the G direction in FIG. 18 is defined as data “0”, and the state in which the ferroelectric capacitor is polarized in the H direction in FIG. It is defined as “1”.

(Write operation)
In the write operation, first, a predetermined voltage is applied to the word line 51. As a result, all the select transistors 49 connected to the word line 51 are turned on. When data “0” is written to the ferroelectric capacitor 43, a voltage of 0 V is applied to the bit line 50 and a write voltage Vw (> 0 V) is applied to the gate control line 52. Thereby, the ferroelectric capacitor 43 is polarized in the G direction in FIG. Therefore, data “0” is written in the ferroelectric capacitor 43. On the other hand, when data “1” is written to the ferroelectric capacitor 43, a write voltage Vw is applied to the bit line 50 and a voltage of 0 V is applied to the gate control line 52. Thereby, the ferroelectric capacitor 43 is polarized in the H direction in FIG. Therefore, data “1” is written in the ferroelectric capacitor 43.

  When data is written, disturbance occurs in other memory cells 41 on the gate control line 52 connected to the memory cell 41 to which the data is written. For example, when data “0” is written in the ferroelectric capacitor 43 of a predetermined memory cell 41, the other memory cells 41 on the gate control line 52 connected to the memory cell 41 are also transferred from the gate control line 52 to the write voltage Vw. Is applied. In this case, an electric field in the G direction in FIG. 18 is applied to the ferroelectric capacitors 43 of the other memory cells 41. As a result, when the ferroelectric capacitor 43 holds the data “1” (polarization direction H), the amount of polarization of the ferroelectric capacitor 43 is reduced, resulting in disturbance.

(Read operation)
In the read operation, first, a predetermined voltage is applied to the word line 51. As a result, all the select transistors 49 connected to the word line 51 are turned on. Then, a read voltage Vr (> 0 V) is applied to the bit line 50. As a result, an electric field in the H direction in FIG. 18 is applied to the ferroelectric capacitor 43, and as a result, the ferroelectric capacitor 43 is polarized in the H direction in FIG. A positive charge corresponding to the amount of polarization of the ferroelectric capacitor 43 is induced at the gate of the field effect transistor 42. When the data held in the ferroelectric capacitor 43 is data “1” (polarization direction H), more positive charges are generated than the data “0” (polarization direction G). 42 gates. Thereby, when the data of the ferroelectric capacitor 43 is data “1”, the field effect transistor 42 is turned on more strongly than the case of data “0”. For this reason, in the case of data “1”, the current of the data signal output via the field effect transistor 42 becomes larger than in the case of data “0”. The output data signal is converted into a voltage by the resistor 9. The voltage waveform of the data signal converted into this voltage has the same shape as the voltage waveform (see FIG. 7) of the data signal of the ferroelectric memory according to the first embodiment. Then, when the data signal is input to the differentiation circuit 10, a differentiation signal obtained by differentiating the voltage waveform of the data signal is output from the differentiation circuit 10. Then, the sense amplifier 11 compares the voltage of the differential signal with the voltage of the reference signal to determine data “1” or “0”. The operation of the ferroelectric memory according to the fourth embodiment at this time is the same as the operation of the ferroelectric memory according to the first embodiment.

  In the ferroelectric memory according to the fourth embodiment, a voltage equal to or higher than the coercive voltage at which the polarization of the ferroelectric capacitor 43 is inverted is applied as the read voltage Vr. Thereby, when the ferroelectric capacitor 43 holds data “0” (polarization direction G), the data is destroyed and becomes data “1” (polarization direction H). For this reason, a rewrite operation is performed after the read operation. That is, after the read operation, the write voltage Vw is applied to the gate control line 52 and the voltage of 0 V is applied to the bit line 50. As a result, the ferroelectric capacitor 43 polarized in the H direction in FIG. 18 by the read operation is polarized in the G direction in FIG. 18, so that data “0” is rewritten in the ferroelectric capacitor 43.

  In the fourth embodiment, with the configuration described above, in a ferroelectric memory that performs a rewrite operation after a read operation, even when the disturb amount generated in the ferroelectric capacitor 43 changes, erroneous determination of data is possible. Generation | occurrence | production can be suppressed.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above description of the embodiments but by the scope of claims for patent, and further includes all modifications within the meaning and scope equivalent to the scope of claims for patent.

  For example, in the above-described embodiment, the ferroelectric capacitor is used as the storage unit. However, the present invention is not limited to this, and a storage unit other than the ferroelectric capacitor may be used.

  In the above-described embodiment, the data is discriminated by comparing the voltage of the differential signal of the data signal with the voltage of the reference signal using the sense amplifier. However, the present invention is not limited to this, and the predetermined comparison is performed. Using a circuit or the like, the initial slope of the data signal is stored, and then the data is discriminated by comparing the slope of the data signal after a predetermined period and the stored slope of the data signal at the initial stage of the rise. You may do it.

  In the fourth embodiment, a case where a one-transistor one-capacitor type memory cell including a single selection transistor and a single ferroelectric capacitor is used as a memory cell other than the output stage of the memory will be described as an example. However, the present invention is not limited to this, and memory cells having various configurations other than the one-transistor one-capacitor type may be used as memory cells other than the output stage.

1 is an equivalent circuit diagram showing a configuration of a memory cell of a ferroelectric memory according to a first embodiment of the present invention. FIG. 2 is an equivalent circuit diagram showing a configuration of a ferroelectric memory using the memory cell according to the first embodiment shown in FIG. 1. FIG. 3 is an equivalent circuit diagram showing a configuration of a differentiation circuit of the ferroelectric memory according to the first embodiment shown in FIG. 2. FIG. 3 is an equivalent circuit diagram showing a configuration of a sense amplifier of the ferroelectric memory according to the first embodiment shown in FIG. 2. FIG. 6 is a schematic diagram for explaining a polarization state during a write operation of the memory cell according to the first embodiment of the present invention. FIG. 5 is a schematic diagram for explaining a polarization state during a read operation of the memory cell according to the first embodiment of the present invention. FIG. 5 is a voltage waveform diagram for explaining a read operation of the memory cell according to the first embodiment of the present invention. FIG. 8 is a voltage waveform diagram corresponding to the data signal shown in FIG. 7. FIG. 8 is a voltage waveform diagram corresponding to the data signal shown in FIG. 7. FIG. 5 is an equivalent circuit diagram showing a configuration of a ferroelectric memory according to a modification of the first embodiment of the present invention. FIG. 5 is an equivalent circuit diagram showing a configuration of a ferroelectric memory according to a second embodiment of the present invention. FIG. 12 is an equivalent circuit diagram showing a configuration of an integrating circuit of the ferroelectric memory according to the second embodiment shown in FIG. 11. FIG. 10 is an equivalent circuit diagram showing a configuration of an integrating circuit of a ferroelectric memory according to a modification of the second embodiment of the present invention. It is the equivalent circuit schematic which showed the structure of the ferroelectric memory by 3rd Embodiment of this invention. It is a voltage waveform diagram for demonstrating read-out operation | movement of the ferroelectric memory by 3rd Embodiment of this invention. FIG. 6 is an equivalent circuit diagram showing a configuration of a memory cell of a ferroelectric memory according to a fourth embodiment of the present invention. It is an equivalent circuit diagram for demonstrating the structure of the ferroelectric memory by 4th Embodiment of this invention. FIG. 17 is an equivalent circuit diagram showing a configuration of a ferroelectric memory using the memory cell according to the fourth embodiment shown in FIG. 16. It is the equivalent circuit diagram which showed the structure of the memory cell of the ferroelectric memory by an example of the past. It is an equivalent circuit diagram showing a configuration of a memory cell of a conventional 1T2C type ferroelectric memory. It is a schematic diagram for explaining the polarization state during the write operation of a conventional 1T2C type memory cell. It is a schematic diagram for demonstrating the polarization state at the time of read-out operation | movement of the conventional 1T2C type | mold memory cell. It is a voltage waveform diagram for demonstrating the read-out operation | movement of the memory cell proposed conventionally.

Explanation of symbols

1, 31, 41 Memory cell 2, 32, 42 Field effect transistor (transistor)
3a, 3b, 33, 43 Ferroelectric capacitor (memory means, capacitor)
4, 34 Memory cell array 5a, 5b, 35 Electrode line 6, 36, 46 Voltage supply line 7, 37 Signal output line 8, 38, 48 Control line 9 Resistance 10 Differentiation circuit 11 Sense amplifier (first data discrimination circuit)
12 sense amplifier (second data discrimination circuit)
13, 23 Integration circuit 44 Gate control terminal (terminal)
49 selection transistor 50 bit line 51 word line 52 gate control line

Claims (8)

A memory cell including storage means for holding one of the first data and the second data;
A memory comprising: a first data discrimination circuit that discriminates the first data or the second data based on a change rate of the data signal read from the memory cell. A differential circuit that is connected between the memory cell and the first data determination circuit and outputs a differential signal of the data signal read from the memory cell;
The memory according to claim 1, wherein the first data discrimination circuit discriminates the first data or the second data based on the differential signal. The storage means includes a capacitor that holds one of the first data and the second data,
The memory cell includes a transistor having a gate to which the capacitor is connected and a pair of source / drain, and outputting the data signal corresponding to the data held by the capacitor,
The memory according to claim 1, wherein one of the source / drain of the transistor is connected to the first data determination circuit. The capacitor includes a first capacitor that is polarized in a predetermined direction in a write operation and a second capacitor that is polarized in a direction opposite to the predetermined direction in the write operation,
The memory according to claim 3, wherein the first capacitor and the second capacitor are connected to a gate of the transistor.   The first data discriminating circuit is configured such that the output signal of either the first data or the second data substantially rises and the other output signal of the first data or the second data is The memory according to claim 4, wherein the first data or the second data is discriminated at a timing during the rise. An integrating circuit connected between the differentiating circuit and the first data discriminating circuit and outputting an integrating signal of the differential signal;
The memory according to claim 2, wherein the first data determination circuit determines the first data or the second data based on the integration signal.   7. The apparatus according to claim 1, further comprising a second data determination circuit configured to determine the first data or the second data based on a change amount of the data signal read from the memory cell. The listed memory.   The memory according to claim 1, wherein the storage unit includes a ferroelectric capacitor having a ferroelectric film.

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