JP2005251273A5

JP2005251273A5 -

Info

Publication number: JP2005251273A5
Application number: JP2004059414A
Authority: JP
Filing date: 2004-03-03
Publication date: 2007-04-05

Claims

A memory cell array including a plurality of memory cells for storing data and a plurality of sub-word lines connected to the plurality of memory cells;
A sub word line driver for driving the plurality of sub word lines;
A reference memory cell array including a plurality of reference memory cells used for reading data and a plurality of reference read word lines connected to the plurality of reference memory cells;
A reference read word line driver for driving the plurality of reference read word lines;
The semiconductor memory device, wherein the sub word line driver and the reference read word line driver have the same circuit configuration.

The semiconductor memory device according to claim 1, wherein the sub word line driver and the reference read word line driver are controlled by a plurality of common sub decode signals.

The input relationship between the plurality of subdecode signals input to the subword line driver and the plurality of subdecode signals input to the reference read word line driver are interchanged with each other. Semiconductor memory device.

A main word line connected to an input terminal of the sub word line driver;
The semiconductor memory device according to claim 2, wherein the sub word line driver receives the sub decode signal after receiving an input signal from the main word line.

A read main word line connected to an input terminal of the reference read word line driver;
3. The semiconductor memory device according to claim 2, wherein the reference read word line driver receives the subdecode signal after receiving an input signal from the read main word line.

A plurality of memory cells storing data, and a memory cell array including a plurality of bit lines and a plurality of digit lines connected to the plurality of memory cells;
A bit line current selection circuit for selecting the plurality of bit lines;
The bit line current selection circuit includes a plurality of bit line current selection gates,
The plurality of bit line current selection gates are arranged to be shifted from each other in the direction of the bit line.

The bit line current selection circuit includes first and second bit line current selection circuits,
The first bit line current selection circuit has a first plurality of bit line current selection gates arranged to be shifted from each other in the direction of the bit line,
The semiconductor memory device according to claim 6, wherein the second bit line current selection circuit has a second plurality of bit line current selection gates arranged in the same manner as the first plurality of bit line current selection gates.

Further comprising a digit line current selection circuit for selecting the plurality of digit lines, the digit line current selection circuit including a plurality of digit line current selection gates;
The semiconductor memory device according to claim 6, wherein the plurality of digit line current selection gates are shifted from each other in the direction of the digit line.

A plurality of memory cells;
A plurality of reference memory cells for generating a reference value for data detection when reading data from the plurality of memory cells;
A plurality of bit line pairs that extend in a first direction in common to the plurality of memory cells and the plurality of reference memory cells;
A plurality of sub-word lines arranged extending in a second direction intersecting with the plurality of bit line pairs and provided corresponding to the plurality of memory cells;
A plurality of reference read word lines arranged extending in the second direction and provided corresponding to the plurality of reference memory cells;
A plurality of main word lines each extending in the second direction for each predetermined number of the sub word lines;
A plurality of read main word lines each extending in the second direction for each of the predetermined number of reference read word lines;
The first sub-word line is selected from the predetermined number of sub-word lines, and the first reference read word line is selected from the predetermined number of reference read word lines. A sub-decode line for transmitting a common sub-decode signal for selecting a word line;
A sub-word line driver that drives the first sub-word line selected by the signal from the main word line and the common sub-decode signal;
A semiconductor memory device comprising: a reference read word line driver that drives the first reference read word line selected by a signal from the read main word line and the common subdecode signal.

The semiconductor memory device according to claim 9, wherein each of the plurality of memory cells and the plurality of reference memory cells includes an access transistor and a TMR element, and stores data according to a change in a resistance value of the TMR element.

The memory cell selected by the first sub-word line is connected to the first bit line of the bit line pair,
10. The semiconductor memory device according to claim 9, wherein the reference memory cell selected by the first reference read word line is connected to a second bit line paired with the first bit line.

12. The semiconductor memory device according to claim 11, wherein the activation of the common subdecode signal is slower than the activation of the selected main word line and read main word line.