JP2005250619A5 - - Google Patents

Claims (6)

A memory controller that writes data to a nonvolatile memory composed of a plurality of physical blocks in accordance with an external access instruction,
An area dividing unit that divides the nonvolatile memory into a first physical block group and a second physical block group that has a slower write time or erase time than the first physical block group;
A read / write controller that performs control to write data from the outside to the first physical block group of the nonvolatile memory;
A speed guarantee rank holding unit for holding parameters for guaranteeing the data writing speed;
Having a memory controller. The area dividing unit performs a measurement test of a time required for writing or erasing the plurality of physical blocks of the nonvolatile memory in advance, and a physical block having a short time with respect to a predetermined threshold is set as the first physical block group 2. The memory controller according to claim 1, wherein a region of the nonvolatile memory is divided by using a long-time physical block as the second physical block group. A write data determination unit for classifying the type of data from the outside;
3. The memory controller according to claim 1, wherein the data determined by the write data determination unit as data that does not require a speed guarantee is written to the second physical block group. 4. A non-volatile memory composed of a plurality of physical blocks;
A non-volatile memory device comprising the memory controller according to claim 1. The nonvolatile memory device according to claim 4, wherein the memory controller further writes system information that cannot be accessed from the outside to the second physical block group. A non-volatile storage device comprising a non-volatile memory comprising a plurality of physical blocks and the memory controller according to claim 1;
A host device that gives an external access instruction to the nonvolatile storage device;
A non-volatile memory system.