JP2005243006A5 - - Google Patents

Claims (6)

A central processing circuit including a plurality of units and a control circuit, an antenna, a power supply circuit, and a clock generation circuit;
The control circuit is one or more selected from the plurality of units based on a power supply signal including information on power supply by the antenna and a load signal obtained from an event signal supplied from each of the plurality of units. A first control signal for stopping power supplied to the second control signal, a second control signal for changing a power supply potential supplied to one or a plurality selected from the plurality of units, one or a plurality selected from the plurality of units One or more selected from the third control signal for stopping the supply of the clock signal to is output to one or both of the power supply circuit and the clock generation circuit. A central processing circuit including a plurality of units and a control circuit, an antenna, a power supply circuit, a clock generation circuit, a first switch provided between the plurality of units and the power supply circuit, and the plurality of units and the clock generation circuit; A second switch provided between
The control circuit is one or more selected from the plurality of units based on a power supply signal including information on power supply by the antenna and a load signal obtained from an event signal supplied from each of the plurality of units. A first control signal for stopping power supplied to the second control signal, a second control signal for changing a power supply potential supplied to one or a plurality selected from the plurality of units, one or a plurality selected from the plurality of units One or more selected from the third control signal for stopping the supply of the clock signal to is output to one or both of the first switch and the second switch. In claim 1 or claim 2 ,
Having a glass substrate,
The plurality of units and the control circuit are provided on the glass substrate. In claim 1 or claim 2 ,
Have a flexible substrate,
The plurality of units and the control circuit are provided on the flexible substrate. In any one of claims 1 to 4,
The plurality of units are a plurality selected from a bus interface, a data cache, an instruction decoder, a reservation station, an instruction cache, an integer arithmetic unit, a floating point unit, a branch unit, a load / store unit, and a general-purpose register. Semiconductor device. In any one of claims 1 to 4,
The semiconductor device, wherein the plurality of units are a plurality selected from a pipeline unit, a peripheral memory controller, and a peripheral bus controller.