JP2005242412A - Interface control device, method, and program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To further easily transfer data on ATA standards even in a drive having a plurality of pickups. <P>SOLUTION: When it is determined that crowd control processing for OP1 is executed without executing crowd control processing for OP0 in step S346, a crowd processing part advances processing to step S348 to execute the crowd control processing for OP1. When the crowd control processing for OP1 is executed, and the processing is terminated, the crowd processing part returns the processing to step S342, and repeats the processing that follows to control the next crowd processing (including the crowd processing of unprocessed OP0 corresponding to the crowd processing of OP1 controlled this time). <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an interface control apparatus and method, and a program, and more particularly, to an interface control apparatus and method suitable for use in an interface of an ATA device, and a program.

  Conventionally, IDE (Integrated Drive Electronics) has been used as an interface between a hard disk and a host. The IDE is a specification of a hard disk interface for PC / AT (Personal Computer / Advanced Technology) compatible machines. The IDE signal line uses the ISA (Industry Standard Architecture) bus standardized as a specification for PC / AT compatible machines as it is, and there is a simple address decoder and buffer for connecting the hard disk to the host. The IDE controller can be developed at a lower price compared to the standard hard disk interface SCSI (Small Computer System Interface) controller in general. It was effectively standardized as a hard disk interface specification for PC / AT compatible machines. This IDE was later expanded to the Enhanced IDE for the purpose of improving transfer speed, increasing the capacity limit, and increasing the number of connected devices.

  However, since there was no clear standard in the early IDEs, each drive manufacturer expanded its own functions, causing compatibility problems between different manufacturers.

  Therefore, ANSI (AT Attachment Interface) using this IDE was established as a standard by the American National Standards Institute (ANSI). This standard is currently managed by a group called ANSI X3T92, which standardizes SCSI (Small Computer System Interface). This ATA has also been improved and expanded, from the initial ATA-1 to new ones like ATA-2, ATA-3, ATA-4, ATA-5, ATA-6, ATA-7, Serial ATA. Standards have been established. For example, the maximum data transfer rate is 8.33MB / s for ATA-1, 16.7MB / s for ATA-2 and ATA-3, 33.3MB / s for ATA-4, 66.7MB / s for ATA-5, ATA- 6 is 100 MB / s, ATA-7 is 133 MB / s, and Serial ATA is 150 MB / s.

  As a standard for packet interfaces for connecting devices other than hard disks, such as CD-ROM (Compact Disc-Read Only Memory), to the IDE controller used for such a standard, ATAPI (ATA Pachet Interface) was established. ATAPI can convert SCSI commands to ATA commands, making it relatively easy to develop CD-ROM drives that do not require expensive SCSI interfaces. This ATAPI was originally a standard independent of ATA, but since the ATA-4 standard, they have been unified. Therefore, ATA-4 is also called ATA / ATAPI-4. Therefore, in the following, devices other than hard disks such as CD-ROM are also referred to as ATA devices.

  In such a standard, in order to increase the data transfer speed, for example, the PIO transfer (Program I / O transfer) in which the CPU controls the data transfer and the DMA (Direct Memory Access transfer) controller control the data transfer. Single word DMA transfer in which one data is transferred by one process, Multiword DMA transfer in which a DMA controller controls data transfer and multiple data are transferred in one process, and higher speed data transfer Various transfer methods such as UltraDMA transfer are used (for example, see Non-Patent Document 1).

  FIG. 1 is a diagram for explaining an example of data transfer in the PIO transfer method.

  In FIG. 1, a CPU (Central Processing Unit) 1 is connected to an SDRAM (Synchronous Dynamic Random Access Memory) 2 via a bus 3. In addition, ATA host hardware 4 including an IDE controller is connected to the bus 3, and a drive 5 that is an ATA device is further connected to the ATA host hardware 4. In such an apparatus, for example, data held in the SDRAM 2 is transferred to the drive 5 and written to a recording medium (not shown) (for example, a CD (Compact Disc) or a DVD (Digital Versatile Disc)) mounted on the drive 5. In some cases, or conversely, when data recorded on the recording medium is read and transferred to the SDRAM 2, in the PIO transfer method, the CPU directly controls the data transfer process.

  That is, the CPU 1 executes, for example, an IN / OUT instruction, accesses the ATA register of the ATA host hardware 4, executes the MOV instruction, and reads / writes the buffer memory space of the ATA host hardware 4. The CPU 1 repeats such an operation by executing the LOOP instruction.

  That is, as shown by the double arrows 6 and 7, when the data transfer occurs, the CPU 1 accesses the SDRAM 2 and the ATA host hardware 4 and performs processing related to the data transfer. The drive 5 is accessed by the ATA host hardware 4 based on a command from the CPU 1 as indicated by a double arrow 8. Therefore, as shown in FIG. 2, the CPU 1 accesses the ATA host hardware 4 (and SDRAM 2) for each transfer processing unit (for each register) and instructs processing. The ATA host hardware 4 accesses the register (PIO) 9 based on an instruction from the CPU 1 and processes one register for one instruction from the CPU 1. In FIG. 2, the processing related to the five registers on the left in the drawing shows an example of writing processing to the recording medium, and the processing related to the five registers on the right in the drawing is an example of reading processing from the recording medium. It is shown. As shown in FIG. 2, in the case of reading from the recording medium, processing related to the read data is required. Therefore, the number of communication between the CPU 1 and the ATA host hardware 4 is compared with the number of reading to the recording medium. Double.

  As described above, in the case of the PIO transfer method, since the CPU 1 directly controls data transfer, the bus 3 is frequently used in addition to actual data transfer such as access to each device or instruction fetch by the CPU 1. Become. In this case, the CPU 1 must frequently execute processing for data transfer. Therefore, the processing load related to data transfer is increased, and it is difficult to improve the data transfer speed.

  Therefore, in ATA-2 and ATA-3, a single word DMA transfer system and a multiword DMA transfer system are adopted. FIG. 3 shows an example of data transfer in the case of the single word DMA transfer system and the multiword DMA transfer system. In the following, when there is no need to distinguish between the single word DMA transfer method and the multiword DMA transfer method, the single word DMA transfer method is referred to as a single word / multiword DMA transfer method.

  As shown in FIG. 3, in the case of the single word / multiword DMA transfer method, the data transfer is controlled not by the CPU 1 but by the DMA 11 which is the DMA controller. The DMA 11 is connected to the bus 3 in the same manner as the CPU 1 and the like, and accesses the SDRAM 2 and the ATA host hardware 4 instead of the CPU 1 and controls the transfer process as indicated by the double arrow 12 and double arrow 13. . By doing so, in the case of the single word / multiword DMA transfer system, the CPU 1 is not burdened by data transfer, and the load on the CPU 1 can be reduced.

  In order to further increase the speed, the UltraDMA transfer method is adopted after ATA-4. In the case of the UltraDMA transfer method, as shown in FIG. 4, the DMA 15 that is a DMA controller built in the ATA host hardware 14 that becomes the bus master on the bus 3 controls the data transfer. That is, the data transfer via the bus 3 becomes the data transfer itself by a normal bus master, and only the access to the SDRAM 2 by the ATA host hardware 14 as indicated by the double arrow 16. At this time, of course, the CPU 1 does not control the transfer process. By doing so, the load on the CPU 1 and the bus 3 during data transfer is reduced.

  FIG. 5 is a diagram schematically showing an example of access by the CPU 1 when the PIO transfer method and the UltraDMA transfer method are combined.

  As shown in FIG. 5, the host hardware 4 accesses the register (PIO) 17 in the case of the PIO transfer method, executes the processing held in the register (PIO) 17, and in the case of the UltraDMA transfer method, the register (DMA) 18 is accessed, and the processing held in register (DMA) 18 is executed. As described above, in the case of the PIO transfer method, the ATA host hardware 4 executes one process of the register (PIO) 17 based on one instruction of the CPU 1, so the CPU 1 accesses for each data transfer processing unit. However, in the case of the UltraDMA transfer method, the ATA host hardware 4 can execute a plurality of processes held in the register (DMA) 18 by a single instruction from the CPU 1, so that data transfer is possible. A plurality of processing unit data can be transferred continuously. Accordingly, the number of accesses to the ATA host hardware 4 by the CPU 1 decreases.

"Thorough research on ATA (IDE) / ATAPI", CQ Publisher, P30-P33

  In recent years, on the ATA standard, various interface control methods involving such complicated processing have been proposed as standards. However, in the ATA standard, the number of pickups of the ATA device is one, and there is a problem that a device having a plurality of pickups cannot be controlled by the ATA.

  On the other hand, it is conceivable to control a drive having a plurality of pickups by using a unique protocol, but in this case, the versatility of the interface of the drive is reduced, and there is a possibility that it cannot be connected to another device. .

  The present invention has been made in view of such a situation, and enables even a drive having a plurality of pickups to more easily transfer data on the ATA standard. .

  The interface control apparatus according to the present invention corresponds to each PRD table based on each of a plurality of PRD tables in which related information of data transfer performed between the ATA device and an external storage unit of the ATA device is described. Parallel branching means for branching the PRD process, which is a process related to data transfer, for each pickup corresponding to each PRD table, and a control means for controlling the progress of each PRD process branched in parallel by the parallel branching means Features.

  The PRD process is composed of a plurality of phases including a plurality of processes related to data transfer, and the control means advances the PRD process at the end or start of a predetermined phase among the plurality of phases included in the PRD process. By switching the pickups, the PRD process corresponding to each pickup can be advanced in parallel.

  The control means starts the first phase of the PRD process for performing the next read process after the last phase of the PRD process for performing the write process for each pickup and performs the read process for each pickup. After the last phase of the PRD process is completed, the first phase of the PRD process for performing the next writing process can be started.

  The control means can switch the pickup for processing at either the end of the phase for performing data transfer or the end of the phase for performing status reporting in the PRD processing for performing the writing processing. .

  The control means can switch a pickup to be processed at the start of a phase of issuing a command instructing data transfer in a PRD process for performing a read process.

  The control means starts the first phase of the PRD process for performing the next reading process after the last phase of the PRD process for performing the writing process for all the pickups and performs the reading process for all the pickups. After the last phase of the PRD process is completed, the first phase of the PRD process for performing the next writing process can be started.

  The control means can switch the pickup for processing at either the end of the phase for performing data transfer or the end of the phase for performing status reporting in the PRD processing for performing the writing processing. .

  The control means switches the pickup to perform processing at either the end of the phase of issuing the command instructing the reading process of the PRD processing that performs the reading process or the phase of performing the status report. Can be.

  Controls permission or prohibition of data transfer by the PRD process, and gives permission for data transfer to the PRD process corresponding to any one of all pickups, and PRD process corresponding to other pickups If the data transfer is prohibited in the PRD process of the pickup that gave the data transfer permission, the pickup that permits the data transfer is switched and the data transfer is switched when the pickup to be processed is switched. When the PRD process of the pickup that has been prohibited is completed, the data transfer control means is further provided for controlling the PRD process so that the data transfer permission is not given. The control means performs the process by the data transfer control means. If data transfer permission is not granted for the PRD process to which the pickup is switched, PRD Without progress management, it is possible to switch the pickup again performs processing.

  The interface control method of the present invention corresponds to each PRD table based on each of a plurality of PRD tables in which related information of data transfer performed between the ATA device and an external storage unit of the ATA device is described. The PRD process, which is a process related to data transfer, includes a parallel branch step that branches in parallel for each pickup corresponding to each PRD table, and a control step that controls the progress of each PRD process branched in parallel by the parallel branch step process. It is characterized by that.

  The program of the present invention performs data transfer corresponding to each PRD table based on each of a plurality of PRD tables in which related information of data transfer performed between the ATA device and an external storage unit of the ATA device is described. PRD processing, which is processing related to each PRD table, executes in a computer a parallel branch step for branching in parallel for each pickup corresponding to each PRD table, and a control step for controlling the progress of each PRD process branched in parallel by the processing of the parallel branch step Let

  In the interface control apparatus and method of the present invention, and the program, based on each of a plurality of PRD tables in which related information of data transfer performed between the ATA device and an external storage unit of the ATA device is described. The PRD process, which is a process related to data transfer corresponding to each PRD table, is branched in parallel for each pickup corresponding to each PRD table, and the progress of each PRD process branched in parallel is controlled.

  According to the present invention, data transfer can be controlled. In particular, even a drive having a plurality of pickups can more easily transfer data according to the ATA standard.

  Embodiments of the present invention will be described below. Correspondences between constituent elements described in the claims and specific examples in the embodiments of the present invention are exemplified as follows. This description is to confirm that specific examples supporting the invention described in the claims are described in the embodiments of the invention. Therefore, even if there are specific examples that are described in the embodiment of the invention but are not described here as corresponding to the configuration requirements, the specific examples are not included in the configuration. It does not mean that it does not correspond to a requirement. On the contrary, even if a specific example is described here as corresponding to a configuration requirement, this means that the specific example does not correspond to a configuration requirement other than the configuration requirement. not.

  Further, this description does not mean that all the inventions corresponding to the specific examples described in the embodiments of the invention are described in the claims. In other words, this description is an invention corresponding to the specific example described in the embodiment of the invention, and the existence of an invention not described in the claims of this application, that is, in the future, a divisional application will be made. Nor does it deny the existence of an invention added by amendment.

  In the present invention, an interface control apparatus (for example, an interface control apparatus whose internal configuration example is shown in FIG. 6) for controlling an interface of an ATA device (for example, the drive 22 in FIG. 6) having a plurality of pickups is provided. . In this interface control apparatus, a plurality of PRD tables (for example, FIG. 13) describing information related to data transfer performed between the ATA device and a storage unit (for example, the SDRAM 24 in FIG. 6) outside the ATA device. Based on each of the PRD tables), PRD processing (for example, PRD processing 451 to 457 in FIG. 56) that is processing related to data transfer corresponding to each PRD table is branched in parallel for each pickup corresponding to each PRD table. 62. A branching unit (for example, step S346 in FIG. 62) and a control unit (for example, step S347 and step S348 in FIG. 62) for controlling the progress of each PRD process branched in parallel by the parallel branching unit. To do.

  The PRD process is composed of a plurality of phases (for example, a first phase to a sixth phase) consisting of a plurality of processes related to data transfer, and the control means is a predetermined one of a plurality of phases included in the PRD process. By switching the pickup that advances the PRD process at the end or start of the phase, the PRD process corresponding to each pickup can be advanced in parallel.

  The control means starts the first phase of the PRD process for performing the next read process after the last phase of the PRD process for performing the write process for each pickup and performs the read process for each pickup. After the end of the last phase of the PRD process, the first phase of the PRD process for performing the next write process can be started (for example, the cloud process 471 in FIG. 56).

  The control means switches a pickup to be processed at either the end of the phase (R) for performing data transfer or the end of the phase (S) for performing status reporting in the PRD process for performing the writing process. (For example, “Write” in FIG. 57).

  The control means can switch the pickup to be processed (for example, FIG. 59) at the start of the phase of issuing the command (D) for instructing data transfer in the PRD process for performing the reading process.

  The control means starts the first phase of the PRD process for performing the next reading process after the last phase of the PRD process (for example, FIG. 69) for performing the writing process of all the pickups is completed. It is possible to start the first phase of the PRD process for performing the next writing process after the last phase of the PRD process for performing the reading process of the pickup is completed.

  The control means switches the pickup to perform processing at either the end of the phase of performing data transfer or the end of the phase of performing status reporting of the PRD processing that performs writing processing (for example, FIG. 70). Can be.

  The control means switches the pickup to be processed at either the end of the phase of issuing the command for instructing the read process or the end of the phase of performing the status report in the PRD process for performing the read process ( For example, as shown in FIG.

  Controls permission or prohibition of data transfer by the PRD process (Data transfer permission / prohibition in FIG. 71), and grants data transfer permission to the PRD process corresponding to any one of the pickups. Data transfer is prohibited for PRD processing corresponding to other pickups, and when data transfer is performed in the PRD processing of a pickup that is permitted to transfer data, data transfer is performed when the pickup to be processed is switched. When the pickup that permits the data transfer is switched and the PRD process of the pickup for which the data transfer is prohibited is completed, the data transfer control means (for example, the cloud in FIG. A processing unit 441), and the control means includes a pickup for performing processing by the data transfer control means. If the data transfer permission is not given to the replacement PRD process, the pickup to be processed is switched again (for example, step S447 in FIG. 73) without proceeding with the PRD process. it can.

  In the present invention, an interface control method for an interface control apparatus (for example, an interface control apparatus whose internal configuration example is shown in FIG. 6) for controlling the interface of an ATA device having a plurality of pickups (for example, the drive 22 in FIG. 6). Is provided. This interface control method is based on each of a plurality of PRD tables in which information related to data transfer performed between an ATA device and a storage unit external to the ATA device (for example, SDRAM 24 in FIG. 6) is described. The PRD process, which is a process related to data transfer corresponding to each PRD table, was branched in parallel by the parallel branch step (step S346 in FIG. 62) for branching in parallel for each pickup corresponding to each PRD table and the parallel branch step process. Control steps (step S347 and step 348 in FIG. 62) for controlling the progress of each PRD process.

  In the present invention, there is provided a program for causing a computer (for example, an interface control device whose internal configuration example is shown in FIG. 6) to perform interface control processing for controlling the interface of the ATA device (for example, the drive 22 of FIG. 6). Is done. This program is based on each PRD table based on each of a plurality of PRD tables in which information related to data transfer performed between the ATA device and an external storage unit of the ATA device (for example, the SDRAM 24 in FIG. 6) is described. A parallel branch step (step S346 in FIG. 62) for branching the PRD process, which is a process related to data transfer corresponding to the table, in parallel for each pickup corresponding to each PRD table, and each PRD branched in parallel by the process of the parallel branch step Control steps (step S347 and step 348 in FIG. 62) for controlling the progress of the process.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 6 shows a configuration example of ATA host hardware of an ATA (AT Attachment interface) interface control device to which the present invention is applied.

  The ATA interface control device shown in FIG. 6 is, for example, a video device such as a video data recording / playback device, and the ATA host hardware 21 is configured as an IDE (Integrated Drive Electronics) controller of a drive 22 that is an ATA device. For example, the device is connected to a CPU (Central Processing Unit) 23 via a bus 42 such as a PCI (Peripheral Components Interconnect bus) bus and is also connected to an SDRAM (Synchronous Dynamic Random Access) via a bus 41 similar to the bus 42. Memory) 24. The ATA host hardware 21 is controlled by the CPU 23 and controls data transfer between the SDRAM 24 and the drive 22 by using a method compliant with the ATA standard. For example, the data held by the SDRAM 24 is acquired and stored in the drive 22. Write to a recording medium such as a mounted CD (Compact Disc) or DVD (Digital Versatile Disc), read data recorded on a recording medium mounted on the drive 22, supply it to the SDRAM 24, and hold it To do.

  The ATA host hardware 21 is controlled by the CPU 23, and controls the operation of the entire ATA host hardware 21, an ATA host 31, an ATA host 31, a through PIO (Program I / O transfer) control unit 33, and an IDMA (Intelligence Direct Memory Access). transfer) A bus 32 for connecting to the control unit 37, a through PIO control unit 33 for controlling transfer processing in a through PIO transfer mode, which will be described later, and a process for one PIO script held in an SRAM (Static Random Access Memory) 52 A single PIO script processing unit 34 for executing PIO, a PIO execution unit 35 for executing processing relating to the PIO transfer mode, an ATA interface processing unit 36 connected to the drive 22 for performing interface processing of the drive 22, and transfer in an IDMA transfer mode to be described later IDMA control unit 37 that controls processing, IDMA PIO control unit 38 that controls processing related to PIO transfer in the IDMA transfer mode, And composed of a DMA execution unit 39 for executing the processing related DMA transfer IDMA transfer mode.

  The ATA host 31 includes an input / output control unit 51, an SRAM 52, and a register 53 that are connected to the CPU 23 via the bus 42. The input / output control unit 51 controls communication with the CPU 23 performed via the bus 42, for example, supplies and holds information supplied from the CPU 23 to the SRAM 52 and the register 53, and stores information such as processing results in the CPU 23. Or supply. As will be described later, the SRAM 52 holds information related to data transfer processing supplied from the CPU 23 via the input / output control unit 51, and stores the information via the bus 32 as necessary via the through PIO control unit 33 or To the IDMA control unit 37. As will be described later, the register 53 holds setting information related to ATA host hardware and data transfer processing supplied from the CPU 23 via the input / output control unit 51, and stores the information via the bus 32 as necessary. To the through PIO control unit 33 and the IDMA control unit 37.

  The through PIO control unit 33 obtains necessary information from the SRAM 52 and the register 53 when the CPU 23 instructs the data transfer in the through PIO transfer mode in which the transfer processing in the PIO transfer mode is continuously executed. The script processing unit 34 is controlled to execute data transfer processing in the through PIO transfer mode.

  The single PIO script processing unit 34 is controlled by the through PIO control unit 33 and the IDMA PIO control unit 38, processes the supplied PIO scripts one by one, and executes PIO processing related to the PIO transfer mode included in the PIO script. This is executed by the unit 35.

  The PIO execution unit 35 is controlled by the PIO script processing unit 34, accesses the drive 22 via the ATA interface processing unit 36, and executes processing related to the requested PIO transfer mode.

  The ATA interface processing unit 36 receives access to the drive 22 from the PIO execution unit 35 and the DMA execution unit 39 and supplies it to the drive 22 or requests data read from the recording medium mounted on the drive 22. To the original PIO execution unit 35 and DMA execution unit 39.

  When the CPU 23 instructs the data transfer processing in the IDMA transfer mode in which the data transfer processing in the PIO transfer mode and the data transfer processing in the DMA transfer mode are successively executed by the CPU 23, the necessary information is transmitted from the SRAM 52 and the register 53. And the IDMA PIO processing unit 38 and the DMA execution unit 39 are controlled to execute the data transfer processing in the IDMA transfer mode.

  The IDMA PIO processing unit 38 is controlled by the IDMA control unit 37 and controls the processing related to the PIO transfer mode in the IDMA transfer mode by controlling the single PIO script processing unit 34.

  The DMA execution unit 39 is controlled by the IDMA control unit 37 and executes processing related to the DMA transfer mode in the IDMA transfer mode. That is, the SDRAM 24 is connected to the DMA execution unit 39 via the bus 41, and data exchange between the SDRAM 24 and the ATA interface processing unit 36 (drive 22) is controlled without using the CPU 23.

  That is, the ATA host hardware 21 performs data transfer in two modes, a through PIO transfer mode and an IDMA transfer mode. Although the details of each mode will be described later, the relationship between each part of the ATA host hardware 21 is hierarchized so as to correspond to the hierarchized processing of the through PIO transfer mode and the IDMA transfer mode.

  Such a configuration can be applied to devices other than video equipment. For example, a general-purpose personal computer called a PC / AT (Personal Computer / Advanced Technology) compatible machine uses ATA as an interface standard. Any device can be applied.

  In the above description, the ATA host hardware 21, the drive 22, the CPU 23, and the SDRAM 24 are described as processing units constituting one device. However, the present invention is not limited to this, and the above-described units are different devices. Alternatively, some of the above-described units may be configured as separate bodies. For example, the ATA host hardware 21, the CPU 23, and the SDRAM 24 may be configured as an ATA interface control device, and the drive 22 may be an external device connected to the ATA interface control device, or the ATA host hardware 21 may be an ATA interface. The controller 22 may be a recording / playback device, the CPU 23 may be a control device, the SDRAM 24 may be configured as a data storage device, and the devices may be connected based on ATA standards.

  FIG. 7 is a schematic diagram for explaining the state transition in the data transfer process of the ATA host hardware 21 of FIG.

  When the power is turned on, the ATA host hardware 21 shifts to an ATA device reset (Reset) mode 61 and resets (initializes) the drive 22 that is an ATA device. Specifically, the ATA host 31 accesses the drive 22 via the ATA interface processing unit 36 and initializes the state of the drive 22. When the device reset is completed (device reset is completed), the ATA host hardware 21 shifts to the standby mode (IDLE) 62 and waits until an instruction to start the transfer process from the CPU 23 is received.

  The transfer processing mode executed by the ATA host hardware 21 includes a through PIO transfer mode (through PIO) 63 that continuously executes data transfer in the PIO transfer mode, data transfer in the PIO transfer mode, and data in the DMA transfer mode. There is an IDMA transfer mode (IDMA) 64 that continuously executes at least one of the transfers.

  When the data transfer in the through PIO transfer mode is instructed by the CPU 23 (through PIO Start), the ATA host hardware 21 shifts to the normal mode (Normal) 71 of the through PIO transfer mode 63 and based on a PIO script described later. Execute PIO processing. In the PIO processing, when an instruction to add a PIO script is given, the ATA host hardware 21 performs acquisition processing of a semaphore that is a flag for synchronizing processes operating in parallel, and acquires the semaphore ( Semaphore acquisition), PIO script addition mode (PIO script addition) 72 is entered, and an additional process for holding the PIO script supplied from the CPU 23 in the SRAM 52 is performed. When the PIO script addition process ends, the ATA host hardware 21 returns the acquired semaphore (semaphore return), shifts to the normal mode 71, and executes the PIO process.

  Note that while the ATA host hardware 21 shifts to the PIO script addition mode 72 and performs the addition process of the PIO script supplied from the CPU 23, the PIO process being executed in the normal mode 71 is continued. In such a case, the PIO process is paused when one process is completed without being interrupted.

  Further, when the ATA host hardware 21 performs a PIO process in the normal mode 71 and a pause request is generated by, for example, a read process or an instruction from another program (Read Reg value, other program Pause), The system shifts to a pause mode (Pause) 73 and pauses PIO processing. When a temporary stop release request is generated, the ATA host hardware 21 releases the temporary stop (pause release), and shifts to the normal mode 71.

  When all the PIO processes are completed in the normal mode 71, the ATA host hardware 21 normally ends the through PIO mode 63 (normal end), and shifts to the standby mode 62.

  Further, when a forced termination request is generated in the normal mode 71 or the pause mode 73 (Abort instruction), the ATA host hardware 21 shifts to the forced termination mode (Abort) 74 and performs a forced termination process based on the request. Then, the through PIO mode 63 is abnormally terminated (abnormal termination), and the standby mode 62 is entered.

  In the standby mode 62, when data transfer in the IDMA transfer mode is instructed by the CPU 23 (IDMA Start), the ATA host hardware 21 shifts to the normal mode (Normal) 81 of the IDMA transfer mode 64, and the PRD table to be described later. A PRD process, which is a process related to data transfer in the IDMA transfer mode based on, is executed. In the PRD process, when an instruction to add a PRD table is given, the ATA host hardware 21 performs a semaphore acquisition process. When the semaphore is acquired (semaphore acquisition), the PRD table addition mode (PRD table addition) 82 is entered. Then, an additional process for holding the PRD table supplied from the CPU 23 in the SRAM 52 is performed. When the PRD table addition process ends, the ATA host hardware 21 returns the acquired semaphore (semaphore return), shifts to the normal mode 81, and executes the PRD process.

  Note that while the ATA host hardware 21 shifts to the PRD table addition mode 82 and performs the process of adding the PRD table supplied from the CPU 23, the PRD process being executed in the normal mode 81 is continued. In such a case, the PRD process is paused when one process is completed without being interrupted.

  Further, during execution of the PRD process in the normal mode 81, the ATA host hardware 21 generates a pause request (Read Reg value, other program Pause), for example, by a read process or an instruction from another program. The process shifts to a pause mode (Pause) 83 to pause the PRD process. When a temporary stop release request is generated, the ATA host hardware 21 releases the temporary stop (pause release) and shifts to the normal mode 81.

  In the normal mode 81, when all the PRD processes are completed, the ATA host hardware 21 ends the IDMA mode 64 normally (normal end) and shifts to the standby mode 62.

  Further, when a forced termination request is generated in the normal mode 81 or the pause mode 83 (Abort instruction), the ATA host hardware 21 shifts to the forced termination mode (Abort) 84 and performs a forced termination process based on the request. The IDMA mode 64 is abnormally terminated (abnormal termination), and the standby mode 62 is entered.

  As described above, the ATA host hardware 21 shifts to each mode for each process, and executes the process of the shifted mode. Such mode transition is executed under the control of the ATA host 31. The ATA host 31 shifts the mode based on an instruction supplied from the CPU 23. An instruction command, status, data, and the like related to data transfer from the CPU 23 are held in the SRAM 52 and the register 53. Each unit of the ATA host hardware 21 executes various processes based on the information held in the SRAM 52 and the register 53.

  FIG. 8 is a diagram illustrating a configuration example of data held in the SRAM 52 and the register 53. Since the SRAM 52 and the register 53 are actually configured as one RAM (Random Access Memory) and configured as a part of the storage area of the RAM, in the following, the SRAM 52 and the register are not connected to each other in the RAM (not shown). This will be described as a different area.

  As shown in FIG. 8, the SRAM 52 includes a 128-byte area 101 at addresses 0x0000 to 0x007F, a 32-byte area 102 at addresses 0x0080 to 0x009F, a 32-byte area 103 at addresses 0x00A0 to 0x00BF, and 32 at addresses 0x00C0 to 0x00DF. A byte area 104, a 32-byte area 105 having addresses 0x00EO to 0x00FF, a 256-byte area 106 having addresses 0x0100 to 0x01FF, and a 512-byte area 107 having addresses 0x0200 to 0x03FF are included.

  In the area 101, 32 through PIO scripts, which are PIO scripts for 4-byte through PIO, are described. In the area 102, eight 4-byte PIO CPU interrupt factor generation conditions or eight 4-byte read repetition / IfGoto condition tables are described. Further, in the area 103, two 4 byte read repetition / IfGoto condition tables are described.

  The area 104 is configured as a User addition register and holds two 4-byte calculation results. The area 105 is an extension area of the area 106 in which the IDMA PRD table or the SDRAM address additional setting table is described. In the area 107, a PIO script for IDMA is described.

  The register 53 includes a 128-byte area 111 at addresses 0x0400 to 0x043F, a 16-byte area 112 at addresses 0x0440 to 0x047F, a 16-byte area 113 at addresses 0x0480 to 0x04BF, and a 16-byte area at addresses 0x04C0 to 0x04FF. 114.

  Setting information related to the entire ATA is described in the area 111, setting information related to the through PIO transfer mode is described in the area 112, and setting information related to the IDMA transfer mode is described in the area 113. An area 114 is a reserved area.

  FIG. 9 is a diagram illustrating a configuration example of the through PIO script described in the area 101.

  In FIG. 9, a completion flag (CPT) 121 of bit number 31 is a flag indicating the completion of processing. “0” is set when writing to the table, and “1” is set when processing is completed. The ATA host 31 reads this flag after issuing the Read command. When the value is “1”, the Read command result described in the ATA register value 128 described later is valid. In the CPU interrupt condition 122 of bit numbers 30 to 28, information for determining which condition to use among the PIO CPU interrupt factor generation conditions written in another table is described.

  In the read repetition condition (Rd repetition condition) 123 of bit numbers 27 to 24, information for determining which of the read repetition conditions written in another table is used is described. This setting is valid only for reading and invalid for writing. The time weight (TW) 124 of bit number 23 is a flag indicating whether or not the process is temporarily stopped. When the process is started without being temporarily stopped, the value is set to “0”. When the process is paused and the process is started after waiting for the set wait time, the value is set to “1”.

  An INTRQ wait (IW) 125 of bit number 22 is a flag indicating whether or not processing is temporarily stopped until an INTRQ signal indicating a CPU interrupt request supplied from the drive 22 is supplied, and does not wait for the INTRQ signal. When processing is started, the value is set to “0”. When processing is paused and processing is started after waiting for the INTRQ signal, the value is set to “1”. The A write / read setting (RXW) 126 of bit number 21 is a flag for setting whether to execute a writing process or a reading process, and is a recording area (hereinafter referred to as an ATA register) of a recording medium of the drive 22. This value is set to “0” when it is set to execute a read process for reading information, and this value is set to “1” when it is set to execute a write process for writing information to the ATA register. The

  The ATA address 127 of bit numbers 20 to 16 describes the address of the ATA register to be read / written. Bit number 20 describes the value of chip select signal CS1, bit number 19 describes the value of chip select signal CS0, bit number 18 describes the value of device address signal DA2, and bit number 17 A value of the device address signal DA1 is described, and a bit number 16 describes the value of the device address signal DA0. In the special mode, if the value of the ATA address 127 is “0”, the ATA register is not read or written. When the value of the ATA address 127 is “0” and “0x0001” is designated as the value of data to be read / written, the ATA host hardware 21 shifts to the PIO pause mode, and the ATA address 127 When the value is “0” and “0x0FFF” is designated as the value of the data to be read / written, this indicates the end of the through PIO transfer mode (EOF).

  The ATA register value 128 of bit numbers 15 to 0 describes the contents written to the ATA register and the contents read from the ATA register. Note that 16 bits are used only for the contents of the data register, and for information relating to other registers, only 8 bits are valid.

  When the CPU 23 holds the script as described above in the area 52 of the SRAM 52 and instructs the through PIO start, the ATA host hardware 21 executes the data transfer process in the PIO transfer mode according to the script procedure of the SRAM 52, and the drive Read / write data to / from 22 ATA registers.

  FIG. 10 is a diagram illustrating a configuration example of the PIO CPU interrupt factor generation condition described in the area 102.

  The reserve (RSV) 131 of bit numbers 31 to 21 of the PIO CPU interrupt factor generation condition 102 is a reserved area and is not normally used. In the following, description of the reserve (preliminary area) is omitted.

  The INTRQ setting 132 of bit number 20 is setting information for instructing whether or not to use the INTRQ signal from the CPU 23 as an interrupt factor. When this value is “1”, the PIO CPU interrupt factor is set, and this value is When “0”, the INTRQ signal is ignored. In the AND / OR setting 134 of bit number 16, when a plurality of bits are valid in the PIO CPU interrupt condition valid bit setting 135, the AND (OR) of these interrupt factor generation conditions is used as an interrupt factor generation condition. This is setting information that specifies whether a logical sum (OR) is used as an interrupt factor generation condition.

  The PIO CPU interrupt condition valid bit setting 135 of bit numbers 15 to 8 designates which of the lower 8 bits of the register value held as a response to the PIO Read command is used as a PIO CPU interrupt factor generation condition. Setting information. The PIO CPU interrupt condition value 136 of bit numbers 7 to 0 indicates the PIO CPU interrupt factor when the valid bit in the PIO CPU interrupt condition valid bit setting 135 is among the register values held in response to the PIO Read command. This is setting information that specifies whether or not to generate.

  In other words, the setting contents of the CPU interrupt condition specified by the CPU interrupt condition 122 of bit numbers 30 to 28 of the through PIO script described in the area 101 are described in the area 102. A plurality of these settings are described, and the CPU interrupt condition 122 specifies which setting is used as the CPU interrupt factor generation condition. For example, if the INTRQ signal is not used as an interrupt factor and the BUSY and DRQ bits in the status register are both “0” and the ERR bit is “1”, the ATA In the status register, since the bit number of the BUSY bit is 7, the bit number of the DRQ bit is 3, and the bit number of the ERR bit is 0, the host 31 sets the value of this PIO CPU interrupt factor generation condition to “+ Set to "0x00018901".

  FIG. 11 is a diagram illustrating a configuration example of a read repetition / IfGoto condition table described in the area 102.

  In the AND / OR setting 142 of the bit number 16, when a plurality of bits are valid in the read repetition / IfGoto condition valid bit setting 143, the logical product (AND) of these conditions is set as the read repetition / IfGoto condition, This is setting information for designating whether the sum (or) is read and repeated / ifGoto condition.

  The read repetition / IfGoto condition valid bit setting 143 of bit numbers 15 to 8 designates which of the lower 8 bits of the register value held as a response to the PIO Read command is used for the read repetition / IfGoto condition. Setting information. The read repetition / IfGoto condition value 144 of bit numbers 7 to 0 is the PIO Read command when the valid bits in the read repetition / IfGoto condition valid bit setting 143 are among the register values held in response to the PIO Read command. Is setting information for specifying whether to repeat the process or to execute the IfGoto command.

  That is, in the area 102, the setting contents of the repetition condition of the Reed command specified by the read repetition condition 123 of the bit numbers 27 to 24 of the through PIO script described in the area 101, or two lines of the IDMA PIO script described later The setting contents of the execution condition of the IfGoto command designated by the IfGoto condition 200 of the bit numbers 23 to 20 of the eye (+4 bytes) are described. A plurality of these settings are described, and which setting is used as a condition is specified by the read repetition condition 123 or the IfGoto condition 200. For example, when the value of the PIO read repetition / IfGoto condition table is “+ 0x00000000”, the Read command is not repeated. Also, for example, when the value of this read repetition / IfGoto condition table is “+ 0x00008888”, since the bit number of the BUSY bit is 7 and the bit number of the DRQ bit is 3 in the repetition status register, the repetition status The idle reading is repeated until the BUSY bit value of the register becomes “0” and the DRQ bit value becomes “0”.

  The area 102 is shared by the PIO CPU interrupt factor generation condition and the read repetition / IfGoto condition table, and any one of these is described. A table of read repetition / IfGoto conditions is also described in the area 103.

  FIG. 12 is a diagram illustrating a configuration example of the user addition register configured in the area 104.

  A user addition value (User addition value) 151 of bit numbers 31 to 0 is a register used for calculating an error rate in the IDMA transfer mode, and this User addition value 151 is specified by setting an IDMA PIO script described later. The PIO read value is added to the value stored in the User addition value 151, and the calculation result is stored in the User addition value 151. An initial value is set as the value of the User addition value 151 at the time of the Write command.

  FIG. 13 is a diagram illustrating a configuration example of a PRD table for IDMA configured in the area 105 and the area 106.

  In FIG. 13, a completion flag (CPT) 161 of bit number 31 in the first row (+0 byte) is a flag indicating the completion of processing. “0” is set when writing to the table, and “1” is set when processing is completed. Set. The ATA host 31 reads this flag after issuing the Read command. If the value is “1”, the ATA host 31 determines that the IDMA processing corresponding to the PRD table is completed. No Data Transfer (NDT) 162 of bit number 28 in the first row (+0 byte) is a flag for controlling DMA transfer. When the value of this flag is “1”, DMA processing is not executed. In this case also, the PIO process is executed.

  SDRAM 0 start address (SDRAM 0 Start Address) 163 with bit numbers 27 to 0 in the first row (+0 byte), and SDRAM 1 start address (SDRAM 1 Start Address) 167 with bit numbers 27 to 0 in the third row (+8 bytes) Stores the start address of the SDRAM accessed by the ATA host hardware 21 in the process in the IDMA transfer mode. After an access is made based on the setting of SDRAM0, an access is made based on the setting of SDRAM1. The SDRAM 0 length (SDRAM 0 Length) 166 with bit numbers 27 to 0 in the second row (+4 bytes) stores the setting of the length of SDRAM 0 accessed by the IDMA.

  The processing flag (Exe) 164 of bit number 31 in the second row (+4 bytes) indicates whether or not processing is currently being performed. The processing flag 164 is a flag for determining what processing is being performed when the processing ends abnormally. The continuation (CTN) 165 of bit number 28 in the second row (+4 bytes) stores information relating to whether or not the SDRAM address setting continues for three or more addresses (there is an additional SDRAM address). . For example, when the value of the continue 165 is “0”, there is no additional SDRAM address, and when the value is “1”, there is an additional SDRAM address.

  Device start LBA 168 (device Start LBA) of bit numbers 31 to 0 in the fifth line (+16 bytes) stores information of the start LBA when accessing the drive 22. Device sector length 169 (device sector Length) of bit numbers 31 to 0 in the sixth line (+20 bytes) stores information specifying the length of access to drive 22 by the number of sectors. When the setting of the extended PRD table is invalid, when the value of the device sector length 169 is “0”, this indicates that this PRD table is EOR. If the extended PRD table setting is enabled, follow the EOF setting.

  The table type (TBL Type) 171 of the seventh line (+24 bytes) bit number 26 is a flag indicating the type of information stored in the area 106. For example, a value of “0” indicates that a normal PRD table is stored, and a value of “1” indicates that an SDRAM address additional setting table is stored. The pickup selection flag (OP) 172 of the seventh line (+24 bytes) bit number 25 stores information specifying the pickup when there are a plurality of pickups of the drive 22, as will be described later.

  The 7th line (+24 bytes) bit number 24 write / read setting (RXW) 173 is a flag for setting whether to execute write processing or read processing in DMA processing, and reads information in the ATA register. When setting to execute read processing, this value is set to “0”, and when setting to execute write processing for writing information to the ATA register, this value is set to “1”.

  7th line (+24 bytes) DMA execution command PIO script number (DMA Exe command PIO script No.) 174 for bit numbers 5 to 0, 8th line (+28 bytes) single DMA end status read for bit numbers 29 to 24 PIO script number (Mono DMA end status Read PIO script number) 175, 8th line (+28 bytes) PIO script number for issuing a single DMA command with bit numbers 21 to 16 (Mono DMA command issuing PIO script number) 176 , 8th line (+28 bytes) PIO script number for PRD end process of bit numbers 13 to 8 (PRD end process PIO script No.) 177, 8th line (+28 bytes) PIO start process PIO of bit numbers 5 to 0 The script number (PRD start processing PIO script No.) 178 shows the start number of the PIO script executed in each phase in the IDMA transfer mode. There has been stored.

  FIG. 14 is a diagram illustrating a configuration example of an SDRAM address addition setting table for IDMA configured in the area 106.

  In FIG. 14, SDRAM 1 start address (SDRAM 1 Start Address) 181 with bit number 27 to 0 in the first row (+0 byte), SDRAM 2 start address (SDRAM 2 Start with bit number 27 to 0 in the third row (+8 byte)) Address) 183, and SDRAM 3 start address (SDRAM 3 Start Address) 185 of bit numbers 27 to 0 in the fifth line (+16 bytes) are the start of SDRAM accessed by ATA host hardware 21 in the process in the IDMA transfer mode. Stores the address. After an access is made based on the setting of SDRAM0, an access is made based on the setting of SDRAM1. The SDRAM 1 length (SDRAM 1 Length) 182 with bit numbers 27 to 0 in the second row (+4 bytes) and the SDRAM 2 length (SDRAM 2 Length) 184 with bit numbers 27 to 0 in the fourth row (+12 bytes) are: Stores the setting of the length of SDRAM accessed by IDMA.

  The processing flag (Exe) 164 of bit number 31 in the second row (+4 bytes) indicates whether or not processing is currently being performed. The processing flag 164 is a flag for determining what processing is being performed when the processing ends abnormally. The continuation (CTN) 165 of bit number 28 in the second row (+4 bytes) stores information relating to whether or not the SDRAM address setting continues for three or more addresses (there is an additional SDRAM address). . For example, when the value of the continue 165 is “0”, there is no additional SDRAM address, and when the value is “1”, there is an additional SDRAM address.

  The knot EOF (NEOF) 186 of bit number 31 in the sixth line (+20 bytes) stores information that prevents the hardware from recognizing EOF. That is, the knot EOF 186 stores a fixed value “1”. The table type (TBL Type) 187 of the seventh line (+24 bytes) bit number 26 is the same as the table type 171 of FIG. In the case of FIG. 14, since the table is an SDRAM address additional setting table, the value “1” is stored.

  When the value of the continue 165 described with reference to FIG. 13 is “1”, the next table always stores the SDRAM address additional setting table shown in FIG.

  The area 106 is shared by the IDMA PRD table (table number 8 PRD table) and the SDRAM address additional setting table.

  FIG. 15 is a diagram illustrating a configuration example of a PIO script for IDMA configured in the area 107.

  In FIG. 15, the configuration of bit numbers 30 to 0 in the first line (+0 byte) is the same as that of the through PIO script described with reference to FIG. That is, in the first line, the CPU interrupt condition 192 of bit numbers 30 to 28 corresponds to the CPU interrupt condition 122, and the read repetition condition (Rd repetition condition) 193 of bit numbers 27 to 24 corresponds to the read repetition condition 123. The time wait (TW) 194 of bit number 23 corresponds to the time weight 124, the INTRQ wait (IW) 195 of bit number 22 corresponds to the INTRQ wait 125, and the write / read setting (RW) 196 of bit number 21 Corresponds to the write / read setting 126, the ATA address (197) of bit numbers 20 to 16 corresponds to the ATA address 127, and the ATA register value 198 of bit numbers 15 to 0 corresponds to the ATA register value 128.

  In the case of FIG. 15, EOF 191 is stored in the bit number 31 of the first row (+0 byte), and when the value of this bit is “1”, one block of PIO script control is executed after the execution of this script is completed. Processing is terminated. However, when the process moves to another script due to the IfGoto condition, the value of this EOF 191 is ignored.

  IfGoto jump destination script number (IfGoto Jump destination Scr No.) 199 of bit numbers 29 to 24 in the second row (+4 bytes) stores the script number of the jump destination when various states match the IfGoto condition. The The IfGoto condition number (IfGoto condition No.) 200 of bit numbers 23 to 20 in the second row (+4 bytes) stores the number of the condition table used as the IfGoto condition.

  The read data addition register (Rd Data addition Reg) 201 of bit numbers 19 to 16 in the second row (+4 bytes) is used when an error rate or the like is added to an internal register. The setting of which register is added to the value is stored. For example, when the value of this register is “0” to “7”, the ATA host 31 adds the read value to the user addition register stored in the area 104 of that number. For example, when the value of this register is “8”, the ATA host 31 does not perform addition, and when the value of the register is “9” to “15”, it reserves.

  The LBA and Tag substitution mode 202 of the bit numbers 11 to 8 in the second line (+4 bytes) is used to change the ATA register value when the ATA interface processing unit 36 of the ATA host hardware 21 writes to the ATA register of the drive 22. , Information specifying that the IDMA control unit 37 writes to the ATA register in place of the LBA value or Tag value automatically generated. For example, the ATA interface processing unit 36 does not substitute if this value is “0”, and substitutes the Tag value into bit numbers 7 to 3 of the ATA register value if the value is “1”. Further, when the value is “2”, the ATA interface processing unit 36 substitutes the value of the bit number “7” to “0” of the LBA value into the bit number 7 to 0 of the ATA register value, and the value is “3”. When the value is “4”, the bit numbers 7 to 0 of the ATA register value are substituted for the bit numbers “15” to “8” of the LBA value. When the value of bit numbers “23” to “16” of the LBA value is substituted for 0 and the value is “5”, bit numbers “27” to “24” of the LBA value are assigned to bit numbers 3 to 0 of the ATA register value. When the value is “6”, the LBA bit numbers “31” to “24” are substituted into the ATA register bit numbers 7 to 0, and the value is “7”. If there is, substitute the value of bit number “15” to “0” of LBA value into bit number 15 to 0 of ATA register value, Is “8”, the bit numbers “31” to “16” of the LBA value are substituted into the bit numbers 15 to 0 of the ATA register value, and the reservation is made when the value is “9” to “15”. .

  The INTRQ temporary stop specification information (IRQPS) 203 of bit number 1 in the second line (+4 bytes) is used to temporarily stop PIO processing when a PIO CPU interrupt factor is generated by the INTRQ signal during PIO processing access in IDMA transfer mode. It is information that specifies whether to do. When this value is “0”, the process is continued without being paused, and when this value is “1”, the PIO process is paused. The read data temporary stop specification information (RDPS) 204 of bit number 0 in the second row (+4 bytes) is used to pause PIO processing when a PIO CPU interrupt factor occurs in the read data of PIO processing in IDMA transfer mode. It is information that specifies whether or not. When this value is “0”, the process is continued without being paused, and when this value is “1”, the PIO process is paused.

  A plurality of combinations of these scripts are used for a single DMA command issuance PIO script, a single DMA end status read PIO script, or a PRD end PIO script for IDMA processing which is IDMA transfer mode processing.

  FIG. 16 is a diagram illustrating a configuration example of the mode / status information in the setting information related to the entire ATA configured in the area 111 of the register 53.

  In the mode / status information of the area 111A (address 0x0400 to 0x0403) that is a part of the area 111, the IDMA process start flag (IDMSt) 211 of bit number 28 is a flag for setting the IDMA process start. When the value is “1”, the IDMA process is started from the PRD table of table number 0. When the value of the IDMA process start flag 211 is “0”, the IDMA process is not started. For example, when the value of this flag is set to “1” in the through PIO transfer mode, the IDMA process is reserved, and immediately after entering the standby state, the IDMA transfer mode is started and the IDMA process is started. A through PIO processing start flag (ThrPIOSt) 212 of bit number 24 is a flag for setting the start of through PIO control processing. When the value of this flag is “1”, through PIO control processing from the through PIO script of script number 0 Is started. When the value of the through PIO start flag 212 is “0”, the through PIO control process is not started. For example, if the value of this flag is set to “1” in the IDMA transfer mode, the through PIO control process is reserved, and immediately after entering the standby state, the mode shifts to the through PIO transfer mode and the through PIO control process is started. The In the top status (TOP Status) 213 of bit numbers 2 to 0, information indicating the status of the ATA host hardware 21 is stored. When the value of the top status 213 is “0”, the ATA host hardware 21 is in a standby state (IDLE), and when the value is “1”, the ATA host hardware 21 is performing through PIO control processing. When the value is “2”, the ATA host hardware 21 is in IDMA processing. When the value is “4”, the ATA host hardware 21 is resetting the drive 22 that is an ATA device.

  That is, in this mode / status information, information on the top level status of the ATA host hardware 21 and the start reservation process set by itself is stored. For example, when executing IDMA processing, the value of this mode / status information is set to “0x10000000”.

  FIG. 17 is a diagram illustrating a configuration example of the suspension information among the setting information related to the entire ATA configured in the area 111 of the register 53.

  In the temporary stop information of the area 111B (addresses 0x0404 to 0x0407) that is a part of the area 111, the read repetition wait amount (Read repetition WAIT amount) 214 of the bit numbers 15 to 8 indicates how many clock read repetition waits in terms of the system clock. It is information that specifies whether to generate. When the current situation matches the read repetition condition stored in the bit numbers 27 to 24 of the PIO script register in FIG. 9, information for setting how long a wait is generated and the read is performed again is described.

  In this suspension information, the time wait amount (TIME WAIT amount) 215 of bit numbers 7 to 0 is set to be suspended before the PIO command is generated, for example, in the time wait 124 of FIG. This is a register for setting whether to pause for about a period of time.

  FIG. 18 is a diagram illustrating a configuration example of the through PIO processing setting in the setting information related to the through PIO transfer mode configured in the area 112.

  In the through PIO processing setting of the area 112A (address 0x0440 to 0x0443) which is a part of the area 112, the abort setting (ABT) 221 of bit number 9 is a flag for designating forcible termination (abort) of the through PIO. When the value of this flag is “1”, the through PIO transfer mode is shifted to the standby state at a safe timing. However, if the semaphore has been acquired, the semaphore is given priority, and the semaphore is returned and then forcibly terminated.

  A pause setting (PS Off) 222 of bit number 8 is a flag for designating an operation related to pause. When the value of this flag is “1”, the ATA host hardware 21 is released from the pause state. When the normal mode is entered and the value of this flag is “0”, the pause state is maintained as it is.

  Bit number 1 INTRQ pause setting (IRQ PS) 223 is a flag that specifies whether or not to pause PIO processing when a PIO CPU interrupt factor is generated by the INTRQ signal during access processing in the through PIO transfer mode. When the value of this flag is “0”, the ATA host hardware 21 continues the PIO processing without pausing. When the value of this flag is “1”, the PIO processing is performed based on the INTRQ signal. Pause.

  The read data pause setting (RD PS) 224 of bit number 0 is a flag that specifies whether or not to pause the PIO processing when a PIO CPU interrupt factor is generated by the read data in the through PIO transfer mode. When the value of the flag is “0”, the ATA host hardware 21 continues the PIO process without pausing. When the value of the flag is “1”, the PIO process is temporarily performed based on the read data. Stop.

  FIG. 19 is a diagram illustrating a configuration example of semaphore settings in the setting information related to the through PIO transfer mode configured in the area 112.

  The through PIO semaphore 225 with the bit number 0 in the semaphore setting of the area 112B (address 0x0448 to 0x044B) that is a part of the area 112 has the right to add or change a through PIO script while executing the through PIO control processing. It is a flag which shows. If the ATA host 31 reads this semaphore setting and the value is “0”, it means that semaphore allocation has failed. On the other hand, when this semaphore setting is read and the value is “1”, the ATA host 31 determines that the semaphore acquisition is successful, and performs processing related to the PIO script. When acquiring the semaphore, the ATA host 31 updates this semaphore setting and returns the semaphore.

  That is, the ATA host 31 reads the semaphore setting when adding a through PIO command, secures the semaphore, adds a through PIO table, and returns the semaphore. While the ATA host 31 secures the semaphore, the process related to the PIO script is paused before the next single PIO process, so it is necessary to return the semaphore as soon as possible. Note that the ATA host 31 may update any PIO script as long as a semaphore is secured. However, if a table currently being executed or an unexecuted table is updated, inconsistency may occur in processing. Therefore, it is desirable to update only the processed table.

  FIG. 20 is a diagram illustrating a configuration example of a first IDMA process setting which is one of setting information related to setting information related to the IDMA transfer mode configured in the area 113.

  The single DMA sector length (Mono DMA Sector Length) 231 of the bit numbers 31 to 16 of the first IDMA processing setting of the region 113A (address 0x0480 to 0x0483) which is a part of the region 113 is a single DMA processing. This is information for setting how many sectors of data are to be processed. When one DMA process is completed in the calculation of IDMA PIO command LBA substitution, the value of this setting is added to the LBA. The abort setting (ABT) 232 of bit number 9 is a flag for designating forcible termination (abort) of IDMA. When the value of this flag is “1”, the IDMA transfer mode is shifted to the standby state at a safe timing. At this time, the ATA host hardware 21 refers to the value of the temporary stop flag 236 at the end of the status report phase, confirms that the operation mode is in the paused state at the end of the status report phase, and forcibly ends IDMA processing. To do. Note that if the forced termination process is executed in the IDMA process, a mismatch occurs between the number of DMA commands and the number of DMA data transfers. Therefore, a device reset or a process equivalent thereto is always performed.

  The IDMA processing pause release setting (PRD PS Off) 233 of bit number 8 is a flag for releasing the pause of IDMA processing and shifting to the normal mode, and only when the value “1” is written to this flag. This value is enabled, and the pause of IDMA processing is canceled by this value.

  The pickup switching timing setting (Wr OP Chg Tmg) 234 of bit number 5 designates where the switching timing of the pickup to be processed is set in the writing process when there are a plurality of pickups of the drive 22 as described later. Information. For example, when the value of this setting is “0”, the switching process is performed before the report script process, and when the value of this setting is “1”, it is performed after the report or END script process. Device number (Dev Num) 235 of bit number 4 is information indicating what kind of device is the drive that is the ATA device. For example, when the value is “0”, the drive 22 is 1 Dev-2OP in which two pickups of the drive 22 are processed as one device in the ATA interface, and when the value is “1”, the drive 22 The two pickups of the 2 are 2 Dev-2OP processed as two devices in the ATA interface. As will be described later, the processing timing of the ATA host hardware 21 varies depending on the difference in the drive 22. If the number of pickups in the drive 22 is one (that is, 1 Dev-1OP), this value may be either.

  The status report phase end pause flag (St End PS) 236 of bit number 3 is a flag indicating a paused state at the end of the status report phase of the PIO script. When this value is “1”, It is in a suspended state. This pause is performed by a pause interrupt at the end of the single PRD table. As described above, the value of this flag is referred to at the time of forced termination (abort) processing. If the abort process is simply performed without referring to this flag, there is a possibility that a problem such as forcible termination while the ATA bus is occupied may occur. The bit number 2 single PRD table end pause setting flag (Mn PRD END PS) 237 is a flag that specifies whether or not the IDMA process is paused every time one process of the PRD table ends. When “0” is “0”, it is not paused. When the value is “1”, it is paused.

  FIG. 21 is a diagram illustrating a configuration example of a second IDMA process setting which is one of setting information related to setting information related to the IDMA transfer mode configured in the area 113.

  The extended PRD setting (Ex PRD) 238 of the bit number 28 of the second IDMA processing setting in the area 113B (addresses 0x0484 to 0x0487) that is a part of the area 113 specifies whether or not to expand the number of PRD tables. If the value is “0”, the flag is not expanded (eight PRD tables), and if the value is “1”, an expanded PRD table (the ninth PRD table) exists.

  The EOF number 239 of bit numbers 27 to 24 stores information specifying the number of the last PRD table that becomes EOF. This flag is valid only when the value of the extended PRD setting 238 is “1” (when an extended PRD table exists). The PRD table (extended PRD table) shares the storage area with the SDRAM address addition setting table for IDMA (area 106). In this area 106, when an SDRAM address additional setting table for IDMA is stored following the PRD table, the EOF number specifies the number of the PRD table.

  The read DMA queue limit number (Read DMA Cue Limit Number [RUB]) 240 of bit numbers 15 to 0 stores the limit queuing number per pickup. When the drive 22 is 1 Dev-2OP, a queuing number twice as large as this setting is given to one device. Therefore, in this case, this setting is set to half or less of the device limit queuing number. Also, in 1Dev-2OP, the OP number is put in the MSB of the tag number so that the tag number between the OPs is not confused. Since the tag number is 5 bits, only 16 tags can be given per OP. Therefore, in order to avoid confusion between Tag numbers in the same OP, it is desirable to set this setting to 16 or less for 1 Dev-2OP. For 2Dev-2OP, it is desirable to set this setting to 32 or less for the same reason.

  FIG. 22 is a diagram illustrating a configuration example of a third IDMA process setting which is one of setting information related to setting information related to the IDMA transfer mode configured in the area 113.

  A 1RUB process byte number setting (DMA 1RUB Prcess Byte Number) 238 of bit numbers 27 to 0 of the third IDMA processing setting in the area 113C (addresses 0x0494 to 0x0497), which is a part of the area 113, is used when performing DMA processing. Information specifying the number of bytes to be processed in 1 RUB is stored. This information is used to prevent sending extra data to the device when writing to the device, and to determine which DMA termination is completed at the end of one RUB when split DMA is used when reading the device. Is done.

  FIG. 23 is a diagram illustrating a configuration example of a semaphore setting that is one of setting information related to setting information related to the IDMA transfer mode configured in the area 113.

  The IDMA PIO semaphore (IDM PIO SMF) 242 with bit number 0 in the semaphore setting of the area 113D (addresses 0x048C to 0x048F) that is a part of the area 113 indicates a semaphore indicating the right to add or change the IDMA PRD table during IDMA processing. Is a flag indicating the reservation. When the value of this flag is “0”, it indicates that semaphore acquisition has failed, and when the value is “1”, it indicates that semaphore acquisition has been successful. When the IDMA process is being executed, the ATA host 31 cannot add or change the PRD table unless it acquires a semaphore. When the state of the ATA host hardware 21 is the standby mode or the through PIO transfer mode, the PRD table can be added or changed without acquiring a semaphore.

  When adding or changing the PRD table, the ATA host 31 reads the semaphore settings, secures the semaphore, adds the PRD table, and returns the semaphore. While the ATA host 31 secures the semaphore, the process related to the PRD table is temporarily stopped before the process related to the next PRD table, so it is necessary to return the semaphore as soon as possible. Note that the ATA host 31 may update any PRD table as long as a semaphore is secured. However, if a table currently being processed or an unexecuted table is updated, inconsistency may occur in the processing. It is desirable to update only the processed table.

  FIG. 24 is a diagram illustrating a configuration example of LBA setting, which is one of setting information related to setting information related to the IDMA transfer mode configured in the area 113.

  The execution LBA information (Execute DMA LBA) 243 of the bit numbers 31 to 0 of the LBA setting of the area 113E (address 0x0490 to 0x0493 or address 0x049C to 0x049F), which is a part of the area 113, is currently being executed or most recently DMA transfer mode Stores information about the LBA that executed the data transfer.

  FIG. 25 is a diagram illustrating a configuration example of interrupt factor setting, which is one of setting information related to setting information related to the IDMA transfer mode configured in the area 113.

  When the IDMA PIO INTRQ interrupt factor (IDM PIO IRQ IRQ) 244 of the bit number 15 of the interrupt factor setting of the region 113F which is a part of the region 113 is “1”, the IDMA PIO transfer mode drive 22 is transferred to the drive 22 This flag indicates that a CPU interrupt factor has occurred due to the INTRQ signal of the drive 22 during the access. When the IDMA PIO read data interrupt factor (IDM PIO RD IRQ) 245 of bit number 14 is “1”, it indicates that the CPU interrupt factor is generated by the data read from the drive 22 in the IDMA PIO transfer mode. Flag.

  When the value of the temporary stop flag (IDM PIO PS) 246 of bit number 13 is “1”, it is a flag indicating that a temporary stop has occurred during processing in the IDMA PIO transfer mode. When the value of the single PRD end stop flag (IDM PIO PS) 247 of bit number 12 is “1”, the processing of the 1PRD table is ended and a pause is generated. is there.

  An all PRD table end flag (IDM ALL PRD END) 248 of bit number 9 is a flag indicating that the processing of all the PRD tables is ended when the value is “1”. The 1PRD table end flag (IDM Mn PRD END) 249 of bit number 8 is a flag indicating that the processing of one PRD table is ended when the value is “1”.

  If the value of all through PIO processing end flag (THR PIO ALL END) 250 of bit number 3 is “1”, through PIO control processing, which is transfer processing in the through PIO transfer mode, has been completed for all scripts. It is a flag which shows. A through PIO pause flag (THR PIO PS) 251 of bit number 2 is a flag indicating that a pause has occurred during the through PIO control process when the value is “1”. The bit number 1 through PIO INTRQ interrupt factor (THR PIO IRQ IRQ) 252 is a flag indicating that a CPU interrupt factor is generated by the INTRQ signal in the through PIO mode when the value is “1”. A bit number 0 through PIO read data interrupt factor (THR PIO RD IRQ) 253 is a flag indicating that a CPU interrupt factor is generated by data read from the drive 22 in the through PIO mode when the value is “1”. It is.

  The ATA host 31 is controlled by the CPU 23 to store the register information as described above in the built-in SRAM 52 and register 53, and each part of the ATA host hardware 21 is shown in FIG. 7 based on the register information. While performing such mode transition, data transfer processing is performed in the through PIO transfer mode or IDMA transfer mode.

  Next, data transfer processing (through PIO control processing) in the through PIO transfer mode will be described.

  FIG. 26 is a diagram illustrating functional blocks of the ATA host hardware 21 in the through PIO transfer mode.

  The transfer process in the through PIO transfer mode is performed by the through PIO processing hardware 255 including the through PIO control unit 33, the single PIO script processing unit 34, the PIO execution unit 35, and the ATA interface 36 among the units of the ATA host hardware 21. It is executed by.

  In the through PIO transfer mode, first, as indicated by an arrow 261, the CPU 23 stores a through PIO script for executing a plurality of PIO transfer processes in the area 101 of the SRAM 52. When the CPU 23 instructs the through PIO processing hardware 255 to start the processing of the through PIO script as indicated by an arrow 262, the through PIO processing hardware 255 indicates that the SRAM 52 Necessary information is acquired from the through PIO script executed from the area 101. Then, through PIO control processing is executed based on the acquired information, the drive 22 is accessed and data transfer processing is performed as indicated by an arrow 265, and information (if necessary) (as indicated by an arrow 264) For example, status information and data read from the drive 22 are supplied to the SRAM 52 and stored therein. Through PIO processing hardware 255 Processes such as arrows 263 to 265 are repeated to complete all PIO processing based on the through PIO script. When the through PIO control processing is completed, the processing result is supplied to the CPU 23 as indicated by an arrow 266.

  An example of a specific process flow of the through PIO control process as described above will be described with reference to the flowchart of FIG.

  When the CPU 23 instructs the start of the through PIO control process, the through PIO control unit 33 first unlocks the semaphore in step S1, and in step S2, a PIO script pointer indicating the number of the PIO script to be executed is displayed. Initialization is performed, for example, reset to “0”. In step S3, it is determined whether or not the semaphore has been secured, and the process waits until it is secured. When the semaphore is secured, the through PIO control unit 33 fetches (acquires) the PIO script designated by the PIO script pointer in step S4.

  In step S5, the through PIO control unit 33 determines whether or not the fetched PIO script is an EOF indicating the end of the through PIO control process. If it is determined that it is not an EOF, the process proceeds to step S6. In step S6, the single PIO script processing unit 34 is controlled by the through PIO control unit 33 and executes single PIO script processing. Details of the single PIO script processing will be described with reference to the flowchart of FIG.

  When the single PIO script processing ends, the through PIO control unit 33 sets the ATA register value 128 of the script register (in this case, the through PIO script) as necessary in step S7. For example, the through PIO control unit 33 sets “Complete = 1” indicating the completion of the PIO processing to the ATA register value 128. For example, when data is read from the ATA register of the drive 22, the through PIO control unit 33 sets the read data to the ATA register value 128.

  In step S8, the through PIO control unit 33 that has set the ATA register value 128 generates an external interrupt factor according to the values of the through PIO INTRQ interrupt factor 252, the through PIO read data interrupt factor 253, and the through PIO pause flag 251. set. At this time, an interrupt is supplied to the CPU 23.

  When the external interrupt factor is set, the through PIO control unit 33 advances the process to step S9, and the through PIO INTRQ interrupt factor 252, the through PIO read data interrupt factor 253, the INTRQ pause setting 223, and the read data pause setting 224. The value of the through PIO temporary stop flag 251 is set according to the setting.

  In step S10, the through PIO control unit 33 determines whether or not the value of the through PIO temporary stop flag 251 is “1”. If it is determined that the value is “1”, the process proceeds to step S11, and the PIO Wait until you get a pause release. When the PIO temporary stop cancellation is acquired, the through PIO control unit 33 advances the process to step S12. If it is determined in step S10 that the value of the through PIO temporary stop flag 251 is “0”, the through PIO control unit 33 omits the process of step S11 and proceeds to step S12.

  In step S12, the through PIO control unit 33 increments the PIO script pointer, returns the process to step S3 to execute the process for the next PIO script, and repeats the subsequent processes.

  As described above, the through PIO control unit 33 sequentially processes a plurality of PIO scripts stored in the area 101 of the SRAM 52. When the last PIO script is fetched and it is determined in step S5 that the script is EOF, the through PIO control unit 33 advances the process to step S13.

  The through PIO control unit 33 locks the semaphore in step S13. When the all through PIO processing end flag 250 and the through PIO INTRQ interrupt factor 252 are set in step S14, the through PIO control processing ends.

  When the through PIO control process is completed, the ATA host 31 shifts the state of the ATA host hardware 21 from the through PIO transfer mode to the standby mode.

  Next, the single PIO script process executed in step S6 of FIG. 27 will be described with reference to the flowchart of FIG.

  The single PIO script processing unit 34 that has started the single PIO script processing waits for the waiting time in step S31 based on the setting of the time wait amount 215 of the suspension information. When the standby time has elapsed, the single PIO script processing unit 34 proceeds to step S32, determines whether or not the value of the INTRQ weight 125 is “1”, and determines that it is “1”. The process proceeds to step S33 and waits until the INTRQ signal is acquired from the ATA device (drive 22). When the INTRQ signal is acquired, the INTRQ signal is included in the PIO CPU interrupt factor generation condition stored in the area 102 in step S34. If it is, the value of the interrupt factor setting through PIO INTRQ interrupt factor 252 is set to “1”, and the process proceeds to step S35. If it is determined in step S32 that the value of the INTRQ weight 125 is not “1”, the single PIO script processing unit 34 ends the processes of step S33 and step S34, and proceeds to step S35.

  In step S35, the single PIO script processing unit 34 determines whether or not the value of the ATA address 127 of the through PIO script is “00000”. If it is determined that the value is not “00000”, the process proceeds to step S36. .

  In step S36, the single PIO script processing unit 34 checks the value of the write / read setting 126, determines whether the process to be executed is a write process, and determines that the process is a write process, step S37. Proceed with the process. In step S <b> 37, the PIO execution unit 35 is controlled by the single PIO script processing unit 34, and performs a writing process on the ATA register (writing process on the recording medium attached to the driver 22) via the ATA interface processing unit 36. To do. When the writing process by the PIO execution unit 35 is completed, the single PIO script processing unit 34 ends the single PIO script process and returns the process to step S6 in FIG. When the process returns to step S6, the through PIO control unit 33 ends the process of step S6 as described above, and proceeds to step S7.

  If it is determined in step S36 of FIG. 28 that the write process is not performed, the single PIO script processing unit 34 advances the process to step S38. In step S <b> 38, the PIO execution unit 35 is controlled by the single PIO script processing unit 34 and executes a read process for the ATA register (read process for the recording medium attached to the driver 22) via the ATA interface processing unit 36. To do. When the reading process by the PIO execution unit 35 is completed, the single PIO script processing unit 34 advances the process to step S39, and the register value read from the ATA device is the read repetition selected by the read repetition condition 123 of the through PIO script. It is determined whether or not the / IfGoto condition is met. If it is determined that the / IfGoto condition is met, the process proceeds to step S40.

  The single PIO script processing unit 34 that has proceeded to step S40 waits for the time specified by the read repetition wait amount 214, returns the processing to step S38, and repeats the subsequent processing.

  If it is determined in step S39 that the register value read from the ATA device does not meet the read repetition / IfGoto condition, the single PIO script processing unit 34 proceeds to step S41, and reads the register value ( If the read data) matches the PIO CPU interrupt factor generation condition stored in area 102, the value of the through PIO read data interrupt factor 253 in the interrupt factor setting is set to “1” and single PIO script processing is performed. The process ends, and the process returns to step S6 of FIG. When the process returns to step S6, the through PIO control unit 33 ends the process of step S6 as described above, and proceeds to step S7.

  If it is determined in step S35 of FIG. 28 that the value of the ATA address 127 is “00000”, the single PIO script processing unit 34 proceeds to step S42, and the ATA register value is “0x0001”. In this case, the access to the ATA register is omitted and the value of the through PIO temporary stop flag 251 of the interrupt factor setting is set to “1”. In other cases, the access to the ATA register is simply omitted. When the process of step S42 is completed, the single PIO script processing unit 34 ends the single PIO script process and returns the process to step S6 of FIG. When the process returns to step S6, the through PIO control unit 33 ends the process of step S6 as described above, and proceeds to step S7.

  As described above, the single PIO script processing unit 34 executes single PIO script processing.

  That is, in the through PIO transfer mode, when the through PIO processing hardware 255 of the ATA host hardware 21 starts the through PIO control processing, as shown in FIG. 29, first, in the step S51, the data is stored in the area 101 of the SRAM 52. The through PIO script 101-1 with the script number 0 is executed among the through PIO scripts being processed. As described with reference to FIG. 9, the through PIO script 101-1 includes a completion flag 121, a CPU interrupt condition 122, a read repetition condition 123, a time wait 124, an INTRQ wait 125, a write / read setting 126, an ATA Various information such as the address 127 and the ATA register value 128 is included, and the through PIO processing hardware 255 executes single PIO script processing based on the information and the like.

  When the through PIO processing hardware 255 finishes the single PIO script processing for the through PIO script 101-1 with the script number 0, the processing proceeds to step S52, and then the script number similar to that in step S51. The process for one through PIO script 101-2 is started. In this way, the through PIO processing hardware 255 performs single PIO script processing for each through PIO script stored in the SRAM area 101, and in step S53, the through PIO script 101- with the script number N is processed. Repeat until the process for (N + 1) is executed. Then, the process proceeds to step S54, and when the EOF 267 is detected from the through PIO script 101- (N + 2) with the script number N + 1, the through PIO processing hardware 255 ends the through PIO control process.

  As described above, since the through PIO processing hardware 255 of the ATA host hardware 21 executes single PIO script processing continuously based on a plurality of through PIO scripts, as shown in FIG. A plurality of PIO processes are executed simply by accessing the ATA host hardware 21 first, supplying a through PIO script, and instructing execution.

  Therefore, the CPU 23 and the ATA host hardware 21 need only be accessed at the first and last two times. Not only can the bus 42 occupy the PIO process, but also the data transfer process of the CPU 23 can be reduced. The CPU 23 can transfer data more easily.

  As described with reference to FIG. 7, in the above through PIO transfer mode, the single PIO script processing described with reference to the flowchart of FIG. 28 is forcibly terminated by the forced termination instruction (abort instruction). There is a case. However, the single PIO script processing unit 34 controls the PIO execution unit 35 and causes the PIO execution unit 35 to execute the processes of step S37 and step S38. At this time, if an abort process (forced termination process) is performed and the single PIO script processing unit 34 terminates the process, the PIO execution unit 35 cannot return the processing result to the single PIO script processing unit 34, which is inconvenient. May occur.

  Therefore, the single PIO script processing unit 34 waits for the processing of the PIO execution unit 35 to be completed when the abort processing is performed.

  The abort process by the single PIO script processing unit 34 will be described with reference to the flowchart of FIG.

  In step S61, the single PIO script processing unit 34 that has generated an abort command and started the abort process requests the PIO execution unit 35 to determine whether the process is being executed. The single PIO script processing unit 34 is executing the processing of steps S37 and S38 in the flowchart of FIG. 28 in the single PIO script processing being executed, and requests the PIO execution unit 35 to perform the processing. If it is determined that the process is being executed, the process proceeds to step S62 and waits until the process of the PIO execution unit 35 is completed. When the processing of the PIO execution unit 35 is completed and the processing result is returned, the single PIO script processing unit 34 proceeds to step S63, ends the single PIO script processing being executed, and ends the abort processing. To do.

  In step S61, if the PIO execution unit 35 has not been requested to perform processing and it is determined that the processing is not being executed, the single PIO script processing unit 34 skips step S62 and proceeds to step S63. Proceed with the process, terminate the single PIO script process being executed without waiting, and then terminate the abort process.

  As described above, the single PIO script processing unit 34 can safely abort (forcibly terminate) the single PIO script processing by waiting for the processing of the PIO execution unit 35 and then aborting.

  Next, data transfer processing (through PIO control processing) in the IDMA transfer mode will be described.

  FIG. 32 is a diagram showing functional blocks of the ATA host hardware 21 in the IDMA transfer mode.

  The transfer processing in the IDMA transfer mode includes PIO processing hardware 271 including an IDMA PIO control unit 38, a single PIO script processing unit 34, and a PIO execution unit 35, and an IDMA control unit 37 among the units of the ATA host hardware 21. It is executed by the IDMA PRD control hardware 272, the DMA processing hardware 273 including the DMA execution unit 39, and the ATA interface processing unit 36.

  In the IDMA transfer mode, data transfer by PIO processing and data transfer by DMA processing are performed. Therefore, in addition to the IDMA PIO script that is a PIO script for the IDMA transfer mode, the SRAM 52 stores a PRD table, and when the PIO process is selected by the PRD table, the PIO process based on the IDMA PIO script is executed. When DMA processing is selected according to the PRD table, DMA transfer by the DMA execution unit 39 is performed.

  That is, first, as indicated by an arrow 281, the CPU 23 stores a plurality of IDMA PIO scripts in the area 107 of the SRAM 52. Further, the CPU 23 stores a plurality of IDMA PIO scripts in the area 105 of the SRAM 52 (also in the area 106A as necessary) as indicated by an arrow 282. When the CPU 23 instructs the IDMA PRD control hardware 272 to start executing the IDMA process as indicated by an arrow 283, the IDMA PRD control hardware 272 indicates the area 105 (or the SRAM 52) (or as indicated by the arrow 285). When necessary information is acquired from the PRD table to be executed from the area 106A) and IDMA PIO processing is performed based on the information, the PIO processing hardware 271 is controlled as indicated by an arrow 286 to control IDMA PIO. Execute the process. When the IDMA PRD control hardware 272 starts the IDMA PIO control process, the PIO processing hardware 271 acquires necessary information from the IDMA PIO script executed from the area 107 of the SRAM 52 as indicated by an arrow 284. Then, IDMA PIO control processing is executed based on the acquired information, and the drive 22 is accessed via the ATA interface processing unit 36 as indicated by an arrow 288. The ATA interface processing unit 36 reads / writes data from / to the ATA register of the drive 22 as indicated by an arrow 290.

  Further, when performing the DMA processing based on the information acquired from the PRD table, the IDMA PRD control hardware 272 controls the DMA processing hardware 273 to execute the DMA processing as indicated by an arrow 287. The DMA processing hardware 273 accesses the drive 22 via the ATA interface processing unit 36 as indicated by an arrow 289. The ATA interface processing unit 36 reads / writes data from / to the ATA register of the drive 22 as indicated by an arrow 290. The DMA processing hardware 273 executes the DMA processing as described above, and exchanges data with the SDRAM 24 as indicated by an arrow 291.

  The IDMA PRD control hardware 272 executes the control process described above for each PRD table. Note that the CPU 23 adds a new PRD table to the area 105 of the SRAM 52 during the series of processes as described above as necessary.

  As described above, the PIO script control processing (IDMA PIO control processing) in the IDMA transfer mode is basically the same as the above-described through PIO script processing, and the processing for each PIO script is executed continuously. However, in the case of IDMA PIO script processing, as shown in FIG. 33, an IfGoto command exists, and processing for PIO scripts can be executed in an order other than the order of script numbers.

  That is, in the IDMA PIO transfer mode, the PIO processing hardware 271 of the ATA host hardware 21 includes, for example, the IDMA PIO script stored in the area 101 of the SRAM 52 in step S71 as shown in FIG. The IDMA PIO script 107-1 with the script number X is executed. As described with reference to FIG. 15, the IDMA PIO script 107-1 includes an EOF (Complete Flag) 191, a CPU interrupt condition 192, a read repetition condition 193, a time wait 194, an INTRQ wait 195, In addition to write / read setting 196, ATA address 197, ATA register value 198, etc., IfGoto jump destination script number 199, IfGoto condition number 200, read data addition register 201, INTRQ pause designation information 203, and read data pause Various information such as the designation information 204 is included, and the PIO processing hardware 271 executes IDMA PIO processing based on the information and the like.

  When the PIO processing hardware 271 completes the process for the IDMA PIO script 107-X with the script number X, the process proceeds to step S72, performs IfGoto jump processing based on the IDMA PIO script 107-X, and step S73. The processing for the IDMA PIO script 107-M with the script number M, which is the jump destination, is started. As described above, the PIO processing hardware 271 performs the process in the specified order while performing the IfGoto process on each IDMA PIO script stored in the area 107 of the SRAM 52. In step S74, the script number N The process for the IDMA PIO script 107-N is executed. Then, the process proceeds to step S55, and when the EOF 300 is detected from the IDMA PIO script 107- (N + 1) with the script number N + 1, the PIO processing hardware 271 ends the IDMA PIO script process.

  As described above, the PIO processing hardware 271 of the ATA host hardware 21 can continuously execute a single PIO script process based on a plurality of IDMA PIO scripts as in the case of the through PIO script process. it can.

  Next, IDMA PIO control processing will be described with reference to the flowchart of FIG.

  In FIG. 34, the IDMA PIO control unit 38 of the PIO processing hardware 271 is controlled by the IDMA PRD control hardware 272, and when the IDMA PIO control processing is started, in step S81, a PIO script that designates an IDMA PIO script to be processed. The pointer value is initialized and the start script number value is set. In step S82, the IDMA PIO control unit 38 fetches (acquires) the IDMA PIO script designated by the PIO script pointer in step S82.

  In step S83, the IDMA PIO control unit 38 determines whether or not the value of the EOF register indicating whether or not EOF has been acquired is true. If it is determined that the value is not true, the process proceeds to step S84. In step S84, if the fetched IDMA PIO script is EOF, the IDMA PIO control unit 38 sets the fetched EOF in the EOF register. That is, the IDMA PIO control unit 38 processes the IDMA PIO script that is EOF, and then determines that it is EOF. If the fetched IDMA PIO script is not EOF, the IDMA PIO control unit 38 does not update the EOF register.

  When the process of step S84 ends, the IDMA PIO control unit 38 advances the process to step S85. In step S85, the single PIO script processing unit 34 is controlled by the IDMA PIO control unit 38, and for the fetched IDMA PIO script, the single PIO script in the through PIO transfer mode described with reference to the flowchart of FIG. A single PIO script process similar to the process is executed. However, in this case, the single PIO script processing unit 34 that has finished the single PIO script processing returns the processing to step S85. If the process is returned from the single PIO script processing unit 34 and it is determined that the process in step S85 is completed, the IDMA PIO control unit 38 advances the process to step S86.

  In step S86, if the IDMA PIO script to be executed is a PIO Read command and a script for adding read data, the IDMA PIO control unit 38 adds the read data to the value of the read data addition register 201, The value is stored in the read data addition register 201, and the process proceeds to step S87. If it is not a script for adding read data, the IDMA PIO control unit 38 advances the process to step S87 without updating the read data addition register 201.

  In step S87, if the IDMA PIO script to be executed is a PIO Read command, the IDMA PIO control unit 38 overwrites the ATA register value 198 of the script and stores the read data. If the IDMA PIO script to be executed is not a PIO Read command, the IDMA PIO control unit 38 does not update the ATA register value 198. In step S88, the IDMA PIO control unit 38 sets external interrupt factors according to the values of the IDMA PIO INTRQ interrupt factor 244, the IDMA PIO read data interrupt factor 245, and the pause flag 246. In step S89, the IDMA PIO control unit 38 sets IDMA PIO. The value of the pause flag 246 is set according to the setting of the INTRQ interrupt factor 244 and the IDMA PIO read data interrupt factor 245.

  In step S90, the IDMA PIO control unit 38 determines whether or not the value of the temporary stop flag 246 is “1”. If it is determined that the value is “1”, the process proceeds to step S91. Wait until you get a pause release. When acquiring the PIO temporary stop cancellation, the IDMA PIO control unit 38 advances the process to step S92. If it is determined in step S90 that the value of the pause flag 246 is “0”, the IDMA PIO control unit 38 omits the process of step S91 and proceeds to step S92.

  In step S92, the IDMA PIO control unit 38 determines whether or not the acquired information matches the IfGoto condition. If the IDMA PIO control unit 38 determines that the information matches, the IDMA PIO control unit 38 proceeds to step S93, resets the EOF register, and sets the PIO script pointer. Set to the IfGoto script number. That is, in this case, the IDMA PIO control unit 38 performs IfGoto processing, jumps to the IDMA PIO script designated to be processed next, and starts processing for the IDMA PIO script. When the process of step S93 ends, the IDMA PIO control unit 38 returns the process to step S82 and repeats the subsequent processes.

  If it is determined in step S92 that the acquired information does not match the IfGoto condition, the IDMA PIO control unit 38 proceeds to step S94, increments the PIO script pointer, and returns the process to step S82. That is, in this case, the IDMA PIO control unit 38 does not perform the IfGoto process, but performs the processes in the order of the script numbers as in the case of the through PIO transfer mode.

  As described above, by repeating the processing from step S82 to step S94, the IDMA PIO control unit 38 performs processing for the IDMA PIO script in the designated order.

  If it is determined in step S83 that the value of the EOF register is true, the IDMA PIO control unit 38 ends the IDMA PIO control process.

  By performing the processing as described above, the PIO processing hardware 271 can continuously execute single PIO script processing in the IDMA transfer mode as in the case of the through PIO transfer mode. In this case, since the execution order of the IDMA PIO scripts is determined by the IfGoto condition or the like, the PIO processing hardware 271 performs processing for each IDMA PIO script in the specified order.

  The abort process is also performed in this IDMA PIO control process. However, as in the case of the through PIO transfer mode, the single PIO script processing unit 34 performs the abort process as described with reference to the flowchart of FIG. If the PIO execution unit 35 is executing the process, it waits without performing the end process, and executes the end process after the process ends. To.

  Similarly, the IDMA PIO control unit 38 also executes the abort process and executes the process of step S85 of the IDMA PIO control process described with reference to the flowchart of FIG. 34, that is, a single PIO script processing unit. When the single PIO script processing unit 34 is executing the process, the process waits without performing the end process, and the end process is executed after the process ends.

  The abort process by the IDMA PIO control unit 38 will be described with reference to the flowchart of FIG.

  In step S111, the IDMA PIO control unit 38 that has generated an abort command and started the abort process requests the single PIO script processing unit 34 to determine whether the process is being executed. The IDMA PIO control unit 38 is executing the process of step S85 in the flowchart of FIG. 34 in the IDMA PIO control process being executed, and requests the single PIO script processing unit 34 to execute the process. If it is determined that there is, the process proceeds to step S112 and waits until the process of the single PIO script processing unit 34 is completed. When the processing of the single PIO script processing unit 34 is completed and the processing result is returned, the IDMA PIO control unit 38 proceeds to step S113, ends the IDMA PIO control processing being executed, and ends the abort processing. To do.

  In step S111, if the single PIO script processing unit 34 has not been requested to perform processing and it is determined that the processing is not being executed, the IDMA PIO control unit 38 omits step S112 and performs step S113. The process proceeds to (1), the IDMA PIO control process being executed is terminated without waiting, and the abort process is terminated.

  As described above, the IDMA PIO control unit 38 can safely abort (forcibly terminate) the IDMA PIO control process by waiting for the process of the single PIO script processing unit 34 and then aborting.

  As described above, in the IDMA transfer mode, DMA processing is performed in addition to the PIO processing by the IDMA PIO control processing as described above. The control is performed based on the PRD table stored in the SRAM 52.

  That is, as shown in FIG. 36, the IDMA PRD control hardware 272 performs processing in units of GOP (Group Of Phase), which is a set of phases including a plurality of PIO processes, by repeatedly executing the PRD table. In the case of this GOP unit processing (GOP processing), as shown in FIG. 36, similarly to the above-described PIO processing, processing (PRD processing) related to the PRD table is performed as in steps S121 to S123. The IDMA PIO control process and the DMA process described above are performed in each PRD process based on the information in the PRD table.

  As shown in FIG. 37, the process for the PRD table is composed of several PIO script phases and a DMA actual transfer phase. That is, the ATA host hardware 21 controls the PIO command group related to DMA transfer in several phases. In other words, the ATA host hardware 21 issues the first phase for issuing a PIO command for starting PRD processing (PRD start PIO command), and the second phase for issuing a DMA PIO command for executing write processing or read processing. (DMA PIO command), the third phase (DMA Exe command) that issues a PIO command that executes DMA transfer, and the fourth phase (DMA execution) that performs DMA transfer, and then reports the status The fifth phase (Status Report) for issuing the PIO command is executed, and the sixth phase (1 PRD end PIO) for issuing the PIO command indicating that the 1PRD processing is completed is executed to complete one PRD processing. .

  The PRD table includes an instruction for executing such a PRD process continuously a plurality of times.

  For example, when the PRD table 311 is instructed to write data (3 RUB) for three processing units from the SDRAM to the LBA as the PRD table, the ATA host hardware 21 performs the start command (Start) as the first phase. 321 is issued, the write command (W) 322 is issued as the second phase, the DMA execution command (D) 323 is issued as the third phase, and the fourth phase in which the DMA transfer 324 is performed by the command is executed. Then, a status report command 325 is issued as the fifth phase. In the PRD table 311, 3 RUB, that is, write processing for three times is instructed, so the ATA host hardware 21 repeats the second to fifth phases three times and then the sixth phase. An end command (END) 326 is issued, and the PRD process for the PRD table 311 is ended.

  In FIG. 37, since the PRD table 312 exists as the next table of the PRD table 311, the ATA host hardware 21 starts the PRD process for the PRD table 312 after completing the PRD process for the PRD table 311. The PRD process for the PRD table 312 is basically the same as the PRD process for the PRD table 311, but as shown in FIG. 37, the PRD table 312 instructs to write 2RUB of data from the SDRAM to the LBA. Therefore, after executing the first phase, the ATA host hardware 21 repeats the second to fifth phases twice, then executes the sixth phase and ends the PRD process.

  In FIG. 37, each phase process is indicated by a single square. Actually, each PIO script phase is composed of a plurality of PIO access scripts. Executed.

  In FIG. 37, the case has been described where both the PRD table 311 and the PRD table 312 are tables for executing the writing process, that is, the case where the PRD process for performing the writing process is continued. In this case, as described above, the PRD process for the PRD table 312 is executed after the process for the PRD table 311 is completed.

  On the other hand, when PRD tables for executing read processing are continuous, each PRD processing for these PRD tables is partially executed in parallel as shown in FIG. In the case of read processing, the ATA host hardware 21 can issue the next command and store it in the queue (queuing) without waiting for completion of the previous command for each command in the second phase. . The maximum number of commands that can be queued (the limit queuing number) is predetermined.

  Therefore, the ATA host hardware 21 first executes the first phase and the second phase in the PRD process for each PRD table in order, and issues commands until the limit queuing number is reached. When the commands for the limit queuing number are issued, the ATA host hardware 21 executes DMA transfer for each command one by one. At this time, the ATA host hardware 21 queues a new command every time the DMA transfer process is performed once (every time the queued command is executed once). That is, the ATA host hardware 21 is configured to queue the commands for the limit queuing number while there are unissued commands.

  For example, as shown in FIG. 38, when performing PRD processing on the PRD table 331 for reading 3RUB data, the ATA host hardware 21 executes a series of processing of the PRD processing in a procedure surrounded by a frame 341. To do. In other words, in the second phase, the ATA host hardware 21 first issues a read command (R) for 3 RUBs, and thereafter executes the third phase, the fourth phase, and the fifth phase as 1 As a set, the process of that set is repeated three times. The ATA host hardware 21 finally executes the sixth phase, and ends the PRD process for the PRD table 331.

  At this time, as shown in FIG. 38, there is a PRD table 332 that reads data for 50 RUBs as a table to be processed next to the PRD table 331. At this time, if the limit queuing number is 6, even if the ATA host hardware 21 issues a 3RUB read command in the PRD process of the PRD table 331, the queue can still be queued for 3RUB. Therefore, the ATA host hardware 21 issues a PRD processing start command for the PRD table 332 and then queues the read command for 3 RUBs before executing the processing after the third phase of the PRD processing for the PRD table 331. Let

  Since the number of issued commands has reached the limit queuing number, the ATA host hardware 21 next performs the third phase, the fourth phase, and the fifth phase of the PRD process for the PRD table 331. Execute. As a result, the queued read command is reduced by one, so the ATA host hardware 21 next issues one PRD processing read command for the PRD table 332. When the above processing is repeated and the PRD processing for the PRD table 331 is completed, the ATA host hardware 21 next executes the third phase, the fourth phase, and the fifth phase of the PRD processing for the PRD table 332, As in the case of the PRD table 331 described above, the PRD process for the PRD table 332 is advanced by alternately executing issuance of a read command.

  As described above, when PRD tables for executing read processing are continuous, a part of the PRD processing for these tables is executed in parallel.

  In addition, when the PRD table for executing the reading process is changed from the PRD table for executing the reading process, as shown in FIG. 39, after the PRD process of the PRD table for executing the reading process executed first is completed. Then, the PRD process of the PRD table for executing the writing process is started.

  On the other hand, when the PRD table for executing the read process is changed from the PRD table for executing the write process to the PRD table for executing the read process, as shown in FIG. Then, the PRD process of the PRD table for executing the read process is started.

  That is, in such a case, the respective PRD processes are not executed in parallel. Each PRD process is executed as described with reference to FIGS. 37 and 38. Similarly to the case of FIG. 37, also in FIG. 38 and FIG. 39, the processing of each phase is shown by one square, but actually, each of these PIO script phases includes a plurality of PIO access scripts. A plurality of PIO commands are executed.

  Next, a specific processing flow of the IDMA processing as described above by the ATA host hardware 21 will be described.

  First, the GOP process for controlling the IDMA process in GOP units as described above will be described with reference to the flowchart of FIG.

  When the IDMA control unit 37 of the IDMA PRD control unit of the ATA host hardware 21 that has shifted to the IDMA transfer processing mode starts GOP processing, first, in step S131, initialization processing is performed to initialize the values of the variables. To do.

  That is, the IDMA control unit 37 has a command processing variable that accumulates the number of processed sectors, a command accumulation sector length that is a command processing variable, and a command reservation RUB that is a command processing variable that counts the number of reserved (queued) RUBs. Command tag that is a variable for command processing that holds the Tag value, data transfer cumulative sector length that is a variable for data transfer processing that accumulates the number of processed sectors, a read / write pointer for each pointer FIFO described later, and The value of the data transfer tag, which is a variable for data transfer processing that holds the Tag value, is set to “0”.

  The IDMA control unit 37 that has executed the initialization process proceeds to step S132, and executes a command start preparation process. Details of the command start preparation process will be described with reference to the flowchart of FIG. When the command start preparation process is completed, the IDMA control unit 37 advances the process to step S133 and executes the command start process. The major command start process will be described with reference to the flowchart of FIG. After completing the command start process, the IDMA control unit 37 advances the process to step S134 to execute the command execution process. Details of the command execution processing will be described with reference to the flowchart of FIG. When the command execution process ends, the IDMA control unit 37 advances the process to step S135.

  In step S135, the IDMA control unit 37 determines whether or not to shift to the data transfer process based on the processing result of the command execution process. If it is determined not to shift, the process returns to step S132, and the subsequent steps Repeat the process.

  If it is determined in step S135 to shift to the data transfer process, the IDMA control unit 37 advances the process to step S136, and executes a data transfer start preparation process. Details of the data transfer start preparation process will be described with reference to the flowchart of FIG. When the data transfer start preparation process is completed, the IDMA control unit 37 advances the process to step S137 and executes the data transfer service process. Details of the data transfer service process will be described with reference to the flowchart of FIG. When the data transfer service process ends, the IDMA control unit 37 advances the process to step S138, and executes the data transfer execution process. Details of the data transfer execution process will be described with reference to the flowchart of FIG. When the data transfer service process ends, the IDMA control unit 37 advances the process to step S139, and executes a data transfer status report process. Details of the data transfer status report processing will be described with reference to the flowchart of FIG. When the data transfer status reporting process ends, the IDMA control unit 37 advances the process to step S140.

  In step S140, the IMDA control unit 37 determines whether or not to execute the data transfer end process based on the processing result of the data transfer status report process. If it is determined to execute the data transfer, the process proceeds to step S141. Execute transfer end processing. Details of the data transfer end process will be described with reference to the flowchart of FIG. When the data transfer end process ends, the IDMA control unit 37 advances the process to step S142.

  If it is determined in step S140 that the data transfer process is not to be executed, the IDMA control unit 37 omits the process in step S141 and advances the process to step S142.

  In step S142, the IDMA control unit 37 executes a switching process. That is, in step S142, the IDMA control unit 37 performs a turn process for switching the pickup when there are two pickups of the drive 22 (1 Dev-2OP), and the switching of the OP after the status report at the time of reading or writing, Enter the turn-off state and wait until it is turned on. Note that this process is omitted when the drive 22 has one pickup or 2 Dev-2OP. When the process of step S142 ends, the IDMA control unit 37 advances the process to step S143, determines whether or not to end the GOP process, and determines that it does not end, returns the process to step S132, and thereafter Repeat the process. If it is determined in step S143 that the GOP process is to be ended, the IMDA control unit 37 ends the GOP process.

  Next, details of the command start preparation process executed in step S132 of FIG. 40 will be described with reference to the flowchart of FIG.

  When the command start preparation process is started, in step S161, the IDMA control unit 37 determines whether the command accumulated sector length value is equal to the command final sector length value and the value of the variable CMD END is false (FALSE). Determine whether. If it is determined that the command cumulative sector length value is equal to the command last sector length value and the variable CMD END value is false (FALSE), that is, if it is determined that the command is not issued, the IDMA control unit 37 starts processing for the next PRD table, proceeds to step S162, requests the next PRD table, and in step S163, based on the processing result, determines whether or not the next PRD table exists. judge.

  If the PRD table is normally acquired based on the request and it is determined that the next PRD table exists, the IDMA control unit 37 proceeds to step S164, holds (latches) each information of the new PRD table, In step S165, the command start LBA is latched, and in step S166, the value of the command accumulated sector length is set to “0”.

  Next, in step S167, the IDMA control unit 37 sets a PRD number in the data transfer PRD pointer FIFO. FIG. 42 is a diagram illustrating a configuration example of the data transfer PRD pointer FIFO. Each time the IDMA control unit 37 acquires a new PRD table, the data transfer PRD pointer FIFO 401 stores the number of the PRD table (PRD number), and a PRD data transfer PRD pointer FIFO pointer 402 is added.

  When the PRD number is set in the data transfer PRD pointer FIFO, in step S168, the IDMA control unit 37 sets the value “1” in the processing flag 164 of the PRD table, ends the command start preparation process, and performs step S132 in FIG. Return processing to. When the process returns to step S132, the IDMA control unit 37 ends the process of step S132 as described above, and proceeds to step S133.

  In step S163, if the PRD table cannot be acquired based on the request in step S162 and it is determined that the next PRD table does not exist, the IDMA control unit 37 proceeds to step S169 and sets the value of the variable CMD END. Is set to true (TRUE), the command start preparation process is terminated, and the process returns to step S132 in FIG. When the process returns to step S132, the IDMA control unit 37 ends the process of step S132 as described above, and proceeds to step S133.

  Further, when it is determined in step S161 that the command accumulated sector length value is not equal to the command final sector length value, or the value of the variable CMD END is true (TRUE), that is, in the PRD process for this PRD table. If it is determined that there is a continuation of command issuance, the IDMA control unit 37 omits steps S162 to S169, ends the command start preparation process, and returns the process to step S132 in FIG. When the process returns to step S132, the IDMA control unit 37 ends the process of step S132 as described above, and proceeds to step S133.

  The IDMA processing unit 37 executes the command start preparation process as described above, acquires the PRD table, and acquires necessary information included in the PRD table.

  Next, details of the command start process executed in step S133 of FIG. 40 will be described with reference to the flowchart of FIG.

  First, in step S181, the IDMA control unit 37 determines whether or not the value of the command accumulated sector length is “0” and the value of the variable CMD END is false.

  When it is determined that the command accumulated sector length value is “0” and the value of the variable CMD END is false (FALSE) and the process is related to the first PIO command of the PRD, the IDMA control unit 37 Advances to step S182. In step S182, the IDMA PIO control unit 38 of the PIO processing hardware 271 is controlled by the IDMA control unit 37, and executes the IDMA PIO control process as described with reference to the flowchart of FIG. However, in this case, when it is determined in step S83 that the value of the EOF register is true and the IDMA PIO control process is completed, the IDMA PIO control unit 38 returns the process to step S182 in FIG. When the process returns to step S182, the IDMA processing unit 37 ends the command start process and returns the process to step S133 of FIG. When the process returns to step S133, the IDMA control unit 37 ends the process of step S133 as described above, and proceeds to step S134.

  If it is determined in step S181 in FIG. 43 that the value of the command accumulated sector length is not “0” or the value of the variable CMD END is true (TRUE), the IDMA control unit 37 performs the process in step S182. The process is omitted, the command start process is terminated, and the process returns to step S133 in FIG. When the process returns to step S133, the IDMA control unit 37 ends the process of step S133 as described above, and proceeds to step S134.

  The IDMA control unit 37 executes the command start process as described above and issues a PIO command.

  Next, details of the command execution process executed in step S134 of FIG. 40 will be described with reference to the flowchart of FIG.

  The IDMA control unit 37 that has started the command execution process first determines whether or not the value of the variable CMD END is true. If the value of the variable CMD END is false (FALSE) and it is determined that there is a continuation of the PIO command, the IDMA control unit 37 advances the process to step S202. In step S202, the IDMA PIO control unit 38 of the PIO processing hardware 271 is controlled by the IDMA control unit 37, and executes the IDMA PIO control process as described with reference to the flowchart of FIG. However, in this case, when it is determined in step S83 that the value of the EOF register is true and the IDMA PIO control process is terminated, the IDMA PIO control unit 38 returns the process to step S202 in FIG. When the process returns to step S202, the IDMA control unit 37 advances the process to step S203.

  In step S203, the IDMA control unit 37 adds the sector number of 1RUB to the command accumulated sector length, adds the value “1” to the command reserved RUB number, and adds the value “1” to the command Tag. In step S204, the IDMA control unit 37 shifts to the turn-off state and waits until the turn-on state is reached. If the drive 22 has one pickup, this process is omitted.

  Thereafter, in step S205, the IDMA control unit 37 determines whether the number of reserved RUBs is less than the limit queue number, the value of the write / read setting (RXW) 173 is read, and the value of the variable CMD END is not true (TRUE). Determine whether or not. If it is determined that the number of reserved RUBs is less than the limit queue number, the value of the write / read setting (RXW) 173 is read, and the value of the variable CMD END is not true (TRUE), the IDMA control unit 37 performs step S206. Control is performed so that the command start preparation process is executed again. When the process of step S206 is completed, the IDMA control unit 37 ends the command execution process and returns the process to step S134 of FIG. When the process returns to step S134, the IDMA control unit 37 ends the process of step S134 as described above, and proceeds to step S135.

  In step S205, it is determined that the number of reserved RUBs is larger than the limit queue number, the value of the write / read setting (RXW) 173 is “Write”, or the value of the variable CMD END is true (TRUE). In this case, the IDMA control unit 37 omits the process of step S206 to end the command transfer process in order to shift to the data transfer process, and returns the process to step S134 of FIG. When the process returns to step S134, the IDMA control unit 37 ends the process of step S134 as described above, and proceeds to step S135.

  Furthermore, when it is determined in step S201 that the value of the variable CMD END is true (TRUE), the IDMA control unit 37 ends the processes of steps S202 to S206, ends the command execution process, and the process illustrated in FIG. The process returns to step S134. When the process returns to step S134, the IDMA control unit 37 ends the process of step S134 as described above, and proceeds to step S135.

  The IDMA control unit 37 executes the command execution process as described above and issues a PIO command.

  Next, details of the data transfer start preparation process executed in step S136 of FIG. 40 will be described with reference to the flowchart of FIG.

  The IDMA control unit 37 that has started the data transfer start preparation process first determines whether or not the value of the data transfer accumulated sector length is the same as the data transfer last sector length in step S221, and the data transfer accumulated sector length is determined. If it is determined that the value of is the same as the last sector length of the data transfer, the process proceeds to step S222 to start the process for the next PRD table.

  In step S222, the IDMA control unit 37 determines whether or not the next data transfer PRD table exists. If it is determined that the next data transfer PRD table exists, the process proceeds to step S223. In step S223, the PRD No. 1st / 2nd of the data transfer SDRAM pointer FIFO 421 shown in FIG. 46 is set. In step S224, the value “0” is set in the data transfer accumulated sector length. In step S225, the data transfer last sector is set. The length is set, and the data transfer start LBA is set in step S226. In step S 227, if there is no read transfer permission in this process, after transitioning to turn-off (Turn Off), the process waits until obtaining a turn-on with read transfer permission (Turn On). If the acquired turn-on does not have permission, it is turned off again and waits until a new permission for read transfer is obtained. If the drive 22 has one pickup, this process is omitted.

  When the process of step S227 ends, the IDMA control unit 37 ends the data transfer start preparation process and returns the process to step S136 of FIG. When the process returns to step S136, the IDMA control unit 37 ends the process of step S136 as described above, and proceeds to step S137.

  In FIG. 46, read or write DMA processing is performed with one PRD table, but the SDRAM address may be divided into several parts. Therefore, SDRAM information to be divided in one PRD table read process or write process is stored in this FIFO from the first to the last, and from this information, the SDRAM address and length (number of sectors) are DMA execution units. 39. The first and second information of the PRD number in which the SDRAM address is written is stored in this FIFO.

  In step S221 of FIG. 45, if it is determined that the data transfer accumulated sector length is not equal to the data transfer final sector length, there is a continuation of command issuance, so the IDMA control unit 37 omits the processing of steps S222 to S226. Then, the process proceeds to step S227.

  If it is determined in step S222 that the next data transfer PRD does not exist, 1GOP processing is completed, so the IDMA control unit 37 proceeds to step S228, shifts to a turn-off state, and prepares for data transfer start. The process is terminated and the GOP process of FIG. 40 is terminated. If the drive 22 has one pickup, the process of step S228 is omitted.

  Next, details of the data transfer start preparation process executed in step S137 of FIG. 40 will be described with reference to the flowchart of FIG.

  The IDMA control unit 37 that has started the data transfer start preparation process first shifts to a turn-off state when the command is read and does not have permission for read transfer in step S241, and waits until it shifts to a turn-on state with read transfer permission. To do. Further, even when the turn-on state is entered, when the turn-on state is entered without permission for read transfer, the IDMA control unit 37 waits until the turn-on state is entered again and the read transfer permission is entered again. .

  When transitioning to the turn-on state with permission for read transfer, the IDMA control unit 37 advances the process to step S242. If the drive 22 has one pickup, this process is omitted. The IDMA PIO control unit 38 is controlled by the IMDA control unit 37 and executes the IDMA PIO control process as described with reference to the flowchart of FIG. However, in this case, when it is determined in step S83 that the value of the EOF register is true and the IDMA PIO control process is terminated, the IDMA PIO control unit 38 returns the process to step S242 in FIG. When the process returns to step S242, the IDMA control unit 37 ends the data transfer service process and returns the process to step S137 of FIG. When the process returns to step S137, the IDMA control unit 37 ends the process of step S137 as described above, and proceeds to step S138.

  Next, details of the data transfer execution process executed in step S138 of FIG. 40 will be described with reference to the flowchart of FIG.

  The IDMA control unit 37 that has started the data transfer execution process first determines whether or not the value of No Data Transfer 162 in the PRD table is “1” in step S261. If it is determined that the value of No Data Transfer 162 is not “1”, the IDMA control unit 37 advances the process to step S262, supplies a START command to the DMA execution unit 39 of the DMA processing hardware 273, and performs DMA data transfer. Let it begin.

  When the process of step S262 ends, the IDMA control unit 37 advances the process to step S263, refers to the PRD table (or SDRAM address additional setting table), and determines whether the next SDRAM address exists. If it is determined that the next SDRAM address exists, the IDMA control unit 37 proceeds to step S264 to increment the value of the data transfer SDRAM Adrs, Length pointer FIFO pointer 422 shown in FIG. 46 by “1”, and then proceeds to step S265. At this time, the address and length information of the SDRAM corresponding to the value of the data transfer SDRAM Adrs, Length pointer FIFO pointer 422 are supplied to the DMA execution unit 39. When the process of step S265 ends, the IDMA control unit 37 returns the process to step S263 and repeats the subsequent processes.

  The IDMA control unit 37 that has performed the processing of all the SDRAM addresses by repeating the processing of Step S263 to Step S265 determines that the next SDRAM address does not exist and is waiting for the end of data transfer in Step S263. The transfer execution process ends, and the process returns to step S138 in FIG. When the process returns to step S138, the IDMA control unit 37 ends the process of step S138 as described above, and proceeds to step S139.

  If it is determined in step S261 that the value of No Data Transfer 162 in the PRD table is “1”, the IDMA control unit 37 ends the data transfer execution process and returns the process to step S138 of FIG. When the process returns to step S138, the IDMA control unit 37 ends the process of step S138 as described above, and proceeds to step S139.

  Next, details of the data transfer status report processing executed in step S139 of FIG. 40 will be described with reference to the flowchart of FIG.

  In step S281, the IDMA control unit 37 that has started the data transfer status reporting process first has a command “Write” (the executed process is a write process), and the OP (pickup) switching timing of the drive 22 is determined. In the case of before the status report, after transitioning to the turn-off state, wait until the transition to the turn-on state. If the drive 22 has one pickup, this process is omitted.

  When the turn-on state is entered or the drive 22 has only one pickup, the IDMA control unit 73 advances the process to step S282. In step S282, the IDMA PIO control unit 38 is controlled by the IMDA control unit 37, and executes the IDMA PIO control process as described with reference to the flowchart of FIG. However, in this case, when it is determined in step S83 that the value of the EOF register is true and the IDMA PIO control process is terminated, the IDMA PIO control unit 38 returns the process to step S282 in FIG. When the process returns to step S282, the IDMA control unit 37 advances the process to step S283.

  In step S283, the IDMA control unit 37 increments the data transfer accumulated sector length value by the number of sectors of 1 RUB. In step S284, the IDMA control unit 37 decrements the command reserved RUB number by “1”. In step S285, the IDMA control unit 37 decrements the number of data transfer tags. Incremented by "1", and in step S286, it is determined whether or not the data transfer accumulated sector length matches the data transfer PRD sector. If it is determined that the data transfer PRD sector matches, the IDMA control unit 37 determines in step S141 in FIG. Control is performed to execute the transfer end process, the data transfer state report process is ended, and the process returns to step S139 in FIG. When the process returns to step S139, the IDMA control unit 37 ends the process of step S139 as described above, and proceeds to step S140.

  49, if it is determined in step S286 that the data transfer accumulated sector length does not match the data transfer PRD sector, the IDMA control unit 37 performs control so as not to execute the data transfer end process in step S141 of FIG. Then, the data transfer status reporting process is terminated, and the process returns to step S139 in FIG. When the process returns to step S139, the IDMA control unit 37 ends the process of step S139 as described above, and proceeds to step S140.

  Next, an example of the data transfer end process will be described with reference to the flowchart of FIG.

  In step S301, the IDMA PIO control unit 38 is controlled by the IMDA control unit 37, and executes the IDMA PIO control process as described with reference to the flowchart of FIG. However, in this case, when it is determined in step S83 that the value of the EOF register is true and the IDMA PIO control process is terminated, the IDMA PIO control unit 38 returns the process to step S301 in FIG. When the process returns to step S301, the IDMA control unit 37 advances the process to step S302.

  In step S302, the IDMA control unit 37 sets the value of the completion flag of the PRD table to “1”, sets the value of the processing flag to “0”, and sets a CPU interrupt due to the end of 1PRD processing in step S303. .

  In step S304, the IDMA control unit 37 determines whether or not the value of the temporary stop flag 247 at the end of the single PRD is “1” with reference to the interrupt factor setting in the area 113F, and the value is “1”. If it is determined that there is, it is paused, so the process proceeds to step S305 and waits until the pause is released.

  When the temporary stop is released, the IDMA control unit 37 advances the process to step S306. In step S304, if the value of the temporary stop flag 247 at the end of the single PRD is not “1” and it is determined that the pause is not in progress, the IDMA control unit 37 advances the process to step S306.

  In step S306, the IDMA control unit 37 increments the value of the data transfer PRD pointer FIFO pointer by “1”, ends the data transfer end process, and returns the process to step S141 in FIG. When the process returns to step S141, the IDMA control unit 37 ends the process of step S141 as described above, and proceeds to step S142.

  As described above, the IDMA PRD control hardware 272 of the ATA host hardware 21 controls the PIO processing hardware 271 and the DMA processing hardware 273 while continuously performing PIO processing and DMA based on a plurality of PRD tables. In order to execute the processing, as shown in FIG. 51, the CPU 23 first accesses the ATA host hardware 21, supplies a PRD table, a DMA PIO script, etc. Processing and DMA processing are executed.

  Therefore, the CPU 23 and the ATA host hardware 21 need only access the first and last two times, and access to the PIO register (register (PIO)) 53A and the DMA register (register (DMA)) 53B of the ATA device. Since access is continuously executed by the ATA host hardware 21 without the CPU 23 access, not only can the bus 42 occupy the PIO processing and DMA processing but also the data transfer processing of the CPU 23 can be reduced. CPU 23 can transfer data more easily.

  As described with reference to FIG. 7, in the IDMA transfer mode described above, the GOP process described with reference to the flowchart of FIG. 40 by the forced termination instruction (abort instruction) is also the case of the IDMA PIO control process. Similarly, it may be forcibly terminated. However, the IDMA control unit 37 of the IDMA PRD control hardware 272 controls the PIO processing hardware 271 to execute the IDMA PIO control processing in the middle of the GOP processing, or controls the DMA execution unit 39 of the DMA processing hardware 273. To execute DMA processing. At this time, when the abort process (forced termination process) is performed and the IDMA control unit 37 terminates the process, each unit that is executing the process cannot return the processing result to the IDMA control unit 37, which may cause inconvenience. is there.

  Therefore, when performing the abort process, the IDMA control unit 37 waits until each unit that has executed the process completes the process.

  The abort process performed by the IDMA control unit 37 will be described with reference to the flowchart of FIG.

  In step S321, the IDMA control unit 37 that has generated an abort command and started the abort process requests the IDMA PIO control unit 38 of the PIO processing hardware 271, and determines whether the process is being executed. To do. When the IDMA control unit 37 requests the IDMA PIO control unit 38 to perform the process in the GOP process being executed and determines that the process is being executed, the process proceeds to step S322, and the process of the IDMA PIO control unit 38 Wait until is finished. When the processing of the IDMA PIO control unit 38 is completed and the processing result is returned, the IDMA control unit 37 then proceeds to step S323 and requests the DMA execution unit 39 of the DMA processing hardware 273 to perform the processing. It is determined whether the process is being executed. When the IDMA control unit 37 requests the DMA execution unit 39 to perform processing in the GOP processing being executed and determines that the processing is being executed, the process proceeds to step S324, and the processing of the DMA execution unit 39 ends. Wait until When the processing of the DMA execution unit 39 ends and the processing result is returned, the IDMA control unit 37 advances the processing to step S325, ends the GOP processing being executed, and ends the abort processing.

  In step S321, if the IDMA PIO control unit 38 is not requested to perform the process and it is determined that the process is not being executed, the IDMA control unit 37 omits the process in step S322 and performs the process in step S323. Proceed. Similarly, in step S323, if the DMA execution unit 39 has not been requested to perform processing and it is determined that the processing is not being executed, the IDMA control unit 37 skips step S324 and proceeds to step S325. Proceed, finish the GOP process being executed without waiting, and then end the abort process.

  As described above, by waiting after the processes of the IDMA PIO control unit 38 and the DMA execution unit 39 are aborted, the IDMA control unit 37 can safely abort (forcibly terminate) the GOP process.

  In the above, the case where the drive 22 has one pickup has been described. However, besides this, the drive 22 can perform the above-described processing even when there are a plurality of pickups, for example. However, in that case, as described later, it is necessary to perform the processing described above for each pickup. In the following, a case where there are two pickups in the drive 22 will be described.

  A drive having two pickups for reading and writing data to and from a recording medium, for example, can perform writing and reading processes simultaneously on both pickups, so that it is twice that of a drive having one pickup. Write processing and read processing can be performed at a rate. In addition, when two pickups write or read the same data, such a drive can also improve the reliability of the reading process and the writing process.

  In addition, while performing the writing process with one pickup and reading the written data with the other pickup, the drive writes while confirming whether the data is normally recorded on the recording medium. Processing can also be performed. Further, while one pickup is performing the reading process, the other pickup can perform a data writing process different from the data read by the background process.

  In such a drive, as described above, the pickups need to be controlled independently of each other in order to operate in cooperation in some cases and to operate independently in other cases. That is, when the drive has a plurality of pickups as described above, it is necessary for the ATA host hardware 21 to be able to execute the above-described processing related to the through PIO transfer mode and the IDMA transfer mode for each pickup.

  However, in the ATA standard, there is no protocol for a case where an ATA device has a plurality of pickups. That is, operating the drive having two pickups as described above is not defined in the ATA standard.

  Therefore, in order to operate such a drive as described above in a manner compliant with the ATA standard as described above, a drive having two pickups is shown in FIG. 53A on the ATA standard. Data transfer is performed by operating as two devices having one pickup, or data transfer is performed by operating as one device having one pickup, as shown in FIG. 53B. Need to do.

  In FIG. 53A, the ATA host hardware 21 performs data transfer as if the two pickups OP0 and OP1 of the drive are two devices of the device 431 and the device 432 on the ATA standard. . On the other hand, in the case of FIG. 53B, the ATA host hardware 21 conceals the two pickups OP0 and OP1 of the drive and performs data transfer as one device 433 on the ATA standard.

  Actually, in any case, the ATA host hardware 21 issues a command and transfers data to each of the two pickups (OP0 and OP1) of the drive as shown in FIG. . For example, in FIG. 54, the No. 0 GOP process and the No. 3 GOP process are performed on the pickup OP0, the No. 1 GOP process, the No. 2 GOP process, .4 GOP processing is performed. At this time, DMA transfer of each pickup is performed alternately by 1 RUB so as to proceed in parallel. In other words, the ATA host hardware 21 advances the processing for OP0 and the processing for OP1 in parallel, and when exchanging with the drive, the ATA host hardware 21 alternately performs them in a predetermined unit so that these multiple pickups are handled. It works as if it were processing at the same time.

  As described above, the data transfer by the ATA host hardware 21 includes the through PIO transfer mode and the IDMA data transfer mode. However, in the through PIO mode, each command issuance and data transfer are independent, and the ATA host hardware 21 only needs to perform these processes alternately for each pickup, so each PIO process corresponds. If the pickups can be identified, the control for each pickup can be realized by basically the same operation as in the case of one pickup described above.

  However, in the IDMA transfer mode, each DMA process is composed of a plurality of phases, and in the read process, part of each DMA process is performed in parallel, so the ATA host hardware 21 proceeds with the process. It is necessary to control (manage). In the following, the control in the IDMA transfer mode by the ATA host hardware 21 will be described.

  FIG. 55 is a diagram showing functional blocks of the ATA host hardware 21 in the IDMA transfer mode when the drive 22 has two pickups OP0 and OP1.

  As described above, the ATA host hardware 21 needs to perform GOP processing for each pickup and control the processing procedure. That is, a process of performing parallel branching (fork) so that a plurality of PRD processes allocated to OP0 and OP1 are performed for each OP, and processing that branches in parallel after each process is completed (fork) It is necessary to perform a join.

  In order to perform such a control process, the IDMA control unit 37 forks each PRD process and performs a cloud process for performing control so that the PRD process is joined after the process is completed, and performs a GOP process for the forked OP0. The OP0 GOP processing unit 442, the OP1 GOP processing unit 443 that performs GOP processing on the forked OP1, the OP0 GOP processing unit 442, and the OP1 GOP processing unit 443 are each a part of the PIO processing hardware 271 and a DMA execution unit. 39 (DMA processing hardware 273) is configured by selectors 444A and 444B that perform switching processing. Hereinafter, when it is not necessary to distinguish between the selector 444A and the selector 444B, they are referred to as a selector 444.

  Here, the GOP process indicates a process in which a plurality of PRD processes configured by only one of the read process and the write process for one pickup are combined. That is, the GOP process executed in the OP0 GOP processing unit 442 is a plurality of PRD processes configured by at least one of a read process PRD process for the pickup OP0 and a write process PRD process for the pickup OP0. The GOP process executed in the GOP processing unit 443 is a plurality of PRD processes configured by at least one of a read process PRD process for the pickup OP1 and a write process PRD process for the pickup OP1.

  When the cloud processing unit 441 of the IDMA control unit 37 acquires the PRD table stored in the SRAM 52, the cloud processing unit 441 controls which of the PRD processes by the PRD table of the OP0 GOP processing unit 442 or OP1 GOP processing unit 443 corresponds. The PRD process is executed by the PRD table.

  The OP0 GOP processing unit 442 is controlled by the cloud processing unit 441 to execute each PRD process for OP0, and controls each unit of the PIO processing hardware 271 and the DMA execution unit 39 to perform GOP processing for OP0. .

  The OP1 GOP processing unit 442 is controlled by the cloud processing unit 441 to execute each PRD process for OP1, and controls each unit of the PIO processing hardware 271 and the DMA execution unit 39 to perform GOP processing for OP1. .

  The selector 444A connects the OP0 GOP processing unit 442 and the OP1 GOP processing unit 442 to each unit of the PIO processing hardware 271, and the selector 444A selects the OP0 GOP processing unit 442 as necessary. And the OP1 GOP processing unit 442 is connected to the DMA execution unit 39.

  In the following, the case of performing data transfer by operating as two devices having one pickup as described above, and the case of performing data transfer by operating as if appearing as one device having one pickup However, first, a case will be described in which data transfer is performed by operating as if it were two devices having one pickup.

  FIG. 56 is a diagram illustrating an example of a cloud process and a GOP process schedule executed based on the PRD table.

  When the ATA host hardware 21 executes the PRD process for the PRD table 451 to the PRD table 457 shown in FIG. 56, the IDMA control unit 37 first refers to the PRD table (PRD0) number 0. Since this PRD table is a table for the read processing for OP0, the cloud processing unit 441 of the IDMA control unit 37 causes the OP0 GOP processing unit 442 to execute the PRD processing 451 for this PRD table.

  Similarly, the cloud processing unit 441 refers to the PRD table (PRD1) of number 1, causes the PRD processing 452 to be executed by the GOP processing unit 443 for OP1, refers to the PRD table (PRD2) of number 2, and the PRD. The processing 453 is executed by the OP0 GOP processing unit 442 and the number 3 PRD table (PRD3) is referred to, the PRD processing 454 is executed by the OP1 GOP processing unit 443 and the number 4 PRD table (PRD4) is referenced. Then, the PRD process 455 is executed by the OP1 GOP processing unit 443, the PRD table (PRD5) of number 5 is referred to, the PRD process 456 is executed by the OP0 GOP processing unit 442, and the PRD table of number 6 ( Referring to PRD 6), the PRD process 457 is executed by the OP0 GOP processing unit 442.

  In FIG. 56, the diagram shown on the left side of the PRD table shows the cloud processing by the cloud processing unit 441, and the processing corresponding to “OP0” in the upper stage is the processing by the OP0 GOP processing unit 442. The processing corresponding to “OP1” in the lower row is processing by the OP1 GOP processing unit 443.

  At this time, since both the PRD process 451 and the PRD process 453 are read processes (Read) and the order of the processes is continuous, the OP0 GOP processing unit 442 executes these processes as one GOP process 461. . The PRD process 456 and the PRD process 457 are a write process (Write) and a read process (Read), respectively, and the same process is not continuous. Therefore, the OP0 GOP processing unit 442 executes the PRD process 456 as the GOP process 464 and executes the PRD process 457 as the GOP process 465.

  Similarly, the OP1 GOP processing unit 443 executes the PRD processing 452 that performs the reading processing (Read) as one GOP processing 462, and the PRD processing 454 and the PRD processing 455 in which the processing order is continuous (both are the writing processing). (Write)) is executed as one GOP process 463.

  In this way, the cloud processing unit 441 executes the GOP processing (PRD processing) by branching in parallel. That is, in the example of FIG. 56, the cloud processing unit 441 forks the GOP processing 461 to GOP processing 465 by one cloud processing (Crowd) 471, and joins the branched processing after the processing.

  At this time, the two pickups OP0 and OP1 are processed as two devices in the ATA standard. Therefore, the start timing of the GOP process is independent between the processes for each pickup (upper stage and lower stage). That is, the OP0 GOP processing unit 442 can execute the next GOP processing 464 immediately after the end of the GOP processing 461 regardless of the progress of the GOP processing by the OP1 GOP processing unit 443. The same applies to the start timing of the GOP process 465, and the OP0 GOP processing unit 442 can start the next GOP process 465 immediately after the end of the GOP process 464. The same applies to the OP1 GOP processing unit 443, and the OP1 GOP processing unit 443 can start the next GOP processing 463 immediately after the end of the GOP processing 462. In other words, the cloud processing unit 441 can cause the OP0 GOP processing unit 442 and the OP1 GOP processing unit 443 to execute a plurality of GOP processes by one cloud processing.

  As shown in FIG. 56, each DMA transfer (including command issuance) of GOP processing for each pickup executed in parallel cannot be performed simultaneously (transferred simultaneously) on the ATA. At the unit level, it is necessary to do either one by one.

  Therefore, specifically, as described with reference to FIG. 54, DMA transfer corresponding to the pickup OP0 (DMA transfer by the OP0 GOP processing unit 442) and DMA transfer corresponding to the pickup OP1 (OP1 GOP processing). DMA transfer by the unit 443) is alternately performed every 1 RUB.

  This DMA transfer processing (DMA processing) is configured by a plurality of phases as shown in FIG. 37, for example. For example, as shown in FIG. 57, the DMA processing includes a phase for issuing a DMA command (read command (R) or write command (W)) instructing read processing or write processing, and DMA Exe instructing execution of DMA. It consists of a phase for issuing a command (D), a phase for performing DMA data transfer (DMA), and a phase for reporting status (S).

  In such DMA processing, the processing load of the DMA transfer phase is the largest compared to the processing load of other phases. By the way, it is desirable that the processing by the OP0 GOP processing unit 442 and the OP1 GOP processing unit 443 should be averaged as much as possible. For example, if processing is concentrated on either side, the load on the GOP processing unit will increase, and there is a possibility that it will not operate normally at that moment. Therefore, the DMA transfer phase processing is performed every 1 RUB as described above. Make it switchable.

  For example, in the case of read processing, the switching timing is set immediately before issuing a DMA execution command as shown on the left side of FIG. 57, and in the case of write processing, the switching timing is shown on the right side of FIG. As described above, either one is selected from the end of the DMA transfer or the end of the status report.

  A specific example of the OP switching process will be described.

  As shown in FIG. 58, when all the PRD processes in one cloud process are write processes (Write), the GOP process by the OP0 GOP processor 442 and the GOP process by the OP1 GOP processor 443 are respectively Each time the DMA transfer phase is completed, it is switched and executed alternately.

  In FIG. 58, only the case of switching at the end of DMA transfer is described. The case of switching at the end of status reporting is basically the same as the case of FIG. 58 except that the timing is different.

  As shown in FIG. 59, when all the PRD processes in one cloud process are read processes (Read), the GOP process by the OP0 GOP processing unit 442 and the GOP process by the OP1 GOP processing unit 443 are respectively performed. Initially, a DMA command is issued (queuing), but thereafter, each GOP process is switched and executed alternately just before each DMA execution command is issued.

  Note that the process proceeds and, for example, when the GOP processing by the OP0 GOP processing unit 442 is completed and the GOP processing is performed only in the OP1 GOP processing unit 443, the OP1 GOP processing unit 443 performs the OP0 GOP processing. When OP switching is performed from the processing of the processing unit 442, the GOP processing unit 442 for OP0 has finished the GOP processing, so the processing is returned to the OP1 side without doing anything, and the GOP processing is performed by the GOP processing unit 443 for OP1. To continue.

  As shown in FIG. 60, even when the PRD process of the read process (Read) and the PRD process of the write process (Write) coexist, the operation is basically the same as described above, and at each switching timing. The DMA transfer is performed one by one. Note that, as shown in the OP1 stage in the figure, in addition to the switching timing described above, a switching process always occurs when one GOP process ends.

  As described above, in the case of 2Dev-2OP, the two pickups OP0 and OP1 are treated as different devices according to the ATA standard. That is, the GOP processing by the OP0 GOP processing unit 442 and the GOP processing by the OP1 GOP processing unit 443 may be performed independently of each other as long as the DMA command order and the DMA data transfer order are matched within each processing. Is done. Therefore, as shown in FIG. 56, both a read process and a write process can be included in one cloud process.

  FIG. 61 is a diagram illustrating a control relationship among the cloud processing unit 441, the OP0 GOP processing unit 442, the OP1 GOP processing unit 443, and the selector 444.

  When the cloud processing unit 441 forks the PRD process to the OP0 GOP processing unit 442, the cloud processing unit 441 issues a GopSTART command 601 to the OP0 GOP processing unit 442. The OP0 GOP processing unit 442 executes the assigned PRD processing based on the GopSTART command 601, and when the processing is completed, issues a GopNext Req command 602 to the cloud processing unit 441 to request the next PRD processing. To do. Based on this request, the cloud processing unit 441 issues a GopNext PRD command 603 to the OP0 GOP processing unit 442 and assigns the next PRD process.

  In addition, the cloud processing unit 441 issues a TurnON command and an RdTRNSF permission command 604 at a predetermined timing to the OP0 GOP processing unit 442 that is waiting in the TurnOFF state during the GOP processing, and the OP0 GOP processing unit. 442 shifts to the TurnON state and issues a read transfer permission. The OP0 GOP processing unit 442 resumes the PRD processing based on the TurnON command, and supplies the RdTRNSF Exe command 605 to the cloud processing unit 441 along with the read data based on the RdTRNSF permission command during DMA transfer. At that time, the OP0 GOP processing unit 442 also supplies a TurnOFF command to the cloud processing unit 441 and shifts to the TurnOFF state.

  When there is no PRD process assigned to the OP0 GOP processing unit 442, the cloud processing unit 441 issues a GopEND command 606 to the OP0 GOP processing unit 442. When completing the GOP processing, the OP0 GOP processing unit 442 issues a GopFINISH command 607 to the cloud processing unit 441.

  Note that the cloud processing unit 441 performs the same processing on the OP1 GOP processing unit 443, and the GopSTART command 611 corresponding to the GopSTART command 601, the GopNext PRD command 613 corresponding to the GopNext PRD command 603, the TurnON command, and the RdTRNSF The TurnON command and the RdTRNSF permission command 614 corresponding to the permission command 604 and the GopEND command 616 corresponding to the GopEND command 606 are issued at the same timing as in the case of the OP0 GOP processing unit 442, respectively.

  The OP1 GOP processing unit 443 also performs the same processing on the cloud processing unit 441, and the GopNext Req command 612 corresponding to the GopNext Req command 602, the TurnOFF command and the TurnOFF command corresponding to the RdTRNSF Exe command 605, and the RdTRNSF Exe A command 615 and a GopFINISH command 617 corresponding to the GopFINISH command 607 are issued at the same timing as in the case of the OP0 GOP processing unit 442, respectively.

  Further, the cloud processing unit 441 supplies a TurnOP command 618 indicating that the OP switching process has been performed to the selector 444 at a predetermined timing.

  As described above, in the IDMA control unit 37, the cloud processing unit 441 performs cloud processing and controls the OP0 GOP processing unit 442, the OP1 GOP processing unit 443, and the selector 444 to perform GOP processing (PRD processing). ) Is executed.

  Next, the entire cloud control process for controlling the cloud process as described above will be described with reference to the flowchart of FIG.

  First, in step S341, the cloud processing unit 441 performs an initialization process to initialize each variable and setting. For example, the cloud processing unit 441 sets (sets) the OP0 # PRD pointer, which is a pointer for assigning the PRD table (PRD processing) to the pickup OP0, and similarly sets the PRD table (PRD processing) to the pickup OP1. ) Is set (set) to “0”. Further, the cloud processing unit 441 sets (sets) the value of the CROWD END PRD pointer for specifying the PRD table for which the cloud processing is to be ended to “0”. Further, the cloud processing unit 441 fetches the PRD table, and OP0 # CrntRXW, which is a flag indicating whether the processing currently performed by the OP0 GOP processing unit 442 is write processing (write) or read processing (read). Similarly, a value of OP1 # CrntRXW that is a flag indicating whether the process currently performed by the OP1 GOP processing unit 443 is a write process (write) or a read process (read) is set. Set (set) a value.

  When the initialization process ends, the cloud processing unit 441 proceeds to step S342, waits until the semaphore is acquired, and locks the semaphore when the semaphore is acquired. The cloud processing unit 441 that acquired and locked the semaphore advances the processing to step S343, refers to the Crowd END PRD pointer, and indicates EOF indicating the end of the entire cloud control processing or Abort indicating the forced termination of the entire cloud control processing. Whether or not is detected is determined. If it is determined that neither EOF nor Abort is detected, the cloud processing unit 441 proceeds to step S344 in order to control the new cloud process, and refers to each PRD table stored in the SRAM 52. The processing order of each PRD table corresponding to the cloud process to be controlled is confirmed, the PRD table that is the last table in one cloud process is specified, and the table number is set in the Crowd END PRD pointer. As described above, in the case of 2Dev-2OP (when two pickups appear to be two devices), the table number of the PRD table set in EOF is set in the Crowd END PRD pointer.

  When the setting of the Crowd END PRD pointer is completed, the cloud processing unit 441 proceeds to step S345 to release the semaphore lock. In step S346, it is determined whether or not to perform the cloud control process for OP0 that controls the GOP process forked to OP0. If it is determined to perform, the process proceeds to step S347, and the cloud control process for OP0 is performed. Execute. The details of the cloud control processing for OP0 will be described later with reference to the flowcharts of FIGS. When the cloud control process for OP0 is executed and the process ends, the cloud processing unit 441 returns the process to step S342, and the next cloud process (the cloud of the unprocessed OP1 corresponding to the cloud process of OP0 controlled this time) In order to control (including processing), the subsequent processing is repeated.

  If it is determined in step S346 that the cloud control process for OP1 is not executed and the cloud control process for OP1 is executed, the cloud processing unit 441 proceeds to step S348 and executes the cloud control process for OP1. To do. Details of the cloud control processing for OP1 will be described later with reference to FIGS. 66 to 68. When the cloud control process for OP1 is executed and the process ends, the cloud processing unit 441 returns the process to step S342, and the next cloud process (the cloud of the unprocessed OP0 corresponding to the cloud process of OP1 controlled this time) In order to control (including processing), the subsequent processing is repeated.

  As described above, the cloud processing unit 441 controls all cloud processes by repeating the processes in steps S342 to S348 while appropriately executing the processes. If it is determined in step S343 that either EOF or Abort has been detected from the Crowd END PRD pointer, the cloud processing unit 441 proceeds to step S349 and indicates that control processing for all cloud processes has been completed. ALL END IRQ external interrupt factor to notify outside is set, and the entire cloud control process is terminated.

  The cloud processing unit 441 executes the entire cloud control process for controlling the progress of each cloud process as described above.

  Next, details of the cloud control processing for OP0 executed in step S347 of FIG. 62 will be described with reference to the flowcharts of FIGS.

  First, in step S361, the cloud processing unit 441 waits until the pickup OP0 (GOP processing unit 442 for pickup OP0) can shift to the TurnON state in which the GOP process is executed. Since the OP0 GOP processing unit 442 and the OP1 GOP processing unit 443 alternately perform the GOP processing, the GOP processing is executed while repeating the TurnON state for executing the processing and the TurnOFF state for waiting.

  When OP0 can shift to the TurnON state, the cloud processing unit 441 proceeds to Step S362, issues a GopSTART command 601 to the OP0 GOP processing unit 442, and starts GOP processing. Then, the cloud processing unit 441 proceeds to step S363, sets the value of OP0 # CrntRXW to “NULL”, and determines whether the OP0 GOP processing unit 442 shifts to the TurnOFF state in step S364 (OP0 GOP processing). A Turn OFF command 605 from the unit 442), a GopNext Req command 602 requesting the next PRD table (PRD processing) from the OP0 GOP processing unit 442, or a GopFINISH command 607 for notifying the end of the GOP processing. Wait until you get it.

  When any of these commands is acquired from the OP0 GOP processing unit 442, the cloud processing unit 441 proceeds to step S365, and determines whether or not the OP0 GOP processing unit 442 has shifted to the TurnOFF state. . When it is determined that the acquired command is the TurnOFF command 605 and the OP0 GOP processing unit 442 has shifted to the TurnOFF state, the cloud processing unit 441 proceeds to Step S366, and the OP1 GOP processing unit 443 transmits the TurnON command 614. Switch the Turn, for example.

  Then, in step S367, the cloud processing unit 441 waits until the Turn is switched again (until the TurnOFF command 615 is acquired from the OP1 GOP processing unit 443), and when acquiring the TurnOFF command 615 from the OP1 GOP processing unit 443, The process proceeds to step S368, and the Turn is switched by, for example, issuing a TurnON command 604 to the OP0 GOP processing unit 442. The cloud processing unit 441 that switched Turn returns the processing to Step S364 and repeats the subsequent processing.

  If it is determined in step S365 that the acquired command is not the TurnOFF command 605 and the OP0 GOP processing unit 442 has not shifted to the TurnOFF state, the cloud processing unit 441 advances the processing to step S371 in FIG.

  In step S371 in FIG. 64, the cloud processing unit 441 determines whether the acquired command is the GopNext Req command 602. If the cloud processing unit 441 determines that the acquired command is the GopNext Req command 602, the cloud processing unit 441 proceeds to step S372, Fetch the PRD table and update the OP0 # PRD pointer.

  When the process of step S372 ends, the cloud processing unit 441 proceeds to step S373 and determines whether or not the PRD table specified by the OP0 # PRD pointer matches the PRD table specified by the Crowd END PRD pointer. . When it is determined that the value of the OP0 # PRD pointer does not match the value of the Crowd END PRD pointer and the PRD table specified by the OP0 # PRD pointer does not match the PRD table specified by the Crowd END PRD pointer, the cloud processing unit 441 Advances the process to step S374 to add an SDRAM address, which is an access destination address of the SDRAM 24, or determine whether the fetched PRD table is not a PRD table for the pickup OP0.

  The cloud processing unit 441 that determines that the fetched PRD table is not the PRD table for the pickup OP0 and does not add the SDRAM address, proceeds to step S375, increments the OP0 # PRD pointer, and fetches the next PRD table. Therefore, the process returns to step S372, and the subsequent processes are repeated.

  Also, in step S374, the fetched PRD table is the PRD table for the pickup OP0, and the cloud processing unit 441 that has determined that the SDRAM address corresponding to the PRD process is to be added proceeds to step S376, where OP0 # CrntRXW It is determined whether the value is “NULL” or the RXW of the fetched PRD table.

  When it is determined that the value of OP0 # CrntRXW is “NULL” or the RXW of the fetched PRD table, the cloud processing unit 441 has the same type of PRD table processed last time as the PRD table processed last time, or GOP Recognizing that this is the first PRD table of the process, the process proceeds to step S377, and the GopNEXT PRD command 603 is issued to the OP0 GOP processing unit 442, and the OP0 GOP processing unit 442 performs the PRD processing of the PRD table. Let it run. When the GopNEXT PRD command 603 is issued, the cloud processing unit 441 increments the OP0 # PRD pointer in step S378, returns the process to step S364 in FIG. 63, and repeats the subsequent processes.

  In step S373 in FIG. 64, the value of the OP0 # PRD pointer matches the value of the Crowd END PRD pointer, and it is determined that the PRD table specified by the OP0 # PRD pointer matches the PRD table specified by the Crowd END PRD pointer. In this case, the cloud processing unit 441 recognizes that one cloud process has been completed, proceeds to step S379, issues a GopEND command 606 to the OP0 GOP processing unit 442, and terminates the GOP process. Instruct. The cloud processing unit 441 that issued the GopEND command 606 returns the process to step S364 in FIG. 63 and repeats the subsequent processes.

  Furthermore, if it is determined in step S376 in FIG. 64 that the value of OP0 # CrntRXW is neither “NULL” nor the RXW of the fetched PRD table, the cloud processing unit 441 determines the type of processing of the PRD table to be processed this time. Since it is different from the previous time, it is recognized that one GOP process has been completed, the process proceeds to step S379, the GopEND command 606 is issued to the OP0 GOP processing unit 442, and the end of the GOP process is instructed. The cloud processing unit 441 that issued the GopEND command 606 returns the process to step S364 in FIG. 63 and repeats the subsequent processes.

  If it is determined in step S371 that the acquired command is not the GopNext Req command 602, the cloud processing unit 441 proceeds to step S381 in FIG.

  In step S381 in FIG. 65, the cloud processing unit 441 determines whether or not the GopFINISH command 607 has been acquired. If the cloud processing unit 441 determines that the GopFINISH command 607 has been acquired, the cloud processing unit 441 proceeds to step S382 and sets “1” in the OP0 FINISH flag. "Is set.

  When the OP0 FINISH flag is set to “1”, the cloud processing unit 441 advances the processing to step S383, and checks whether the PRD table specified by the OP0 # PRD pointer matches the PRD table specified by the Crowd END PRD pointer. judge. When it is determined that the value of the OP0 # PRD pointer matches the value of the Crowd END PRD pointer and the PRD table specified by the OP0 # PRD pointer matches the PRD table specified by the Crowd END PRD pointer, the cloud processing unit 441 The process advances to step S384 to end the cloud process and wait until the OP1 cloud process ends. When the cloud processing for OP1 ends, the cloud processing unit 441 ends the cloud control processing for OP0 and returns the processing to step S347 in FIG. When the process returns to step S347, the cloud processing unit 441 that has performed the entire cloud control process returns the process to step S342 as described above, and repeats the subsequent processes.

  If it is determined in step S381 in FIG. 65 that the GopFINISH command 607 has not been acquired, the cloud processing unit 441 returns the process to step S364 in FIG. 63 and repeats the subsequent processes. 65, the value of the OP0 # PRD pointer does not match the value of the Crowd END PRD pointer, and the PRD table specified by the OP0 # PRD pointer does not match the PRD table specified by the Crowd END PRD pointer. If determined to be, the cloud processing unit 441 proceeds with the process to step S361 of FIG. 63, and repeats the subsequent processes for the next GOP process.

  Next, details of the cloud control processing for OP1 executed in step S348 of FIG. 62 will be described with reference to the flowcharts of FIGS. Note that the OP1 cloud control process is basically performed in the same manner as the OP0 cloud control process described above.

  That is, first, the cloud processing unit 441 waits until the pickup OP1 (GOP processing unit for pickup OP1 443) can shift to the TurnON state, which is a mode for executing the GOP processing, in step S401 of FIG.

  When OP1 can shift to the TurnON state, the cloud processing unit 441 proceeds to step S402, issues a GopSTART command 611 to the OP1 GOP processing unit 443, and starts GOP processing. Then, the cloud processing unit 441 proceeds to step S403, sets the value of OP1 # CrntRXW to “NULL”, and acquires a TurnOFF command 615 from the OP1 GOP processing unit 443 in step S404, or acquires a GopNext Req command. Wait until 612 is acquired or the GopFINISH command 617 is acquired.

  When any of these commands is acquired from the OP1 GOP processing unit 443, the cloud processing unit 441 proceeds to Step S405, and determines whether the OP1 GOP processing unit 443 has shifted to the TurnOFF state. . When acquiring the TurnOFF command 615 and determining that the OP1 GOP processing unit 443 has shifted to the TurnOFF state, the cloud processing unit 441 proceeds to Step S406 and issues the TurnON command 604 to the OP0 GOP processing unit 442. Equivalent to switch the Turn.

  Then, in step S407, the cloud processing unit 441 waits until the Turn is switched again (until the TurnOFF command 605 is acquired from the OP0 GOP processing unit 442), and acquires the TurnOFF command 605 from the OP0 GOP processing unit 442. The process proceeds to step S408, and the Turn is switched by, for example, issuing a TurnON command 614 to the OP1 GOP processing unit 443. The cloud processing unit 441 that switched Turn returns the processing to Step S404 and repeats the subsequent processing.

  If it is determined in step S405 that the acquired command is not the TurnOFF command 615 and the OP1 GOP processing unit 443 has not shifted to the TurnOFF state, the cloud processing unit 441 advances the processing to step S411 in FIG.

  In step S411 in FIG. 67, the cloud processing unit 441 determines whether or not the acquired command is the GopNext Req command 612. If the cloud processing unit 441 determines that the acquired command is the GopNext Req command 612, the process proceeds to step S412. Fetch the PRD table and update the OP1 # PRD pointer.

  When the process of step S412 ends, the cloud processing unit 441 proceeds to step S413, and determines whether or not the PRD table specified by the OP1 # PRD pointer matches the PRD table specified by the Crowd END PRD pointer. . When it is determined that the value of the OP1 # PRD pointer does not match the value of the Crowd END PRD pointer and the PRD table specified by the OP1 # PRD pointer does not match the PRD table specified by the Crowd END PRD pointer, the cloud processing unit 441 Advances the process to step S414 to add an SDRAM address, which is an access destination address of the SDRAM 24, or determine whether the fetched PRD table is a PRD table for the pickup OP1.

  The cloud processing unit 441 that determines that the fetched PRD table is not the PRD table for the pickup OP1 and does not add the SDRAM address, proceeds to step S415, increments the OP1 # PRD pointer, and fetches the next PRD table. Therefore, the process is returned to step S412 and the subsequent processes are repeated.

  Also, in step S414, the fetched PRD table is the PRD table for the pickup OP1, and the cloud processing unit 441 that has determined to add the SDRAM address corresponding to the PRD process proceeds to step S416, and the OP1 # CrntRXW It is determined whether the value is “NULL” or the RXW of the fetched PRD table.

  When it is determined that the value of OP1 # CrntRXW is “NULL” or the RXW of the fetched PRD table, the cloud processing unit 441 has the same type of PRD table processed last time as the PRD table processed this time, or GOP Recognizing that it is the first PRD table of the process, the process proceeds to step S417, and the GopNEXT PRD command 613 is issued to the OP1 GOP processing unit 443, and the OPD GOP processing unit 443 performs the PRD process of the PRD table. Let it run. When the GopNEXT PRD command 613 is issued, the cloud processing unit 441 increments the OP1 # PRD pointer in step S418, returns the processing to step S404 in FIG. 66, and repeats the subsequent processing.

  Also, in step S413 in FIG. 64, the value of the OP1 # PRD pointer matches the value of the Crowd END PRD pointer, and it is determined that the PRD table specified by the OP1 # PRD pointer matches the PRD table specified by the Crowd END PRD pointer. In such a case, the cloud processing unit 441 recognizes that one cloud process has ended, proceeds to step S419, issues a GopEND command 616 to the OP1 GOP processing unit 443, and terminates the GOP process. Instruct. The cloud processing unit 441 that issued the GopEND command 616 returns the process to step S404 in FIG. 66 and repeats the subsequent processes.

  Furthermore, in step S416 in FIG. 67, when it is determined that the value of OP1 # CrntRXW is not “NULL” and is not the RXW of the fetched PRD table, the cloud processing unit 441 determines the type of processing of the PRD table to be processed this time. Since this is different from the previous time, it is recognized that one GOP process has been completed, the process proceeds to step S419, the GopEND command 616 is issued to the OP1 GOP processing unit 443, and the end of the GOP process is instructed. The cloud processing unit 441 that issued the GopEND command 616 returns the process to step S404 in FIG. 66 and repeats the subsequent processes.

  If it is determined in step S411 that the acquired command is not the GopNext Req command 612, the cloud processing unit 441 advances the processing to step S421 in FIG.

  68, the cloud processing unit 441 determines whether or not the GopFINISH command 617 has been acquired. If the cloud processing unit 441 determines that the GopFINISH command 617 has been acquired, the cloud processing unit 441 proceeds to step S422 and sets “1” in the OP1 FINISH flag. "Is set.

  When “1” is set in the OP1 FINISH flag, the cloud processing unit 441 advances the processing to step S423, and determines whether or not the PRD table specified by the OP1 # PRD pointer matches the PRD table specified by the Crowd END PRD pointer. judge. When it is determined that the value of the OP1 # PRD pointer matches the value of the Crowd END PRD pointer and the PRD table specified by the OP1 # PRD pointer matches the PRD table specified by the Crowd END PRD pointer, the cloud processing unit 441 The process advances to step S424 to end the cloud process and wait until the OP0 cloud process ends. When the cloud processing for OP0 ends, the cloud processing unit 441 ends the cloud control processing for OP1 and returns the processing to step S348 in FIG. When the process is returned to step S348, the cloud processing unit 441 that has performed the entire cloud control process returns the process to step S342 and repeats the subsequent processes as described above.

  If it is determined in step S421 in FIG. 68 that the GopFINISH command 617 has not been acquired, the cloud processing unit 441 returns the process to step S404 in FIG. 66 and repeats the subsequent processes. In step S423 in FIG. 68, the value of the OP1 # PRD pointer does not match the value of the Crowd END PRD pointer, and the PRD table specified by the OP1 # PRD pointer does not match the PRD table specified by the Crowd END PRD pointer. If determined to be, the cloud processing unit 441 proceeds to step S401 in FIG. 66, and repeats the subsequent processes for the next GOP process.

  As described above, the cloud processing unit 441 executes the entire cloud control process (including the cloud control process for OP0 and the cloud control process for OP1) that controls the cloud process, and controls each cloud process. As a result, each GOP process is executed on the GOP processing unit 442 for OP0 or the GOP processing unit 443 for OP1 corresponding to the GOP processing, so the ATA hardware 21 is connected to the drive 22 having two pickups. On the other hand, according to the ATA standard, a GOP process for each pickup can be executed as if it were a GOP process for two devices to perform a transfer process. Therefore, the CPU 23 can easily transfer data even when the drive 22 has a plurality of pickups.

  In the above description, a case has been described in which data transfer is performed by operating the drive 22 having two pickups so as to appear as two devices having one pickup (2 Dev-2OP). Next, a case where data transfer is performed by operating the drive 22 having two pickups so as to appear as one device having one pickup (1 Dev-2OP) will be described.

  FIG. 69 is a diagram for explaining an example of a schedule of cloud processing and GOP processing executed based on the PRD table. The configuration of FIG. 69 corresponds to the configuration of FIG.

  Similarly to the case of FIG. 56, the cloud processing unit 441 performs cloud processing even when the data transfer is performed by operating the drive 22 having two pickups so as to appear as one device having one pickup. Thus, each GOP process is forked and executed by the OP0 GOP processing unit 442 or the OP1 GOP processing unit 443. However, in this case, the pickup OP0 and the pickup OP1 are handled as the same pickup in the ATA standard, so the cloud processing unit 441 controls the GOP processing for OP0 and the GOP processing for OP1 independently. Unlike in the case of FIG. 56, the writing process (write) and the reading process (read) are not mixed in each cloud process.

  That is, in FIG. 69, when executing the PRD process based on the PRD table group shown on the right side in the figure, which is the same table as in FIG. 56, the cloud processing unit 441 is executed in the OP0 GOP processing unit 442. Until both the GOP process 661 composed of the PRD process 651 and the PRD process 653 and the GOP process 662 composed of the PRD process 652 of the read process executed in the OP1 GOP processing unit 443 are completed. The GOP processing unit 442 and the OP1 GOP processing unit 443 are not allowed to execute the next GOP processing. Therefore, the GOP process 661 and the GOP process 662 are configured as one cloud process 671.

  When the cloud processing 441 is completed (after joining the forked GOP processing once), the cloud processing unit 441 forks the GOP processing 663 and the GOP processing 664 as the next cloud processing 672 and causes each unit to execute them. This cloud process 672 is configured only by a GOP process that performs a write process. Since the next GOP process 665 is a read process, the cloud processing unit 441 further sets this as the next cloud process 673, and after the cloud process 672 ends (the GOP process 663 and the GOP process 664 are completed, Then fork and run.

  In order to control in this way, the cloud processing unit 441 uses, as shown in FIG. 70, the OP switching timing, for example, in the case of read processing, immediately after issuing the DMA command and at two places at the end of the status report. In the case of processing, it is selected from either the end of DMA transfer or the end of status reporting.

  Therefore, the process related to OP switching in the case where all the GOP processes constituting one cloud process are configured by PRD processes that perform a write process (write) is described with reference to FIG. Since it is the same as the case of performing data transfer by operating as if it appears as a device (2 Dev-2OP), its description is omitted. In addition, as described with reference to FIG. 58, the same applies to the case where switching is performed at the end of DMA transfer or the case where switching is performed at the end of status reporting. .

  On the other hand, as shown in FIG. 71, the switching process when all the PRD processes in one cloud process are read processes (Read) is performed at two places immediately after issuing the DMA command and at the end of the status report. Done. This is because, in this method, only one queue is prepared for queuing the read command in order to make the drive 22 appear as one device having one pickup. This is because it is necessary to share the processing for the pickup OP0 and the processing for the pickup OP1. Accordingly, in this case, the limit queuing number in each of the processing for the pickup OP0 and the processing for the pickup OP1 is set to a value that is half the limit queuing number of the prepared queue.

  In the read process, the DMA command queuing is first performed until the limit queuing number is reached. At this time, the cloud processing unit 441 performs the pickup OP0 so that the subsequent DMA transfer is performed alternately. And the DMA command (R) for the pickup OP0 are alternately stored in the queue. Therefore, immediately after the DMA command is issued is set as the read processing switching timing.

  Further, since DMA transfer is alternately performed between the pickup OP0 and the pickup OP1, the end of status reporting is further set as a switching timing. Therefore, in the cloud processing in this case (cloud processing composed only of read processing), as shown in FIG. 71, the DMA command of OP0 and the DMA of OP1 are switched by switching immediately after issuing the DMA command first. When the commands are alternately queued and the total number of both reaches the limit queuing number by switching at the end of status reporting, the DMA transfer corresponding to OP0 and the DMA transfer corresponding to OP1 are performed once. Thereafter, the DMA command is issued once for each pickup, and the queuing number decreased by two by DMA transfer is increased to the limit queuing number.

  By repeating the above process, the ATA host hardware 21 executes a cloud process including only the GOP process of the read process.

  In the cloud processing of read processing, as shown in FIG. 72, the cloud processing unit 441 controls permission / prohibition of data transfer using an RdTRNSF permission command or the like, so that the command order and data transfer order are correctly set. DMA transfer is controlled so as to be associated.

  If the cloud processing unit 441 does not perform this control, for example, if the number of DMA command queuing for each pickup is different from each other, the queuing is continued in the GOP processing for one pickup, In the GOP process for the other pickup, DMA transfer may be started. When such a situation occurs, the queued command order and the data transfer order are different, which may cause inconvenience.

  Therefore, when a DMA transfer is performed in the GOP process of one pickup, the cloud processing unit 441 issues an RdTRNSF permission command for permitting data transfer to the GOP process of the other pickup, and each GOP process By not allowing the DMA transfer without the permission, the DMA transfer corresponding to OP0 and the DMA transfer corresponding to OP1 are surely performed alternately. Accordingly, the cloud processing unit 441 can correctly associate the command order with the data transfer order.

  When the GOP process for one pickup is completed and only the GOP process for the other pickup remains, only the GOP process remains for the DMA transfer. In this case, the cloud processing unit 441 performs the DMA transfer. RdTRNSF authorization command is not issued even if transfer is performed.

  With reference to the flowchart of FIG. 73, the Turn control process for controlling the transition of the Turn right by the cloud processing unit 441 will be described.

  First, in step S441, the cloud processing unit 441 sets a Turn right to the pickup OP0, and sets the OP0 GOP processing unit 442 to the TurnON state. Next, in step S442, the cloud processing unit 441 issues a RdTRNSF permission command to the OP0 GOP processing unit 442, thereby granting data transfer permission to the OP0 GOP processing unit 442, and managing the data transfer permission destination. Set OP0 to variable Read TRNSF permission.

  The cloud processing unit 441 that has finished the process of step S442 proceeds to the process of step S443, and waits until the GOP processing unit in the TurnON state shifts to the TurnOFF state. When a TurnOFF command is issued from the GOP processing unit in the TurnON state and the GOP processing unit shifts to the TurnOFF state, the cloud processing unit 441 proceeds to step S444, and the ROPTRNSF Exe is set by the GOP processing unit set to the variable ReadTRNSF permission. When the command is issued, the variable ReadTRNSF permission is updated and the data transfer permission destination is switched.

  In step S445, the cloud processing unit 441 determines whether or not the GOP processing unit on the side without the Turn right has ended the cloud processing (Crowd END). Then, the Turn right command is issued to the GOP processing unit without the Turn right to switch the Turn right. The cloud processing unit 441 that has switched the Turn right advances the processing to Step S448.

  If it is determined in step S445 that the GOP processing unit without the Turn right has not finished the cloud processing (Crowd END), the cloud processing unit 441 proceeds to step S447, and in step S443, the TurnOFF state Without switching the Turn right by issuing a TurnON command to the GOP processing unit that has shifted to (2), the GOP processing unit is set to the variable ReadTRNSF permission, and the process proceeds to step S448.

  In step S448, the cloud processing unit 441 determines whether to end the Turn control process. If it is determined not to end, the cloud processing unit 441 returns the process to Step S443 and repeats the subsequent processes. If it is determined in step S448 that the Turn control process is to be terminated, the cloud processing unit 441 terminates the Turn control process.

  As described above, the cloud processing unit 441 controls the setting of the Turn right and the data transfer permission destination. In this case, the entire cloud control process, the OP0 cloud control process, and the OP1 cloud control process seem to appear as two devices having one pickup described with reference to the flowcharts of FIGS. Since this is the same as the case where data transfer is performed by operating (2 Dev-2OP), the description thereof is omitted. However, in this case, when performing DMA transfer, each GOP processing unit determines whether or not data transfer permission has been issued to itself, and performs DMA transfer only when permitted.

  As described above, the cloud processing unit 441 controls the cloud processing while controlling the permission or prohibition of the data transfer, so that the ATA host hardware 21 is in accordance with the ATA standard for the drive 22 having two pickups. The transfer process can be performed by executing the GOP process for each pickup as if it were a GOP process for one pickup. Therefore, the CPU 23 can easily transfer data even when the drive 22 has a plurality of pickups.

  As described above, the ATA host hardware 21 of the present invention allows the CPU 23 to perform PIO processing or the like based on the information such as the PIO script and the PRD table stored in the SRAM 52 and the register 53 built in the ATA host hardware 21. There is no upper limit as long as the DMA processing can be continuously executed without access by the CPU 23 and the data size to be transferred can be specified by information such as a PIO script or a PRD table. It is easy to continuously read and write video data that cannot be transferred by DMA transfer. Further, the number of communications (communication data amount) between the CPU 23 and the ATA host hardware 21 at this time is also a case where information such as a PIO script or a PRD table is stored in the SRAM 52 or the register 53, and a case where a processing end is notified Therefore, the CPU 23 can greatly reduce the load due to data transfer. This also allows the ATA host hardware to reduce the bus occupancy.

  The series of processes described above can be executed by hardware or can be executed by software. In this case, for example, the ATA host hardware 21 in FIG. 6 may be configured as a part of a personal computer as shown in FIG.

  In FIG. 74, the CPU 711 of the personal computer 701 executes various processes according to a program stored in a ROM (Read Only Memory) 712 or a program loaded from the storage unit 723 to the RAM 713. The RAM 713 also stores data necessary for the CPU 711 to execute various processes as appropriate.

  The CPU 711, the ROM 712, and the RAM 713 are connected to each other via a bus 714. An input / output interface 720 is also connected to the bus 714.

  The input / output interface 720 includes an input unit 721 including a keyboard and a mouse, a display including a CRT and an LCD, an output unit 722 including a speaker, a storage unit 723 including a hard disk, a modem, and the like. A communication unit 724 is connected. The communication unit 724 performs communication processing via the network 12 including the Internet.

  A drive 725 is also connected to the input / output interface 720 as necessary, and a removable medium 726 such as a magnetic disk, an optical disk, a magneto-optical disk, or a semiconductor memory is appropriately mounted, and a computer program read from them is loaded. It is installed in the storage unit 723 as necessary.

  When the above-described series of processing is executed by software, a program constituting the software is installed from a network or a recording medium.

  For example, as shown in FIG. 74, the recording medium is distributed to distribute the program to the user separately from the apparatus main body, and includes a magnetic disk (including a flexible disk) on which the program is recorded, an optical disk ( Removable media 726 composed of CD-ROM (compact disk-read only memory), DVD (digital versatile disk), magneto-optical disk (including MD (mini-disk) (registered trademark)), or semiconductor memory In addition to being configured, it is configured by a ROM 712 in which a program is recorded, a hard disk included in the storage unit 723, and the like distributed to the user in a state of being incorporated in the apparatus main body in advance.

  In the present specification, the step of describing the program recorded on the recording medium is not limited to the processing performed in chronological order according to the described order, but is not necessarily performed in chronological order. It also includes processes that are executed individually.

  Further, in this specification, the system represents the entire apparatus constituted by a plurality of apparatuses.

It is a block diagram explaining the conventional PIO transfer mode. It is a schematic diagram explaining CPU access in the conventional PIO transfer mode. It is a block diagram explaining the conventional single word / multiword DMA transfer mode. It is a block diagram explaining the conventional UltraDMA transfer mode. It is a schematic diagram explaining CPU access in the conventional UltraDMA transfer mode. It is a block diagram which shows the structural example of the ATA host hardware to which this invention is applied. It is a figure explaining the mode of a state transition in the data transfer process of the ATA host hardware of FIG. It is a figure which shows the structural example of the data hold | maintained at SRAM and the register | resistor of FIG. It is a figure which shows the structural example of the through PIO script described in the area | region 101 of FIG. It is a figure which shows the structural example of the PIO CPU interrupt factor generation condition described in the area | region 102 of FIG. FIG. 9 is a diagram illustrating a configuration example of a table of read repetition / IfGoto conditions described in an area 102 in FIG. 8. It is a figure which shows the structural example of the user addition register comprised in the area | region 104 of FIG. It is a figure which shows the structural example of the PRD table for IDMA comprised in the area | region 105 and the area | region 106 of FIG. FIG. 9 is a diagram illustrating a configuration example of an SDRAM address addition setting table for IDMA configured in an area 106 in FIG. 8. FIG. 9 is a diagram illustrating a configuration example of a PIO script for IDMA configured in an area 107 in FIG. 8. FIG. 9 is a diagram illustrating a configuration example of mode / status information in setting information related to the entire ATA configured in the area 111 of the register 53 in FIG. 8. FIG. 9 is a diagram illustrating a configuration example of temporary stop information among setting information related to the entire ATA configured in an area 111 of the register 53 of FIG. 8. FIG. 9 is a diagram illustrating a configuration example of through PIO processing setting in setting information related to a through PIO transfer mode configured in an area 112 in FIG. 8. FIG. 9 is a diagram showing a configuration example of semaphore setting among setting information related to the through PIO transfer mode configured in the area 112 of FIG. 8. It is a figure which shows the structural example of the 1st IDMA process setting which is one of the setting information regarding the setting information regarding the IDMA transfer mode comprised in the area | region 113 of FIG. It is a figure which shows the structural example of the 2nd IDMA process setting which is one of the setting information regarding the setting information regarding the IDMA transfer mode comprised in the area | region 113 of FIG. It is a figure which shows the structural example of the 3rd IDMA process setting which is one of the setting information regarding the setting information regarding the IDMA transfer mode comprised in the area | region 113 of FIG. It is a figure which shows the structural example of the semaphore setting which is one of the setting information regarding the setting information regarding the IDMA transfer mode comprised in the area | region 113 of FIG. It is a figure which shows the structural example of the LBA setting which is one of the setting information regarding the setting information regarding the IDMA transfer mode comprised in the area | region 113 of FIG. It is a figure which shows the structural example of the interruption factor setting which is one of the setting information regarding the setting information regarding the IDMA transfer mode comprised in the area | region 113 of FIG. It is a figure which shows the functional block of the ATA host hardware 21 in the through PIO transfer mode to which this invention is applied. It is a flowchart explaining through PIO control processing. It is a flowchart explaining a single PIO script process. It is a flowchart explaining the process regarding the PIO script of through PIO transfer mode. It is a figure explaining the example of CPU access in through PIO transfer mode. It is a flowchart explaining an abort process. It is a figure which shows the functional block of the ATA host hardware 21 in IDMA transfer mode to which this invention is applied. It is a flowchart explaining the process regarding the IDMA PIO script of IDMA transfer mode. It is a flowchart explaining IDMA PIO control processing. It is a flowchart explaining the other example of an abort process. It is a flowchart explaining the process regarding the PRD table of IDMA transfer mode. It is a figure explaining the detailed structural example of the process with respect to a PRD table. It is a figure explaining the example of the process with respect to the PRD table in case READ continues. It is a figure explaining the example of the process with respect to the PRD table in case READ and WRITE coexist. It is a flowchart explaining the GOP process which controls an IDMA process in GOP unit. It is a flowchart explaining the detail of a command start preparation process. It is a figure which shows the structural example of a data transfer PRD pointer FIFO. It is a flowchart explaining the detail of a command start process. It is a flowchart explaining the detail of a command execution process. It is a flowchart explaining the detail of a data transfer start preparation process. It is a figure which shows the structural example of a data transfer SDRAM pointer FIFO. It is a flowchart explaining the detail of a data transfer start preparation process. It is a flowchart explaining the detail of a data transfer execution process. It is a flowchart explaining the detail of a data transfer state report process. It is a flowchart explaining the example of a data transfer end process. It is a figure explaining the example of CPU access in IDMA transfer mode. It is a flowchart explaining an abort process. It is a figure explaining the response | compatibility by the ATA host hardware 21 with respect to the drive which has two pick-ups. It is a figure explaining the mode of DMA transfer when a GOP process is branched in parallel with respect to two pickups. It is a figure which shows the functional block of the ATA host hardware 21 in IDMA transfer mode when the drive 22 has two pickups OP0 and OP1. It is a figure explaining the example of the schedule of the cloud process performed based on a PRD table, and a GOP process. It is a figure explaining the switching timing of a pickup. It is a figure explaining the cloud process comprised only by a write process. It is a figure explaining the cloud process comprised only by a read process. It is a figure explaining the cloud process in which the read process and the write process are mixed. It is a figure explaining the exchange of the command of a cloud process part and a GOP process part. It is a flowchart explaining a cloud whole control process. It is a flowchart explaining the cloud control process for OP0. It is a flowchart following FIG. 63 explaining the cloud control processing for OP0. FIG. 65 is a flowchart for explaining OP0 cloud control processing, following FIG. 64. It is a flowchart explaining the cloud control processing for OP1. FIG. 67 is a flowchart following FIG. 66 for explaining the cloud control processing for OP1. It is a flowchart following FIG. 67 explaining the cloud control processing for OP1. It is a figure explaining the example of the schedule of the cloud process performed based on a PRD table, and a GOP process. It is a figure explaining the switching timing of a pickup. It is a figure explaining the cloud process comprised only by a read process. It is a figure explaining the cloud process comprised only by a read process. It is a flowchart explaining a Turn control process. And FIG. 16 is a block diagram illustrating a configuration example of a personal computer.

Explanation of symbols

  21 ATA host hardware, 22 drives, 23 CPU, 24 SDRAM, 31 ATA host, 33 through PIO control unit, 34 single PIO script processing unit, 35 PIO execution unit, 36 ATA interface processing unit, 37 IDMA control unit, 38 IDMA PIO control unit, 39 DMA execution unit, 51 I / O control unit, 52 SRAM, 53 registers, 255 through PIO processing hardware, 268 ATA register (PIO), 271 PIO processing hardware, 272 IDMA PRD control hardware, 273 DMA Processing hardware, 401 data transfer PRD pointer FIFO, 402 data transfer PRD pointer FIFO pointer, 421 data transfer SDRAM pointer FIFO, 422 data transfer SDRAM Adrs, Length pointer FIFO pointer, 425 register (PIO), 426 register (DMA), 441 Cloud processing , 442 OP0 GOP processing unit, 443 OP1 GOP processing unit, 444A and 444B selector, 711 CPU, 712 ROM, 713 RAM, 714 bus, 720 I / O interface, 721 input unit, 722 output unit, 723 storage unit, 724 Communication unit, 725 drive, 726 removable media

Claims (11)

An interface control device for controlling an interface of an ATA device having a plurality of pickups,
Based on each of a plurality of PRD tables in which information related to data transfer performed between the ATA device and an external storage unit of the ATA device is described, processing related to the data transfer corresponding to each PRD table Parallel branching means for branching a certain PRD process in parallel for each pickup corresponding to each PRD table;
An interface control apparatus comprising: control means for controlling the progress of each PRD process branched in parallel by the parallel branching means. The PRD process is composed of a plurality of phases including a plurality of processes related to the data transfer,
The control means switches the PRD process corresponding to each pickup in parallel by switching a pickup that advances the PRD process at the end or start of a predetermined phase among the plurality of phases included in the PRD process. The interface control device according to claim 1, wherein The control means starts the first phase of the PRD process for performing the next read process after the last phase of the PRD process for performing the write process for each pickup, and performs the read process for each pickup. The interface control apparatus according to claim 2, wherein after the last phase of the PRD process for performing the first write process is completed, the first phase of the PRD process for performing the next write process is started. The control means switches the pickup that performs processing at either the end of the phase of performing data transfer or the end of the phase of performing status reporting of the PRD processing that performs write processing. The interface control device according to claim 3. 4. The interface control device according to claim 3, wherein the control unit switches the pickup that performs processing at the start of a phase of issuing a command instructing data transfer in the PRD processing that performs read processing. 5. . The control means starts the first phase of the PRD process for performing the next read process after the last phase of the PRD process for performing the write process for all the pickups, and reads all the pickups. The interface control apparatus according to claim 2, wherein after the last phase of the PRD process for performing the first write process is completed, the first phase of the PRD process for performing the next write process is started. The control means switches the pickup that performs processing at either the end of the phase of performing data transfer or the end of the phase of performing status reporting of the PRD processing that performs write processing. The interface control device according to claim 6. The control means includes the pickup that performs the process at either the end of the phase of issuing the command instructing the read process of the PRD process that performs the read process or the phase of performing the status report. The interface control device according to claim 3, wherein switching is performed. Controls permission or prohibition of the data transfer by the PRD process, and grants the data transfer permission to the PRD process corresponding to any one of all the pickups, and supports other pickups The data transfer is prohibited for the PRD process to be performed, and if the data transfer is performed in the PRD process of the pickup that has given the data transfer permission, the data transfer is permitted when the pickup to perform the process is switched. When the PRD process of the pickup that switches the pickup and gives the prohibition of data transfer is completed, further comprises a data transfer control means for controlling the PRD process so as not to allow the data transfer,
When the data transfer control means does not allow the data transfer to the PRD process of the switching destination of the pickup to be processed, the control means performs the process again without proceeding with the PRD process. The interface control apparatus according to claim 8, wherein the pickup to be performed is switched. An interface control method for an interface control device for controlling an interface of an ATA device having a plurality of pickups,
Based on each of a plurality of PRD tables in which information related to data transfer performed between the ATA device and an external storage unit of the ATA device is described, processing related to the data transfer corresponding to each PRD table A parallel branch step for branching a PRD process in parallel for each pickup corresponding to each PRD table;
And a control step for controlling the progress of each PRD process branched in parallel by the process of the parallel branch step. In a program that causes a computer to control the interface of an ATA device having multiple pickups,
The first process based on a forced termination instruction of the first process issued to a first process related to data transfer performed between the ATA device and a storage unit external to the ATA device. A determination step of determining whether or not the second process relating to the data transfer is being executed, and is a process derived from the process and using the process result in the first process;
When it is determined that the second process is being executed by the process of the determination step, a standby step of waiting for the end process based on the forced end instruction until the second process ends;
And a termination step of terminating the first processing by performing the termination processing based on the forced termination instruction when it is determined by the processing of the determination step that the second processing is not being executed. program.

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