JP2005236965A - Signal receiving circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To perform impedance matching of an entire transmission line, including fine transmission lines, in a simple circuit configuration. <P>SOLUTION: First and second transmission lines 100 and 106 are connected to each other in series. A first terminator 101 is connected to the first transmission line 100 in parallel and is provided externally of a semiconductor device 105. A second terminator 103 is connected to the second transmission line 106 in parallel and is provided inside the semiconductor device 105. The values of the first and second terminators are adjusted so that the combined resistance value of the first and second terminators 101 and 103 and the second transmission line 106 matches with the impedance of the first transmission line 101. Impedance matching of the entire transmission line can be achieved with this simple construction, thus, a stable, high quality signal can be transmitted. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a signal receiving circuit for transmitting and receiving an AV signal including video and audio with high quality, and a video and audio receiving apparatus including the signal receiving circuit.

  In recent years, with development of AV equipment such as a DVD recorder and a TV, a technique for transmitting high-definition baseband video / audio signals using a high-speed interface is required. Examples of high-speed interfaces include DVI (Digital Visual Interface) and HDMI (High-Definition Multimedia Interface) standards. Here, DVI is a standard used when digitally transmitting a video signal to an LCD or CRT. HDMI is a digital interface standard for next-generation televisions based on DVI and adding functions for home appliances while maintaining backward compatibility.

  However, when these high-speed interfaces are used for connection between LSIs or devices to transmit a video / audio signal at a high speed, a high-frequency video / audio signal is used. For this reason, the distance between the signal transmission circuit, the signal reception circuit, and the transmission line through which they pass cannot be ignored. Therefore, it is necessary to consider the impedance of the transmission path of the high frequency signal by introducing the concept of distance. Furthermore, when the impedance of the signal source and the impedance of the load do not match, a so-called reflection phenomenon occurs in which a part of the signal from the signal source rebounds without being transmitted to the load side. As a result, the noise generated due to the reflection phenomenon becomes so large that it cannot be ignored, and the operation of the apparatus may be adversely affected.

  In order to solve these problems, a method of preventing reflection is generally used by matching impedance between a transmission line and an LSI or between devices at a transmitting end or a receiving end. FIG. 13 shows a conceptual diagram of the principle of impedance matching of a transmission line. The impedance of the transmission line 1300 is Zo (Ω), and the terminating resistor 1301 for matching with Zo is Rout (Ω). A termination resistor 1301 corresponding to the transmission line 1300 is connected in parallel to the transmission line 1300 as shown in FIG. Then, the value of the termination resistor 1301 is adjusted so that the impedance Zo of the transmission line 1300 and the impedance Rout of the termination resistor 1301 are equal. Then, the transmission line 1300 having the characteristic impedance Zo is considered to be equivalent to continuing infinitely, and no reflection is generated in principle.

  FIG. 14 is an example in which impedance matching is performed based on the principle of impedance matching in a signal receiving circuit using a transmission line and a semiconductor device. As shown in FIG. 14, a termination resistor 1401 for performing impedance matching between the transmission line 1400 and the semiconductor receiving device 1405 is externally attached to the semiconductor receiving device 1405. Here, the termination resistor 1401 has a resistance value equal to the impedance Zo of the transmission line 1400. However, in the method of FIG. 14, since the termination resistor is externally attached, the area of the printed circuit board on which the signal receiving circuit 14 is wired becomes large.

  In order to reduce the area of the printed circuit board on which the signal receiving circuit is wired, a termination resistor is built in FIG. That is, FIG. 15 shows another example in which impedance matching is performed based on the principle of impedance matching in a signal receiving circuit using a transmission line and a semiconductor device. As shown in FIG. 15, a termination resistor 1503 for performing impedance matching between the transmission line 1500 and the semiconductor receiving device 1505 is built in the semiconductor receiving device 1505. The impedance Zo of the transmission line 1500 and the impedance Rin of the termination resistor 1503 are equal. In this method, since the termination resistor is built in, the area of the printed circuit board on which the signal receiving circuit is wired is smaller than that in FIG. However, since this method incorporates a termination resistor, the resistance value varies depending on voltage fluctuations, temperature fluctuations, and manufacturing process characteristics. Therefore, it becomes difficult to match the impedance of the transmission line 1500.

In order to solve these problems, Patent Document 1 discloses a technique in which a termination resistor is built in the semiconductor receiving device 1605 and the termination resistor is a variable resistor. FIG. 16 shows an example of Patent Document 1. Specifically, a plurality of CMOS transistors and resistors connected in series are connected in parallel to the transmission line 1600. The gate line of each CMOS transistor is connected to the switch control unit. A voltage characteristic and temperature characteristic detection unit is connected in front of the switch control unit. Next, the operation of FIG. 16 will be described. First, when the detection unit detects a voltage variation, a temperature variation, or a resistance value shift due to a manufacturing process, it sends a command signal corresponding to the situation to the switch control unit. The switch control unit determines an appropriate resistance value of the variable resistor in response to the command signal. Then, a switch on / off signal for obtaining an appropriate resistance value is transmitted to the CMOS transistor. Then, the CMOS transistor is turned on / off corresponding to the signal, and the termination resistance Rin has an appropriate resistance value.
JP 2002-344300 A

  However, these impedance matching methods have the following problems.

  In the method of FIG. 14, the termination resistor 1401 and the semiconductor device 1405 are branched and connected via a minute transmission line 1406 such as an input / output lead wire or an electrode wiring. That is, it is considered that the transmission line 1400, the minute transmission line 1406, and the termination resistor 1401 are connected in parallel. Accordingly, as shown in the impedance graph of FIG. 14, the impedance is reduced by the impedance of the minute transmission line 1406, resulting in impedance mismatching. Therefore, reflection cannot be suppressed.

  In the method of FIG. 15, since the termination resistor 1503 is built in, the resistance value varies due to voltage fluctuation, temperature fluctuation, and manufacturing process characteristics. Therefore, it becomes difficult to match the impedance of the transmission line 1500. Furthermore, since there is no element that matches the impedance of the minute transmission line 1506, impedance mismatching occurs.

  Even in the case of Patent Document 1, impedance mismatch occurs due to the impedance of a minute transmission line 1606 such as an input / output lead wire or an electrode wiring. Since the termination resistor is built in as a variable resistor, a mechanism for adjusting the termination resistance value such as a switch control unit and a voltage characteristic and temperature characteristic detection unit is required. Therefore, the circuit configuration of the entire apparatus becomes complicated. Furthermore, the variable resistor is generally formed using a CMOS transistor as shown in FIG. A capacitance component exists between the drain and gate of the CMOS transistor or between the gate and source. As a result, the frequency characteristic of the variable termination resistor is poor, and the resistance value varies depending on the signal frequency. Therefore, as shown in the impedance graph of FIG. 16, the impedance of the CMOS transistor portion is locally reduced, and the impedance Zo of the transmission line 1600 is not constant.

  The present invention solves these problems, and an object thereof is to achieve impedance matching of the entire transmission line including a minute transmission line with a simple circuit configuration. Furthermore, the present invention provides a signal receiving circuit having excellent frequency characteristics and a video / audio receiving apparatus including the same by absorbing a variation in the built-in termination resistance with a configuration using a semiconductor receiving device having a built-in termination resistor. is there.

  In order to solve the above problem, the present invention 1 provides a signal receiving circuit including a first transmission line and a second transmission line, a semiconductor device, a first termination resistor, and a second termination resistor. In this signal receiving circuit, the first transmission line and the second transmission line are connected in series with each other. The semiconductor device receives a signal via the first transmission line and the second transmission line. The first termination resistor is connected in parallel to the first transmission line and is externally attached to the semiconductor device. The second termination resistor is connected in parallel to the second transmission line and is built in the semiconductor device.

  With such a simple configuration, the impedance Zo of the first transmission line and the impedance of the entire transmission line viewed from the first transmission line can be matched. Therefore, the impedance of the entire transmission line viewed from the first transmission line has a constant value. As a result, signal reflection can be prevented and a high-quality stable signal can be transmitted without distorting the signal waveform. Furthermore, since no element having a capacitance component is used to synthesize the impedance Zo of the first transmission line and the impedance of the entire transmission line viewed from the first transmission line, the frequency characteristics are good even in the transmission of high-frequency signals. .

  According to the second aspect of the present invention, in the first aspect, the combined resistance value Rt1 of the first termination resistor, the second termination resistor, and the second transmission line matches the impedance value Zo of the first transmission line. The resistance value Rout of the first termination resistor and the resistance value Rin of the second termination resistor are adjusted.

  With such a simple configuration, the impedance Zo of the first transmission line and the combined resistance Rt1 can be matched. Therefore, the impedance of the entire transmission line viewed from the first transmission line has a constant value. As a result, signal reflection can be prevented and a high-quality stable signal can be transmitted without distorting the signal waveform. Furthermore, since an element having a capacitive component is not used to synthesize the impedance Zo of the first transmission line and the combined resistance value Rt1, the frequency characteristics are good even in transmission of a high-frequency signal.

  A third aspect of the present invention provides the signal receiving circuit according to the first aspect, wherein the second transmission line includes a first series resistor externally connected in series to the semiconductor device. In this signal receiving circuit, the combined resistance value Rt2 of the first termination resistor, the second termination resistor, the impedance of the second transmission line, and the first series resistance matches the impedance value Zo of the first transmission line. Thus, the resistance value Rout of the first termination resistor, the resistance value Rin of the second termination resistor, and the first series resistance Rs1 are adjusted.

  When the impedance value Zo of the first transmission line is higher than the impedance value Zo ′ of the second transmission line (Zo> Zo ′), a first series resistor is inserted in series with the second transmission line. The resistance value Rout of the first termination resistor and the resistance value of the second termination resistor are matched so that the combined resistance value Rt2 of the combined resistor Rt1 and the first series resistor Rs1 matches the impedance Zo of the first transmission line. Rin and the first series resistance Rs1 are adjusted. As a result, the impedance value Zo of the first transmission line is larger than the impedance value Zo ′ of the second transmission line, and the two termination resistors, the resistance value Rout of the first termination resistor and the second termination resistor Rin, make the entire transmission line. Even when impedance matching cannot be performed, the impedance of the entire transmission line has a substantially constant value.

  A fourth aspect of the present invention provides the signal receiving circuit according to the first aspect, wherein the first transmission line includes a second series resistor in series with the second transmission line. In this signal receiving circuit, the combined resistance value Rt3 of the first termination resistance, the second termination resistance, the impedance of the second transmission line, and the second series resistance matches the impedance value Zo of the first transmission line. Thus, the resistance value Rout of the first termination resistor, the resistance value Rin of the second termination resistor, and the second series resistance Rs2 are adjusted.

  When the impedance value Zo of the first transmission line is higher than the combined resistance value Rt1 (Zo> Rt1), a second series resistor is inserted in series with the first transmission line. Then, the resistance value Rout of the first termination resistor and the second termination resistance are matched so that the combined resistance value Rt3 obtained by adding the second series resistance Rs2 to the combined resistance value Rt1 matches the impedance value Zo of the first transmission line. And the resistance value Rs2 of the second series resistor are adjusted. As a result, it is impossible to adjust the first termination resistor Rout and the second termination resistor Rin alone, and the relationship between the impedance Zo of the first transmission line and the combined resistor Rt1 becomes Zo> Rt1. Thus, the impedance of the entire transmission line can be adjusted to a constant value Zo. In addition, this configuration can make the impedance uniform more easily than the third aspect in which the first series resistance is inserted when the first transmission line Zo is higher than the second transmission line Zo ′.

  A fifth aspect of the present invention provides the signal receiving circuit according to the first aspect, further comprising a first surge countermeasure component connected in parallel to the second transmission line and externally attached to the semiconductor device. In this signal receiving circuit, the first resistance Rt4 of the first terminal resistance, the second terminal resistance, and the impedance of the second transmission line is matched with the impedance value Zo of the first transmission line. The resistance value Rout of the first termination resistor and the resistance value Rin of the second termination resistor are adjusted.

  In general, surge countermeasure components are inserted into a circuit for the purpose of preventing destruction of a semiconductor device due to high-voltage and high-frequency noise such as static electricity. However, surge countermeasure components have a capacitance component. For this reason, the impedance is reduced at the portion where the surge countermeasure component is inserted, and impedance mismatch occurs. Therefore, a first surge resistance component is inserted in parallel with the second transmission line so that the combined resistance value Rt4 equal to the combined resistance value Rt1 matches the impedance value Zo of the first transmission line. And the resistance value Rin of the second termination resistor are adjusted. As a result, the surge countermeasure component prevents damage to the semiconductor device due to noise, and the impedance of the entire transmission line is kept substantially constant. As a result, signal reflection in the entire transmission line can be prevented.

  A sixth aspect of the present invention provides the signal receiving circuit according to the fifth aspect of the present invention, further comprising a coil connected in series to the first termination resistor. In this signal receiving circuit, the combined resistance value Rt5 of the first termination resistor, the second termination resistor, and the impedance of the second transmission line matches the impedance value Zo of the first transmission line. The resistance value Rout of the first termination resistor and the resistance value Rin of the second termination resistor are adjusted.

  When a surge countermeasure component is inserted into the circuit, the surge countermeasure component has a capacitive component, and therefore the impedance decreases in a quadratic curve at the location where the surge countermeasure component is inserted. In particular, when the capacitance component of the surge countermeasure component is large, the local impedance drop is even greater, and the first termination resistor and the second termination resistor cannot be matched completely. On the other hand, the coil has a characteristic of increasing the impedance in a quadratic curve. Therefore, when the coil is inserted in series with the first termination resistor using this characteristic, the impedance due to the surge countermeasure component cancels out the impedance of the coil. Accordingly, the surge compensation component prevents the destruction of the semiconductor device due to noise, and the coil compensates for the impedance change due to the surge. As a result, the impedance can be kept constant, and high-quality and stable signal transmission can be performed without distorting the signal waveform.

  A seventh aspect of the present invention provides the signal receiving circuit according to the first aspect, further including a second surge countermeasure component connected in parallel to the first transmission line. In this signal receiving circuit, the combined resistance Rt6 of the first termination resistor, the second termination resistor, and the impedance of the second transmission line matches the impedance value Zo of the first transmission line. The resistance value Rout of the first termination resistor and the resistance value Rin of the second termination resistor are adjusted.

  Generally, surge countermeasure components are inserted into a circuit for the purpose of preventing destruction of a semiconductor device due to high voltage / high frequency noise such as static electricity, but the surge countermeasure components have a capacitance component. For this reason, the impedance is reduced at the place where the surge countermeasure component is inserted, and impedance mismatching occurs. Therefore, a surge countermeasure component is inserted in parallel with the first transmission line, and the resistance value of the first termination resistor is matched so that the combined resistance value Rt6 equal to the combined resistance value Rt1 matches the impedance Zo of the first transmission line. Rout and the resistance value Rin of the second termination resistor are adjusted. As a result, the surge countermeasure component can prevent the destruction of the semiconductor device due to noise, and can keep the impedance of the entire transmission line substantially constant, thereby preventing the reflection of the signal in the entire transmission line.

  The present invention 8 provides the signal receiving circuit according to the seventh invention, further comprising a coil connected in series to the first termination resistor. In the signal receiving circuit, the first termination is adjusted so that a combined resistance value Rt7 of the first termination resistor, the second termination resistor, and the impedance of the second transmission line matches the first transmission line Zo. The resistance value Rout of the resistor and the resistance value Rin of the second termination resistor are adjusted.

  When a surge countermeasure component is inserted into the circuit, the surge countermeasure component has a capacitive component, and therefore the impedance decreases in a quadratic curve at the location where the surge countermeasure component is inserted. In particular, when the capacitance component of the surge countermeasure component is large, the local impedance drop is even greater, and the first termination resistor and the second termination resistor cannot be matched completely. On the other hand, the coil has a characteristic of increasing the impedance in a quadratic curve. Therefore, when the coil is inserted in series with the first termination resistor using this characteristic, the impedance due to the surge countermeasure component cancels out the impedance of the coil. Accordingly, the surge compensation component prevents the destruction of the semiconductor device due to noise, and the coil compensates for the impedance change due to the surge. As a result, the impedance of the entire transmission line can be kept constant, and high-quality and stable signal transmission can be realized without distorting the signal waveform.

  A ninth aspect of the present invention provides the signal receiving circuit according to the first aspect, including a third transmission line, a fourth transmission line, a third terminating resistor, a fourth terminating resistor, and an operation signal receiving circuit. In this signal receiving circuit, the third transmission line transmits a signal having a phase opposite to that of the first transmission line, the fourth transmission line is connected in series with the third transmission line, and is opposite to the second transmission line. Transmit phase signal. The third termination resistor is connected in parallel to the third transmission line and is externally attached to the semiconductor device. The fourth termination resistor is connected in parallel to the fourth transmission line and is built in the semiconductor device. The semiconductor device has a differential signal receiving circuit, and further receives a signal through the third transmission line and the fourth transmission line. The first termination resistor, the second termination resistor, the third termination resistor, the fourth termination resistor, and the combined resistance value Rt8 of the second transmission line, and the combined impedance value of the first transmission line and the third transmission line The resistance value Rout18 of the first termination resistor, the resistance value Rout28 of the second termination resistor, the resistance value Rin18 of the third termination resistor, and the resistance value Rin28 of the fourth termination resistor are adjusted so as to match Zo. ing.

  Even when a differential receiving circuit is included, the impedance of the entire transmission line can be matched with a simple configuration. As a result, even when two signals having opposite phases are transmitted, reflection of each signal can be prevented, and a high-quality stable signal can be transmitted without distorting the signal waveform.

  A tenth aspect of the present invention provides the signal receiving circuit according to the ninth aspect, further including a common mode filter. In this signal receiving circuit, the common mode filter is connected in series to the first transmission line and the second transmission line, and is connected in series to the third transmission line and the fourth transmission line. The first termination resistor, the second termination resistor, the third termination resistor, the fourth termination resistor, the combined resistance value Rt9 of the second transmission line and the common mode filter, the first transmission line, and the first transmission line The resistance value Rout19 of the first termination resistor, the resistance value Rout29 of the second termination resistor, the resistance value Rin19 of the third termination resistor, and the fourth termination resistor so that the combined impedance value Zo of the three transmission lines matches. The resistance value Rin29 is adjusted.

  In general, a common mode filter is used in a circuit having a differential signal receiving circuit for the purpose of preventing the destruction of a semiconductor device due to high voltage / high frequency noise such as static electricity, but the common mode filter has a very high impedance. have. Therefore, the impedance rises at the location where the common mode filter is inserted, and impedance mismatch occurs. Therefore, each termination resistor is set so that the combined resistance Rt9 of the resistance values of the first, second, third, and fourth termination resistors and the impedance value of the common mode filter matches the impedance Zo of the first transmission line. Adjust the resistance value. Accordingly, the impedance of the entire transmission line can be kept substantially constant while inserting the common mode filter to prevent the semiconductor device from being destroyed by noise, and the reflection of the signal in the entire transmission line can be prevented.

  The video / audio receiving apparatus according to the eleventh aspect of the present invention includes the signal receiving circuit according to the first aspect of the present invention, and control means for outputting a signal received by the signal receiving circuit to an output apparatus.

  High-quality and stable signals can be transmitted without distorting the signal waveform. Therefore, by applying the signal receiving circuit according to the first aspect of the present invention to the video / audio reception device, it is possible to transmit an image or audio signal in a high quality state and realize a video / audio reception device with good image quality and sound quality.

  When the signal receiving circuit of the present invention is used, the impedance of the transmission line is matched with the impedance of the minute transmission line by an input / output lead wire or electrode wiring connecting the semiconductor device and the transmission line by a simple mechanism. Can do. Accordingly, high-quality and stable signal transmission can be realized without distorting the signal waveform.

  Hereinafter, the present invention will be described in detail with reference to FIGS.

<First Embodiment>
FIG. 1 is a block diagram of the signal receiving circuit according to the first embodiment of the present invention and its impedance graph. This signal receiving circuit is provided on a printed circuit board, for example. On the output side of the signal receiving circuit, a semiconductor device used for AV equipment such as a DVD recorder or a TV is provided. Various signals such as an audio signal and an image signal input from the input terminal of the signal receiving circuit are input to the semiconductor device.

(1-1) Configuration The signal receiving circuit 1 of FIG. 1 includes a first transmission line 100, a second transmission line 106, a semiconductor device 105, a first termination resistor 101, and a second termination resistor 103. The first transmission line 100 is a wiring on a printed circuit board (not shown) and has a signal input end 102. The second transmission line 106 includes input / output lead wires and electrode wirings of the semiconductor device 105 and is connected to the first transmission line 100 in series with each other. The semiconductor device 105 includes a receiver 104 for receiving signals. The receiver 104 is connected in series to the second transmission line 106 and receives a signal via the first transmission line 100 and the second transmission line 106. The first termination resistor 101 is connected in parallel to the first transmission line 100 and is externally attached to the semiconductor device 104. The second termination resistor 103 is built in the semiconductor device 105 and connected in parallel to the second transmission line 106. One end of each of the first termination resistor 101 and the second termination resistor 103 is connected to the power source Vtt.

  Although FIG. 1 shows the signal receiving circuit 1 using only one first termination resistor 101 and one second termination resistor 103, a configuration using a plurality of these may be used. The potential of the power supply Vtt is not particularly limited and may be ground.

(1-2) Impedance matching Next, how the impedance is matched in the signal receiving circuit 1 of FIG. 1 will be described. In the signal receiving circuit 1, the resistance value Rt1 of the combined resistance on the output side viewed from the first transmission line 100 and the input impedance Zo of the first transmission line 100 are matched (Rt1≈Zo). Here, the combined resistance value Rt1 is a combined resistance value of the first termination resistor 101, the second termination resistor 103, and the second transmission line 106. That is, in the signal receiving circuit 1, the following two resistance values that affect the combined resistance value Rt1 are adjusted so as to match the impedance of the entire transmission line.

(A) Resistance value Rout1 of the first termination resistor 101
(B) Resistance value Rin1 of the second termination resistor 106
Specifically, first, the resistance value Rin1 of the second termination resistor 103 is adjusted so as to be equal to the input impedance Zo ′ of the second transmission line 106. Thereby, the impedance of the second transmission line 106 can be regarded as a constant value Zo ′.

  The resistance value Rout1 of the first termination resistor 101 is adjusted to a value obtained based on the following equation (1). The following equation (1) represents a condition that the combined resistance value Rt1 on the output side viewed from the first transmission line 100 matches the input impedance Zo of the first transmission line 100.

  By modifying the above equation (1), the resistance value Rout1 of the first termination resistor 101 can be expressed by the following equation (2).

  When the resistance value Rout1 of the first termination resistor 101 is adjusted to the value obtained by the above equation (2), the impedance over the entire transmission line can be set to a substantially constant value Zo. Therefore, it is possible to suppress signal reflection and noise caused by the reflection.

  The impedance graph of FIG. 1 shows the relationship between the distance from the input end 102 and the impedance in the signal transmission direction. As described above, when the resistance value Rout1 of the first termination resistor 101 and the resistance value Rin1 of the second termination resistor 103 are adjusted, the impedance is substantially constant over the entire transmission line. In the impedance graph, a hatched portion corresponding to the position of the semiconductor device 105 represents an impedance error due to the manufacturing process of the semiconductor device 105. This error occurs for the following reason. Elements incorporated in the semiconductor device 105 are miniaturized due to restrictions on area and design. For this reason, an error is likely to occur in the element characteristics, and the sum of the impedance errors of the elements is generated as the illustrated impedance fluctuation.

(1-3) Effect In the present embodiment, the first transmission line 100 has a simple configuration in which the first termination resistor 101 and the second termination resistor 103 are connected in parallel to the first transmission line 100 and the second transmission line 106, respectively. And the output combined resistance value Rt1 viewed from the first transmission line 100 are matched. As a result, since the impedance of the entire transmission line is constant, signal reflection can be prevented. Therefore, a high-quality signal can be stably transmitted without distorting the signal waveform. Furthermore, since no capacitor or coil is used to match the input impedance Zo of the first transmission line 100 and the output-side combined resistance value Rt1, the frequency characteristics of the signal receiving circuit are good even in the transmission of high-frequency signals.

Second Embodiment
(2-1) Configuration FIG. 2 is a configuration diagram and an impedance graph of a signal receiving circuit according to the second embodiment of the present invention. The signal receiving circuit 2 of the present embodiment is suitable when the impedance value Zo of the first transmission line 200 is higher than the impedance value Zo ″ of the second transmission line 206 (Zo >> Zo ′).

  The signal receiving circuit 2 of FIG. 2 has a first series resistor 208 on the second transmission line 206. The first series resistor 208 is connected in series to the semiconductor device 205 and is externally attached to the semiconductor device 205. Other configurations of the signal receiving circuit 2 are the same as those in the first embodiment. That is, the first transmission line 200 and the second transmission line 206 are connected in series. A receiver 204 built in the semiconductor device 205 is connected in series to the second transmission line 206. A first termination resistor 201 having a resistance value Rout2 is connected in parallel to the first transmission line 200 and is externally attached to the semiconductor device 205. The second termination resistor 203 having the resistance value Rin2 is built in the semiconductor device 205 and connected in parallel to the second transmission line 206. One end of each of the first termination resistor 201 and the second termination resistor 203 is connected to the power supply Vtt.

  The potential of the power supply Vtt is not particularly limited and may be ground.

(2-2) Impedance Matching Next, how the impedance is matched in the signal receiving circuit 2 of FIG. 2 will be described. First, the problem in the case where the first series resistor 208 is not provided will be clarified, and then the case where it exists will be described.

(2-2-1) When there is no first series resistance First, let us consider a case where there is no first series resistance 208 in the signal receiving circuit 2 of FIG. This corresponds to the case where the impedance Zo of the first transmission line 100 is higher than the impedance Zo ′ of the second transmission line 106 (Zo >> Zo ′) in the signal receiving circuit 1 of FIG. In this case, since Rout1 becomes large in the above-described equation (1), the combined resistance value Rt1 can be approximated by the following equation (3). That is, the value of the impedance Rt1 on the output side viewed from the first transmission line 100 is “Rin1”, and the impedance cannot be set to a constant value Zo over the entire transmission line. Therefore, in the case of Zo >> Zo ′, it can be seen that the impedances may not be matched by the first termination resistor 201 and the second termination resistor 203 alone.

(2-2-2) When there is a first series resistance On the other hand, in the signal receiving circuit 2 of FIG. 2, the resistance value Rt2 of the combined resistance on the output side viewed from the first transmission line 200 and the first transmission line 200 Is matched with the input impedance Zo. Here, the combined resistance value Rt2 is a combined resistance value of the first termination resistor 201, the second termination resistor 203, the second transmission line 206, and the first series resistor 208. That is, in the signal receiving circuit 2, the following three resistance values that affect the combined resistance value Rt2 are adjusted to match the impedance.

(A) Resistance value Rout2 of the first termination resistor 201
(B) Resistance value Rin2 of the second termination resistor 203
(C) Resistance value Rs1 of the first series resistor 208
Specifically, first, the resistance value Rin2 of the second termination resistor 203 is adjusted to be equal to the impedance value Zo ′ of the second transmission line 206. Thereby, the impedance of the second transmission line 206 can be regarded as an apparent constant value Zo ′.

  The resistance value Rs1 of the first series resistor 208 is adjusted based on the following equation (4). The following equation (4) indicates a condition that the combined resistance value Rt2 on the output side viewed from the first transmission line 200 matches the input impedance Zo of the first transmission line 200.

  Now consider the case of Zo >> Zo '. Since Rout2 is large in the above equation (4), the combined resistance value Rt2 and the impedance matching condition are expressed by the following equation (5). The resistance value Rs1 of the first series resistor 208 is adjusted to a value obtained from the following equation (6) obtained by modifying the following equation (5). The resistance value Rout2 of the first termination resistor 201 is adjusted to Rout2 = Zo in consideration of matching with the first transmission line 100.

  As described above, by using the first series resistor 208 in addition to the first termination resistor 201 and the second termination resistor 203, even when the impedance difference between the first transmission line 201 and the second transmission line 206 is large ( Zo >> Zo ′), and the impedance over the entire transmission line can be set to a substantially constant value Zo. Therefore, even in the case of Zo >> Zo ′, it is possible to suppress the reflection of signals and the occurrence of noise caused by the reflection.

  The impedance graph of FIG. 2 shows the relationship between the distance from the input end 202 and the impedance in the signal transmission direction. A solid line indicates the impedance of the signal receiving circuit 2 including the first series resistor 208. As shown by the solid line, in the signal receiving circuit 2, even if the impedance difference between the first transmission line 200 and the second transmission line 206 is large (Zo >> Zo ′), the impedance of the entire transmission line has a constant value Zo. Have.

  The dotted line indicates the impedance when the first series resistor 208 is not used. When the first series resistor 207 is not inserted, the output-side impedance Rt2 = Rin2 viewed from the first transmission line 200 is obtained. That is, on the output side from the connection point 207 between the first transmission line 200 and the second transmission line 206, the impedance decreases. This is because the impedance Zo of the first transmission line 200 is higher than the impedance Zo ′ of the second transmission line 206.

(2-3) Effect In the present embodiment, in the case where the impedance Zo of the first transmission line 200 is higher than the impedance Zo ′ of the second transmission line 206, the first transmission line 200 is further added to the first termination resistance 201 and the second termination resistance 203. A series resistor 208 is used. As a result, even when Zo >> Zo ′, the output-side impedance viewed from the first transmission line 200 can be kept at a constant value Zo.

<Third Embodiment>
(3-1) Configuration FIG. 3 is a configuration diagram and an impedance graph of a signal receiving circuit according to the third embodiment of the present invention. As in the second embodiment, the signal receiving circuit 3 of the present embodiment is suitable when the impedance value Zo of the first transmission line 300 is higher than the impedance value Zo ″ of the second transmission line 306 (Zo >> Zo ').

  The signal receiving circuit 3 in FIG. 3 has a second series resistor 308 on the first transmission line 300. The second series resistor 308 is connected in series to the second transmission line 306. Other configurations of the signal receiving circuit 3 are the same as those in the first embodiment. That is, the first transmission line 300 and the second transmission line 306 are connected in series. A receiver 304 built in the semiconductor device 305 is connected in series to the second transmission line 306. A first termination resistor 301 having a resistance value Rout3 is connected in parallel to the first transmission line 300 and is externally attached to the semiconductor device 305. A second termination resistor 303 having a resistance value Rin3 is built in the semiconductor device 305 and connected in parallel to the second transmission line 306. One end of each of the first termination resistor 301 and the second termination resistor 303 is connected to the power source Vtt.

  The potential of the power supply Vtt is not particularly limited and may be ground.

(3-2) Impedance matching Next, how the impedance is matched in the signal receiving circuit 3 of FIG. 3 will be described. First, the case where the second series resistor 308 is not provided will be clarified, and the case where it is next will be described.

(3-2-1) When there is no second series resistance First, let us consider a case where there is no second series resistance 308 in the signal receiving circuit 3 of FIG. This corresponds to the same condition (Zo >> Zo ′) as in the second embodiment. That is, in the signal receiving circuit 1 of FIG. 1, this corresponds to the case where the impedance Zo of the first transmission line 100 is higher than the impedance Zo ′ of the second transmission line 106 (Zo >> Zo ′). In this case, since Rout1 becomes large in the above-described equation (1), the combined resistance value Rt1 can be approximated by the following equation (7). That is, the impedance value Rt1 on the output side as viewed from the first transmission line 100 is “Rin1”, and “Rin1” is adjusted to match Zo ′. Impedance cannot be made constant value Zo. Therefore, it can be seen that when Zo >> Zo ′, the impedance cannot be matched only by the first termination resistor 301 and the second termination resistor 303.

(3-2-2) When there is a second series resistance On the other hand, in the signal reception circuit 3 of FIG. 3, the resistance value Rt3 of the combined resistance when viewed from the first transmission line 300 and the first transmission line 300 The input impedance value Zo is matched. Here, the combined resistance value Rt3 is a combined resistance value of the first termination resistor 301, the second termination resistor 303, the second transmission line 306, and the second series resistor 308. That is, in the signal receiving circuit 3, the following three resistance values that affect the combined resistance value Rt3 are adjusted to match the impedance.

(A) Resistance value Rout3 of the first termination resistor 301
(B) Resistance value Rin3 of the second termination resistor 303
(C) Resistance value Rs2 of the second series resistor 308
Specifically, first, the resistance value Rin3 of the second termination resistor 303 is adjusted to be equal to the impedance value Zo ′ of the second transmission line 306. As a result, the second transmission line 306 can be apparently regarded as a constant value Zo ′.

  The resistance value Rout3 of the first termination resistor 301 and the resistance value Rs2 of the second series resistor 308 are adjusted based on the following equation (8). The following equation (8) represents a condition that the combined resistance value Rt3 on the output side viewed from the first transmission line 300 matches the input impedance Zo of the first transmission line 300.

  Now consider Zo >> Zo '. From the circuit diagram of FIG. 3, the output-side circuit viewed from the first transmission line 300 and the second series resistor 308 is the same as the output-side circuit viewed from the transmission line 100 of FIG. That is, the part of the first term of the above equation (8), that is, the part of the first transmission line 300 and the first termination resistor 301 is expressed by the approximate expression (7) described above using the condition of Zo >> Zo ′. (Expression (9) below). Then, the above equation (8) can be expressed as the following equation (10) using the following equation (9). The resistance value Rs2 of the second series resistor 308 is adjusted to a value obtained from the following equation (11) obtained by modifying the following equation (10). Further, the resistance value Rout3 of the first termination resistor 301 is adjusted to Rout3 = Zo in consideration of matching with the first transmission line 300.

  As described above, by using the second series resistor 308 in addition to the first termination resistor 301 and the second termination resistor 303, the impedance value Zo of the first transmission line 300 is more than the impedance value Zo ′ of the second transmission line 306. Can be substantially constant (Zo >> Zo '), the impedance over the entire transmission line can be made to be a substantially constant value Zo. Therefore, even in the case of Zo >> Zo ′, it is possible to suppress the reflection of signals and the occurrence of noise caused by the reflection.

  The impedance graph of FIG. 3 shows the relationship between the distance from the input end 302 and the impedance in the signal transmission direction. A solid line indicates the impedance of the signal receiving circuit 3 including the second series resistor 308. As indicated by the solid line, in the signal receiving circuit 3, even when the impedance value Zo of the first transmission line 300 is larger than the impedance value Zo ′ of the second transmission line 306 (Zo >> Zo ′), the impedance of the entire transmission line Has a constant value Zo.

  A dotted line shows an impedance graph when the second series resistor 308 is not used. When the second series resistor 308 is not inserted, the output-side impedance Rt3 = Rin3 = Zo ′ viewed from the first transmission line 300 is obtained. That is, the impedance decreases from the connection point between the first transmission line 300 and the second transmission line 306 on the output side. This is because the impedance Zo of the first transmission line 300 has a higher value than that of the second transmission line Zo ′.

(3-3) Effect In this embodiment, when the impedance Zo of the first transmission line 300 is higher than the impedance Zo ′ of the second transmission line 306 (Zo >> Zo ′), the first termination resistor 301 and the second termination In addition to the resistor 303, a second series resistor 308 is further used. Thereby, even if Zo >> Zo ′, the output-side impedance viewed from the first transmission line 300 can be kept at a constant value Zo.

<Fourth embodiment>
(4-1) Influence on Impedance by Inserting Surge Countermeasure Parts FIG. 4 illustrates the influence on the impedance by the signal receiving circuit 4 in which the surge countermeasure parts are inserted. In the signal receiving circuit 4 of FIG. 4, a first transmission line 400 and a termination resistor 401 are connected in parallel. The termination resistor 401 is connected to the semiconductor device 405 in series. A surge countermeasure component 408 is connected in parallel to the first transmission line 400 between the first transmission line 400 and the termination resistor 401. In the signal receiving circuit 4, the impedance value Zo of the first transmission line 400 and the resistance value Rtest of the termination resistor 401 are matched.

  Generally, surge suppression components have low impedance because surge suppression components have a capacitive component. Using this property, surge suppression components are used to protect semiconductor devices from high voltage and high frequency noise due to static electricity and the like. However, due to the capacitance component of the surge countermeasure component, the impedance of the surge countermeasure component portion is locally reduced as shown in the impedance graph of FIG. Therefore, in order to further prevent the reflection phenomenon when transmitting a signal, it is preferable to compensate for a decrease in impedance caused by a surge countermeasure component.

(4-2) Configuration FIG. 5 is a configuration diagram and an impedance graph of a signal receiving circuit according to the fourth embodiment of the present invention. When the impedance Zo ′ of the second transmission line 506 is higher than the impedance Zo of the first transmission line 500 (Zo> Zo ′), the signal receiving circuit 5 of the present embodiment has the first in parallel with the second transmission line 506. A surge countermeasure component 508 is connected. The first surge countermeasure component 508 is externally attached to the semiconductor device 505. Other configurations of the signal receiving circuit 5 are the same as those in the first embodiment. That is, the first transmission line 500 and the second transmission line 506 are connected in series. The receiver 504 built in the semiconductor device 505 is connected in series to the second transmission line 506. A first termination resistor 501 having a resistance value Rout4 is connected in parallel to the first transmission line 500 and is externally attached to the semiconductor device 505. A second termination resistor 503 having a resistance value Rin4 is built in the semiconductor device 505 and connected in parallel to the second transmission line 506. One end of each of the first termination resistor 501 and the second termination resistor 503 is connected to the power source Vtt.

  The potential of the power supply Vtt is not particularly limited and may be ground.

(4-3) Impedance matching Next, how the impedance is matched in the signal receiving circuit 5 of FIG. 5 will be described. The impedance of the transmission line in the signal receiving circuit 5 in FIG. 5 is matched in the same manner as the signal receiving circuit 1 in FIG. That is, in the signal receiving circuit 5, the resistance value Rt4 ′ of the combined resistance on the output side viewed from the first transmission line 500 and the input impedance Zo of the first transmission line 500 are matched. Here, the combined resistance value Rt4 ′ is a combined resistance value of the first termination resistor 501, the second termination resistor 503, and the second transmission line 506. That is, in the signal receiving circuit 5, the following two resistance values that affect the combined resistance value Rt4 ′ are adjusted so as to match the impedance of the entire transmission line.

(A) Resistance value Rout4 of the first termination resistor 501
(B) Resistance value Rin4 of the second termination resistor 503
Specifically, first, the resistance value Rin4 of the second termination resistor 503 is adjusted so as to be equal to the impedance value Zo ′ of the second transmission line 506. Thereby, the impedance of the second transmission line 506 can be regarded as an apparent constant value Zo ′.

  Next, the resistance value Rout4 of the first termination resistor 501 is adjusted to a value obtained based on the following equation (12). The following equation (12) indicates a condition that the combined resistance value Rt4 ′ on the output side viewed from the first transmission line 500 matches the input impedance Zo of the first transmission line 500.

The first termination resistor Rout4 is adjusted to a value obtained from an equation obtained by modifying the above equation (12).

  When the resistance value Rout4 of the first termination resistor 501 is adjusted in this way, the impedance in the transmission line can be set to a substantially constant value Zo. Furthermore, the local fall of the impedance by having inserted the 1st surge countermeasure component 508 into the 2nd transmission line 506 can be reduced.

  Here, in this embodiment, the first surge countermeasure component 508 is connected in parallel to the second transmission line 506 (Zo ′> Zo) having an impedance Zo ′ higher than the impedance Zo of the first transmission line 500. Yes. As already described in (4-1), since the surge countermeasure component has a capacitive component, the impedance of the surge countermeasure component falls locally. Therefore, the surge countermeasure component is connected in parallel to the second transmission line 506 having a high impedance. Then, the local impedance reduction due to the surge countermeasure component is raised by the impedance Zo ′ of the second transmission line 506. Therefore, the local impedance reduction of the surge countermeasure component is reduced.

  The impedance graph of FIG. 5 shows the relationship between the distance from the input end 502 and the impedance in the signal transmission direction. The solid line of the signal receiving circuit 5 in which the impedance of the transmission line is matched using the first termination resistor 501 and the second termination resistor 503 and the first surge countermeasure component 508 is connected in parallel to the second transmission line 506. Indicates impedance. The dotted line is an impedance graph when the two resistances of the first termination resistor 501 and the second termination resistor 503 are not used and a surge countermeasure component is inserted. As shown by the solid line in the impedance graph of FIG. 5, when the resistance value Rout4 of the first termination resistor 501 and the resistance value Rin4 of the second termination resistor 503 are adjusted, the impedance in the transmission line becomes substantially constant. Furthermore, the local drop in impedance when the surge countermeasure component is inserted is reduced.

(4-4) Effect In this embodiment, the first termination resistor 501 and the second termination resistor 503 are connected in parallel to the first transmission line 500 and the second transmission line 506, respectively. When the impedance Zo ′ of the second transmission line 506 is higher than the impedance Zo of the first transmission line 500 (Zo ′> Zo), the first surge countermeasure component 508 is connected to the second transmission line 506 in parallel. Thereby, even if it is a case where a surge countermeasure component is inserted, the impedance of a transmission line can be kept constant and the local fall of the impedance in surge countermeasure component insertion can be reduced. Therefore, a signal from which high-frequency noise has been removed by a surge countermeasure component can be transmitted with reduced waveform distortion.

<Fifth Embodiment>
(5-1) Configuration FIG. 6 is a configuration diagram and an impedance graph of a signal receiving circuit according to the fifth embodiment of the present invention. The signal receiving circuit 6 of this embodiment is suitable when the impedance value Zo of the first transmission line 600 is higher than the impedance value Zo ′ of the second transmission line 606 and when a surge countermeasure component is inserted (Zo >> Zo '). In the signal receiving circuit 6 of the present embodiment, a first surge countermeasure component 608 is connected in parallel to the second transmission line 606. The first surge countermeasure component 608 is externally attached to the semiconductor device 605. Other configurations of the signal receiving circuit 6 are the same as those of the second embodiment. That is, the first transmission line 600 and the second transmission line 606 are connected in series. A receiver 604 built in the semiconductor device 605 is connected to the second transmission line 606 in series. A first termination resistor 601 having a resistance value Rout5 is connected in parallel to the first transmission line 600 and is externally attached to the semiconductor device 605. A second termination resistor 603 having a resistance value Rin5 is built in the semiconductor device 605 and connected in parallel to the second transmission line 606. One end of each of the first termination resistor 601 and the second termination resistor 603 is connected to the power supply Vtt. The first series resistor 610 is on the second transmission line 606 and is externally connected in series to the semiconductor device 605.

  The potential of the power supply Vtt is not particularly limited and may be ground.

(5-2) Impedance matching Next, how the impedance is matched in the signal receiving circuit 6 of FIG. 6 will be described. First, the problem in the case where the first series resistor 610 is not provided will be clarified, and the case where it exists next will be described.

(5-2-1) When there is no first series resistance First, let us consider a case where there is no first series resistance 610 in the signal receiving circuit 6 of FIG. This corresponds to the case where the impedance Zo of the first transmission line 500 is higher than the impedance Zo ′ of the second transmission line 506 (Zo >> Zo ′) in the signal receiving circuit 5 of FIG. In this case, since Rout4 is increased in the above equation (12), the combined resistance value Rt4 ′ can be approximated by the following equation (13). Here, the resistance value Rin4 of the second termination resistor 503 is adjusted to the impedance value Zo ′ of the second transmission line 506 (Rin4 = Zo ′). That is, the value of the output-side impedance Rt4 ′ viewed from the first transmission line 500 is “Rin4”, and the impedance cannot be set to a constant value Zo over the entire transmission line. Therefore, in the case of Zo >> Zo ′, it can be seen that the impedance may not be matched only by the first termination resistor 601 and the second termination resistor 603.

(5-2-2) When there is a first series resistance On the other hand, in the signal receiving circuit 6, the resistance value Rt4 ″ of the combined resistance on the output side viewed from the first transmission line 600 and the input impedance of the first transmission line 600. Zo is matched (Rt4 "≒ Zo). Here, the combined resistance value Rt4 "is a combined resistance value of the first terminating resistor 601, the second terminating resistor 603, the second transmission line 606, and the first series resistor 610. That is, in the signal receiving circuit 6, the combined resistance value Rt4" is a combined resistance value. The following three resistance values that affect the resistance value Rt4 "are adjusted to match the impedance of the entire transmission line.

(A) Resistance value Rout5 of the first termination resistor 601
(B) Resistance value Rin5 of the second termination resistor 603
(C) Resistance value Rs3 of the first series resistor 610
Specifically, first, the resistance value Rin5 of the second termination resistor 603 is adjusted to be equal to the impedance value Zo ′ of the second transmission line 606. Thereby, the impedance of the second transmission line 606 can be regarded as an apparently constant value Zo ′.

  The resistance value Rs3 of the first series resistor 610 is adjusted based on the following equation (14). The following equation (14) indicates a condition that the combined resistance value Rt4 ″ on the output side viewed from the first transmission line 600 matches the input impedance Zo of the first transmission line 600.

  Now consider the case of Zo >> Zo '. Since Rout5 is large in the above equation (14), the combined resistance value Rt4 "and the impedance matching condition are represented by the following equation (15). The resistance value Rs3 of the first series resistor 610 is represented by the following equation (15 In addition, the resistance value Rout5 of the first termination resistor 601 is adjusted to Rout5 = Zo in consideration of the matching with the first transmission line 600.

  In this way, the resistance value Rs3 of the first series resistor 610, the resistance value Rout5 of the first termination resistor 601 and the resistance value Rin5 of the second termination resistor are adjusted. Thereby, even when the impedance Zo of the first transmission line 600 is higher than the impedance Zo ′ of the second transmission line (Zo >> Zo ′), the impedance of the transmission line can be set to a substantially constant value Zo. Furthermore, the local fall of the impedance by connecting the 1st surge countermeasure component 608 in parallel with the 2nd transmission line 606 can be reduced.

  Here, in this embodiment, the first surge countermeasure component 608 is connected in parallel to the first series resistor 610 and the second transmission line 606. Since the impedance Zo ′ of the second transmission line 606 is equal to the second termination resistance value Rin4, the combined resistance value of the first series resistance 610 and the second transmission line 606 is given by the equation (15). It is almost equal to the impedance Zo of one transmission line 600. In the present embodiment, the impedance Zo of the first transmission line is higher than the impedance Zo ′ of the second transmission line 606 (Zo> Zo ′). Considering the above, the first surge countermeasure component 608 is inserted in parallel at a location having a high impedance equal to the high impedance Zo of the first transmission line 600. As already described in (4-1), since the surge countermeasure component has a capacitive component, the impedance of the surge countermeasure component falls locally. Therefore, the surge countermeasure component is connected in parallel near the first series resistor 610 and the second transmission line 606, which have high impedance when combined. Then, the local impedance drop due to the surge countermeasure component is raised by the combined impedance (Rs3 + Zo ′ = Zo) with the first series resistor 610 and the second transmission line 606. Therefore, the reduction of surge countermeasure parts is reduced.

  The impedance graph of FIG. 6 shows the relationship between the distance from the input end 602 and the impedance in the signal transmission direction. The solid line indicates that the impedance of the transmission line is matched using the first termination resistor 601, the second termination resistor 603, and the first series resistor 610 when Zo >> Zo ′, and the second line is parallel to the second transmission line 606. 1 shows the impedance of the signal receiving circuit 6 to which the surge countermeasure component 608 is connected. As shown by the solid line, in the signal receiving circuit 6, even if the impedance difference between the first transmission line 600 and the second transmission line 602 is large (Zo >> Zo ′), the impedance of the entire transmission line is a substantially constant value. have. Furthermore, the local drop of the impedance at the time of surge countermeasure component insertion is reduced.

  A dotted line is an impedance graph when Zo >> Zo ′ and when the first series resistor 610 is not used. When the first series resistor 610 is not inserted, the impedance on the output side viewed from the first transmission line 600 is lowered. In particular, a local decrease is observed in the surge countermeasure component insertion part.

(5-3) Effect In this embodiment, the impedance value Zo of the first transmission line 600 is higher than the impedance value Zo ′ of the second transmission line 606 (Zo >> Zo ′), and the first surge This is a case where the countermeasure component is connected to the second transmission line 506 in parallel. In the present embodiment, the first termination resistor 601 and the second termination resistor 603 are connected in parallel to the first transmission line 600 and the second transmission line 606, respectively, and the first series resistor 610 is disposed on the second transmission line 610 on the semiconductor device. 605 is externally connected in series. As a result, even when Zo >> Zo 'and surge suppression components are inserted, the impedance of the transmission line can be kept substantially constant, and local reduction in impedance when surge suppression components are inserted can be reduced. it can. Therefore, a signal from which high-frequency noise has been removed by a surge countermeasure component can be transmitted with reduced waveform distortion.

<Sixth Embodiment>
(6-1) Configuration FIG. 7 is a configuration diagram and an impedance graph of a signal receiving circuit according to the sixth embodiment of the present invention. Similarly to the fifth embodiment, the signal receiving circuit 7 of the present embodiment has a case where the impedance value Zo of the first transmission line 700 is higher than the impedance Zo ′ of the second transmission line 706 (Zo >> Zo ′), and This is suitable when inserting surge countermeasure components.

  In the signal receiving circuit 7 of the present embodiment, a second surge countermeasure component 708 is connected in parallel to the first transmission line 700. The second surge countermeasure component 708 is externally attached to the semiconductor device 705. Other configurations of the signal receiving circuit 7 are the same as those of the third embodiment. That is, the first transmission line 700 and the second transmission line 706 are connected in series. A receiver 704 built in the semiconductor device 705 is connected in series to the second transmission line 706. A first termination resistor 701 having a resistance value Rout6 is connected in parallel to the first transmission line 700 and is externally attached to the semiconductor device 705. A second termination resistor 703 having a resistance value Rin6 is built in the semiconductor device 705 and connected in parallel to the second transmission line 706. One end of each of the first termination resistor 701 and the second termination resistor 703 is connected to the power source Vtt. The second series resistor 710 is on the first transmission line 700 and is externally connected in series to the second transmission line 706. The potential of the power supply Vtt is not particularly limited and may be ground.

(6-2) Impedance Matching Next, how the impedance is matched in the signal receiving circuit 7 of FIG. 7 will be described. First, the case where the second series resistor 710 is not provided will be clarified, and the case where it is next will be described.

(6-2-1) When there is no second series resistance First, let us consider a case where the signal receiving circuit 7 of FIG. This corresponds to the same condition (Zo >> Zo ′) as in the fifth embodiment. That is, in the signal receiving circuit 5 of FIG. 5, this corresponds to the case where the impedance Zo of the first transmission line 500 is higher than the impedance Zo ′ of the second transmission line 506 (Zo >> Zo ′). In this case, since Rout4 is increased in the above equation (12), the combined resistance value Rt4 ′ can be approximated by the following equation (16). Here, the resistance value Rin4 of the second termination resistor 503 is adjusted to the impedance value Zo ′ of the second transmission line 506 (Rin4 = Zo ′). That is, the value of the output-side impedance Rt4 ′ viewed from the first transmission line 500 is “Rin4”, and the impedance cannot be set to a constant value Zo over the entire transmission line. Therefore, it can be seen that when Zo >> Zo ′, the impedance cannot be completely matched only by the first termination resistor 701 and the second termination resistor 703.

(6-2-2) When there is a second series resistance On the other hand, in the signal receiving circuit 7, the resistance value Rt6 of the combined resistance on the output side viewed from the first transmission line 700 and the input impedance Zo of the first transmission line 700 Are matched (Rt6 ≒ Zo). Here, the combined resistance value Rt6 is a combined resistance value of the first termination resistor 701, the second termination resistor 703, the second transmission line 706, and the second series resistor 710. That is, in the signal receiving circuit 7, the following three resistance values that affect the combined resistance value Rt6 are adjusted to match the impedance of the entire transmission line.

(A) Resistance value Rout6 of the first termination resistor 701
(B) Resistance value Rin6 of the second termination resistor 703
(C) Resistance value Rs4 of the second series resistor 710
Specifically, first, the resistance value Rin6 of the second termination resistor 703 is adjusted to be equal to the impedance value Zo ′ of the second transmission line 706. Thereby, the impedance of the second transmission line 706 can be apparently regarded as a constant value Zo ′.

  The resistance value Rs4 of the first series resistor 710 is adjusted based on the following equation (17). The following equation (17) represents a condition in which the combined resistance value Rt6 on the output side viewed from the first transmission line 700 matches the input impedance Zo of the first transmission line 700.

  Now consider Zo >> Zo '. From the circuit diagram of FIG. 7, the output-side circuit viewed from the first transmission line 700 and the second series resistor 710 is the same as the output-side circuit viewed from the transmission line 500 of FIG. That is, the first term of the above equation (17), that is, the first termination resistor 701 and the second termination resistor 703 is expressed by the approximate equation (16) described above using the condition of Zo >> Zo ′. (The following formula (18)). Then, the above equation (17) can be expressed as the following equation (19) using the following equation (18). The resistance value Rs4 of the second series resistor 708 is adjusted to a value obtained from an equation obtained by modifying the following equation (19). Further, the resistance value Rout6 of the first termination resistor 701 is adjusted to Rout6 = Zo in consideration of matching with the first transmission line 700.

  In this way, the resistance value Rs4 of the second series resistor 710, the resistance value Rout6 of the first termination resistor 701, and the resistance value Rin6 of the second termination resistor 703 are adjusted. Thereby, even when the impedance Zo of the first transmission line 700 is higher than the impedance Zo ′ of the second transmission line 706 (Zo >> Zo ′), the impedance of the transmission line can be set to a substantially constant value Zo. . Furthermore, local reduction in impedance due to the second surge countermeasure component being connected in parallel to the first transmission line 700 can be reduced.

  Here, in the present embodiment, the second surge countermeasure component 708 is connected in parallel to the first transmission line 700 (Zo >> Zo ′) having an impedance Zo higher than the impedance Zo ′ of the second transmission line 706. ing. As already described in (4-1), since the surge countermeasure component has a capacitive component, the impedance of the surge countermeasure component falls locally. Therefore, the surge countermeasure component is connected in parallel to the first transmission line 700 having a high impedance. Then, the local impedance drop due to the surge countermeasure component is raised by the impedance Zo of the first transmission line 700. Therefore, the local impedance reduction of the surge countermeasure component is reduced.

  The impedance graph of FIG. 7 shows the relationship between the distance from the input end 702 and the impedance in the signal transmission direction. The solid line indicates that when Zo >> Zo ′, the impedance of the transmission line is approximately matched using the first termination resistor 701, the second termination resistor 703, and the second series resistor 710, and is parallel to the first transmission line 700. The impedance graph of the signal receiving circuit 7 to which the 2nd surge countermeasure component 708 is connected is shown. As indicated by the solid line, in the signal receiving circuit 7, even when the impedance Zo of the first transmission line 700 is larger than the impedance Zo ′ of the second transmission line 706 (Zo >> Zo ′), the impedance of the entire transmission line is almost equal. It becomes a constant value. Furthermore, the local drop in impedance upon insertion of surge countermeasure components is reduced.

  The dotted line is an impedance graph when Zo >> Zo ′ and when the second series resistor 710 is not used. When the second series resistor 710 is not inserted, the impedance on the output side viewed from the first transmission line 700 is lowered. In particular, a local decrease is observed in the surge countermeasure component insertion part.

(6-3) Effect In the present embodiment, the impedance value Zo of the first transmission line 700 is higher than the impedance Zo ′ of the second transmission line 706 (Zo >> Zo ′), and the second surge countermeasure This is a case where the component 708 is connected to the first transmission line 706 in parallel. In the present embodiment, the first termination resistor 701 and the second termination resistor 703 are connected in parallel to the first transmission line 700 and the second transmission line 706, respectively, and the second series resistor 710 is connected in series to the first transmission line 700. doing. As a result, even when Zo >> Zo 'and surge suppression components are inserted, the impedance of the transmission line can be kept substantially constant, and local reduction in impedance when surge suppression components are inserted can be reduced. it can. Therefore, a signal from which high-frequency noise has been removed by a surge countermeasure component can be transmitted with reduced waveform distortion.

  In the fourth to sixth embodiments of the present invention, the arrangement of the surge countermeasure components is not limited to that shown in FIGS. 5 to 7, and the arrangement is made anywhere as long as it is near an element having a high impedance in the transmission line. May be. Moreover, you may incorporate in a semiconductor device.

<Seventh embodiment>
(7-1) Configuration FIG. 8 is a configuration diagram and an impedance graph of a signal receiving circuit according to the seventh embodiment of the present invention. The signal receiving circuit 8 of the present embodiment is effective when a surge countermeasure component capable of removing high voltage / high frequency noise is connected to the surge countermeasure component used in the fourth to sixth embodiments. is there.

  In the signal receiving circuit 8 of FIG. 8, a coil 811 is connected in series to the first termination resistor 801. The other configuration of the signal receiving circuit 8 is the same as that of the fourth embodiment. That is, the first transmission line 800 and the second transmission line 806 are connected in series. A receiver 804 built in the semiconductor device 805 is connected to the second transmission line 806 in series. A first termination resistor 801 having a resistance value Rout7 is connected in parallel to the first transmission line 800 and is externally attached to the semiconductor device 805. A second termination resistor 803 having a resistance value Rin7 is built in the semiconductor device 805 and connected in parallel to the second transmission line 806. One end of each of the first termination resistor 801 and the second termination resistor 803 is connected to the power source Vtt. The surge countermeasure component is connected to the second transmission line 806 in parallel with the second transmission line 806 and is externally attached to the semiconductor device 805. The potential of the power supply Vtt is not particularly limited and may be ground.

(7-2) Impedance matching Next, how the impedance is matched in the signal receiving circuit 8 of FIG. 8 will be described. In the signal receiving circuit 8, the resistance value Rt5 of the combined resistance on the output side viewed from the first transmission line 800 and the input impedance Zo of the first transmission line 800 are matched. Here, the combined resistance value Rt5 is a combined resistance value of the first termination resistor 801, the second termination resistor 803, and the second transmission line 806. That is, in the signal receiving circuit 8, the following two resistance values that affect the combined resistance value Rt5 are adjusted so as to match the impedance of the transmission line.

(A) Resistance value Rout7 of the first termination resistor 801
(B) Resistance value Rin7 of the second termination resistor 803

Specifically, first, the resistance value Rin7 of the second termination resistor 803 is adjusted to be equal to the impedance value Zo ′ of the second transmission line 806. As a result, the impedance of the second transmission line 806 can be regarded as an apparently constant value Zo ′.

  The resistance value Rout7 of the first termination resistor 801 is adjusted to a value obtained based on the following equation (20). The following equation (20) represents a condition in which the combined resistance value Rt5 on the output side viewed from the first transmission line 800 matches the input impedance Zo of the first transmission line 800.

By transforming the above equation (20), an equation representing the resistance value Rout7 of the first termination resistor 801 is obtained.

  Here, the impedance between the surge countermeasure component and the coil will be described. In general, surge suppression components have a capacitive component, so the impedance is low. In the surge countermeasure component, the smaller the capacitance component, the smaller the rate of impedance reduction. When using a surge countermeasure component with a small capacitance component, as in the fourth to sixth embodiments, the transmission line matched by the first termination resistor and the second termination resistor is located near the transmission line having a high impedance. By inserting the surge countermeasure component, the impedance of the surge countermeasure component can be reduced. In addition, the magnitude of the capacitance component of the surge countermeasure component depends on the magnitude of the voltage and frequency of noise to be removed. A surge countermeasure component having a large capacitance component can remove higher voltage and high frequency noise than a surge countermeasure component having a small capacitance component. However, if a surge countermeasure component having a large capacitance component is used to remove even higher high-voltage / high-frequency noise, the rate at which the impedance of the surge countermeasure component decreases also increases. In this case, the impedance of the surge countermeasure component can be reduced only by inserting the surge countermeasure component in the vicinity of the transmission line having a high impedance among the transmission lines matched using the first termination resistor or the second termination resistor. It becomes difficult.

  On the other hand, the coil generally has high impedance characteristics. In particular, the coil has a higher impedance value as the signal becomes higher in frequency. Using these properties, the coil and the surge countermeasure component are connected in parallel to the circuit. Then, the high impedance of the coil and the low impedance of the surge countermeasure component are offset. Therefore, even when the surge countermeasure component has a large capacitance component and the impedance is significantly lowered, a coil having an impedance that can cancel out the impedance of the surge countermeasure component may be inserted near the surge countermeasure component. Thereby, the impedance of surge countermeasure components can be matched.

  Therefore, when the first termination resistor 801 and the second termination resistor 803 are adjusted as described above, the impedance in the transmission line can be set to a substantially constant value Zo. Furthermore, the impedance in inserting the surge countermeasure component can be matched by inserting the coil 811.

  The impedance graph of FIG. 8 shows the relationship between the distance from the input end 802 and the impedance in the signal transmission direction. The solid line indicates the impedance of the signal receiving circuit 8 in which the impedances of the transmission line and the surge countermeasure component are approximately matched using the first termination resistor 801, the second termination resistor 803, and the coil 811. A dotted line shows the impedance characteristics of each of the coil and the surge countermeasure component. As shown in the impedance graph of FIG. 8, when the resistance value Rout7 of the first termination resistor 81 and the resistance value Rin7 of the second termination resistor 803 are adjusted and the coil is inserted near the surge countermeasure component, the transmission line The overall impedance can be kept almost constant.

(7-3) Effect In the present embodiment, when the surge countermeasure component 808 that lowers the impedance further than the surge countermeasure component used in the fourth to sixth embodiments is connected in parallel to the second transmission line, the coil 811 1 Connected in series to a terminating resistor 801. Then, the impedance of the surge countermeasure component 808 is canceled by the impedance of the coil 811. Furthermore, since the resistance values Rout and Rin of the first and second termination resistors 801 and 803 are adjusted, impedance matching of the entire transmission line can be performed and signal reflection in the entire transmission line can be prevented.

  In addition, in 7th Embodiment, although the coil was added to FIG. 4 of 4th Embodiment, you may insert a coil similarly in FIG. 6 of 5th Embodiment, and FIG. 7 of 6th Embodiment.

<Eighth Embodiment>
(8-1) Configuration The present invention can also be applied to a differential signal receiving circuit.

  FIG. 9 is a block diagram and an impedance graph of a signal receiving circuit according to the eighth embodiment of the present invention. The signal receiving circuit of FIG. 9 includes first to fourth transmission lines 900 a, 900 b, 906 a, 906 b, first to fourth termination resistors 920, 910, 921, 911, and a semiconductor device 905. The first transmission line 900a and the third transmission line 900b are wirings on a printed board (not shown) and have signal input ends 907 and 908, respectively. The second transmission line 906a and the fourth transmission line 906b include input / output lead wires and electrode wirings of the semiconductor device 905. The first transmission line 900a and the second transmission line 906a are connected in series, and the third transmission line 900b and the fourth transmission line 906b are connected in series. The semiconductor device 905 includes a differential signal receiving circuit 904 for receiving two signals having opposite phases to each other. The second transmission line 906a is connected to one input terminal of the differential signal receiving circuit 904, and the fourth transmission line 906b is connected to the other input terminal. The first termination resistor 920 having the Rout18 value is connected in parallel to the first transmission line 900a and is externally attached to the semiconductor device 905. The second termination resistor 910 having a Rin18 value is connected in parallel to the second transmission line 906a and is built in the semiconductor device 905. The third termination resistor 921 having the Rout28 value is connected in parallel to the third transmission line 900b and is externally attached to the semiconductor device 905. A fourth termination resistor 911 having a Rin28 value is connected in parallel to the fourth transmission line 906 b and is built in the semiconductor device 905. One end of each of the first to fourth termination resistors 920, 910, 921, and 911 is connected to the power supply Vtt.

  Since the distance between the first transmission line 900a and the third transmission line 900b is very short, the combined impedance of the first transmission line 900a and the third transmission line 900b can be regarded as Zo. Further, since the distance between the second transmission line 906a and the fourth transmission line 906b is very short, the combined impedance of the second transmission line 906a and the fourth transmission line 906b can be regarded as Zo ′.

  The potential of the power supply Vtt is not particularly limited and may be ground.

(8-2) Impedance Matching Next, how the impedance is matched in the signal receiving circuit 9 of FIG. 9 will be described.

  In the signal receiving circuit 9, the resistance value Rt8 of the combined resistance on the output side viewed from the first and third transmission lines 900a and 900b and the combined input impedance Zo of the first and third transmission lines 900a and 900b are matched. (Rt8 ≒ Zo). Here, the combined resistance value Rt8 is a combined resistance value of the first termination resistor 920, the second termination resistor 910, the third termination resistor 921, the fourth termination resistor 911, and the second and fourth transmission lines 906a and 906b. That is, in the signal receiving circuit 9, the following four resistance values that affect the combined resistance value Rt8 are adjusted to match the impedance of the entire transmission line.

(A) Resistance value Rout18 of the first termination resistor 920
(B) Resistance value Rin18 of the second termination resistor 910
(C) Resistance value Rout28 of the third termination resistor 921
(D) Resistance value Rin28 of the fourth termination resistor 911
Specifically, first, the resistance values Rin18 and Rin28 of the second termination resistor 910 and the fourth termination resistor 911 are adjusted so as to be equal to the combined impedance value Zo ′ of the second and fourth transmission lines 906a and 906b. (Rin18 + Rin28 ≒ Zo '). Thereby, the combined impedance of the second and fourth transmission lines 906a and 906b can be regarded as an apparently constant value Zo ′.

  The resistance value Rout18 of the first termination resistor 920 and the resistance value Rout28 of the third termination resistor 921 are adjusted to values obtained based on the following equations (21) and (22). The following equations (21) and (22) indicate that the combined resistance value Rt8 on the output side seen from the first and third transmission lines 900a and 900b matches the combined input impedance Zo of the first and third transmission lines 900a and 900b. The conditions to do are shown. Here, since the signal receiving circuit 9 includes the differential signal receiving circuit 904, there are two types of impedance, that is, differential impedance and common mode impedance. In the combined input impedance Zo of the first and third transmission lines 900a and 900b, the differential impedance is Zd8 and the common mode impedance is Zcom8. Of the combined resistance value Rt8, the differential resistance value is Rt8d, and the common mode resistance value is Rt8com. The following expression (21) is a conditional expression for matching the differential resistance value Rt8d with the differential impedance Zd8, and the following expression (22) is a condition for matching the common mode resistance value Rt8com with the common mode impedance Zcom8. It is a formula.

  When the resistance value Rout18 of the first termination resistor 920 and the resistance value Rout28 of the third termination resistor 921 are adjusted so as to satisfy the above equations (21) and (22), the differential impedance and common over the entire transmission line are adjusted. The mode impedance can be set to substantially constant values Zd8 and Zcom8. Therefore, it is possible to suppress signal reflection and noise caused by the reflection.

  The impedance graph of FIG. 9 shows the relationship between the distance from the input ends 907 and 908 and the impedance in the signal transmission direction. The solid line indicates the impedance of the signal receiving circuit 9 including the first, second, third, and fourth termination resistors 920, 910, 921, 911. The dotted lines indicate the differential and common mode impedance when the first termination resistor 920 and the third termination resistor 921 are not used. As shown by the solid line, even when a differential signal receiving circuit is used, the differential and common mode impedance of the entire transmission line have constant values Zd8 and Zcom8.

(8-3) Effect In the present embodiment, the signal receiving circuit including the differential signal receiving circuit has a simple configuration using the first, second, third, and fourth termination resistors 920, 910, 921, 911. The combined differential and common mode impedances Zd8 and Zcom8 of the first and third transmission lines 900a and 900b and the output-side combined resistance values Rt8d and Rtcom8 viewed from the first and third transmission lines 900a and 900b are adjusted. As a result, the differential and common mode impedance of the entire transmission line is approximately constant, so that even in the transmission of two signals, each reflection can be prevented and a stable signal with high quality can be obtained without distorting the signal waveform. Can be transmitted.

(8-4) Another Example of Eighth Embodiment FIG. 10 shows a signal receiving circuit of another example of the eighth embodiment and its impedance graph. The signal receiving circuit 10 includes a node 1003 on the first transmission line 1000a and a node 1009 on the third transmission line 1000b. The node 1003 is a connection point between the first transmission line 1000a and the first termination resistor 1020. The node 1009 is a connection point between the third transmission line 1000b and the third termination resistor 1021. A resistor 1022 is connected between the node 1003 and the node 1009. Other configurations of the signal receiving circuit 10 are the same as those in FIG. The combined resistance values Rt8d ′ and Rt8com ′ on the output side viewed from the first and third transmission lines 1000a and 1000b, and the combined differential and common mode impedance Zd8 ′ of the first and third transmission lines 1000a and 1000b, Each resistance value is adjusted so as to match Zcom8 ′. Here, the combined resistance values Rt8d ′ and Rt8com ′ are a combined differential and common mode combination of the first to fourth termination resistors 1020, 1010, 1021, 1011, the resistor 1022, and the second and fourth transmission lines 1006a and 1006b. Resistance. The adjusted resistance values are the resistance values Rout18 ′, Rin18 ′, Rout28 ′, Rin28 ′ of the first to fourth termination resistors 1020, 1010, 1021, 1011 and the resistance value of the resistor 1022, respectively. Rout38. That is, the resistance values Rin18 ′ and Rin28 ′ of the second termination resistor 1010 and the fourth termination resistor 1011 are adjusted to be equal to the combined impedance value Zo ′ of the second and fourth transmission lines 1006a and 1006b (Rin18 ′). + Rin28 '≒ Zo'). The resistance values Rout18 ′ and Rout28 ′ of the first termination resistor 1020 and the third termination resistor 1021 and the resistance value Rout38 ′ of the resistor 1022 are adjusted according to the equations (23) and (24).

  The impedance graph of FIG. 10 shows the relationship between the distance from the input terminals 1007 and 1008 and the impedance in the signal transmission direction. A solid line indicates the impedance of the signal receiving circuit 10 including the first, second, third, and fourth termination resistors 1020, 1010, 1021, 1011, and the resistor 1022. The dotted lines indicate the differential and common mode impedance when the first termination resistor 1020, the third termination resistor 1021 and the resistor 1022 are not used. As indicated by the solid line, the differential and common mode impedances of the entire transmission line have constant values Zd8 ′ and Zcom8 ′ even when the differential signal receiving circuit is supported.

  Thus, a resistor may be newly added between the node 1003 on the first transmission line and the node 1009 on the third transmission line. A plurality of resistors may be added. Thereby, since the freedom degree of adjustment of the differential impedance and common impedance of the whole transmission line goes up, it becomes easier to match the whole transmission line.

<Ninth Embodiment>
(9-1) Configuration FIG. 11 is a configuration diagram and impedance graph of a signal receiving circuit according to the ninth embodiment of the present invention. The signal receiving circuit 11 in FIG. 11 has a configuration further including a common mode filter 1130 in the signal receiving circuit 9 in FIG. 9. Generally, a common mode filter is used to remove high-voltage / high-frequency noise such as static electricity and prevent the destruction of a semiconductor device due to high-voltage / high-frequency noise such as static electricity. However, the common mode filter has very high impedance characteristics. Therefore, in the common mode impedance, the impedance becomes very high at the location where the common mode filter is inserted.

  In the signal receiving circuit 11, a common mode filter 1130 is connected in series between the first and third transmission lines 1100a and 1100b and the second and fourth transmission lines 1106a and 1106b. The other configuration of the signal receiving circuit 11 is the same as that of the eighth embodiment according to FIG. That is, the semiconductor device 1105 includes a differential signal receiving circuit 1104 for receiving two signals having opposite phases. A second transmission line 1106a is connected to one input terminal of the differential signal receiving circuit 1104, and a fourth transmission line 1106b is connected to the other input terminal. The first transmission line 1100a and the second transmission line 1106a are connected in series with each other, and the third transmission line 1100b and the fourth transmission line 1106b are connected in series with each other. A first termination resistor 1120 having an Rout19 value is connected in parallel to the first transmission line 1100 a and is externally attached to the semiconductor device 1105. The second termination resistor 1110 having the Rin19 value is connected in parallel to the second transmission line 1106 a and is built in the semiconductor device 1105. The third termination resistor 1121 is connected in parallel to the third transmission line 1100 b and is externally attached to the semiconductor device 1105. A fourth termination resistor 1111 having a Rin29 value is connected in parallel to the fourth transmission line 1106 b and is built in the semiconductor device 1105. One end of each of the first to fourth termination resistors 1120, 1110, 1121, and 1111 is connected to the power supply Vtt. The potential of the power supply Vtt is not particularly limited and may be ground.

  Since the distance between the first transmission line 1100a and the third transmission line 1100b is very short, the combined impedance of the first transmission line 1100a and the third transmission line 1100b can be regarded as Zo. Further, since the distance between the second transmission line 1106a and the fourth transmission line 1106b is very close, the combined impedance of the second transmission line 1106a and the fourth transmission line 1106b can be regarded as Zo ′.

(9-2) Impedance Matching Next, how the impedance is matched in the signal receiving circuit 11 of FIG. 11 will be described. In the signal receiving circuit 11, the combined resistance value Rt9 on the output side viewed from the first and third transmission lines 1100a and 1100b is matched with the combined input impedance Zo of the first and third transmission lines 1100a and 1100b. (Rt9 ≒ Zo). Here, the combined resistance value Rt9 is a combined resistance value of the first to fourth termination resistors 1120, 1110, 1121, 1111, the second and fourth transmission lines 1106a, 1106b, and the common mode filter 1130. In other words, in the signal receiving circuit 11, the following four resistance values that affect the combined resistance value Rt9 are adjusted to match the impedance of the entire transmission line.

(A) Resistance value Rout19 of the first termination resistor 1120
(B) Resistance value Rin19 of the second termination resistor 1110
(C) Resistance value Rout29 of the third termination resistor 1121
(D) Resistance value Rin29 of the fourth termination resistor 1111
Specifically, first, the resistance values Rin19 and Rin29 of the second termination resistor 1110 and the fourth termination resistor 1111 are adjusted to be equal to the combined impedance value Zo ′ of the second and fourth transmission lines 1106a and 1106b. (Rin19 + Rin29 ≒ Zo '). Thereby, the impedance of the second and fourth transmission lines 1106a and 1106b can be regarded as an apparently constant value Zo ′.

  The resistance value Rout19 of the first termination resistor 1120 and the resistance value Rout29 of the third termination resistor 1121 are adjusted to values obtained based on the following equations (25) and (26). The following equations (25) and (26) indicate that the combined resistance value Rt9 on the output side viewed from the first and third transmission lines 1100a and 1100b matches the combined input impedance Zo of the first and third transmission lines 1100a and 1100b. The conditions to do are shown. Here, since the signal receiving circuit 11 includes the differential signal receiving circuit 1104, there are two types of impedance, that is, differential impedance and common mode impedance. In the combined input impedance Zo of the first and third transmission lines, the differential impedance is Zd9 and the common mode impedance is Zcom9. Of the combined resistance value Rt9, the differential resistance value is Rt9d, and the common mode resistance value is Rt9com. The following expression (25) is a conditional expression for matching the differential resistance value Rt9d with the differential impedance Zd9. The following expression (26) is a conditional expression for matching the common mode resistance value Rt9com with the common mode impedance Zcom9.

Here, R _CMF is the impedance of the common mode filter.

  When the resistance value Rout19 of the first termination resistor 1120 and the resistance value Rout29 of the third termination resistor 1121 are adjusted so as to satisfy the above equations (25) and (26), the differential impedance and common over the entire transmission line The mode impedance can be set to substantially constant values Zd9 and Zcom9. Therefore, even when a common mode filter is inserted, signal reflection and noise caused by the reflection can be suppressed.

  The impedance graph of FIG. 11 shows the relationship between the distance from the input terminals 1107 and 1108 and the impedance in the signal transmission direction. A solid line indicates the differential and common mode impedance of the signal receiving circuit 11 including the common mode filter 1130 and including the first, second, third, and fourth termination resistors 1120, 1110, 1121, and 1111. As indicated by the solid line, in the signal receiving circuit 11, even when the common mode filter 1130 is inserted, an extreme increase in impedance of the transmission line due to the insertion of the common mode filter is reduced.

  Dotted lines indicate the differential and common mode impedance when the first termination resistor 1120 and the third termination resistor 1121 are not used, although the common mode filter 1130 is included. When the first termination resistor 1120 and the third termination resistor 1121 are not used, the impedance is extremely increased at the common mode filter insertion portion. This is because the common mode filter has a very high impedance.

(9-3) Effect In the present embodiment, when a common mode filter is inserted, the first, second, third, and fourth termination resistors 1120, 1110, 1121, and 1111 are used. Thereby, even when the common mode filter is inserted, the differential impedance of the entire transmission line can be made constant, and the impedance of the entire transmission line and the common mode filter can be made almost constant. Therefore, a signal from which high voltage / high frequency noise such as static electricity is removed by the common mode filter can be transmitted in a high quality state while preventing reflection.

<Other embodiments>
FIG. 12 shows an example in which the signal receiving circuit 9 shown in Embodiment 8 is applied to a display device. A signal receiving circuit in a TMDS (Transition Minimised Differential Signaling) transmission system used in a high-speed differential serial interface such as DVI or HDMI is suitable for a video / audio reproduction / output device. FIG. 12 has a four-channel differential line configuration of R, G, B, and CLK. Description of the specific configuration and operation of FIG. 12 is omitted.

  As described above, when the present invention is installed in an apparatus for transmitting audio and video such as a display apparatus, it is possible to transmit image quality and audio signals in a high quality state. Therefore, it is possible to provide a video / audio receiver having excellent image quality and sound quality.

  The signal receiving circuit according to the present invention can be mounted on a DVD recorder, a television, or a video recorder.

The signal receiving circuit diagram and impedance graph which concern on 1st Embodiment. The signal receiving circuit diagram and impedance graph which concern on 2nd Embodiment. The signal receiving circuit diagram and impedance graph which concern on 3rd Embodiment. Drawing showing impedance characteristics by surge countermeasure parts. The signal receiving circuit diagram and impedance graph which concern on 4th Embodiment. The signal receiving circuit diagram and impedance graph which concern on 5th Embodiment. The signal receiving circuit diagram and impedance graph which concern on 6th Embodiment. The signal receiving circuit diagram and impedance graph which concern on 7th Embodiment. The signal receiving circuit diagram and impedance graph which concern on 8th Embodiment. The signal receiving circuit diagram and impedance graph of the other example concerning 8th Embodiment. The signal receiving circuit diagram and impedance graph which concern on 9th Embodiment. The example of application to the display apparatus of this invention. The conceptual diagram of an impedance matching technique. Drawing which shows the impedance matching method by external termination resistance. The figure which shows the impedance matching method by the semiconductor device with a built-in termination resistor. An impedance matching circuit according to Patent Document 1.

Explanation of symbols

100, 900a First transmission line 101, 920 First termination resistor 102, 907, 908 Input terminal 103, 910 Second termination resistor 104 Receiver 105, 905 Semiconductor device 106, 906a Second transmission line 208 First series resistor 308 Second Series resistors 508, 608, 708 Surge countermeasure component 811 Coil 904 Differential signal receiving circuit 906a Third transmission line 909b Fourth transmission line 911 Fourth termination resistor 921 Third termination resistor 1022 Resistor 1130 Common mode filter

Claims (11)

A first transmission line and a second transmission line connected in series with each other;
A semiconductor device for receiving signals via the first transmission line and the second transmission line;
A first termination resistor connected in parallel to the first transmission line and externally attached to the semiconductor device;
And a second termination resistor connected in parallel to the second transmission line and built in the semiconductor device.   The combined resistance value Rt1 of the first termination resistor, the second termination resistor, and the second transmission line matches the resistance value Rout of the first termination resistor so as to match the impedance value Zo of the first transmission line. The signal receiving circuit according to claim 1, wherein a resistance value Rin of the second termination resistor is adjusted. The second transmission line includes a first series resistor externally connected in series to the semiconductor device,
The combined resistance value Rt2 of the first termination resistance, the second termination resistance, the impedance of the second transmission line, and the first series resistance matches the impedance value Zo of the first transmission line. 2. The signal receiving circuit according to claim 1, wherein a resistance value Rout of one termination resistor, a resistance value Rin of the second termination resistor, and a first series resistance Rs <b> 1 are adjusted. The first transmission line includes a second series resistor in series with the second transmission line,
The combined resistance value Rt3 of the first termination resistor, the second termination resistor, the impedance of the second transmission line, and the second series resistance matches the impedance value Zo of the first transmission line. 2. The signal receiving circuit according to claim 1, wherein a resistance value Rout of one termination resistor, a resistance value Rin of the second termination resistor, and a second series resistance Rs2 are adjusted. A first surge countermeasure component connected in parallel to the second transmission line and externally attached to the semiconductor device;
The resistance value of the first termination resistor so that the combined resistance Rt4 of the first termination resistor, the second termination resistor and the impedance of the second transmission line matches the impedance value Zo of the first transmission line. The signal receiving circuit according to claim 1, wherein Rout and a resistance value Rin of the second termination resistor are adjusted. A coil connected in series to the first termination resistor;
The combined resistance value Rt5 of the first termination resistor, the second termination resistor, the impedance of the second transmission line, and the impedance of the coil matches the impedance value Zo of the first transmission line. 6. The signal receiving circuit according to claim 5, wherein a resistance value Rout of one termination resistor and a resistance value Rin of the second termination resistor are adjusted. A second surge countermeasure component connected in parallel to the first transmission line;
The resistance value of the first termination resistor so that the combined resistance Rt6 of the first termination resistor, the second termination resistor, and the impedance of the second transmission line matches the impedance value Zo of the first transmission line. The signal receiving circuit according to claim 1, wherein Rout and a resistance value Rin of the second termination resistor are adjusted. A coil connected in series to the first termination resistor;
A combined resistance value Rt7 of the first termination resistor, the second termination resistor, and the impedance of the second transmission line, and a resistance value Rout of the first termination resistor so that the first transmission line Zo is matched. The signal receiving circuit according to claim 7, wherein a resistance value Rin of the second termination resistor is adjusted. A third transmission line for transmitting a signal having a phase opposite to that of the first transmission line;
A fourth transmission line connected in series with the third transmission line and transmitting a signal in phase opposite to the second transmission line;
A third termination resistor connected in parallel to the third transmission line and externally attached to the semiconductor device;
A fourth termination resistor connected in parallel to the fourth transmission line and built in the semiconductor device,
The semiconductor device has a differential signal receiving circuit, further receives a signal via the third transmission line and the fourth transmission line,
The first termination resistor, the second termination resistor, the third termination resistor, the fourth termination resistor, and the combined resistance value Rt8 of the second transmission line, and the combined impedance value of the first transmission line and the third transmission line The resistance value Rout18 of the first termination resistor, the resistance value Rout28 of the second termination resistor, the resistance value Rin18 of the third termination resistor, and the resistance value Rin28 of the fourth termination resistor are adjusted so as to match Zo. The signal receiving circuit according to claim 1, wherein: A common mode filter connected in series to the first transmission line and the second transmission line, and connected in series to the third transmission line and the fourth transmission line;
The first termination resistor, the second termination resistor, the third termination resistor, the fourth termination resistor, the combined transmission line Rt9 of the second transmission line and the common mode filter, the first transmission line and the third transmission The resistance value Rout19 of the first termination resistor, the resistance value Rout29 of the second termination resistor, the resistance value Rin19 of the third termination resistor, and the resistance of the fourth termination resistor so that the combined impedance value Zo of the line is matched. 10. The signal receiving circuit according to claim 9, wherein the value Rin29 is adjusted.   A video / audio receiving apparatus comprising: the signal receiving circuit according to claim 1; and a control unit that outputs a signal received by the signal receiving circuit to an output apparatus.

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