JP2006345259A - Receiving part termination system - Google Patents

Receiving part termination system Download PDF

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JP2006345259A
JP2006345259A JP2005169437A JP2005169437A JP2006345259A JP 2006345259 A JP2006345259 A JP 2006345259A JP 2005169437 A JP2005169437 A JP 2005169437A JP 2005169437 A JP2005169437 A JP 2005169437A JP 2006345259 A JP2006345259 A JP 2006345259A
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differential
signal
common mode
transmission
transmission line
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Yasuhiro Takahashi
靖浩 高橋
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Canon Inc
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<P>PROBLEM TO BE SOLVED: To adopt a transmission line equalization system capable of preventing the generation of inter-line skews caused by the dispersion of elements in a differential mode on a receiving end of a differential transmission system and to constitute the transmission line equalization system so as not to operate as equalization (high frequency compensation) in an unnecessary common mode, to suppress the irradiation of the common mode and to perform matched termination in the common mode. <P>SOLUTION: A termination circuit for a differential mode signal is constituted between lines as a two-terminal network and a characteristic for compensating attenuation on a transmission line is provided to the network. A circuit for separating a common mode signal is used for the matching termination of the common mode signal. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、差動伝送路を用い信号の伝送を行う基板間、装置間のインタフェースにおいて、伝送路上で生じる減衰特性を受信端で補償する等化方法に関するものである。   The present invention relates to an equalization method in which attenuation characteristics generated on a transmission line are compensated at a receiving end in an interface between substrates and apparatuses that transmit signals using a differential transmission line.

高速な信号をプリント配線板上のパターンやケーブルで伝送する場合、不要輻射ノイズを抑制するために、低電圧差動信号伝送(Low Voltage Differential Signaling:LVDS)技術が利用されるケースが増えている。   In the case of transmitting a high-speed signal with a pattern or a cable on a printed wiring board, in order to suppress unnecessary radiation noise, a case where low voltage differential signal transmission (LVDS) technology is used is increasing. .

一般に低電圧差動信号伝送において、差動信号が流れる2本の伝送線路間には、逆相のディファレンシャルモード電流だけが流れるように、差動信号送信ICは設計されている。図5は一般的なLVDSインタフェースの伝送方式の一例を示した説明図である。   In general, in low-voltage differential signal transmission, a differential signal transmission IC is designed so that only a differential phase current of opposite phase flows between two transmission lines through which a differential signal flows. FIG. 5 is an explanatory diagram showing an example of a transmission method of a general LVDS interface.

図5において、送信側ドライバIC1と受信側レシーバIC2の間は、奇モードインピーダンスZoo(差動状態における各信号線の基準電位に対する特性インピーダンス)の特性インピーダンスを持つ往路伝送線路3と復路伝送線路4により結ばれている。   In FIG. 5, between the transmission side driver IC 1 and the reception side receiver IC 2, the forward transmission line 3 and the backward transmission line 4 having a characteristic impedance of odd mode impedance Zoo (characteristic impedance with respect to the reference potential of each signal line in the differential state). It is tied by

往路伝送線路3と復路伝送線路4とは電気的特性を等しくし、いわゆる平衡伝送路が形成され差動信号線路となっている。往路伝送線路3と復路伝送線路4とは受信側レシーバIC2の入力端近傍において差動伝送路インピーダンス:Zdiffとほぼ等しいインピーダンスで終端される。一般的なLVDSインタフェースにおいてこの差動伝送路インピーダンスは100Ωの純抵抗に設定される事が多く、100Ωの終端抵抗5で終端されている。   The forward transmission line 3 and the return transmission line 4 have the same electrical characteristics, and a so-called balanced transmission line is formed to be a differential signal line. The forward transmission line 3 and the backward transmission line 4 are terminated with an impedance substantially equal to the differential transmission line impedance Zdiff in the vicinity of the input end of the receiver-side receiver IC 2. In a general LVDS interface, the differential transmission line impedance is often set to a pure resistance of 100Ω, and is terminated by a termination resistor 5 of 100Ω.

ドライバIC1が約3.5mAの電流を駆動する場合、終端抵抗5においては約350mVの電圧が発生することになる。   When the driver IC 1 drives a current of about 3.5 mA, a voltage of about 350 mV is generated in the termination resistor 5.

ドライバIC1に入力される信号に基づいて、往路伝送線路3、復路伝送線路4の間に電位差が生ずる差動信号を生成する。   Based on a signal input to the driver IC 1, a differential signal that generates a potential difference between the forward transmission line 3 and the backward transmission line 4 is generated.

差動信号によりディファレンシャルモード電流は図中の矢印に示す様に、往路伝送線路3と復路伝送線路4では逆方向に流れている。これに対して、受信側レシーバIC2は差動信号を0−5Vあるいは0−3.3V等の電源電位に基づく論理振幅で動作するCMOSレベルに変換し、これをシングルエンド信号出力としてレシーバIC2は出力する。   Due to the differential signal, the differential mode current flows in the reverse direction in the forward transmission line 3 and the backward transmission line 4 as indicated by arrows in the figure. On the other hand, the receiver-side receiver IC2 converts the differential signal into a CMOS level that operates at a logic amplitude based on a power supply potential such as 0-5V or 0-3.3V, and the receiver IC2 uses this as a single-ended signal output. Output.

LVDSの原理は、送信側ドライバIC1で発生した信号電流を、往路伝送線路3と復路伝送線路4の組み合わせによる平衡伝送路と、受信側レシーバIC2近傍の終端抵抗5とで形成されるループに流すことによって、終端抵抗5の部分に信号電圧を発生させて信号を伝送するものである。信号のL論理/H論理は、電流の流れる向きを切り替えることにより識別する。この時、往路伝送線路3と復路伝送線路4を流れる電流は、理想的には大きさが同じで向きが逆である為に、往路伝送線路3と復路伝送線路4に流れる電流によって発生する磁界は互いに打ち消しあい、結果として放射ノイズやクロストークノイズの発生を抑制することができる。また、外来のノイズに対しても、影響の受け方が往路伝送線路3と復路伝送線路4とで相対的に同じであれば、信号の論理に影響せずノイズ耐性にも優れている。   The principle of LVDS is that a signal current generated by the transmission side driver IC 1 is passed through a loop formed by a balanced transmission line formed by a combination of the forward transmission line 3 and the return transmission line 4 and a termination resistor 5 near the reception side receiver IC 2. Thus, a signal voltage is generated in the terminal resistor 5 to transmit the signal. The L logic / H logic of the signal is identified by switching the direction of current flow. At this time, since the currents flowing in the forward transmission line 3 and the backward transmission line 4 are ideally the same in magnitude and reverse in direction, the magnetic field generated by the current flowing in the forward transmission line 3 and the backward transmission line 4 Cancel each other, and as a result, generation of radiation noise and crosstalk noise can be suppressed. Further, even if external noise is affected in the same way by the forward transmission line 3 and the backward transmission line 4, the signal logic is not affected and the noise resistance is excellent.

このような差動伝送方式は、基板上の信号接続のみならず基板間接続、機器間接続等で用いられる。   Such a differential transmission method is used not only for signal connection on a substrate but also for connection between substrates, connection between devices, and the like.

また、近年各種インタフェースおよびネットワークの高速化およびその普及にともない、同軸ケーブルに比べコスト的に有利な平衡ケーブル伝送が主流となっている。   In recent years, with the increase in speed and widespread use of various interfaces and networks, balanced cable transmission, which is advantageous in terms of cost compared to coaxial cables, has become the mainstream.

伝送信号の高速化にともない、プリント基板上の線路、基板間および機器間のケーブルにおける高域減衰特性が無視できなくなっており、受信端で伝送線路での減衰を補償する等化回路、または送信側で事前に伝送線路の減衰量分を強調して送出するプリエンファシス動作、もしくはその両方の手段によって補償を行う事で符号間干渉を防ぎ、正常に受信識別が行われるように操作される。   High-frequency attenuation characteristics in cables on printed circuit boards, between boards, and between equipment are becoming more and more important with the increase in transmission signal speed, and an equalization circuit that compensates for attenuation in transmission lines at the receiving end or transmission On the side, the pre-emphasis operation in which the transmission line attenuation amount is emphasized in advance, or compensation is performed by both means so that intersymbol interference is prevented, and reception is normally performed.

一般にプリント基板上の線路、メタルケーブルの減衰特性は、導体の素材、物理構成によって生じる導体損と、導体を取り巻く絶縁体(誘電体)によって生じる誘電損からなり、ともに周波数が高くなるほど減衰が顕著に表れる。   In general, the attenuation characteristics of lines and metal cables on printed circuit boards consist of conductor loss caused by the material of the conductor and physical configuration, and dielectric loss caused by the insulator (dielectric material) surrounding the conductor. Appear in

基板上の線路、メタルケーブルの減衰特性:Lc(f)は一般に次の近似式で表される。   Attenuation characteristics of lines and metal cables on a substrate: Lc (f) is generally expressed by the following approximate expression.

Figure 2006345259
Figure 2006345259

ここでfは周波数であり、a及びbはそれぞれ導体損失係数、誘電体損失係数であり、線路もしくはケーブル固有の値を持つ。またLc(f)は単位長あたりの減衰量(デシベル値)であり、ケーブル長に比例して減衰量が変化する。   Here, f is a frequency, a and b are a conductor loss coefficient and a dielectric loss coefficient, respectively, and have values inherent to the line or cable. Lc (f) is an attenuation (decibel value) per unit length, and the attenuation changes in proportion to the cable length.

誘電体損失係数bは導体損失係数aと比べはるかに小さな値となるため、比較的周波数の低い領域では伝送損失は周波数のルートに比例すると考えることができる。   Since the dielectric loss coefficient b is much smaller than the conductor loss coefficient a, it can be considered that the transmission loss is proportional to the frequency route in a relatively low frequency region.

このような線路、ケーブルでの減衰特性を補償するために、送信側のプリエンファシス回路ないしは受信側の等化回路に上式の逆振幅特性を与える事によって周波数に対する平坦度を得、符号間干渉を防いでいる。   In order to compensate the attenuation characteristics of such lines and cables, the flatness with respect to the frequency is obtained by giving the reverse amplitude characteristic of the above equation to the pre-emphasis circuit on the transmission side or the equalization circuit on the reception side, and intersymbol interference Is preventing.

送信側でのプリエンファシス方式は、高域の信号振幅を大きくするため、送信ドライバの出力能力の問題、伝送路からの不要輻射問題、さらには受信端での減衰量を送信側で予測する事が困難であるという理由からあまり用いられる事が無い。   The pre-emphasis method on the transmission side increases the signal amplitude in the high band, so the transmission side predicts the problem of output capability of the transmission driver, the problem of unnecessary radiation from the transmission line, and the attenuation at the reception end. Is rarely used because it is difficult.

差動伝送路での減衰特性(周波数−振幅特性)を補償するために、一般に持ちられている受信端での等化回路の例を図6に示す。   FIG. 6 shows an example of an equalization circuit at the receiving end that is generally held in order to compensate for attenuation characteristics (frequency-amplitude characteristics) in the differential transmission path.

同図1は送信ドライバICであり、差動信号が伝送路3および伝送路4を用いて伝送される。   FIG. 1 shows a transmission driver IC, and a differential signal is transmitted using a transmission path 3 and a transmission path 4.

伝送路3および伝送路4を伝送された信号は減衰を受け、特に高い周波数領域の成分がより大きな減衰を受け受信端に到達する。   The signals transmitted through the transmission path 3 and the transmission path 4 are attenuated, and particularly the components in the high frequency region are further attenuated and reach the receiving end.

受信端では伝送路上に配置された抵抗6、8およびコンデンサ7、9、さらに伝送路間に接続された負荷抵抗5によって伝送路上での減衰を補償し、平坦な周波数−振幅特性と成るように定数が設定される。   At the receiving end, attenuation on the transmission line is compensated by the resistors 6 and 8 and the capacitors 7 and 9 arranged on the transmission line, and the load resistor 5 connected between the transmission lines so that a flat frequency-amplitude characteristic is obtained. A constant is set.

図7で、この等化回路の部分に着目し説明する。   FIG. 7 will be described with attention paid to the equalization circuit portion.

同図41は信号源であり差動信号電圧として2・V1の信号源とする。この信号源インピーダンスは2xRsであり、抵抗42および抵抗43で表す。これらから成る信号源から負荷に対して差動電流が流れ負荷48および49に差動出力電圧が現れる。   FIG. 41 shows a signal source which is a 2 · V1 signal source as a differential signal voltage. This signal source impedance is 2 × Rs, and is represented by a resistor 42 and a resistor 43. A differential current flows from the signal source composed of these to the load, and a differential output voltage appears in the loads 48 and 49.

負荷48および負荷49が等しいインピーダンス:Rbである場合、その接合点は仮想グラウンドとみなされ為、解析上簡単のため同図上部について説明する。   When the load 48 and the load 49 have the same impedance: Rb, the junction point is regarded as a virtual ground, so the upper part of FIG.

同図上部について着目すると、信号源41を半分の電圧V1を出力する信号源と考え、またその信号源インピーダンス:Rsとなる。   Focusing on the upper part of the figure, the signal source 41 is considered as a signal source that outputs a half voltage V1, and its signal source impedance is Rs.

このような信号源に抵抗44およびコンデンサ45の並列回路が直列に挿入され、負荷抵抗48に接続されたときの出力電圧:V2(ω)は図8に示すような特性をもつ。   When a parallel circuit of the resistor 44 and the capacitor 45 is inserted in series in such a signal source and connected to the load resistor 48, the output voltage V2 (ω) has the characteristics as shown in FIG.

第1式で表した通常の伝送路の特性は、図8に示す振幅特性と反対の関係となり、ω<ω2の角周波数範囲において定数を選ぶ事によってある程度の補正を行う事が出来る。   The characteristic of the normal transmission path expressed by the first equation is opposite to the amplitude characteristic shown in FIG. 8, and a certain amount of correction can be performed by selecting a constant in the angular frequency range of ω <ω2.

実際には差動信号として扱うため、負荷抵抗48および49はひとつの素子(抵抗)で構成され、その両端に現れる負荷電圧は、2xV2となる。   In actuality, since they are handled as differential signals, the load resistors 48 and 49 are constituted by one element (resistor), and the load voltage appearing at both ends thereof is 2 × V2.

差動伝送方式において、本来伝送すべきディファレンシャルモード信号のみについて考えるとこれまで説明した等化方式および終端処理がなされているが、送信ドライバICの特性により発生しているコモンモード信号および伝送路上に励起されるコモンモード雑音が受信端での不整合反射によってもたらされる不要輻射を考えると、コモンモード信号に対する終端回路を具備する事が望ましい。   In the differential transmission method, when considering only the differential mode signal to be originally transmitted, the equalization method and termination processing described so far are performed, but the common mode signal generated due to the characteristics of the transmission driver IC and the transmission path In view of unwanted radiation caused by mismatched reflection at the receiving end of the excited common mode noise, it is desirable to provide a termination circuit for the common mode signal.

このコモンモード電流成分を抑制するには、差動信号線路のプリント配線板のグラウンド(GND)に対する結合を強くする事が考えられる。そこで、受信側レシーバIC2の入力端近傍に、差動信号伝送線路の差動インピーダンス(Zdiff)に整合した抵抗値を有する部品を、往路伝送線路3、復路伝送線路4の間に直列に配置する通常の終端方法に代わり、センタータップ終端と呼ばれる終端方法を用いて不要輻射ノイズ問題を解決することが考えられている。(参考資料:「トランジスタ技術」1997年7月号特集p.280)。   In order to suppress this common mode current component, it is conceivable to increase the coupling of the differential signal line to the ground (GND) of the printed wiring board. Therefore, a component having a resistance value matched with the differential impedance (Zdiff) of the differential signal transmission line is arranged in series between the forward transmission line 3 and the backward transmission line 4 in the vicinity of the input end of the reception-side receiver IC 2. It is considered to solve the unnecessary radiation noise problem by using a termination method called a center tap termination instead of a normal termination method. (Reference Material: “Transistor Technology” July 1997 Special Issue p.280).

センタタップ終端回路を用いた等化回路の一例を図9に示す。   An example of an equalization circuit using a center tap termination circuit is shown in FIG.

図中1は送信側ドライバICであり、2は受信側レシーバICである。送信側ドライバIC1から受信側レシーバIC2へ、往路伝送線路3及び復路伝送線路4により信号が伝送される。往路伝送線路3と復路伝送線路4とは電気的特性が等しく共に等しい奇モード特性インピーダンス:Zooを持ち、平衡伝送路が形成され差動信号線路となっている。   In the figure, 1 is a transmission side driver IC, and 2 is a reception side receiver IC. A signal is transmitted from the transmission-side driver IC 1 to the reception-side receiver IC 2 through the forward transmission line 3 and the backward transmission line 4. The forward transmission line 3 and the return transmission line 4 have an odd-mode characteristic impedance: Zoo that has the same electrical characteristics and are equal to each other, and a balanced transmission line is formed to be a differential signal line.

受信側レシーバIC2の入力端において、それぞれが差動信号伝送線路の差動特性インピーダンス:Zdiffの1/2である終端抵抗11、12が、往路伝送線路3と復路伝送線路4との間に直列に接続され、抵抗11、12の間に抵抗13の一端を接続しグラウンドへ接続されている。   At the input end of the receiver-side receiver IC 2, termination resistors 11 and 12 each having a differential characteristic impedance of the differential signal transmission line: 1/2 of Zdiff are connected in series between the forward transmission line 3 and the backward transmission line 4. One end of the resistor 13 is connected between the resistors 11 and 12 and connected to the ground.

このように構成したとき、抵抗11と抵抗12の素子値が等しい場合、ディファレンシャルモード信号に対し抵抗13は仮想グラウンドとグラウンドの間に接続された状態となり、負荷は抵抗11と抵抗12の直列合成となる。   In such a configuration, when the element values of the resistor 11 and the resistor 12 are equal, the resistor 13 is connected between the virtual ground and the ground with respect to the differential mode signal, and the load is a series composition of the resistor 11 and the resistor 12. It becomes.

一方コモンモード信号に対しては、それぞれの線路3および線路4を独立に考える事ができ、それぞれがグラウンドをリターンパスとして構成される。   On the other hand, for the common mode signal, the respective lines 3 and 4 can be considered independently, and each is configured with the ground as a return path.

したがってコモンモード信号の終端回路は、線路3に対して抵抗11と、抵抗13の素子値を二倍した値を足した素子値で構成される。線路4に対しても同様に抵抗12と、抵抗13の素子値を二倍した値を足した素子値で構成される。   Therefore, the termination circuit for the common mode signal is configured by an element value obtained by adding a value obtained by doubling the element values of the resistor 11 and the resistor 13 to the line 3. Similarly, the line 4 is composed of a resistance 12 and an element value obtained by adding a value obtained by doubling the element value of the resistance 13.

このような構成にする事によってディファレンシャルモードおよびコモンモードの両方の信号に対して終端する事ができる。   With this configuration, it is possible to terminate both differential mode and common mode signals.

このような終端方式をとった差動伝送方式においても図6と同様の伝送路等化方式が有効である。図9中、抵抗6とコンデンサ7の組み合わせ、および抵抗8とコンデンサ9の組み合わせ、さらには終端抵抗11および12からなる回路構成で与えられる周波数−振幅特性によって伝送路の逆特性を与え、等化を実現する。   The transmission line equalization method similar to that in FIG. 6 is also effective in the differential transmission method employing such a termination method. In FIG. 9, the combination of the resistor 6 and the capacitor 7, the combination of the resistor 8 and the capacitor 9, and the frequency-amplitude characteristic given by the circuit configuration including the terminating resistors 11 and 12 gives the reverse characteristic of the transmission line, and equalization Is realized.

図10は他の従来例である。図9と同様にディファレンシャルモードおよびコモンモードの両方の信号に対して終端を可能とする方式であり、終端方法を変えたものである。この場合も前述同様の等化が実現される。   FIG. 10 shows another conventional example. Similar to FIG. 9, this is a system that enables termination of both differential mode and common mode signals, and the termination method is changed. In this case, the same equalization as described above is realized.

又、従来例としては、例えば特許文献1と特許文献2をあげることが出来る。
特開2004−096351号公報 特開2004−153626号公報
Moreover, as a prior art example, patent document 1 and patent document 2 can be mention | raise | lifted, for example.
JP 2004-096351 A JP 2004-153626 A

前述した従来の等化方式において、それぞれの伝送路ならびに受信端に配置された等化回路素子値ならびに負荷回路素子値が平衡状態にあるときに完全な差動伝送が実現される。   In the above-described conventional equalization method, complete differential transmission is realized when the equalization circuit element values and load circuit element values arranged at the respective transmission lines and reception ends are in equilibrium.

しかしながら従来の等化回路方式ではそれぞれの伝送路に等化回路を個別に配置されているため、素子値のばらつきによって個々の等化特性が異なり、完全な平衡状態とは成らない。これは図9ないしは図10のような終端方式を取った場合の終端抵抗のばらつきによっても平衡状態が保てなくなる。   However, in the conventional equalization circuit method, equalization circuits are individually arranged in the respective transmission lines. Therefore, individual equalization characteristics vary depending on variations in element values, and a complete equilibrium state is not achieved. This is because the balanced state cannot be maintained due to variations in the termination resistance when the termination system as shown in FIGS.

また、等化回路が個々の線路に独立して配置され、それぞれが個々のリアクタンス素子を持つため、遅延時間のばらつきが発生する問題がある。   In addition, since the equalization circuit is arranged independently on each line, and each has an individual reactance element, there is a problem that variation in delay time occurs.

更には、等化回路が平衡伝送路に挿入される形式であるため、本来の目的であるディファレンシャルモード信号のみならず不要なコモンモード信号に対しても高域が強調される結果となり、不要輻射の点で不利となる問題があった。   Furthermore, since the equalization circuit is inserted into the balanced transmission line, the high frequency is emphasized not only for the original purpose differential mode signal but also for the unnecessary common mode signal. There was a problem that was disadvantageous.

本発明では前記問題に鑑み、差動伝送方式において主たる伝送目的であるディファレンシャルモード信号に対し常にバランスの取れた等化回路とすると共に、コモンモード信号に対し無用な高域強調を行わず、不要輻射を低減する等化終端回路を提供する事を目的とする。   In the present invention, in view of the above problems, an equalization circuit that is always balanced with respect to the differential mode signal, which is the main transmission purpose in the differential transmission method, is used, and unnecessary high-frequency emphasis is not performed on the common mode signal. An object is to provide an equalization termination circuit for reducing radiation.

本発明では、ディファレンシャルモード信号用の終端回路とコモンモード信号用の終端回路を独立した構成とし、ディファレンシャルモードに対する終端回路および等化回路を二端子回路網で構成し、それぞれの伝送路間を接続すると共に、コモンモード信号用終端回路を別途構成するようにする。   In the present invention, the termination circuit for the differential mode signal and the termination circuit for the common mode signal are configured independently, the termination circuit for the differential mode and the equalization circuit are configured by a two-terminal network, and the respective transmission lines are connected. In addition, a common mode signal termination circuit is separately configured.

それぞれのモードに対して独立した終端回路を構成するためには、共通の伝送路を伝播してきたそれぞれのモードの信号を分離する必要があり、そのための伝送モード分離回路を用いる。   In order to configure an independent termination circuit for each mode, it is necessary to separate the signals of the respective modes that have propagated through the common transmission line, and a transmission mode separation circuit for that purpose is used.

図2で、具体的に説明する。   This will be specifically described with reference to FIG.

同図3、4はお互い結合された平衡伝送路である。同図右端は受信部であり、ディファレンシャルモード信号は、ディファレンシャルモード等化終端41にて終端される。この終端41は2端子回路網とし、線路間のバランスを保った等化器ならびに終端器となる。   3 and 4 are balanced transmission lines coupled to each other. The right end of the figure is a receiving unit, and the differential mode signal is terminated at a differential mode equalization termination 41. This termination 41 is a two-terminal network, and becomes an equalizer and termination that maintain a balance between the lines.

一方、コモンモード信号は先の等化終端41はハイインピーダンス素子として振舞うため、モード分離回路42に導かれ、コモンモード終端43にて整合終端される。   On the other hand, the common mode signal is led to the mode separation circuit 42 because the previous equalization termination 41 behaves as a high-impedance element, and is matched and terminated at the common mode termination 43.

モード分離回路42は、ディファレンシャルモードとして伝播してきた信号に対してハイインピーダンスとなり、コモンモードとして伝播してきた信号についてのみ透過させる回路網である。   The mode separation circuit 42 is a circuit network that has a high impedance with respect to a signal propagated as a differential mode and transmits only the signal propagated as a common mode.

本発明の差動伝送方式の受信端における等化終端方式は、同図に示すようにモード分離回路42を用い、それぞれのモードの終端回路を並列に配置したものである。   The equalization termination system at the receiving end of the differential transmission system of the present invention uses a mode separation circuit 42 as shown in the figure, and the termination circuits for the respective modes are arranged in parallel.

このようにそれぞれ独立した終端回路ならびに等化回路構成とする事が出来るため、ディファレンシャルモードの終端はバランスの取れた2端子回路網を使用することができ、従来の等化方式で問題となった素子値のばらつき等によって発生する不完全な平衡状態となることと、線路間の遅延時間差を防ぐ事が出来、更には不要なモードの不要輻射を低減した差動等化終端回路を実現できる。   Since the termination circuit and the equalization circuit configuration can be made independent of each other as described above, a balanced two-terminal network can be used for the termination of the differential mode, which is a problem in the conventional equalization method. A differential equalization termination circuit can be realized in which an incomplete equilibrium state caused by variations in element values and the like, a delay time difference between lines can be prevented, and unnecessary radiation of unnecessary modes can be reduced.

以上説明したように本発明によれば、差動伝送方式の受信端において、ディファレンシャルモード信号にのみ等化特性を与え、コモンモード信号に対し不要な高域強調せず、なおかつ整合終端を可能とし、不要輻射の低減、伝送路間の遅延時間差の低減ならびに伝送路上に励起されるコモンモード雑音を効果的に相殺する事が出来る。   As described above, according to the present invention, at the receiving end of the differential transmission system, equalization characteristics are given only to the differential mode signal, unnecessary high frequency emphasis is not applied to the common mode signal, and matching termination is enabled. In addition, unnecessary radiation can be reduced, a delay time difference between transmission lines can be reduced, and common mode noise excited on the transmission line can be effectively canceled out.

本発明の実施例を、図1を用いて説明する。   An embodiment of the present invention will be described with reference to FIG.

同図21、22はそれぞれ送信側の差動信号入力ポートであり、極性が反転したディファレンシャル信号がそれぞれ入力される。   FIGS. 21 and 22 are transmission-side differential signal input ports, respectively, to which differential signals whose polarities are inverted are input.

それぞれ正負反転した信号が差動伝送路25、26をそれぞれ右端の受信部に向けて伝送される。   The positive and negative signals are respectively transmitted through the differential transmission lines 25 and 26 toward the right end receiving unit.

本来の伝送目的であるディファレンシャルモード信号は、抵抗27、28およびインダクタ29から成るディファレンシャルモード信号終端回路で終端され、受信出力ポート23および24に差動出力される。   The differential mode signal, which is originally intended for transmission, is terminated by a differential mode signal termination circuit including resistors 27 and 28 and an inductor 29, and is differentially output to the reception output ports 23 and 24.

一方、コモンモード信号は前記ディファレンシャルモード信号用終端回路では終端されず、トランス30を透過し、コモンモードインピーダンスに整合された抵抗器31にて整合終端される。   On the other hand, the common mode signal is not terminated in the differential mode signal termination circuit, but is transmitted through the transformer 30 and matched and terminated by the resistor 31 matched to the common mode impedance.

トランス30は、ディファレンシャルモード信号(互いに逆相)の信号が入力されると、お互いの電流が発生する磁束の方向が同じとなるため、大きなインダクタンスとして動作し、ディファレンシャルモード信号を透過させない。   When a differential mode signal (a phase opposite to each other) is input, the transformer 30 operates as a large inductance and does not transmit the differential mode signal because the directions of magnetic fluxes generated by the mutual currents are the same.

したがって伝送されてきたディファレンシャルモード信号はディファレンシャルモード信号終端回路(素子27、28、29で構成)でのみ終端され、受信出力ポート23、24に差動出力される。   Therefore, the transmitted differential mode signal is terminated only by the differential mode signal termination circuit (comprising elements 27, 28, and 29), and is differentially output to the reception output ports 23 and 24.

一方互いに同相であるコモンモード信号に対して、先のトランス30はお互いの磁束を打ち消しあう動作をし、低インピーダンス素子として振舞う。したがって、コモンモード信号はトランス30を透過し抵抗31にて整合終端される。また、コモンモード信号は、ディファレンシャルモード信号終端回路の両端に同電位を与えるため、コモンモード電流が流れず受信出力ポート23、24間にコモンモード電圧を与えない。   On the other hand, with respect to common mode signals that are in phase with each other, the previous transformer 30 operates to cancel each other's magnetic flux and behaves as a low impedance element. Therefore, the common mode signal passes through the transformer 30 and is matched and terminated by the resistor 31. Further, since the common mode signal gives the same potential to both ends of the differential mode signal termination circuit, the common mode current does not flow and no common mode voltage is given between the reception output ports 23 and 24.

ディファレンシャルモード信号に対する終端部分の動作について図3にて説明する。   The operation of the termination portion with respect to the differential mode signal will be described with reference to FIG.

同図41は信号源であり差動信号電圧として2・V1の信号源とする。この信号源インピーダンスは2xRsであり、抵抗42および抵抗43で表す。これらから成る信号源から負荷に対して差動電流が流れる。   FIG. 41 shows a signal source which is a 2 · V1 signal source as a differential signal voltage. This signal source impedance is 2 × Rs, and is represented by a resistor 42 and a resistor 43. A differential current flows from the signal source composed of these to the load.

図1に示したディファレンシャルモード信号に対する負荷部分は、仮想グラウンドを考慮すると、図3のように各素子値を等しく二分配して仮想グラウンドに対して対称に素子を配置した回路に書き直す事ができる。ここで各素子値を、
R27'= R27/2 (抵抗51、52)
R28'= R28/2 (抵抗53、54)
L29'= L29/2 (インダクタ55、56)
と表現する。
In consideration of the virtual ground, the load portion for the differential mode signal shown in FIG. 1 can be rewritten into a circuit in which the element values are equally distributed as shown in FIG. 3 and the elements are arranged symmetrically with respect to the virtual ground. . Where each element value is
R27 '= R27 / 2 (resistors 51 and 52)
R28 '= R28 / 2 (resistors 53, 54)
L29 '= L29 / 2 (Inductors 55, 56)
It expresses.

図3上部について着目すると、信号源41を半分の電圧V1を出力する信号源と考え、またその信号源インピーダンス:Rsとなる。   Focusing on the upper part of FIG. 3, the signal source 41 is considered as a signal source that outputs half the voltage V1, and the signal source impedance is Rs.

このような信号源に抵抗51および、インダクタンス55と抵抗53の並列回路が負荷として接続され、このとき仮想グラウンドを基準に考えた負荷電圧:V2(ω)は図4に示すような特性をもち、従来の技術で説明した等化回路を伝送路上に配置した場合と同様の等化特性をディファレンシャルモード負荷に与える事ができる。   A resistor 51 and a parallel circuit of an inductance 55 and a resistor 53 are connected to such a signal source as a load. At this time, the load voltage V2 (ω) considered with reference to the virtual ground has characteristics as shown in FIG. Thus, it is possible to give the differential mode load the same equalization characteristics as when the equalization circuit described in the prior art is arranged on the transmission line.

一方、コモンモード信号に対して上記説明した回路は影響を与えず、コモンモード信号は図1に示される抵抗31で終端され、高域の強調(等化動作)されない。   On the other hand, the circuit described above does not affect the common mode signal, and the common mode signal is terminated by the resistor 31 shown in FIG. 1 and is not emphasized (equalization operation).

本発明の実施例を説明する図The figure explaining the Example of this invention 本発明の実施例の構成を説明する図The figure explaining the structure of the Example of this invention 本発明の実施例の動作を説明する図The figure explaining operation | movement of the Example of this invention 本発明の実施例の動作特性を説明する図The figure explaining the operating characteristic of the Example of this invention 一般的な差動伝送方式の一例を示した説明図An explanatory diagram showing an example of a general differential transmission system 従来の差動伝送方式の等化回路の一例を示した説明図An explanatory view showing an example of a conventional differential transmission type equalization circuit 従来の差動伝送方式の等価回路の動作を説明する図The figure explaining operation of the equivalent circuit of the conventional differential transmission system 従来の差動伝送方式の等価回路の動作特性を説明する図The figure explaining the operation characteristic of the equivalent circuit of the conventional differential transmission system 従来の差動伝送方式の等価終端回路例を示した図A diagram showing an example of a conventional differential transmission equivalent termination circuit 従来の差動伝送方式の等価終端回路例を示した図A diagram showing an example of a conventional differential transmission equivalent termination circuit

符号の説明Explanation of symbols

1 送信ドライバIC
2 受信IC
3、4、25、26 差動伝送路
5 終端抵抗
6、8、11、12、13、14、15、16、44、46、48、49、51、52、53、54 抵抗器
7、9、45、47 コンデンサ
29、55、56 インダクタ
30 トランス
31 コモンモード用終端抵抗
42、43 信号源インピーダンス
1 Transmission driver IC
2 Receiver IC
3, 4, 25, 26 Differential transmission line
5 Terminating resistor
6, 8, 11, 12, 13, 14, 15, 16, 44, 46, 48, 49, 51, 52, 53, 54 Resistors
7, 9, 45, 47 capacitors
29, 55, 56 inductor
30 transformer
31 Common mode termination resistor
42, 43 Signal source impedance

Claims (3)

送信装置と受信装置間を、平衡伝送路を通信媒体として、差動信号を伝送する通信方式で、
受信端で、各差動伝送路間に信号終端器として二端子回路網を配置し、その二端子回路網に任意の周波数−振幅特性を与える事を特徴とする受信部終端方式。
With a communication system that transmits differential signals between a transmission device and a reception device, using a balanced transmission path as a communication medium,
A receiver termination system characterized in that, at the receiving end, a two-terminal network is arranged as a signal terminator between each differential transmission line and an arbitrary frequency-amplitude characteristic is given to the two-terminal network.
ディファレンシャルモード信号と、コモンモード信号を分離するためのモード分離回路を用い、コモンモード用の終端回路を別途構成したことを特徴とする、請求項1に記載の受信部終端方式。   The receiving unit termination system according to claim 1, wherein a mode separation circuit for separating the differential mode signal and the common mode signal is used, and a termination circuit for the common mode is separately configured. ディファレンシャルモード信号と、コモンモード信号を分離するためのモード分離回路に、ディファレンシャルモードを阻止し、コモンモードに対して透過となる巻き方をしたトランスを用いた、請求項3の受信部終端方式。   4. The receiving unit termination system according to claim 3, wherein a transformer having a winding method that blocks the differential mode and transmits the common mode is used for the mode separation circuit for separating the differential mode signal and the common mode signal.
JP2005169437A 2005-06-09 2005-06-09 Receiving part termination system Withdrawn JP2006345259A (en)

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7911244B2 (en) 2007-11-30 2011-03-22 Sony Corporation Differential drive circuit and communication device
JP2012161077A (en) * 2011-01-28 2012-08-23 Silicon Works Co Ltd Pre-emphasis circuit and differential current signal transmission system
JP2013527699A (en) * 2010-04-26 2013-06-27 クアルコム,インコーポレイテッド Level shifter with balanced duty cycle
JP2017181139A (en) * 2016-03-29 2017-10-05 株式会社東京精密 Small digital length measuring unit
JP2019220978A (en) * 2013-08-19 2019-12-26 アリス エンタープライジズ エルエルシーArris Enterprises Llc Optical fiber node whose power consumption is driven by forward data content
WO2024057909A1 (en) * 2022-09-15 2024-03-21 ローム株式会社 Transfer circuit

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7911244B2 (en) 2007-11-30 2011-03-22 Sony Corporation Differential drive circuit and communication device
JP2013527699A (en) * 2010-04-26 2013-06-27 クアルコム,インコーポレイテッド Level shifter with balanced duty cycle
JP2012161077A (en) * 2011-01-28 2012-08-23 Silicon Works Co Ltd Pre-emphasis circuit and differential current signal transmission system
JP2019220978A (en) * 2013-08-19 2019-12-26 アリス エンタープライジズ エルエルシーArris Enterprises Llc Optical fiber node whose power consumption is driven by forward data content
JP2017181139A (en) * 2016-03-29 2017-10-05 株式会社東京精密 Small digital length measuring unit
WO2024057909A1 (en) * 2022-09-15 2024-03-21 ローム株式会社 Transfer circuit

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