JP2005236551A - Video signal converter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize a signal format converting function and a time axis correcting function through common circuitry and simple memory control. <P>SOLUTION: On the basis of a common memory control rule, a format is converted into a standard signal using a memory when a nonstandard signal is input from a camera signal processing means, and converted into a standard signal by performing time axis correction using a memory when the nonstandard signal is input from an analog signal input means. The standard signal is output continuously even when input of the signal is interrupted or resumed. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a technology for converting a video signal such as a moving image and a still image from a progressive signal to an interlace signal, and a technology for converting a non-standard signal such as a video signal reproduced by a video tape recorder into a standard signal (time axis correction). Is related to the video signal recording apparatus.

  In a digital VTR or the like, an interlace signal or a progressive signal output from a camera signal processing unit may be used as an input signal. These VTR input signals are synchronized with a processing cycle (field cycle or frame cycle) required by the processing unit at the subsequent stage. However, these VTR input signals may have a phase shift in a reference phase such as blanking with respect to the processing cycle. Therefore, when an interlace output such as a digital VTR is a standard signal, an interlace signal or a progressive signal input from the camera signal processing means to the digital VTR is a non-standard video signal.

  In addition, even in a video signal reproduced by a video tape recorder, the signal has a period deviation from a processing period (field period or frame period) required by subsequent processing means, blanking, etc. A phase shift may occur with respect to the reference phase, and when the output of the video tape recorder is a standard video signal, the input is a non-standard video signal.

  In the VTR input signal, the input signal may suddenly change from an interlace signal to a progressive signal in synchronization with blanking, or may be switched to the opposite input. Furthermore, in a non-standard signal such as a video signal reproduced by a video tape recorder, the input signal may be switched completely asynchronously with blanking or the like. In this way, the non-standard video signal itself may further vary.

  In the first conventional technique, a video signal is written in a frame or field unit memory, read out from the memory in accordance with a synchronization signal of a standard signal, and an overtaking in frame or field unit is generated between the writing and reading. ing. The first prior art proposes a function of converting a non-standard video signal into a standard signal with a simple configuration (see Patent Document 1).

  However, according to the first prior art, when the video signal is interrupted or the input is switched in the middle, conversion to the standard signal is impossible, and the output video signal is disturbed. Further, it does not have a format conversion function from an interlace signal to a progressive signal.

  In the second conventional technique, the write address is sequentially switched based on the write clock following the time axis fluctuation of the video signal, the video signal is written to the memory, and the read address is read based on the read clock asynchronous with the write clock. Are sequentially switched to read out the video signal from the memory. Thereby, in the second conventional technique, the time-axis fluctuation of the video signal is corrected (see Patent Document 2).

In the second conventional technique, an optimum read address is calculated from the phase difference between the write address and the read address as an operation, and a time axis correction function is realized. In the second prior art, when the phase difference is less than the specified value, the read address is advanced by one field to avoid a memory contention state, and when the memory contention state disappears, the read address is returned by one field to return to the normal phase state. ing. According to the second prior art, the only operation necessary for avoiding the memory race condition is to advance the read address based on the phase difference. However, in the second prior art, it is possible to correct the time axis by the above operation in the memory configured with two fields, but in the memory configured with three fields or more, the operation of advancing the read address and the operation of returning. Etc. are required. In other words, not only the operation for advancing the address but also another operation is required. Further, in the second prior art, as in the first prior art, when the video signal is interrupted or the input is switched in the middle, the conversion to the standard signal becomes impossible and the output video signal Will be disturbed. Furthermore, the second prior art also does not have a format conversion function from an interlace signal to a progressive signal.
Japanese Patent Laid-Open No. 2001-309311 JP-A-7-203379

  As described above, in the first and second prior arts, the function of converting the format of the progressive signal to the interlaced signal, and the function of correcting the time axis of the non-standard signal such as the video signal reproduced by the video tape recorder to the standard signal, Is not realized by a common circuit configuration or common memory control. For this reason, this conventional technology increases the circuit scale, makes the configuration more complicated, makes the memory control more complicated, and changes the standard signal against complex input fluctuations such as input signal switching and input signal interruption. There is a disadvantage in that the video signal cannot be output without interruption and the video signal is disturbed. An object of the present invention is to eliminate these problems.

  The present invention comprises a memory means comprising N fields, a memory control means for controlling a write address and a read address of the memory means, converting an input signal into a predetermined standard signal and outputting it, and a protective means at the output of the memory means. Have Thus, in the present invention, when a common memory control algorithm is used, the signal input to the memory control means is a non-standard signal (progressive signal or interlace signal) output from the camera signal processing means. When the format is converted and the non-standard signal (interlace signal) is output from the analog input signal processing means, the time axis is corrected. Therefore, even when the input signal is interrupted or discontinuously switched, or when there is no video signal in the memory means, an interlace signal output of a predetermined standard signal is realized, and the output video signal is prevented from being disturbed. .

  The present invention provides a common circuit for both functions, for example, a function for converting a format from an interlace signal to a progressive signal and a function for correcting a time axis of a non-standard signal such as a video signal reproduced by a video tape recorder to a standard signal. It can be realized with a configuration and a simple memory control method.

  Further, according to the present invention, it is possible to output a standard signal without interruption even when the input signal is interrupted or switched.

  FIG. 1 is a block diagram showing a first embodiment of a video signal conversion apparatus of the present invention. In the figure, a camera signal processing unit 101 uses a digital video signal source (not shown) such as a digital video camera as a video input source, and outputs a digital video signal output from an imaging device (not shown) of the digital video signal source. Among them, when transmitting a moving image signal, it is mainly output as an interlace signal, and when transmitting a still image signal, it is mainly output as a progressive signal.

  The interlace signal and progressive signal output from the camera signal processing means 101 are synchronized with the field period and frame period, which are processing periods required by the subsequent processing means (not shown), but blanking, etc. This is a signal having a phase shift with respect to the reference phase.

  An analog input signal processing means 102, which is an example of an external signal input means, uses an analog video signal source such as an analog VTR as a video input source, and a reproduced video signal from the analog video signal source is a pseudo NTSC / PAL signal (interlace signal). Is converted to a non-standard signal and output. The non-standard signal output from the analog input signal processing means 102 has a phase shift not only between the field period and the frame period, which are processing periods required by the subsequent processing means, but also with a reference phase such as blanking. Signal.

  When the video signal from the digital video signal source is recorded (camera recording), the selector 103 receives the output of the camera signal processing means 101 and records the video signal from the analog video signal source (analog input signal recording). ), The non-standard signal (a) is output using the output of the analog input signal processing means 102 as an input.

  The memory control means 104 receives the non-standard signal (a) as an input signal, calculates a write address (hereinafter referred to as “Wad”) from the non-standard signal (a), and simultaneously reads the standard signal (b) as a read address (hereinafter referred to as “Rad”). To calculate). (A ′) is a video signal obtained by removing blanking information and synchronization information from the non-standard signal (a), and (b ′) adds blanking information and synchronization information to the standard signal (b). It is the previous signal.

  The memory 105 writes the non-standard signal (a ′) according to the Wad calculated by the memory control means 104 and reads the standard signal (b ′) according to the Rad.

  FIG. 2 is a block diagram illustrating an example of the configuration of the memory control unit 104. The input signal input to the memory control means 104 is a non-standard signal (a), and the write synchronization signal detection means 201 detects synchronization information in the non-standard signal (a) and writes from the detected synchronization information. Generate and output a synchronization signal. The read synchronization signal generation unit 202 generates a synchronization signal for reading as a standard signal, and outputs a read synchronization signal. The W / R pointer control means 203 monitors the phase difference, periodicity, and continuity of the write synchronization signal and the read synchronization signal, sets Wad and Rad, and deletes and adds synchronization information and blanking information. When only a signal that is not worth reading is left in the memory 105, the protection unit 204 outputs a blueback signal that is a protected video signal.

  FIG. 3 is a diagram illustrating a configuration example of parameters for monitoring the configuration of the memory 105 and the state of the memory. In this example, the memory 105 has a 4-field configuration. In the control on the writing side, the signal (a ′) is written in the memory 105 in accordance with the Wad set by the memory control means 104. At the start and end of writing, the write completion flag indicating the state of each field memory and the write signal set the format flag to a predetermined value. The format flag is video signal identification information indicating a progressive signal or an interlace signal. Further, when the write processing is completed in the write completion flag, the flag is set to “true”, and when it is not completed, it is set to “false”.

  In the control on the reading side, the standard signal is read from the memory 105 according to the Rad set by the memory control means 104. When the cyclic order of the read field memory area is disturbed at the end of reading, skip information (hereinafter referred to as a skip flag) indicating that fact and pseudo-field processing information indicating inter-line interpolation processing of the read field signal ( Hereinafter, the pseudo field processing flag M) is set to a predetermined value. When the pseudo field processing is performed, the pseudo field processing flag M is set to “true”, and when the pseudo field processing is not performed, the pseudo field processing flag M is set to “false”.

  FIG. 4 is a flowchart illustrating an example of an algorithm for controlling Wad generated by the memory control unit 104. Here, the flow in the case of writing N fields is shown.

  Before starting the writing of the N field, the writing completion flag of the target field is set to “false” and the writing is started (S401, S402). While writing is in progress, the continuity and periodicity of the write synchronization signal of the write video signal (non-standard video signal) are monitored (S403), and if an unpredicted field head is detected, the unpredicted head is determined. The position of the unpredicted field in the frame (hereinafter referred to as an unpredicted determination frame) to which the field (hereinafter referred to as an unpredicted field) belongs is determined, that is, whether it is the first field or the second field (S404). Furthermore, the position of the Rad at that time, and the fields of both adjacent frames (hereinafter referred to as adjacent fields) that are positioned temporally before and after the unpredicted determination frame in the video time in the written video signal (non-standard video signal). )) Is detected. Here, the adjacent field of both adjacent frames to be measured is a field (first field or second field) at the same position as the unpredicted determination field. Then, an adjacent field that is farther in time from the Rad position than the video time is selected, and after the Wad is set at the head of the selected adjacent field, writing is continued (S405 to S408).

  If the unexpected field head is not detected and the N field has been written to the end (S409), the write completion flag is set to “true”, and the format flag is set to “interlace” or “progressive” ( S410), the writing process is completed. Then, the process proceeds to the next field N + 1 writing step (S411).

  FIG. 5 is a flowchart illustrating an example of an algorithm for controlling Rad generated by the memory control unit 104. Here, the flow in the case of reading N fields is shown. First, the big flow will be explained.

  The Read scheduled field is determined within the blanking period on the reading side. Then, the field to be actually read is determined based on the determination whether the write completion flag of the determined read scheduled field is “true” or “false”. The read address of the field determined to be read is Read. Details will be described below.

  First, a method for setting the Read schedule field will be described. Here, a description will be given using a Write address pointer (= Wad, hereinafter referred to as WP) to which writing is currently performed and a Read address pointer (hereinafter referred to as RP) of a Read scheduled field.

  It is determined whether the format flag of an arbitrary N field to be read is “interlace” or “progressive” (S501). If the determination in S501 indicates progressive, WP-RP <threshold 2 is determined (S502). The threshold 2 will be described later. If the determination in S502 is “true”, the Read scheduled field is provisionally set to the N-2 field (S503).

  When the determination of S501 is “interlace”, or when the determination of S501 is “progressive” and the determination of S502 is not WP-RP <threshold 2 (= “false”), RP-WP < The threshold value 1 is determined (S504). The threshold value 1 will be described later.

  If the determination in S504 is not RP-WP <threshold 1 (= “false”), then the output signal is subjected to pseudo field processing twice or more consecutively using pseudo field processing flags M and M−1 It is determined whether or not it is a signal (S505). The pseudo field processing flag will be described later.

  In S505, when it is determined that the video signal subjected to the pseudo field processing twice or more is not output, the Read scheduled field is provisionally set to the N field (S506).

  In S505, when it is determined that the video signal that has been subjected to the pseudo field processing has been output twice or more in succession, it is determined whether or not “fwd” is set in the skip flag with reference to the skip flag (S507). ). If it is determined in S507 that the skip flag is set to “fwd”, the Read scheduled field is provisionally set to the N + 1 field (S508). If it is determined in S507 that “bak” is set in the skip flag, the Read scheduled field is provisionally set in the N−1 field (S509).

  On the other hand, if it is determined in S504 that RP-WP <threshold 1 is “true”, the format flag is referred again (S510). If it is determined in S510 that the format flag is interlaced, the Read scheduled field is provisionally set to N + 1, and the skip flag is set to “fwd” (S511).

  If it is determined in S510 that the format flag is progressive, the Read scheduled field is temporarily set to N + 2, and at the same time, the Write completion flag of the N + 2 field is forcibly set to “true” (S512).

  Next, a method for setting a field to be actually read will be described. First, it is determined whether or not all Write completion flags in the memory 105 are “false” (S513). If it is determined in S 513 that it is “false”, it is determined that there is no video signal worthy of output in the memory 105. In this case, a protected video signal such as a blue background is output through the protection unit 204 to prevent the video from being disturbed (S514).

  If it is determined in S513 that all the Write completion flags are not “false”, the Write completion flag of the Read scheduled field temporarily set in the above procedure is referred to (S515).

  If the write completion flag of the read scheduled field is determined to be “true” in the result of the write completion flag reference in S515, the temporarily set read scheduled field is set as the read scheduled field and the read operation is performed (S516). ).

  At this time, when the read timing of the standard signal is when the first field is output, the video data of the first field of the memory 105 is read. If the standard signal read timing is the second field output time, the video data of the second field of the memory 105 is read. In this case, since the standard signal read timing is when the first field is output, when the video data of the second field is read, interpolation processing between the lines of the read data is performed and output as a pseudo field. When performing pseudo field processing, the pseudo field processing flag M is set to “true”, and when it is not necessary to perform pseudo field processing, the pseudo field processing flag M is set to “false”.

  Prior to such setting of the pseudo field processing flag M, the contents of the pseudo field processing flag M are copied as the pseudo field processing flag M-1 located immediately before the flag M.

  If the Write completion flag of the Read scheduled field is “false” in the reference result of the Write completion flag in S515, the field one field before the Read scheduled field set so far (Read scheduled field-1) is newly added. Is set as a Read schedule field. In this case, it is determined that the cyclic order of the read field memory area is disturbed at the end of reading, and the skip flag is set to “bak” (S517).

  After performing the process of S517, the process returns to S513 to determine again whether the write completion flag is “true” / “false”.

  By executing the Wad algorithm and the Rad algorithm defined as described above, the video signal as the standard signal output (b) is always output without being disturbed in any case. Hereinafter, the reason will be described with reference to FIG.

  FIG. 6 is a timing chart showing an example of the operation of the memory control unit 104 when the non-standard signal (a) is a progressive signal of the camera signal processing unit 101. The memory 105 is a four-field memory, which is sequentially designated as a field memory # 0, a field memory # 1, a field memory # 2, and a field memory # 3.

  In this case, since the non-standard signal (a) is a progressive signal, video data of two fields is written into the memory 105 using one frame time. The field memory being written is indicated by diagonal lines, and at this time, the write completion flag is in a “false” state.

  In the reading process, the video signal is read as an interlace signal which is a standard signal. One field time is used as the time required for reading, whereby one field of video data is read at each reading time. The input progressive signal (non-standard signal) is in a state in which the time period of the frame unit is coincident with the synchronization of the read standard signal, but is out of phase with blanking. Therefore, there is a phase relationship in which reading is possible and a phase relationship incapable of reading depending on the mutual relationship between the WP output (Wad) and the RP output (Rad). That is, in FIG. 6, the timing period from the state Rad1 in which the read cycle of the RP output (Rad) is the same timing as the write cycle of the WP output (Wad) to the state Rad2 that is relatively delayed by a predetermined time lag. Then, it is possible to continuously read the field data from the memory 15 while avoiding duplication of the reading process and the writing process. Hereinafter, such a timing area is referred to as a readable area 1.

  However, if the read cycle of the RP output (Rad) is relatively delayed with respect to the write cycle of the WP output (Wad) relative to the above-described Rad2, the timing region in which reading is impossible during the read processing occurs, and the memory 15, the field data cannot be continuously read out. Hereinafter, such a timing area is referred to as a non-readable area 1.

  On the other hand, the read period of the RP output (Rad) with respect to the write period of the WP output (Wad) is a timing period from the state Wad3 at the same timing to the state Wad4 that is relatively preceding (overtaking) with a predetermined time lag. The field data can be continuously read / written from the memory 15 while avoiding the overlap between the read process and the write process. Hereinafter, such a timing area is referred to as a readable area 2.

  However, if the read cycle of the RP output (Rad) precedes the above-described Rad4 or more relative to the write cycle of the WP output (Wad), a timing at which reading becomes impossible in the read process occurs, and the memory 15 The field data cannot be read continuously. Hereinafter, such a timing area is referred to as an unreadable area 2.

  In the configuration of the memory 105 according to this embodiment in which video data for one frame (2 fields) is alternately read and written using four field memories, the above-described predetermined time lag (allowable preceding time or allowance in read / write processing) is used. (Delay time) is 1/2 field time in the read cycle.

  In the present invention, the discrimination between the readable areas 1 and 2 and the unreadable areas 1 and 2 is performed by WP (Write address pointer to which writing is currently performed) and RP (Read address pointer of a Read scheduled field). It is discriminated based on the phase difference. This will be described below.

  When a relative shift occurs between the Rad phase position and the Wad phase position, a shift occurs between the read address position of the RP output (Rad) and the write address position of the WP output (Wad). In the present invention, discrimination between the readable areas 1 and 2 and the unreadable areas 1 and 2 is performed based on a determination as to whether or not the deviation is equal to or greater than a predetermined value (threshold 1 and threshold 2).

  In the configuration of this embodiment in which data for one frame (for two fields) is alternately read and written using four field memories, the thresholds 1 and 2 are set to the predetermined time lag described above (allowable Rad preceding in read / write processing). The address corresponds to (time or allowable Rad delay time) and becomes 1/2 field. In FIG. 6, the time shift is indicated by s.

  FIG. 7 shows an example of the operation and output of the memory control means 104 when the RP starts reading from the readable areas 1 and 2 when the non-standard signal (a) is a progressive signal of the camera signal processing means 101. It is a timing chart which shows. FIG. 7 shows a case where the above-mentioned predetermined time lag (allowable Rad leading time or allowable Rad delay time in read / write processing) is within an allowable range.

  In the algorithm on the writing side, the write completion flag is set to “true” at the same time as the writing is completed, so that reading is possible. At the same time, the format flag is set to “progressive”. In the algorithm on the reading side, threshold 1 and threshold 2 are set to 1/2 field. In the readable area 1 and the readable area 2, both the condition of RP-WP <threshold 1 and the condition of WP-RP <threshold 2 are “false” (see S501, S502, and S504 in FIG. 5). Furthermore, since the format being handled is progressive (only frame skip exists), the pseudo field processing flag does not become “true” (see S505 in FIG. 5), and the N field is provisionally set as the Read scheduled field. (See S506 in FIG. 5). In this case, since the Write completion flag is “true”, reading is performed in the set Read scheduled field (see S513 to S517 in FIG. 5).

  Here, the notation of the output signal (standard signal (b)) of the memory control means 104 will be described. “0a” is a signal in the 0th first field period, and “0b” is a signal in the 0th second field period. “0a ′” is a signal obtained by performing pseudo field processing for output of the second field period from the signal of the 0th first field period, and “0b ′” is the signal from the signal of the 0th second field period. This is a signal subjected to pseudo field processing for outputting for one field period. Note that the signals “0a ′” and “0b ′” are not handled in FIGS. 6 and 7 and are referred to in the following description.

  FIG. 8 shows that the RP starts reading from the unreadable region 1 when the non-standard signal (a) input from the selector 103 to the memory control unit 104 is a progressive signal output from the camera signal processing unit 101 ( 7 is a timing chart showing an example of the operation and output of the memory control means 104 when the RP output (Rad) exceeds the allowable Rad delay time and is relatively delayed from the WP output (Wad).

  The algorithm on the writing side is the same as that shown in FIG. In the algorithm on the reading side, threshold 1 and threshold 2 are set to 1/2 field. In the unreadable area 1, the condition of WP-RP <threshold 2 is “false”, and the condition of RP-WP <threshold 1 is “true” (see S501, S502, S504, and S510 in FIG. 5). Therefore, the Read scheduled field is provisionally set to the N + 2 field (see S512 in FIG. 5). In FIG. 8, the read start time of the Read scheduled field N + 2 field is shown at time t81.

  The N + 2 field provisionally set as the Read scheduled field has the Write completion flag rewritten to “true” in S512 of FIG. 5, and is thus set as the Read scheduled field through the determinations of S513 and S515 of FIG. 5. Reading is possible (see S516 in FIG. 5). In the non-standard signal, even if the reference phase such as blanking is deviated from the read standard signal, the field / frame period is synchronized with the read standard signal. For this reason, once the non-standard signal is in a state where the phase relationship is in place and reading is started from the readable area 2, the non-standard signal is not read from the unreadable area thereafter.

FIG. 9 shows that the RP starts reading from the unreadable region 2 in a state where the non-standard signal (a) input from the selector 103 to the memory control unit 104 is a progressive signal output from the camera signal processing unit 101 ( (RP output (Rad) is relatively ahead of WP output (Wad) over the allowable Rad leading time))
6 is a timing chart showing an example of the operation and output of the memory control means 104 in the case.

  The algorithm on the writing side is the same as that shown in FIG. In the algorithm on the reading side, threshold 1 and threshold 2 are set to 1/2 field. In the unreadable area 2, the condition of WP-RP <threshold 2 is “true” (see S501 and S502 in FIG. 5). Therefore, the Read scheduled field is provisionally set to the N-2 field (see S503 in FIG. 5). In FIG. 9, the read start time of the Read schedule field (N-2 field) is shown at time t91.

  Since the write completion flag of the N-2 field temporarily set as the Read scheduled field is “true”, it is set as the Read scheduled field after the determination of S513 and S515 in FIG. 5 and can be read (FIG. 5). 5 S516).

  In a non-standard signal such as a progressive signal, even if the reference phase such as blanking is shifted, the field / frame period is synchronized with the read standard signal. For this reason, once a non-standard signal such as a progressive signal is in a state where the phase relationship is in place and reading is started from the readable area 2, the non-standard signal is not read from the unreadable area 2 thereafter.

  FIG. 10 shows a memory when writing is stopped (WP is stopped) in a state where the non-standard signal (a) input from the selector 103 to the memory control unit 104 is a progressive signal output from the camera signal processing unit 101. 4 is a timing chart showing an example of the operation and output of the control means 104.

  The algorithm on the writing side is the same as that shown in FIG. In the algorithm on the reading side, threshold 1 and threshold 2 are set to 1/2 field. If writing stops for some reason at time t101, the WP stops. At time t101, normal reading is performed, but at time t102, since the condition of WP-RP <threshold 2 is “true” (see S501 and S502 in FIG. 5), the Read scheduled field is the N-2 field. Is temporarily set (see S503 in FIG. 5).

  Since the write completion flag is “true” in the N-2 field temporarily set as the Read scheduled field (see S513 and S515 in FIG. 5), it is set as the Read scheduled field and can be read (see S516 in FIG. 5). ). In this way, standard signal output is possible even when the input signal is interrupted.

  By performing the processing as shown in FIGS. 6 to 10, in any case, format conversion from a progressive signal to an interlace signal is possible, and a standard signal output is always possible.

  FIG. 11 is a timing chart illustrating an example of the operation of the memory control unit 104 in a state where the non-standard signal input from the selector 103 to the memory control unit 104 is an interlace signal of the camera signal processing unit 101. Since the non-standard signal (a) is an interlace signal, one field of video data is written in the memory 105 using one field time. The field memory being written is indicated by diagonal lines, and the write completion flag is “false” in the field memory in this state. At the time of reading, an interlace signal which is a standard signal is read. The time required for reading is a time for reading video data of one field using one field time. The input signal has a field-unit time period that matches the standard signal synchronization to be read, but is out of phase with blanking inserted. Therefore, there are fields and phase relationships that can be read and fields and phase relationships that cannot be read depending on the phases of WP and RP and the state of the write completion flag.

  FIG. 11 shows a case where reading is started from the field memory # 2. The readable area 3 is an area where a certain phase difference can be secured for both WP and RP. In the unreadable area 3, the write completion flag of the target field is “false”, and a new Read scheduled field needs to be set. The unreadable area 4 is an area where neither WP nor RP can secure a certain phase difference.

  In FIG. 12, the non-standard signal (a) is an interlace signal of the camera signal processing unit 101, and the operation and output of the memory control unit 104 when the RP starts reading from the readable region 3 and the unreadable region 3, 4. It is a timing chart which shows an example. In the algorithm on the writing side, the write completion flag becomes “true” at the same time as the writing is completed, so that reading is possible. At the same time, the format flag is set to “interlace”.

  First, a reading process in a phase state of Rad and Wad that is in a reading state from the readable area 3 will be described.

  In the algorithm on the reading side, the threshold value 1 is set in advance to a predetermined value (corresponding to several percent to several tens percent of the number of lines). In addition, first, it is determined that the input format is interlaced (see S501 in FIG. 5). In the readable area 3, the condition of RP-WP <threshold 1 is “false” (see S504 in FIG. 5), and the pseudo field processing is not performed in the initial state. When this is detected (see S505 in FIG. 5), the Read scheduled field is provisionally set to the N field (see S506 in FIG. 5). Since the Write completion flag of the N field temporarily set as the Read scheduled field is “true” (see S513, S515, and S516 in FIG. 5), the memory control means output (B) is obtained as a result.

  In the phase state of Rad and Wad, which is in a read state from the unreadable region 3, the write completion flag of the target field is “false” in any field temporarily set as the Read scheduled field (see FIG. 5 S513 and S515). Therefore, the N-1 field is provisionally set as a new Read scheduled field by the process of S516 of FIG. 5 (see S517 of FIG. 5). As a result, the read start time is time t121, and the memory control means output (A) is obtained.

  In the phase state of Rad and Wad that is in a state of reading from the unreadable region 4, the condition of RP-WP <threshold 1 is “true” (see S504 in FIG. 5), and the Read scheduled field is temporarily set in the N + 1 field. (See S510 and S511 in FIG. 5). Since the Write completion flag of the N + 1 field temporarily set as the Read scheduled field is “true” (see S513 and S515 in FIG. 5), the process of S516 in FIG. 5 is performed. As a result, the processing read start time is time t122, and the memory control means output (C) is obtained.

  Since the interlace signal is a signal whose field / frame period is synchronized but the reference phase is shifted, such as blanking, once the phase relationship becomes the readable area 3, the reading from the unreadable area is performed thereafter. There is nothing to do. By performing the processing shown in FIGS. 11 and 12, a standard signal can always be output in any case.

  FIG. 13 is a timing chart showing an example of the operation and output of the memory control unit 104 when the non-standard signal (a) is alternately output from the progressive signal and the interlace signal of the camera signal processing unit 101.

  In the algorithm on the writing side, the write completion flag becomes “true” at the same time as the writing is completed, and reading is possible. At the same time, the format flag is set to “progressive” or “interlace” according to the input format (see S410 in FIG. 4).

  In the algorithm on the reading side, various processes shown in FIG. 5 are executed after the threshold values 1 and 2 are changed according to the format flag. As shown in FIGS. 6 to 12, once the phase relationship between Wad and Rad is once drawn into a predetermined phase relationship (readable area), as shown in FIG. 13, the progressive signal and the interlace signal are alternately displayed. Even if it is input, the output of the standard signal (b) is not disturbed.

  FIG. 14 is a timing chart showing an example of the operation of the memory control unit 104 when the non-standard signal (a) is the interlace signal of the analog input signal processing unit 102. In the algorithm on the writing side, before starting the writing of the N field, the writing completion flag of the target field is set to “false” and the writing is started (see S401 and S402 in FIG. 4).

  At the time of writing, in the case of an analog input signal, the field period of the input signal may be suddenly disturbed, for example, by changing the channel of the VTR output. Therefore, the continuity and periodicity of the write synchronization signal are always monitored during writing, and it is monitored whether or not an unexpected field head is detected (see S403 in FIG. 4).

  If an unexpected field head is detected, it is determined whether the field is the first field or the second field (see S404 in FIG. 4). When the unexpected field is determined to be the second field, the second field (adjacent second field) of the next frame (adjacent frame) that is temporally ahead of the frame in which the unexpected field is located is temporally related. In the second field (adjacent second field) of the adjacent frame at the rear, the Wad is set at the head position of the adjacent second field that is distant from the Rad at the time of detection and writing is continued. (Refer to S405 and S407 in FIG. 4).

  On the other hand, when the unexpected field is determined to be the first field, the first field of the adjacent frame that is temporally ahead of the unexpected field (adjacent first field) and the first frame of the adjacent frame that is temporally rearward. Among 1 field (adjacent first field), Wad is set at the head position of the adjacent first field that is distant from the Rad at the time of detection and writing is continued (S406, S408 in FIG. 4). reference).

  If an unexpected field head is not detected and the N field write processing reaches the end of the field (see S409 in FIG. 4), the write completion flag is set to “true” and the format flag is set to “interlace”. To complete the writing process (see S410 and S411 in FIG. 4). After performing the above writing step, the process proceeds to the writing step of the next field N + 1.

  In the algorithm on the reading side, as described above, the threshold value 1 is set to a predetermined value (corresponding to several% to several tens% of the number of lines). Therefore, in the phase state where reading starts from the readable area 5, the condition of RP-WP <threshold 1 is “false”. (See S504 in FIG. 5).

  In this case, the Read scheduled field is provisionally set to the N field, the N−1 field, and the N + 1 field according to the state of the pseudo field and the state of the skip flag (see S505, S507, and S509 in FIG. 5).

  On the other hand, in the phase state in which reading is started from the non-readable area 5, the write completion flag of the target field is “false” in any field set as the Read scheduled field. Therefore, the N-1 field is set as a new Read schedule field (see S513, S515, and S517 in FIG. 5).

  On the other hand, in the phase state in which reading is started from the unreadable region 6, the condition of RP-WP <threshold 1 is “true” (see S504 in FIG. 5). Therefore, the Read scheduled field is temporarily set to the N + 1 field, and the skip flag is set to “fwd” (see S510 and S511 in FIG. 5). The temporarily set Read reservation field determines (this setting) a field (Wad) in which Read is actually performed based on the determination of the Write completion flag (S513 and S515 in FIG. 5) (see S516 and S517 in FIG. 5). .

  FIG. 15 is a timing chart showing an example of the operation and output of the memory control means 104. In FIG. 15, the non-standard signal (a) is the interlace signal of the analog input signal processing means 102, and the cycle of the input signal (frame rate, which corresponds to the write cycle) is the read cycle (frame rate of the read signal). The processing in the case of longer than is shown. In this case, Wad is overtaken by Rad during the reading process.

  The algorithm on the writing side is the same as that shown in FIG. In the algorithm on the reading side, the threshold value 1 is set to a predetermined value (corresponding to several percent to several tens percent of the number of lines).

  At time t151, the determination of the Write completion flag in the Read scheduled field becomes “false” (see S515 in FIG. 5). Therefore, the N-1 field is temporarily set and read as a new Read scheduled field, and at the same time, the skip flag is set to “bak” (see S517 in FIG. 5). In such a case, since the write completion flag of the newly scheduled read scheduled field is “true”, the field is set as a scheduled read field and can be read. Since the read video is subjected to pseudo field processing, a pseudo field processing flag is set (see S516 in FIG. 5).

  At time t152, since the pseudo field processing is performed twice or more continuously (see S505 in FIG. 5), the N-1 field is provisionally set based on the skip flag as the Read scheduled field (S50 in FIG. 5). reference). Since the write completion flag of the temporarily set Read scheduled field is “true”, the N−1 field temporarily set as the Read scheduled field is set as the Read scheduled field and can be read (S513 in FIG. 5). , S515, S516). In this way, the time axis correction function is realized when the period of the input signal is longer than that of reading (Wad is overtaken by Rad).

  In FIG. 16, the non-standard signal (a) is an interlace signal of the analog input signal processing means 102, and the operation and output of the memory control means 104 when the period of the input signal is shorter than the read (Wad catches up with Rad). It is a timing chart which shows an example. The algorithm on the writing side is the same as that shown in FIG.

  The algorithm on the reading side sets the threshold value 1 to a predetermined value (corresponding to several% to several tens% of the number of lines). Since RP-WP <threshold 1 is “true” at time t161, when this is detected (see S504 and S510 in FIG. 5), the Read scheduled field is provisionally set to the N + 1 field, and at the same time, the skip flag is set to “fwd”. (See S511 in FIG. 5).

  Since the write completion flag of the temporarily set Read scheduled field is “true”, when this is detected, the N + 1 field temporarily set as the Read scheduled field is set as the Read scheduled field and can be read out. At the same time, a pseudo field processing flag is set. At time t162, since the pseudo field processing is continued twice or more, the Read scheduled field is temporarily set to the N + 1 field based on the skip flag. Since the write completion flag of the temporarily set Read scheduled field is “true”, when this is detected, the N + 1 field temporarily set as the Read scheduled field is permanently set as the Read scheduled field and can be read ( (See S515 and S516 in FIG. 5). In this way, the time axis correction function is realized when the period of the input signal is shorter than the reading (Wad catches up with Rad).

  FIG. 17 is a timing chart showing an example of the operation and output of the memory control means 104 when the non-standard signal (a) is an interlace signal of the analog input signal processing means 102 and the input signal is interrupted. The algorithm on the writing side is the same as that shown in FIG.

  The algorithm on the reading side sets the threshold value 1 to a predetermined value (corresponding to several% to several tens% of the number of lines). At time t171, writing to the memory 105 is stopped and Wad does not change.

  At time t172, since the Write completion flag of the Read scheduled field is “false” (see S515 in FIG. 5), the Read scheduled field is newly temporarily set to N−1 (see S517 in FIG. 5). One field is subjected to pseudo field processing and output (see S513 and S516 in FIG. 5).

  Similarly, at the time t173, the write completion flag of the Read scheduled field temporarily set in the same manner is “false” (see S515 in FIG. 5), so the Read scheduled field is newly temporarily set to N−1 (see S517 in FIG. 5). , N-1 field is output without pseudo field processing (see S513 and S516 in FIG. 5).

  At time t174, since the write completion flag of the temporarily set Read scheduled field is “false” (see S515 in FIG. 5), the Read scheduled field is newly temporarily set to N−1 (see S517 in FIG. 5). The -1 field is subjected to pseudo field processing and output (see S513 and S516 in FIG. 5).

  In this way, even when the input signal (non-standard video signal) is interrupted, it is possible to output the video signal without interrupting the output of the standard signal (b).

  FIG. 18 shows a memory when the non-standard signal (a) is an interlace signal of the analog input signal processing means 102 and the field of the input signal changes from the middle of the 2a field to the 5a field which is discontinuous with respect to the 2a field. 4 is a timing chart showing an example of the operation and output of the control means 104. The algorithm on the writing side is the same as that shown in FIG.

  The algorithm on the reading side sets the threshold value 1 to a predetermined value (corresponding to several% to several tens% of the number of lines). At time t181, during the writing of the signal to the field, a signal that is not continuously continuous with the input signal so far is input (2a field → 5a field), so that the unexpected field head is detected. (See S403 in FIG. 4). The newly detected field head is the first field signal. Therefore, the first field (front adjacent first field) of the next frame (adjacent frame) that is temporally forward with respect to the frame in which the detected unexpected field is located, and the first frame of the adjacent frame that is temporally backward Writing is continued after skipping the Wad to the head position of the adjacent first field that is far in time from the Rad at the time of detection (time t181) among the one field (the first field adjacent to the rear). (S406 and S408 in FIG. 4).

  The details of the read algorithm in FIG. 18 are the same as those in FIG. 14, and the description of the read algorithm in FIG. 14 is referred to in the above description of the read algorithm.

  A read process after the above write change is performed at t181 will be described. Since the Write completion flag of the Read scheduled field is “false” at time t182 (see S513 and S515 in FIG. 5), the N-1 field is temporarily set as a new Read scheduled field, and the skip flag is set to “bak”. (Refer to S517 in FIG. 5). Since the Write completion flag of the provisionally set Read schedule field is “true”, the provisionally set Read schedule field is set as a Read schedule field and can be read. At the same time, a pseudo field processing flag is set (see S513, S515, and S516 in FIG. 5).

  At time t183, since the Write completion flag of the Read scheduled field is “false” (see S513 and S515 in FIG. 5), the N-1 field is temporarily set as a new Read scheduled field (see S517 in FIG. 5). Since the write completion flag of the newly scheduled read scheduled field is also “false” (see S513 and S515 in FIG. 5), the field one field before is provisionally set as the read scheduled field (see S517 in FIG. 5). ). Since the write completion flag of the temporarily set Read scheduled field is “true”, the temporary set Read scheduled field can be read by setting this as the Read scheduled field (S513 and S515 in FIG. 5), and pseudo field processing is performed. (See S516 in FIG. 5).

  At time t184, since the pseudo field processing continues twice or more (see S505 in FIG. 5), the Read scheduled field is temporarily set to the N-1 field based on the skip flag (see S506 in FIG. 5). . Then, as a result of the write completion flag of the temporarily set Read schedule field being “true” (see S514 and S515 in FIG. 5), the temporarily set Read schedule field becomes this setting and can be read (FIG. 5). (See S516).

  In this way, it is possible to output a video signal in which the standard signal (b) output is not disturbed even if the input signal is a periodically discontinuous input.

  FIG. 19 shows a memory when the non-standard signal (a) is an interlace signal of the analog input signal processing means 102 and the field of the input signal changes from the middle of the 3a field to the 5a field which is discontinuous with respect to the 3a field. 4 is a timing chart showing an example of the operation and output of the control means 104. The algorithm on the writing side is the same as the state shown in FIG.

  The algorithm on the reading side sets the threshold value 1 to a predetermined value (corresponding to several% to several tens% of the number of lines). At time t191, while a signal is being written to the field, a signal having no continuity with the input signal so far is periodically input (3a field → 5a field), so that the unexpected field head is detected. (See S403 in FIG. 4). Here, the newly detected field head is the signal of the first field, and writing is performed by skipping the Wad to the head of the adjacent first field farther in the front-rear direction as viewed from the Rad at time t191 (S406 in FIG. 4). , S408). The details of the read algorithm in FIG. 19 are the same as those in FIG. 14, and the description of the read algorithm in FIG. 14 is referred to in the above description of the read algorithm.

  In the example of FIG. 19, it is only necessary to skip Wad. In this way, it is possible to output a video signal in which the standard signal (b) output is not disturbed even if the input signal is a periodically discontinuous input.

  FIG. 20 shows a memory when the non-standard signal (a) is an interlace signal of the analog input signal processing means 102 and the field of the input signal changes from the middle of the 2a field to the 5b field which is discontinuous with respect to the 2a field. 4 is a timing chart showing an example of the operation and output of the control means 104. The algorithm on the writing side is the same as the state shown in FIG.

  The algorithm on the reading side sets the threshold value 1 to a predetermined value (corresponding to several% to several tens% of the number of lines). At time t201, during the writing of the signal to the field, a signal that is not continuously continuous with the input signal so far is input (2a field → 5b field), and the unexpected field head is detected. (See S403 in FIG. 4). Here, the newly detected field head is the signal of the second field. Therefore, the second field (front adjacent second field) of the next frame (adjacent frame) that is temporally forward with respect to the frame in which the detected unexpected field is located, and the second frame of the adjacent frame that is temporally rearward Writing is continued after skipping the Wad to the head position of the adjacent first field that is far in time from the Rad at the time of detection (time t201) of the two fields (the rear adjacent second field). (S405 and S407 in FIG. 4).

  The details of the read algorithm in FIG. 20 are the same as those in FIG. 14, and the description of the read algorithm in FIG. 14 is referred to in the above description of the read algorithm.

  A read process after the above write change is performed at t201 will be described. Since the Write completion flag of the Read scheduled field is “false” at time t202 (see S513 and S515 in FIG. 5), the N-1 field is temporarily set as a new Read scheduled field, and the skip flag is set to “bak”. (Refer to S517 in FIG. 5). Since the write completion flag of the provisionally set Read schedule field is “true”, the provisionally set Read schedule field is set as a Read schedule field and can be read. At the same time, a pseudo field processing flag is set (see S513, S515, and S516 in FIG. 5).

  At time t203, since the Write completion flag of the Read scheduled field is “false” (see S513 and S515 in FIG. 5), the N-1 field is temporarily set as a new Read scheduled field (see S517 in FIG. 5). Since the write completion flag of the newly scheduled Read scheduled field is “true” (see S513 and S515 in FIG. 5), the temporarily set Read scheduled field becomes this setting and can be read (FIG. 5). 5 S516).

  At time t204, since the Write completion flag of the Read scheduled field is “false” (see S513 and S515 in FIG. 5), the N−1 field is newly set as the Read scheduled field (see S517 in FIG. 5). Since the Write completion flag of the newly set Read scheduled field is also “false” (see S513 and S515 in FIG. 5), the field one field before in terms of time is temporarily set as the Read scheduled field (see FIG. 5). S517). Since the write completion flag of the temporarily set Read scheduled field is “true” (S513 and S515 in FIG. 5), the temporarily set Read scheduled field becomes this setting and can be read (see S516 in FIG. 5). ).

  In this way, it is possible to output a video signal in which the standard signal (b) output is not disturbed even if the input signal is a periodically discontinuous input.

  In FIG. 21, the non-standard signal (a) is an interlace signal of the analog input signal processing means 102, and the input signal field changes from the middle of the 3a field to the 5b field that is discontinuous with respect to the 3a field. 6 is a timing chart showing an example of the operation and output of the memory control means 104 of FIG. The algorithm on the writing side is the same as the state shown in FIG.

  The algorithm on the reading side sets the threshold value 1 to a predetermined value (corresponding to several% to several tens% of the number of lines). At time t211, during the writing of the signal to the field, a signal that is not continuously continuous with the input signal so far is input (3a field → 5a field), and the unexpected field head is detected. (See S403 in FIG. 4). Here, the newly detected field head is the signal of the second field. Therefore, the second field (front adjacent second field) of the next frame (adjacent frame) that is temporally forward from the Rad at time t211 and the second field (rear adjacent second) of the adjacent frame that is temporally rearward. Field)), and writing is performed by skipping Wad to the head of the adjacent second field located further away (S406 and S408 in FIG. 4).

  The details of the read algorithm in FIG. 21 are the same as those in FIG. 14, and the description of the read algorithm in FIG. 14 is referred to in the above description of the read algorithm.

  In the example of FIG. 21, it is only necessary to skip Wad. In this way, it is possible to output a video signal in which the standard signal (b) output is not disturbed even if the input signal is a periodically discontinuous input.

  FIG. 22 shows a memory when the non-standard signal (a) is an interlace signal of the analog input signal processing means 102 and the field of the input signal changes from the middle of the 2b field to the 5a field which is discontinuous with respect to the 2b field. 4 is a timing chart showing an example of the operation and output of the control means 104. The algorithm on the writing side is the same as the state shown in FIG.

  The algorithm on the reading side sets the threshold value 1 to a predetermined value (corresponding to several% to several tens% of the number of lines). At time t221, during the writing of the signal to the field, a signal that is not continuously continuous with the input signal so far is input (2b field → 5a field), and the unexpected field head is detected. (See S403 in FIG. 4). The newly detected field head is the first field signal. Therefore, the first field (front adjacent first field) of the next frame (adjacent frame) that is temporally forward with respect to the frame in which the detected unexpected field is located, and the first frame of the adjacent frame that is temporally backward Write is continued after skipping the Wad to the head position of the adjacent first field that is far in time from the Rad at the time of detection (time t221) of one field (the first field adjacent to the rear). (Refer to S406 and S408 in FIG. 4).

  The details of the read algorithm in FIG. 18 are the same as those in FIG. 14, and the description of the read algorithm in FIG. 14 is referred to in the above description of the read algorithm.

  A read process after the above write change is performed at t181 will be described. Since the Write completion flag of the Read scheduled field is “false” at time t222 (see S513 and S515 in FIG. 5), the N-1 field is newly set as the Read scheduled field, and the skip flag is temporarily set to “bak”. (Refer to S517 in FIG. 5). Since the Write completion flag of the temporarily set Read scheduled field is “true”, the temporarily set Read scheduled field becomes the actual setting and can be read. At the same time, a pseudo field processing flag is set. (See S513, S515, and S516 in FIG. 5).

  At time t223, since the Write completion flag of the Read scheduled field is “false” (see S513 and S515 in FIG. 5), the N-1 field is temporarily set as a new Read scheduled field (see S517 in FIG. 5). Since the write completion flag of the temporarily set Read schedule field is “true” (see S514 and S515 in FIG. 5), the temporarily set Read schedule field becomes this setting and can be read (S516 in FIG. 5). reference).

  At time t224, since the Write completion flag of the Read scheduled field is “false” (see S513 and S515 in FIG. 5), the N-1 field is newly set as the Read scheduled field (see S517 in FIG. 5). Since the write completion flag of the newly set Read scheduled field is also “false” (see S513 and S515 in FIG. 5), the field one field before in time is further temporarily set as the Read scheduled field (S517 in FIG. 5). reference). Since the write completion flag of the temporarily set Read scheduled field is “true”, the temporarily set Read scheduled field can be read with this setting (S513 and S515 in FIG. 5) while performing pseudo field processing. This is output (see S516 in FIG. 5).

  In this way, it is possible to output a video signal in which the standard signal (b) output is not disturbed even if the input signal is a periodically discontinuous input.

  FIG. 23 shows the memory control means when the non-standard signal (a) is the interlace signal of the analog input signal processing means 102 and the input signal field changes from the 3b field to the 5a field which is discontinuous with respect to the 3b field. 10 is a timing chart showing an example of operation and output of 104. The algorithm on the writing side is the same as the state shown in FIG.

  The algorithm on the reading side sets the threshold value 1 to a predetermined value (corresponding to several% to several tens% of the number of lines). At time t231, during the writing of the signal to the field, a signal that is not continuously continuous with the input signal so far is input (2b field → 5a field), and the unexpected field head is detected. (See S403 in FIG. 4). The newly detected field head is the first field signal. Therefore, the first field (front adjacent first field) of the next frame (adjacent frame) that is temporally forward with respect to the frame in which the detected unexpected field is located, and the first frame of the adjacent frame that is temporally backward Writing is continued after skipping the Wad to the head position of the adjacent first field that is distant from the Rad at the time of detection (time t231) among the one field (the first field adjacent to the rear). (S406 and S408 in FIG. 4). In the example of FIG. 23, Wad only needs to be skipped.

  In this way, it is possible to output a video signal in which the standard signal (b) output is not disturbed even if the input signal is a periodically discontinuous input.

  FIG. 24 shows the memory control means when the non-standard signal (a) is an interlace signal of the analog input signal processing means 102 and the field of the input signal is changed from the 2b field to the 5b field which is discontinuous with respect to the 2b field. 10 is a timing chart showing an example of operation and output of 104. The algorithm on the writing side is the same as the state shown in FIG.

  The algorithm on the reading side sets the threshold value 1 to a predetermined value (corresponding to several% to several tens% of the number of lines). At time t241, during the writing of the signal to the field, a signal that is not continuously continuous with the input signal so far is input (2b field → 5a field), and the unexpected field head is detected. (See S403 in FIG. 4). Here, the newly detected field head is the signal of the second field. Therefore, the second field (front adjacent second field) of the next frame (adjacent frame) that is temporally forward with respect to the frame in which the detected unexpected field is located, and the second frame of the adjacent frame that is temporally rearward Writing is continued after skipping the Wad to the head position of the adjacent second field that is far in time from the Rad at the time of detection (time t241) of the two fields (the second field adjacent to the rear). (S406 and S408 in FIG. 4).

  The details of the read algorithm in FIG. 18 are the same as those in FIG. 14, and the description of the read algorithm in FIG. 14 is referred to in the above description of the read algorithm.

  A read process after the above write change is performed at t241 will be described. At time t242, the Write completion flag of the Read scheduled field is “false” (see S513 and S515 in FIG. 5), so the N-1 field is temporarily set as a new Read scheduled field, and the skip flag is set to “bak”. (Refer to S517 in FIG. 5). Since the write completion flag of the temporarily set Read scheduled field is “true”, the temporarily set Read scheduled field becomes this setting and can be read. At the same time, a pseudo field processing flag is set (see S513, S515, and S516 in FIG. 5).

  At time t243, since the Write completion flag of the Read scheduled field is “false” (see S513 and S515 in FIG. 5), the N-1 field is newly set as the Read scheduled field (see S517 in FIG. 5). Since the Write completion flag of the newly set Read scheduled field is also “false” (see S513 and S515 in FIG. 5), the field one field before is temporarily set as the Read scheduled field (see S517 in FIG. 5). Since the write completion flag of the temporarily set Read scheduled field is “true”, the temporarily set Read scheduled field is set as a Read scheduled field and can be read (S513 and S515 in FIG. 5). The read scheduled field thus set is read and output while performing pseudo field processing (see S516 in FIG. 5).

  At time t244, since pseudo field processing is performed twice or more times consecutively (see S505 in FIG. 5), the N-1 field is provisionally set as a Read scheduled field based on the skip flag (S506 in FIG. 5). reference). Since the write completion flag of the temporarily set Read scheduled field is “true”, this is set as the Read scheduled field and can be read (see S513, S515, and S516 in FIG. 5). In this way, it is possible to output a video signal in which the standard signal (b) output is not disturbed even if the input signal is a periodically discontinuous input.

  FIG. 25 shows the memory control when the non-standard signal (a) is an interlace signal of the analog input signal processing means 102 and the input signal field changes from the 3b field to the 5b field which is discontinuous with respect to the 3b field. 6 is a timing chart showing an example of the operation and output of the means 104. The algorithm on the writing side is the same as the state shown in FIG.

  The algorithm on the reading side sets the threshold value 1 to a predetermined value (corresponding to several% to several tens% of the number of lines). At time t251, during the writing of the signal to the field, a signal that is not continuously continuous with the input signal so far is input (2b field → 5b field), and the unexpected field head is detected. (See S403 in FIG. 4). Here, the newly detected field head is the signal of the second field. Therefore, the second field (front adjacent second field) of the next frame (adjacent frame) that is temporally forward with respect to the frame in which the detected unexpected field is located, and the second frame of the adjacent frame that is temporally rearward Writing is continued after skipping the Wad to the head position of the adjacent second field that is far in time from the Rad at the time of detection (time t251) of the two fields (the rear adjacent second field). (S406 and S408 in FIG. 4).

  The details of the read algorithm in FIG. 18 are the same as those in FIG. 14, and the description of the read algorithm in FIG. 14 is referred to in the above description of the read algorithm.

  In the example of FIG. 25, Wad only needs to be skipped. In this way, it is possible to output a video signal in which the standard signal (b) output is not disturbed even if the input signal is a periodically discontinuous input.

  Further, when the signal input from the analog input signal processing means changes drastically and there is no video data effective to be output in the memory 105 (all Write completion flags are “false”) (S513 in FIG. 5). For example, the control unit 204 outputs a blue back or the like, and performs control not to output a distorted video signal (see S514 in FIG. 5).

  Furthermore, if the above-described write / read control of the present invention is performed, even if the input signal of the memory control means 104 is switched between the camera signal processing means 101 and the analog input signal processing means 102, the standard signal is similarly applied. It is possible to output without interruption.

  The format output by the camera signal processing unit 101 has been described as a progressive signal or an interlaced signal. However, the format is synchronized with the processing cycle (field cycle or frame cycle) required by the subsequent processing unit. It goes without saying that the present invention is effective if the signal has a format in which a reference phase such as blanking is shifted).

  Although the number of field memories has been described as four, it goes without saying that the present invention is effective even when the number of memories is four or more.

  Although the algorithm for controlling Wad and the algorithm for controlling Rad have been described with reference to FIGS. 4 and 5, the present invention is effective when implemented in the following method or apparatus. That is, if the present invention is implemented in a method or apparatus for converting a video signal that is synchronized with a processing cycle required by a subsequent processing means but is out of phase into a standard signal by a format conversion process using a memory, the present invention It becomes effective. Furthermore, a method and apparatus provided with a Wad control algorithm and a Rad control algorithm for converting a signal whose processing period and phase required by the processing means in the subsequent stage are shifted to a standard signal by time axis conversion processing using a memory The present invention is effective if implemented in the above.

  The algorithm for controlling a series of Wads and the algorithm for controlling Rad are performed by the memory control means 104. Of course, software processing is performed using a microprocessor or the like, and the memory control means 104 only arbitrates the processing timing. It does not matter if the configuration is

  The video signal conversion apparatus according to the present invention has a common function of, for example, converting a format from an interlace signal to a progressive signal and correcting a time axis of a non-standard signal such as a video signal reproduced by an analog video tape recorder to a standard signal. It can be realized by circuit configuration, simple memory control method, and can be applied to format conversion and time axis correction applications that require standard signals to be output without interruption even when input signals are interrupted or switched. .

The block diagram which shows one Embodiment of the video signal converter of this invention. The block diagram which shows the structural example of the memory control means of the video signal converter of this invention. The figure which shows the structural example of the parameter of the memory structure of the video signal converter of this invention, and the state which monitors a memory state. The flowchart which shows an example of the algorithm which controls Wad of this invention. The flowchart which shows an example of the algorithm which controls Rad of this invention. 6 is a timing chart showing an example of the operation of the memory control means of the present invention when the non-standard signal is a progressive signal of the camera signal processing means. 6 is a timing chart showing an example of the operation and output of the memory control means when the non-standard signal is a progressive signal of the camera signal processing means and the RP starts reading from the readable areas 1 and 2; 6 is a timing chart showing an example of the operation and output of the memory control means when the non-standard signal is a progressive signal of the camera signal processing means and RP starts reading from the unreadable area 1; 6 is a timing chart showing an example of the operation and output of the memory control means when the non-standard signal is a progressive signal of the camera signal processing means and the RP starts reading from the unreadable area 2; 6 is a timing chart showing an example of operation and output of the memory control means when the non-standard signal is a progressive signal of the camera signal processing means and writing is stopped (WP is stopped). 6 is a timing chart showing an example of the operation of the memory control means when the non-standard signal is an interlace signal of the camera signal processing means. 7 is a timing chart showing an example of the operation and output of the memory control means when the non-standard signal is an interlace signal of the camera signal processing means and RP starts reading from the readable area 3 and the unreadable area 3 and 4; 6 is a timing chart showing an example of the operation and output of the memory control means when a non-standard signal is alternately outputted from the progressive signal and interlace signal of the camera signal processing means. 6 is a timing chart showing an example of the operation of the memory control means when the non-standard signal is an interlace signal of the analog input signal processing means. 7 is a timing chart showing an example of the operation and output of the memory control means when the non-standard signal is an interlace signal of the analog input signal processing means and Wad is overtaken by Rad. 6 is a timing chart showing an example of the operation and output of the memory control means when the non-standard signal is an interlace signal of the analog input signal processing means and Wad catches up with Rad. 6 is a timing chart showing an example of the operation and output of the memory control means when the non-standard signal is an interlace signal of the analog input signal processing means and the input signal is interrupted. 9 is a timing chart showing a first example of operation and output of the memory control means when the non-standard signal is an interlace signal of the analog input signal processing means and the field of the input signal changes from a field to discontinuous a field. 9 is a timing chart showing a second example of the operation and output of the memory control means 104 when the non-standard signal is an interlace signal of the analog input signal processing means and the input signal field changes from a field to discontinuous a field. It is a timing chart showing a first example of operation and output of the memory control means when the non-standard signal is an interlace signal of the analog input signal processing means and the field of the input signal changes from the a field to the discontinuous b field. 9 is a timing chart showing a second example of the operation and output of the memory control means when the non-standard signal is an interlace signal of the analog input signal processing means and the field of the input signal changes from the a field to the discontinuous b field. 7 is a timing chart showing a first example of operation and output of the memory control means when the non-standard signal is an interlace signal of the analog input signal processing means and the field of the input signal changes from the b field to the discontinuous a field. 9 is a timing chart showing a second example of the operation and output of the memory control means when the non-standard signal is an interlace signal of the analog input signal processing means and the field of the input signal changes from the b field to the discontinuous a field. 6 is a timing chart showing a first example of the operation and output of the memory control means when the non-standard signal is an interlace signal of the analog input signal processing means and the field of the input signal changes from the b field to the discontinuous b field. 9 is a timing chart showing a second example of the operation and output of the memory control means when the non-standard signal is an interlace signal of the analog input signal processing means and the field of the input signal changes from the b field to the discontinuous b field.

Explanation of symbols

101 Camera Signal Processing Unit 102 Analog Input Signal Processing Unit 103 Selector 104 Memory Control Unit 105 Memory 201 Writing Synchronization Signal Detection Unit 202 Reading Synchronization Signal Detection Unit 203 W / R Pointer Control Unit 204 Protection Unit

Claims (4)

Means for supplying non-standard video signals;
Video signal storage means for storing the non-standard video signal supplied from the supply means with N (N is a positive integer of 4 or more) field regions;
The non-standard video signal is sequentially read out while being updated and stored in each field area of the video signal storage means, and the non-standard video signal is interlaced based on write address control and read address control for the video signal storage means. Memory control means for converting to an arbitrary standard video signal consisting of and outputting from the video signal storage means,
When the non-standard video signal is a progressive signal, the memory control means performs the time axis correction on the non-standard video signal so that the time axis of the standard video signal coincides with the interlace signal. When the non-standard video signal is an interlace signal, the non-standard video signal is subjected to time axis correction that matches the time axis with respect to the standard video signal. Convert to standard video signal,
A video signal converter characterized by the above. The video signal converter according to claim 1,
The memory control means includes
When writing the non-standard video signal, the field area to be written is prohibited from being read, the field signal of the non-standard video signal is written to the field area to be written, the read prohibition is canceled and the writing is completed after the writing is completed. Write control for storing video signal identification information for identifying the signal form (interlace / progressive) of the non-standard video signal in the video signal storage means,
At the time of reading the standard video signal, the read control is performed based on the signal form determination of the non-standard video signal being read and whether the field signal of the non-standard video signal is prohibited from being read, and the read field When the signals are in an unexpected order, the read address of the read field signal at that time out of the adjacent field areas adjacent to the field area being read in the video time and at the same field position as the field area A video signal converter characterized in that reading disturbance is minimized by setting an adjacent field area farther in video time as viewed from the viewpoint as a new field area to be written. In the video signal converter according to claim 2,
The memory control means, when the reading of each field signal of the standard video signal is completed, the start address of the field area located next in the video time of the read completion field area and the write address during writing of the current non-standard video signal Based on the phase difference information, the video signal identification information, the pseudo field processing information indicating the presence or absence of inter-line interpolation processing of the readout field signal, and the skip information indicating the readout order disorder of the readout field signal, Next, after temporarily setting a read scheduled field for reading a field signal, the temporarily set read scheduled field is set as a read scheduled field according to the writing completion state of the non-standard video signal for the field. Video signal converter. In the video signal processing device according to any one of claims 1 to 3,
A video signal conversion apparatus, further comprising: protection means for outputting a protected video signal as a standard signal when there is no non-standard video signal written in the video signal storage means.

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