JP3716917B2 - Video signal converter - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
  The present invention provides a video signal converter.SekiThe present invention relates to a frame synchronizer that converts an externally input video signal into a video signal synchronized with a reference synchronization signal.
[0002]
[Prior art]
In recent years, with the development of digital signal processing technology, apparatuses for recording and reproducing digital data obtained by highly efficient encoding video signals and the like have become widespread.
[0003]
In these devices, in order to record conventional analog data, standardization of analog data by a frame synchronizer or the like and transfer to an internal frame frequency are essential.
[0004]
However, although the above-mentioned frame synchronizers are introduced in a large number in television broadcasting stations, etc., they require a large amount of memory, and the control algorithm for preventing overwriting and overtaking of writing and reading operations to the memory is complicated and the circuit scale Because the cost is high, such as large, it was necessary to reduce the cost significantly in order to install it in a product for general use.
[0005]
Therefore, conventionally, a technique for simplifying a control algorithm for preventing overtaking and overtaking of a write operation and a read operation in a memory as disclosed in Japanese Patent Application Laid-Open No. 08-279992 has been proposed.
[0006]
FIG. 16 shows the configuration of a conventional frame synchronizer described in the above publication. In FIG. 16, 100 indicates the entire frame synchronizer, 101 is an analog video input interface, 102 is an analog-digital converter, 103 is a write clock timing generator, 104 is a select switch, 105 is a digital video input interface, 109 is a field memory, 110 is a phase locked loop circuit, 110A is a voltage controlled oscillator, 111 is a write memory controller, 112 is a read memory controller, 113 is a read clock timing generator, 114 is a phase locked loop circuit, 114A is a voltage controlled oscillator, Reference numeral 115 denotes an output interface.
[0007]
In this frame synchronizer 100, a two-digit binary number Y'Z 'for selecting the field memories 106 to 109 to be written is output from the write memory controller 111 based on the input video signal.
[0008]
A two-digit binary number YZ for selecting the field memories 106 to 109 to be read based on the reference video signal S108 is output from the read memory controller 112.
[0009]
Here, two-digit binary numbers [Y′Z ′] and [YZ] indicate the first frame when [Y ′] and [Y] are [0], and [Y ′] and [Y] [1] indicates the second frame, [Z '] and [Z] indicate [0] indicates an odd field (hereinafter referred to as odd field), and [Z'] and [Z] indicate [1] indicates an even field (hereinafter referred to as an even field).
[0010]
The fields [Y'Z '] and [YZ] are the field memory 106 when [00], the field memory 107 when [01], the field memory 108 when [10], and the [11]. Is set to select each of the field memories 109. The read memory controller 112 monitors the value of [Y'Z '], and when the same value as [YZ] is reached, that is, the same field memory is accessed simultaneously. When it is done, it is judged that the possibility of overtaking and overtaking of the write operation and the read operation has been detected, and the reading is shifted by one frame by stopping the change at the next change point of [Y], thereby preventing overtaking and overtaking. It is out. Incidentally, in this case, the video signal S110 output from the frame synchronizer is missing one frame of data from the input video signal (S100, S101, S102, S103) or the data of the same frame is output twice. Will be.
[0011]
[Problems to be solved by the invention]
However, in the above publication, it is described that at least two field memories are used. However, when two field memories are used, a state in which a write operation and a read operation to the same field memory are simultaneously performed easily occurs. As shown in FIG. 17 (a), when two field memories A and B are used, it always occurs depending on the phase difference between the external input synchronizing signal and the reference synchronizing signal, and means for preventing overtaking and overtaking. Or three field memories A, B, and C must be used as shown in FIG.
[0012]
Also, depending on the input source of the external input video signal, distorted video data may be output. Examples include field discontinuities due to playback input of analog VTRs that have been shot together, field discontinuities due to channel switching during input from the tuner, increase / decrease in the number of lines in a frame, mixing of different frame data, Examples include a continuation of one field due to a non-interlace signal input in a game machine or the like, a discontinuity due to a blank signal input and a discontinuity such as a sync signal phase after return. However, the technology described in the above publication does not consider this type of problem.
[0013]
The present invention has been made to solve the above-described problems, and provides a video signal conversion device capable of preventing overtaking and overtaking of write operation and read operation with a very simple configuration, and An object of the present invention is to provide a video signal converter that outputs a normal video signal even when the synchronization signal of the external input video signal is disturbed.
[0014]
[Means for Solving the Problems]
  In order to achieve the above object, the present invention has the following configuration.
  A first gist of the present invention is a video signal conversion device for generating a converted video signal synchronized with a reference synchronization signal inside the device after writing an input video signal inputted in synchronization with an external synchronization signal into a memory. A memory capable of storing at least two fields of the input video signal; writing means for writing one field of the input video signal into the memory in a write cycle period based on the external synchronization signal; and the reference synchronization signal Reading means for reading out one field of the input video signal from the memory as the converted video signal in a read cycle period based on the memory;InsideofFor two field pages, A page management means for managing a reference page as a basis for writing or reading to which field page, and the writing meansReference pageCan be written toWithin the writing cycle periodbookIncludedField page confirmationTimeWrite memory control means for controllingReference pageCan be read fromWithin the writing cycle periodReadingDefuField page confirmationTimeAnd a read memory control means for controlling the video signal conversion device.
  When the write field page is determined, it is set within a first invalid area period without the input video signal within the write cycle period, and when the read field page is determined, the converted video within the read cycle period is set. It is set within the second invalid area period where there is no signal.
  And saidFrom the time of external sync signal generationSaid bookIncludedField page confirmationFirst period to timeAnd saidRead from the generation of the reference sync signalField page confirmationSecond period until timeAnd a differentTime intervalIt is characterized by that.
[0015]
  According to the first aspect of the present invention,From the time of external sync signal generationSaid bookIncludedField page confirmationFirst period to timeWhenRead from the generation of the reference sync signalField page confirmationSecond period until timeDifferent fromTime intervalThus, overwriting and overtaking of the write operation and the read operation can be prevented even with a memory of at least two fields.
  That is, in the prior art, the write memory fixed position and the read memory fixed position are set almost simultaneously with the detection of the external synchronization signal and the reference synchronization signal, but in the present invention, their relative positions are further set.(time)By shifting, the gap period is overtaken and functions as a buffer period for preventing overtaking.
  Then, when the write field page is determined, it is set in a first invalid area period without the input video signal within the write cycle period, and when the read field page is determined, the write field page is determined within the read cycle period. By setting the period within the second invalid area period where there is no converted video signal, the above gist can be realized without adversely affecting the writing and reading of video data.
[0016]
  The second gist of the present invention is as follows:In the case where the page management means manages the field pages to be written and read to different field pages, the second period is set longer than the first period.The video signal converter according to the first aspect is characterized in that.
[0017]
  The third gist of the present invention is as follows:When the page management means manages the field pages to be written and read to the same field page, the first period is set longer than the second period.The video signal converter according to the first aspect is characterized in that.
[0018]
  In the second aspect, the writing field page determination time is set as the start time of the first invalid area period, and the read field page determination time is set as the end time of the second invalid area period. In this case, the write field page determination time is defined as the end of the first invalid area period, and the read field page determination time is defined as the start of the second invalid area period.Is desirable. According to the structure concerned,IncludedField page confirmationTimeAnd readDefuField page confirmationTimeThe amount of deviation can be maximized, and overtaking and overtaking can be prevented reliably.
  Furthermore, the invalid area is desirably a vertical blanking period.
[0019]
    The fourth gist of the present invention is:The start time of the first invalid area period is a start time of the write cycle period, and the start time of the second invalid area period is a start time of the read cycle period.The video signal converter according to any one of the first to third aspects is characterized in that.
[0021]
According to a fifth aspect of the present invention, the field page fixed position of the write memory and the field page fixed position of the read memory are changed according to the state of the input video signal. In the video signal converter described in the above. With this configuration, a more general-purpose device can be obtained.
[0022]
According to a sixth aspect of the present invention, the memory has at least four fields, that is, two frames, the reference page in the page management means and the page in the write / read memory have one frame unit, and the field of the input video signal A field discriminating unit for discriminating and a detecting unit for detecting a field discontinuity of the input video signal based on a discrimination result of the field discriminating unit, and when the detecting unit detects a field discontinuity, The video signal conversion apparatus according to any one of the first to fifth aspects, wherein the page management means holds the frame page that is being written to and read from the memory.
[0023]
In addition, it is desirable to be able to switch whether or not to hold the frame page written and read by the page management means when the detection means detects a field discontinuity.
That is, when an analog VTR video signal with poor recording state is input, field discontinuities are expected to occur frequently due to field misidentification or tape scratches. Since it frequently occurs, it is convenient to make it switchable so that reference page retention due to field discontinuity can be turned ON / OFF as necessary.
[0024]
According to a seventh aspect of the present invention, there is provided an interlace discriminating unit that discriminates whether the input video signal is interlaced or non-interlaced, and a field allocating unit that pseudo-changes a field, and the interlace discriminating unit performs the input video The video signal conversion apparatus according to any one of the first to fifth aspects, wherein when the signal is determined to be non-interlaced, the field is changed in a pseudo manner by the field changing unit. With such a configuration, even when switching between interlaced and non-interlaced, normal video can be output by changing fields in a pseudo manner.
[0025]
The eighth aspect of the present invention is to hold the frame page in which the page management means writes and reads data in the memory when switching from the interlace mode to the non-interlace mode or from the non-interlace mode to the interlace mode. The video signal converter according to any one of Items 1 to 5 is characterized in that:
It is desirable that the threshold levels for switching from the interlace mode to the non-interlace mode and from the non-interlace mode to the interlace mode are variable.
[0026]
According to a ninth aspect of the present invention, there is provided line number detection means for detecting the number of lines in one frame, and when the line number detection means detects a predetermined variation in the number of lines, the page management means stores memory. The video signal converter according to any one of Items 1 to 5, wherein a frame page in which writing and reading are performed is held.
[0027]
According to a tenth aspect of the present invention, there is provided blank detecting means for detecting a blank period of the input video signal and mask means for forcibly muting the input video signal, and the blank detecting means for blanking the input video signal. The video signal converter according to any one of Items 1 to 9, wherein a mute signal is output by the mask means when a period is detected.
In addition, when the blank detection unit detects a blank period of the input video signal, it is desirable to be able to switch whether or not the video signal is forcibly muted by the mask unit.
Further, it is desirable to stop access to the memory during a period in which the input video signal is forcibly muted. Thereby, power consumption can be reduced.
[0028]
According to the sixth to tenth aspects of the present invention, the field discontinuity of the input video signal, the switching between the interlace mode and the non-interlace mode, the number of lines in one frame fluctuates, and the input video signal has a blank period. Even when there is a disturbance in the input video signal, normal video data can be output by holding the frame page in which the page management means writes and reads data in the memory.
[0029]
An eleventh aspect of the present invention resides in the video signal conversion apparatus according to any one of the first to tenth aspects, wherein the memory is shared by the 525/60 system and the 625/50 system. With such a configuration, both systems can be shared and versatility is enhanced.
In the 525/60 system, it is desirable to share the memory with the memory for the three-dimensional YC separation circuit. Such a configuration has an effect of reducing the number of parts.
When the frame page being read from the memory is held by the page management means, it is not an odd / even field output, which is a frame output, but an odd / even field output or even / even field output. be able to.
Further, when reading from the memory, the odd / even field output, odd / odd field output, and even / even field output can be switched.
[0030]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
First, the overtaking and overtaking of the write operation and the read operation when using a memory for two fields (two pages of field pages A and B) will be described with reference to FIGS.
1 to 4 show that writing to the field page A is performed during the period A of the writing memory, and writing to the field page B is performed during the period B. Similarly, the reading memory indicates that reading from the field page A is performed during the period A, and reading from the field page B is performed during the period B.
[0031]
  Each field unit of video data to be written to and read from the field page ATheA0, A1, A2,... In time series order, each field unit of video data to be written to and read from the field page BTheIt is shown as B0, B1, B2,.
[0032]
1 and 2 show that (i) reading is delayed by one field to two fields with respect to writing, that is, the reading memory is set opposite to the writing memory, and (ii) The timing chart when the write-side cycle PWa (T1 to T2) is shorter than the read-side cycle PRa (T3 to T4) is shown.
[0033]
In FIGS. 1 and 2, the write-side period PWa is shorter than the read-side period PRa (PWa <PRa), so that the possibility of overtaking and overtaking occurs.
In the drawing, the read memory is set to the field page B because the write memory is the field page A after the reading end (T3) of the output video data A0 from the field page A on the reading side. At the time T1 immediately after that, the writing of the input video data A1 to the field page A is completed on the writing side, and the write memory is set to the field page B. The reading operation is performed simultaneously.
[0034]
Then, while the reading side is reading data B0 from the field page B, the writing side similarly writes data B1 to the field page B, and writing the data B1 to the field page B is the data B0. When catching up with reading, overtaking and overtaking occur.
[0035]
In FIG. 1, since the writing of the data B1 cannot catch up by the time T4 when the reading of the data B0 is completed, the read data B0 is normally output.
[0036]
However, in FIG. 2, since the writing of the data B1 catches up before the reading time T4 of the data B0 (T1 ′), the field page B is overwritten with the data B1 from T1 ′ to T2, so that the read data B0 is not output normally.
[0037]
FIG. 3 and FIG. 4 are timing charts when the reading is set to be delayed by 0 field to 1 field with respect to the writing, that is, the reading memory is set to be the same as the writing memory.
[0038]
In FIGS. 3 and 4, since the write-side cycle PWb (T1 to T2) is longer than the read-side cycle PRb (T3 to T4), the possibility of overtaking and overtaking occurs.
[0039]
3 and 4, the write memory is set to B after the write to the field page A is completed (T1). At time T3 immediately after that, reading from the field page A is completed on the reading side, and the writing memory is the field page B, so that the reading memory is set to the field page B. Therefore, a write operation and a read operation are simultaneously performed on the field page B which is the same memory area. Then, when data B1 is being written on the writing side, data B1 is read on the reading side, and when the reading catches up with writing, overtaking and overtaking occur.
[0040]
In FIG. 3, since the reading of data B1 (T4 at the end of reading) cannot catch up by the end of writing of data B1 (T2), read data B1 is normally output.
[0041]
However, in FIG. 4, the data B1 read (T4 at the end of reading) catches up (T3 ') before the data B1 write end time T2, and the read is overtaken. Since the updated data B0 (data described in the field page B before the data B1 is written) is output as output video data, the read data B1 is not normally output. With the mechanism described above, overwriting and overtaking of the write operation and the read operation occur.
[0042]
Although not shown, when the write-side write cycle PWa is longer than the read-side read cycle PRa when the read is set to be delayed by 1 to 2 fields with respect to the write as shown in FIGS. In this case, since the data in the same field is output twice (hereinafter referred to as “reading twice”), the overwriting and overtaking of the writing operation and the reading operation do not occur.
[0043]
Similarly, when the writing cycle PWb on the writing side is shorter than the reading cycle PRb on the reading side when the reading is set to be delayed by 0 field to 1 field with respect to the writing as shown in FIGS. Therefore, the overwriting and overtaking of the write operation and the read operation do not occur due to the occurrence of missing data (hereinafter referred to as “drop”).
[0044]
Next, a signal conversion apparatus according to this embodiment using a memory for two fields will be described.
In the present embodiment, the first focus was on the invalid area period IP (vertical blanking period in the case of a video signal) included in the video data shown in FIGS. Since there is no video data in the invalid area period IP and access to the memory does not occur, there is no problem even if it is different from the write or read memory area during the valid period during this period.
[0045]
Therefore, in the present embodiment, the invalid region period IP is used to make the timing position for determining the write memory and the timing position for determining the read memory different in each field period on the writing side and reading side. Thus, by changing the length of the period from each memory determined position to the actual writing and reading end position, the overwriting and overtaking operations of the writing operation and the reading operation are suppressed.
[0046]
5 and 6 are examples of timing charts for writing and reading video data in the video signal conversion apparatus according to the present embodiment. FIG. 5 shows a case where the reading of the output video data is set to be delayed by one field to two fields with respect to the writing of the input video data. FIG. 6 shows that the reading of the output video data is 0 with respect to the writing of the input video data. This is a case where it is set to be delayed by 1 field.
[0047]
In FIG. 5 and FIG. 6, since the reference page = the write memory page, the reference page is omitted. D1 is a timing position for determining the write memory (hereinafter abbreviated as “write memory field page determination position”), and D2 is a timing position for determining the read memory (hereinafter referred to as “read memory field page determination position”). (Abbreviated as “position”).
[0048]
In FIG. 5, the field page fixed position D1 of the write memory is set at the beginning of the vertical blanking period which is the invalid area period IP of the input video data, and the field page fixed position D2 of the read memory is set to the vertical sweep of the output video data. A timing chart when set at the end of the line period IP is shown.
[0049]
In FIG. 5, the write cycle PWc (between T1 and T2) on the basis of the input vertical synchronization signal IS is the read cycle PRc (between T3 and T4) on the basis of the reference vertical synchronization signal RS. Because it is shorter, there is a possibility of overtaking and overtaking.
[0050]
In FIG. 5, after the reading end (T3) of the data A0 from the field page A on the reading side, the write memory at the field page fixed position D2 (T5) of the read memory is the field page A. Set to page B (FIG. 5 shows the case where reading is set to be delayed by 1 to 2 fields with respect to writing).
[0051]
At time T1 immediately after the read memory is set in the field page B, writing of the data A1 is completed on the writing side, and the write memory is set in the field page B by the field page fixed position D1 (T1) of the write memory. Therefore, the write operation and the read operation are performed on the field page B which is the same memory area.
[0052]
When data B0 is being read on the reading side, data B1 is also written on the writing side. If the writing catches up with reading, overtaking and overtaking occur.
[0053]
  However, on the reading side, the actual reading period from the field page fixed position D2 (T5) of the reading memory in which the reading memory is set to the field page B to the end of the reading cycle T4 (when the next reference vertical synchronization signal RS is generated) While PR is only the length of the effective area period B0 of the output video data, the write memory is written from the field page fixed position D1 (T1) of the write memory set to the field page B on the writing side. Write cycle period PW until cycle end T2 (when the next input vertical synchronization signal is generated)c (The length of the vertical blanking period IP + the effective area period B1), and the length of the vertical blanking period IP is a safety margin. In FIG. 5, the write data B1 is read by the end of reading data B0 (T4). Since the writing cannot catch up, the read data B0 is normally output.
[0054]
After the end of reading of data B0 (T4), writing of data B1 is completed on the writing side (T2), and the write memory is set to the field page A by the field page fixed position D1 of the write memory. Thereafter, since the write memory at the field page fixed position D2 (T6) of the read memory for determining the read memory is the field page A, the read memory is set again to the field page B and the data B1 is read. Is called. Therefore, overtaking and overtaking are avoided by dropping the data A1.
[0055]
In FIG. 6, the field page fixed position D1 of the write memory is set at the end of the vertical blanking period IP which is an invalid area of the input video data, and the field page fixed position D2 of the read memory is set to the vertical sweep of the output video data. The timing chart in the case of setting to the beginning of period IP is shown.
[0056]
In FIG. 6, the write cycle (between T1 and T2) defined by the input vertical synchronization signal IS on the write side is longer than the read cycle (between T3 and T4) defined by the reference vertical synchronization signal RS on the read side. The possibility of overtaking and overtaking occurs.
[0057]
In FIG. 6, the writing of the data A1 to the field page A is completed on the writing side (T1), and the writing memory is stored at the field page fixed position D1 (T5) of the writing memory after the vertical blanking period IP has elapsed. Is set in the field page B. Then, at time T3 immediately after that, reading of data A1 is completed on the reading side.
[0058]
Since the write memory at the time of the field page fixed position D2 (T3) of the read memory is the field page B and the read memory is also set to the field page B, the write operation is performed on the field page B which is the same memory area. A read operation is performed. If the reading catches up with the writing while the writing side is writing the data B1, overtaking and overtaking occur.
[0059]
However, on the writing side, the period (D1 (T5) to T2) from when the writing memory is set to the field page B to the end of writing is only the length of the effective area period B1 of the input video data. On the other hand, on the reading side, the period (D2 (T3) to T4) from when the reading memory is set to the field page B to the end of reading is the length PR of (vertical blanking period IP + effective area period B1). The length of the blanking period IP is a safety margin, and in FIG. 6, since the data B1 cannot be read before the data B1 is written, the read data B1 is normally output.
[0060]
  Thereafter, reading of the data B1 is completed on the reading side (T4), Since the write memory at the time when the field page of the read memory is determined by the field page determined position D2 (T4) of the read memory is still the field page B, the read memory is set again to the field page B and the data Since B1 is read, overtaking and overtaking are avoided by reading data B1 twice.
[0061]
For example, if a system of 525 scanning lines and 60 fields per second is applied to FIG. 1, the effective area is 240 lines, the vertical blanking period is 23 lines for the odd field, and the even field is 22 lines. Therefore, the overtaking and overtaking margins in the case of FIG. 5 are calculated as shown in (Equation 1) below, assuming that 22 lines with a smaller vertical blanking period are used.
240 / (240 + 22) * 100 = 91.60 (Formula 1)
Therefore, no overtaking or overtaking occurs even if the writing cycle is shortened to about 91.6%.
[0062]
Similarly, the overtaking and overtaking margins in the case of FIG. 6 are calculated as follows (Formula 2).
(240 + 22) /240*100=109.16 (Formula 2)
Therefore, no overtaking or overtaking occurs even if the writing period is increased to about 109.2%.
[0063]
However, it is necessary to be careful because the vertical blanking period may include data such as teletext data of about 9 lines.
[0064]
For example, in a system with 525 scanning lines and 60 fields per second, if text broadcast data is included in the 9 lines immediately before the effective area of the video data, the overtaking and overtaking margins in FIGS. It is calculated as (Equation 3) and (Equation 4).
249 / (249 + 13) * 100 = 95.03 (Formula 3)
(249 + 13) /249*100=105.22 (Formula 4)
[0065]
Therefore, in FIG. 5, even if the writing cycle is shortened to about 95%, neither overtaking nor overtaking occurs. Similarly, in FIG. 6, no overtaking or overtaking occurs even when the writing period is increased to about 105.2%. In both FIG. 5 and FIG. 6, the above-described overtaking and overtaking margins are sufficient for normal input video.
[0066]
However, when the input video is an analog VTR special playback video, particularly in the case of a high-speed search video, there is a possibility that the overtaking and overtaking margins may be exceeded. However, in the case of a search or the like, the teletext data cannot be reproduced almost properly. In that case, there is no problem even if the valid period is changed to 240 lines.
[0067]
Accordingly, when the input video is in the normal state, the effective period is set to 249 lines, the field page fixed position D1 of the write memory and the field page fixed position D2 of the read memory are set, and the input video is the search video of the analog VTR. By changing the set values of the field page fixed position D1 of the write memory and the field page fixed position D2 of the read memory with an effective period of 240 lines, a sufficient overtaking and overtaking margin can be obtained.
[0068]
Next, the case where the writing cycle and the reading cycle are constantly different will be described with reference to FIGS.
7 (a) and 7 (b) are set so that the reading of the output video data is delayed by one field to two fields with respect to the writing of the input video data, and the field page of the write memory as in FIG. The fixed position D1 is set at the beginning of the vertical blanking period IP, and the field page fixed position D2 of the read memory is set at the end of the vertical blanking period IP.
[0069]
8 (a) and 8 (b) are set so that the reading of the output video data is delayed by 0 field to 1 field with respect to the writing of the input video data, and the field page of the write memory as in FIG. The final position D1 is set at the end of the vertical blanking period IP, and the field page final position 2 of the read memory is set at the beginning of the vertical blanking period IP.
[0070]
7A and 8A show a case where the write cycle is constantly shorter than the read cycle, and the field page fixed position D1 of the write memory is compared with the field page fixed position D2 of the read memory. 7 (b) and 8 (b) are cases where the write cycle is constantly longer than the read cycle, and the field page fixed position D1 of the write memory is the field page fixed of the read memory. This is a case where the traveling speed with respect to the position D2 is slow.
[0071]
First, in FIG. 7A, the speed at which the field page fixed position D1 of the write memory advances with respect to the field page fixed position D2 of the read memory is high, and writing is performed when writing data A3 and reading data A2. The field page fixed position D1 of the memory approaches until just before overtaking the field page fixed position D2 of the read memory (T71), but the overtaking margin RP1 by the field page fixed position D1 of the write memory and the field page fixed position D2 of the read memory Therefore, no overtaking or overtaking occurs.
[0072]
Thereafter, the writing of the data B3 is started at the field page fixed position D1 of the write memory (T72), and the subsequent field page fixed position D2 of the read memory is overtaken by the field page fixed position D1 of the write memory. Since the data B3 of B is overwritten before the reading is executed, the reading of the data A3 is started at the field page final position D2 (T73) of the reading memory, and the drop of the data B2 is started. appear.
[0073]
In FIG. 7 (b), the speed at which the field page fixed position D1 of the write memory advances with respect to the field page fixed position D2 of the read memory is slow, and when the data A2 is written and the data B1 is read, the write memory The field page fixed position D1 approaches until just before the field page fixed position D2 of the read memory is overtaken (T74), but since the write memory is the memory A and the read memory is the memory B, no overtaking or overtaking occurs.
[0074]
Thereafter, at the field page fixed position D2 (T75) of the read memory that has overtaken the field page fixed position D1 of the write memory, the read is set to be delayed by one field to two fields with respect to the write. Two readings occur. Thereafter, writing of the data B2 is started at the field page fixed position D1 (T76) of the writing memory, but since the writing cycle is longer, neither overtaking nor overtaking occurs.
[0075]
In FIG. 8A, the speed at which the field page fixed position D1 of the write memory advances with respect to the field page fixed position D2 of the read memory is fast, and when the data B1 is written and when the data A1 is read, the write memory Although the field page fixed position D1 approaches until just before overtaking the field page fixed position D2 of the read memory (T81), the write memory is A and the read memory is B, so no overtaking or overtaking occurs.
[0076]
Thereafter, the writing of the data A2 is started by the field page fixed position D1 (T82) of the write memory, and then overtaken by the field page fixed position D1 of the write memory. In FIG. 8A, since the reading is set to be delayed by 0 field to 1 field with respect to the writing, the reading of the data A2 is started at the field page fixed position D2 (T83) of the reading memory, and the data B1 Drop occurs. Data A2 is written and data A2 is read at the same time. However, since the writing cycle is shorter, neither overtaking nor overtaking occurs. Similarly, data A4 is dropped after data B3 is read (T84).
[0077]
In FIG. 8 (b), the speed at which the field page fixed position D1 of the write memory advances with respect to the field page fixed position D2 of the read memory is slow, and when the data A3 is written and when the data A3 is read, the write memory The field page determined position D1 approaches until immediately before the field page determined position D2 of the read memory is overtaken (T85), but due to the overtaking margin IP2 by the field page determined position D1 of the write memory and the field page determined position D2 of the read memory. No overtaking or overtaking occurs.
[0078]
Thereafter, the data A3 is read twice by the field page fixed position D2 of the read memory that has overtaken the field page fixed position D1 of the write memory (T86). Thereafter, writing of the data B3 is started at the field page fixed position D1 (T87) of the write memory. However, since the write memory is B and the read memory is A, no overtaking or overtaking occurs.
[0079]
As described above, according to the present embodiment, no overtaking or overtaking occurs even when the writing cycle and the reading cycle are constantly different.
[0080]
Next, the configuration of the video signal conversion apparatus according to the present embodiment will be described with reference to the block diagram shown in FIG.
In FIG. 9, 10 shows the whole frame synchronizer to which the video signal converter is applied, 11 is an analog video input interface (hereinafter abbreviated as “AI / F”), and 12 is an analog-digital converter (hereinafter referred to as “AI / F”). (Abbreviated as “A / D”), 13 is a write clock timing generator (hereinafter abbreviated as “WCTG”), 14 is a select switch, and 15 is a digital video input interface (hereinafter abbreviated as “DI / F”). ), 16 is a memory, 17 is a phase-locked loop circuit (hereinafter abbreviated as “PLL”), 17A is a voltage controlled oscillator (hereinafter abbreviated as “VCO”), 18 is a write memory controller, and 19 is a read memory controller. , 20 is a read clock timing generator (hereinafter abbreviated as “RCTG”), 21 PLL, 21A are VCO, 22 is mosquito interface output (hereinafter, abbreviated as "OI / F"), and 23 is a memory management unit.
[0081]
In the frame synchronizer 10, a signal conversion process of, for example, a composite signal (NTSC signal in which a color (C) signal is frequency-multiplexed with a luminance (Y) signal) will be described below.
[0082]
  First, analog video signals (S1, S2, S3) are input to the AI / F11.
  The AI / F 11 has a selector function and a signal conversion function, and selects one of the input analog video signals (in this case, the composite signal of S1). ChoiceIsThe analog video signal is converted into a component video signal (luminance signal YA, color difference signals RA-YA, BA-YA) and output to A / D12 as video signal S5, and only luminance signal YA is output to WCTG13. Is done.
[0083]
In the A / D 12, the video signal S5 is sampled based on the write clock signal WC supplied from the WCTG 13, and is output to the select switch 14 as the digital video signal S6.
[0084]
The select switch 14 selects one of the digital video signal S6 from the A / D 12 and the digital video signal S7 from the DI / F 15 (S6 in this case) and outputs it to the memory 16.
[0085]
The memory 16 is a memory having a storage capacity of 2 frames (2 frame pages), and writes data according to the write clock signal WC from the WCTG 13 and reads data according to the read clock signal RC from the RCTG 20.
[0086]
Here, the above-described WCTG 13 is provided with a PLL 17 having a VCO 17A. The input video signal (S1, S2, S2, S2, S2, S2, S2 and S2) is provided with the PLL 17 based on the input analog luminance signal YA or digital luminance signal YD (in this case YA). A write clock signal WC synchronized with S3 and S4, in this case S1) is generated, and a write control timing signal S8 which is a basis for write control to the memory 16 is generated.
[0087]
The write control timing signal S8 is composed of an odd / even pulse signal indicating whether the input video signal is an odd field or an even field, a synchronization signal of the input video signal, and the like.
[0088]
The write clock signal WC is output from the WCTG 13 to the A / D 12, the write memory controller 18, and the memory 16, and the write control timing signal S 8 is output to the write memory controller 18.
[0089]
The write memory controller 18 generates a predetermined address of the memory 16 based on the write clock signal WC and the write control timing signal S8, and outputs the write signal WS.
[0090]
[Write control]
Here, an algorithm for write control will be described.
The write memory controller 18 controls the write operation in units of 2 frames (that is, 4 fields).
[0091]
First, the write memory controller 18 determines whether the video signal to be written (S6 or S7, in this case S6) is an odd field or an even field, and a binary number Z 'is generated according to the result. That is, the binary number Z ′ is the result of the field determined by the write memory controller 18, [Z ′] = [0] indicates the odd field, and [Z ′] = [1] indicates the even field.
[0092]
Further, the write memory controller 18 sets the write memory at the field page fixed position D1 of the write memory based on the reference page signal RP that becomes the write frame page input from the memory management unit 23, and according to the result To generate a binary number Y ′.
[0093]
Here, in this embodiment, since processing is performed in units of frames, the field page fixed position D1 of the write memory is set once per frame. In this case, [Y ′] = [0] indicates the first frame, and [Y ′] = [1] indicates the second frame.
Therefore, [Y'Z '] = [00] is the odd field of the first frame, [Y'Z'] = [01] is the even field of the first frame, and [Y'Z '] = [10]. Indicates the odd field of the second frame, and [Y′Z ′] = [11] indicates the even field of the second frame.
[0094]
In the write memory controller 18, when [Y'Z '] is [00], a predetermined write address signal WAD is output to the memory 16 together with the write signal WS, and a video signal (S6 in this case) is written.
[0095]
Similarly, when [Y'Z '] is [01], [Y'Z'] is [10], and [Y'Z '] is [11], the predetermined positions are indicated. Write address WAD is output, and a video signal is written in the memory 16.
[0096]
Here, assuming that the area for writing the first frame data in the memory 16 is the memory area A, and the area for writing the second frame data is the memory area B, when [Y ′] = [0], When Y ′] = [1], writing to the memory area B is performed.
[0097]
On the other hand, a reference video signal S9 that becomes a reference signal (for example, a reference vertical synchronization signal) at the time of reading is input to the RCTG 20, and a read clock signal RC synchronized with the reference video signal S9 is generated by the PLL 21 having the provided VCO 21A. At the same time, a read control timing signal S10 that is the basis of read control to the memory 16 is generated. In this case, the read control timing signal S10 includes an odd / even pulse signal indicating whether the reference video signal S9 is an odd field or an even field, a synchronization signal of the reference video signal, and the like.
[0098]
A read clock signal RC is output from the RCTG 20 to the A / D 12, the read memory controller 19, and the memory 16, and a read control timing signal S 10 is output to the read memory controller 19.
[0099]
The read memory controller 19 outputs a predetermined read address RAD together with the read signal RS to the memory 16 based on the read clock RC, the read control timing signal S10, and the reference page signal RP supplied from the memory management unit 23.
[0100]
The read memory controller 19 controls the read operation so that the write operation and the read operation are not simultaneously performed on the same portion of the memory 16 (that is, the write operation and the read operation are not overtaken or overtaken).
[0101]
Under the control of the read memory controller 19, the video signal VS read from the memory 16 is supplied to the OI / F 22 and output as a video signal S11 synchronized with the reference video signal S9.
[0102]
When outputting the video signal S11, the OI / F 22 performs a mask process called mute (black mute or blue mute) based on the mask signal MS output from the memory management unit 23.
[0103]
[Reading control]
Here, the algorithm of the read control will be described.
The read memory controller 19 controls the read operation in units of 2 frames (that is, 4 fields) similarly to the write memory controller 18, and it is determined whether the reference video signal S9 is an odd field or an even field, and according to the result. To generate a binary number Z.
[0104]
In this case, the binary number Z is the result of the field determined by the read memory controller 19, [Z] = [0] indicates the odd field, and [Z] = [1] indicates the even field.
[0105]
Further, the read memory controller 19 sets the read memory at the field page fixed position D2 of the read memory based on the reference page signal RP serving as the read frame page input from the memory management unit 23, and 2 in accordance with the result. A base Y is generated.
[0106]
In the present embodiment, since processing is performed in units of frames, the field page fixed position D2 of the read memory is set once per frame as in the writing side. In this case, similarly to the writing side, [Y] = [0] indicates the first frame and [Y] = [1] indicates the second frame.
[0107]
Therefore, [YZ] = [00] is the odd field of the first frame, [YZ] = [01] is the even field of the first frame, [YZ] = [10] is the odd field of the second frame, [YZ] = [11] indicates the even field of the second frame.
[0108]
The read memory controller 19 outputs a predetermined read address RAD to the memory 16 together with the read signal RS when [YZ] is [00], and reads the video signal. Similarly, when [YZ] is [01], [YZ] is [10], and [YZ] is [11], predetermined read addresses RAD indicating the respective positions are output, and the memory 16 The video signal VS is read out from.
[0109]
Here, similarly to the writing side, if the area for writing the data of the first frame in the memory 16 is the memory area A and the area for writing the data of the second frame is the memory area B, when [Y] = [0], the memory From area A, when [Y] = [1], reading from memory area B is performed.
[0110]
[Memory Management Department]
FIG. 10 is a circuit block diagram of the memory management unit 23, and FIG. 11 is a flowchart of processing in the memory management unit 23. Hereinafter, the processing of the memory management unit 23 will be described with reference to the drawings.
[0111]
In FIG. 10, 30 is an input synchronization signal processing circuit, 31 is a field discontinuity detection circuit, 32 is a line number error detection circuit, 33 is an interlace / non-interlace discrimination circuit, 34 is a reference page generation circuit, and 35 is a blank detection circuit. , And 36 are mask signal generation circuits.
[0112]
First, the case where the input video signal is disturbed will be described.
The field discontinuity detection circuit 31 performs field discontinuity determination based on the input vertical synchronization signal IVS and horizontal synchronization signal IHS (F1, F1a in FIG. 11), and outputs a field discontinuity determination result FE. Further, the field discontinuity detection circuit 31 holds the field discontinuity determination result FRD of the previous field (F1b).
[0113]
Similarly, the line number error detection circuit 32 determines whether the number of lines in one field satisfies a predetermined value based on the vertical synchronization signal IVS and the horizontal synchronization signal IHS (F1, F1c in FIG. 11). If not, an error flag LE is set. Further, the line number error detection circuit 32 holds the line number determination result LED of the previous field (F1d).
[0114]
Next, the interlace / non-interlace discrimination circuit 33 refers to the field discontinuity determination result FE from the field discontinuity detection circuit 31 and the field discontinuity determination result FED of the previous field for each field according to the vertical synchronization signal IVS. When the field discontinuity exceeds a predetermined number of times, the flag FL1 is set and the odd / even field pseudo replacement signal O / E is output (F2, F2a). Even when the field returns to continuous (normal), the flag FL1 is reset when the normal continuation exceeds a predetermined number of times (F2, F2a).
[0115]
The input synchronization signal processing circuit 30 detects the start of the frame from the input vertical synchronization signal IVS and horizontal synchronization signal IHS. If the flag FL1 of the interlace / non-interlace discrimination circuit 33 is set, odd / The start of the frame is detected according to the pseudo replacement signal O / E in the even field (F3).
[0116]
Based on the above result, the reference page generation circuit 34 manages the area of the memory 16 (F4, F5).
[0117]
  First, according to the frame start signal FS from the input synchronization signal processing circuit 30, the reference page R is set at the frame start.PIs determined (F3a).
[0118]
  In interlace mode, reference page R only when all of the line number determination, the previous field line number determination, the field discontinuity determination, and the previous field discontinuity determination are not errors.PIs updated (F3a).
  In non-interlaced mode, reference page R only when the number of lines is judged and the number of lines in the previous field is not an error.PUpdate.
  Otherwise, reference page RPIs not updated and is retained.
[0119]
  Reference page RP, The write memory is the reference page R at the field page fixed position D1 of the write memory.PIs set as it is (F4a), and the memory area A or the memory area B is designated (F4).
[0120]
  Next, although it is a read memory, since normal video data is output in this embodiment, it is determined whether or not normal video data for one frame has been written. Therefore, the reference page R is set so that the reading is delayed by one to two frames with respect to the writing.PA value obtained by subtracting 1 from this value (in this case, since it is a 2-frame page and is a 1-bit binary number, the value may be inverted) is set at the field page fixed position D2 of the read memory (F5a), and the memory area A or memory area B is designated (F5).
[0121]
  The mask signal is generated as follows. When a blank signal comes in, the horizontal synchronization signal IHS does not come, so the blank detection circuit 35 measures the period of the horizontal synchronization signal IHS (F6), and determines that it is blank when the period exceeds a predetermined value. (F7). The line number determination value L from the line number error detection circuit 32 is also shown in FIG.EAlso, the horizontal synchronization signal error flag FL2 is set in the case of blank determination or line number error. Then, the mask signal generation circuit 36 refers to the horizontal synchronization signal error flag FL2 at the head of the frame pulse, and outputs the mask signal MS when it continues for a predetermined number of times.
[0122]
A description will be given of how data is read and written when external input video data is disturbed by the processing as described above, with reference to FIGS.
[0123]
FIG. 12 shows a timing chart in the case of field discontinuity (odd field continuity) due to splicing or the like.
In FIG. 12, since the odd field 12b of B3 is detected by the field detection after the writing of the odd field 12a of B2, the field becomes discontinuous, the field error flag FE is set, and the write memory B and the read memory B hold. Is done.
[0124]
Data B3 is overwritten in the memory area B in which only the data in the odd field 12a of B2 is written, and after the previous field error flag FED is released, the reference page holding is released and the data B3 is read, so that normal video data is output. The Although not shown in the drawing, even when the even field is continuous, normal video data is output by holding the reference page in the same manner.
[0125]
FIG. 13 shows a timing chart when switching from interlace to non-interlace (odd field only).
In FIG. 13, since the odd field 13b of B3 is detected by the field detection after the writing of the odd field 13a of B2, the field becomes discontinuous, the field error flag FE is set, and the write memory B and the read memory A hold. Is done.
[0126]
However, after writing to the odd field 13b of B3, the odd field 13c of B4 is detected by field detection, and since the odd field is subsequently detected, the field error flag FE remains standing.
[0127]
The field discontinuity count detected by the interlace / non-interlace discriminating circuit 33 is reset at the rising edge of the field error flag FR and is incremented while both the field error flag FE and the previous field error flag FED are set. Indicates how many times the is continued. If it continues for a predetermined number of times (four times in the figure), the non-inter flag FL1 is set, a pseudo field replacement signal O / E is generated, and the pseudo odd field and pseudo even field of B8 are written.
[0128]
Thereafter, holding of the reference page is released, writing after A9 is sequentially performed, and reading is also performed after B2 and subsequent B8, and normal video data is output. The same applies to the case of non-interlace with only the even field.
[0129]
Although not shown, similarly, when switching from non-interlace to interlace, the field error cancellation is counted continuously, and the non-inter flag FL1 is canceled after a predetermined number of times. Then, by holding the reference page RP for the period until switching, normal video data is output.
[0130]
FIG. 14 shows a time chart when there is a fluctuation (decrease) in the number of lines.
In FIG. 14, it is determined that the number of lines in the odd field 14a of B2 is less than a predetermined value, the line number error flag LE is set, and the write memory B and the read memory A are held.
[0131]
Since the data in B3 is overwritten in the memory area B in which the data for which the number of lines in B2 is insufficient is written, the reference page holding is released after the previous line number error flag LED is released, and the data in B3 is read out. Data is output. Although not shown, when the number of lines increases, normal video data is similarly output by holding the reference page.
[0132]
FIG. 15 shows a timing chart in the case of blank input.
In the blank input, the input sync signal does not come, but there are three cases where the vertical sync signal does not come, the horizontal sync signal does not come, and both the vertical sync signal and the horizontal sync signal do not come. FIG. 15 shows a case where the vertical synchronization signal does not come.
[0133]
In FIG. 15, the vertical synchronizing signal does not come during the writing of the odd field 15a of B2, but since the horizontal synchronizing signal continues to operate, it is determined that the line number count value is larger than the predetermined value, and the line number error flag LE rises, and the write memory B and the read memory A are held.
[0134]
  A horizontal synchronization error flag obtained by ORing the frequency error flag (not shown) of the line number error flag LE and the horizontal synchronization signal IHS.FL2Stands. After that, since the line number error flag LE remains on, the horizontal synchronization error flagFL2Will remain standing.
[0135]
The horizontal synchronization error count in the blank detection circuit 35 is reset at the rising edge of the horizontal synchronization signal error flag FL2, and is counted up while both the horizontal synchronization signal error flag FL2 and the previous frame horizontal synchronization error flag FL2D are set. Count how many synchronization errors continue. When a predetermined number of times (four times in the figure) is continued, a blank flag (mask signal) MS is set, and the read data is masked to a black mute signal, for example.
[0136]
Although not shown, when the horizontal synchronizing signal does not come, and when both the vertical synchronizing signal and the horizontal synchronizing signal do not come, the horizontal synchronizing signal does not come. When the frequency error flag disappears, a frequency error flag (not shown) of the horizontal synchronization signal is raised, and a horizontal synchronization signal error flag FL2 obtained by ORing the line number error flag LE and the frequency error flag of the horizontal synchronization signal is raised. Thereafter, the number of horizontal synchronization errors continues as in the case described above. When a predetermined number of times continue, a blank flag (mask signal) MS is set to mask the read data.
[0137]
Here, when an analog VTR video signal having a poor recording state is input, field errors are expected to occur frequently due to field misjudgment, tape damage, or the like. In that case, the screen hold frequently occurs in the output video, or a mask signal is output in some cases, so the reference page holding and mask processing due to the field error can be switched on and off as necessary. It is convenient to make it an expression.
[0138]
In addition, different values may be set for the threshold level when switching from interlace to non-interlace and the threshold level when switching from non-interlace to interlace.
[0139]
Further, power consumption can be reduced by stopping access to the memory during a period in which the video signal is forcibly masked.
[0140]
Further, when the read memory is held or when the frame is read twice, it is possible to take countermeasures such as flicker by setting the output video twice in the same field.
[0141]
By the way, in this embodiment, a memory for two frames is used. However, when an external memory is used, it is more cost-effective to use a general-purpose memory than a dedicated memory. When a 16 MByte general-purpose RAM is used, a system with 525 scanning lines / 60 fields per second (hereinafter abbreviated as “525/60 system”) and a system with 625 scanning lines / 50 fields per second (hereinafter “625”).・ In both cases (abbreviated as “50 systems”), 2 frames can be secured. Therefore, even when the video signal conversion apparatus according to this embodiment is shared by the 525/60 system and the 625/50 system, the memory used can be shared by both systems. In the case of the 525/60 system, since 3 frames can be secured, it can be shared with a memory for a three-dimensional YC separation circuit.
[0142]
As described in the above embodiment, by making the field page fixed position of the write memory different from the field page fixed position of the read memory, the write operation and the read operation can be overtaken and overtaken with a minimum of two fields of memory. Can be prevented.
[0143]
In addition, by managing the reference page RF and forcibly masking the video data, normal video data can be output even if external input video data is disturbed.
[0144]
【The invention's effect】
According to the present invention, it is possible to prevent the overwriting and overtaking of the write operation and the read operation with the memory for a minimum of two fields, so that it is possible to realize a video signal conversion device having a very simple configuration with a small circuit scale. Can do.
[0145]
Even if the sync signal of the input video data such as the composite signal is disturbed, the disturbance of the input sync signal is detected, the memory page for 2 frames is managed, and the video data is forcibly masked. Since normal video data is output, a video signal conversion device with improved image quality can be realized.
[Brief description of the drawings]
FIG. 1 is a timing diagram for explaining a mechanism of overtaking and overtaking.
FIG. 2 is a timing chart for explaining the mechanism of overtaking and overtaking.
FIG. 3 is a timing chart for explaining the mechanism of overtaking and overtaking.
FIG. 4 is a timing chart for explaining the mechanism of overtaking and overtaking.
FIG. 5 is a timing chart of a data read / write operation in the video signal conversion apparatus according to the embodiment of the present invention.
FIG. 6 is a timing chart of a data read / write operation in the video signal conversion apparatus according to the embodiment of the present invention.
FIG. 7 is a timing chart of a data read / write operation when a write cycle and a read cycle are different in the embodiment of the present invention.
FIG. 8 is a timing diagram of a data read / write operation when a write cycle and a read cycle are different in the embodiment of the present invention.
FIG. 9 is a block diagram of a video signal conversion apparatus according to an embodiment of the present invention.
FIG. 10 is a block diagram of a memory management unit 23 according to the embodiment of the present invention.
FIG. 11 is a flowchart illustrating an example of a process flow of the memory management unit 23 illustrated in FIG. 10;
FIG. 12 is a timing diagram of a data read / write operation when there is a field discontinuity in the input video data according to the embodiment of the present invention.
FIG. 13 is a timing diagram of a data read / write operation when the input video data according to the embodiment of the present invention is switched to interlace / non-interlace.
FIG. 14 is a timing diagram of a data read / write operation when there is a line number variation in the input video data according to the embodiment of the present invention.
FIG. 15 is a timing diagram of a data read / write operation when there is a blank input in the input video data according to the embodiment of the present invention.
FIG. 16 is a block diagram of a conventional video signal converter.
FIG. 17 is a timing chart for explaining problems of a conventional video signal conversion apparatus.
[Explanation of symbols]
A, B Field page
A0, A1, A2 video data
B0, B1 video data
D1 Field page fixed position of write memory
D2 Read memory field page position
IP vertical blanking period
IS input vertical sync signal
RS reference vertical sync signal
PWc Write cycle
PRc read cycle
PR actual readout period
10 frame synchronizer
12 Analog to digital converter
16 memory
18 Write memory controller
19 Read memory controller
23 Memory Management Department
30 Input synchronization signal processing circuit
31 Field discontinuity detection circuit
32 line number error detection circuit
33 Interlace / non-interlace discrimination circuit
34 Reference page generation circuit
35 Blank detection circuit
36 Mask signal generation circuit

Claims (22)

In the video signal conversion device that generates the converted video signal synchronized with the reference synchronization signal inside the device after writing the input video signal input in synchronization with the external synchronization signal into the memory,
A memory capable of storing at least two fields of the input video signal;
Writing means for writing one field of the input video signal into the memory in a writing cycle period based on the external synchronization signal;
Reading means for reading one field of the input video signal from the memory as the converted video signal in a reading cycle period based on the reference synchronization signal;
A page management means for managing the reference pages for two fields page, and whether the underlying writing or reading which fields page in the memory,
Enabling write to by that the reference pages to said writing means, and writing the memory control means for controlling the time of confirmation writing fields page within the write cycle period,
The enabling perform a read from the reference page that by the reading means, provided, a read memory control means for controlling the read field pages established within said read cycle period,
When the write field page is determined, it is set within a first invalid area period without the input video signal within the write cycle period,
When the readout field page is determined, it is set in a second invalid area period without the converted video signal in the readout cycle period,
The external sync signal from the time of detection of the first period until the writing field pages determined, the reference and second period from the time of detecting the synchronization signal until the reading field page confirmation, that the time interval different to video signal converting apparatus characterized that you and. The said 2nd period is set longer than the said 1st period, when the said page management means manages the field page which writes in and reads in a different field page, The said 2nd period is set long . Video signal converter. 2. The first period is set longer than the second period when the page management unit manages field pages to be written and read to the same field page. Video signal converter. Claims when said manual Komifu Irudopeji determined is the start of the first invalid area period, when the read differential Irudopeji finalized, characterized in that a at the end of the second invalid area period 2. The video signal converter according to 2 . Wherein an end of the write field Page finalized the first invalid area period, according to claim 3, when the reading field Page finalized, characterized in that at the start of the second invalid area period Video signal converter. 2. The start time of the first invalid area period is a start time of the write cycle period, and the start time of the second invalid area period is a start time of the read cycle period. The video signal converter according to any one of claims 5 to 5. Wherein the first invalid area period second invalid area period, the video signal conversion device according to claim 1 to 6, characterized in that a vertical blanking period. The document Komifu Irudopeji the read differential Irudopeji time determined to the time determined, the video signal conversion device according to claim 1, wherein the changing in accordance with a state of the input video signal.   9. The video signal according to claim 1, wherein the memory is at least four fields, that is, two frames, and the reference page in the page management means and the page in the write / read memory are in units of one frame. Conversion device. Field discrimination means for discriminating a field of the input video signal;
Detecting means for detecting field discontinuity of the input video signal based on the determination result of the field determining means;
10. The video signal conversion apparatus according to claim 9, wherein when the detection unit detects a field discontinuity, the page management unit holds a frame page that is being written to and read from a memory. 11. The switch according to claim 10, wherein, when a field discontinuity is detected by the detection unit, it is possible to switch whether or not to hold a frame page to which the page management unit performs writing and reading. Video signal converter. Interlaced discrimination means for discriminating whether said input video signal harm interlaced or non-interlaced scanning,
Field replacement means for changing fields in a pseudo manner,
10. The video signal conversion apparatus according to claim 9, wherein when the input video signal is determined to be non-interlaced by the interlace determination unit, the field replacement unit artificially replaces the field.   13. The frame management unit holds a frame page in which data is written and read in a memory when switching from an interlace mode to a non-interlace mode or from a non-interlace mode to an interlace mode. The video signal converter described in 1. 14. The video signal converter according to claim 13, wherein threshold levels for switching from the interlace mode to the non-interlace mode and from the non-interlace mode to the interlace mode are variable. Line number detection means for detecting the number of lines in one frame is provided,
10. The frame management apparatus according to claim 9, wherein the page management unit holds a frame page in which writing and reading are performed in a memory when a predetermined variation in the number of lines is detected by the line number detection unit. Video signal converter.   When the page management means holds a frame page from which memory is being read, it is not an odd / even field output, which is a frame output, but an odd / odd field output or even / even field output. 16. The video signal conversion apparatus according to claim 9, wherein the video signal conversion apparatus is a video signal conversion apparatus.   17. The video signal conversion apparatus according to claim 16, wherein when reading from the memory, odd / even field output, odd / odd field output, and even / even field output can be switched. Blank detecting means for detecting a blank period of the input video signal;
Masking means for forcibly muting the input video signal,
The video signal converter according to claim 9, wherein when the blank period of the input video signal is detected by the blank detection means, a mute signal is output by the mask means.   19. The video signal according to claim 18, wherein when the blank detection unit detects a blank period of the input video signal, it is possible to switch whether or not the video signal is forcibly muted by the mask unit. Conversion device.   19. The video signal converter according to claim 18, wherein access to the memory is stopped during a period in which the input video signal is forcibly muted.   21. The video signal converter according to claim 1, wherein the memory is shared by a 525/60 system and a 625/50 system.   21. The video signal converter according to claim 1, wherein the 525/60 system shares a memory with a memory for a three-dimensional YC separation circuit.

Images