JP2005236479A - Rssi circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an RSSI circuit wherein an offset of an output current is nullified even when the amplitude of an input signal is zero by eliminating the effect of dispersion in mutual conductance of transistors. <P>SOLUTION: The RSSI circuit is configured by the connection of multi-stages each comprising a differential amplifier circuit comprising transistors Q1, Q2 for receiving outputs V1p, V1n of a limiter amplifier; a current mirror circuit comprising a MOS transistor Q3 for supplying a bias voltage to the differential amplifier circuit and MOS transistors Q4, Q5 and controlling an output current in response to the input voltages V1p, V1n; a bias cancel circuit comprising a current mirror circuit consisting of MOS transistors Q6, Q7 and a MOS transistor Q8 and for canceling an offset voltage produced in the differential amplifier circuit; and a detection circuit including at least resistors R1, R2, R3, R8 connected to the source of each transistor and a resistor Rrssi connected to an output terminal 6 of the RSSI circuit. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an RSSI circuit used for communication equipment and the like.

Conventionally, an RSSI (Received Signal Strength Indicator) circuit is used for a function of detecting the magnitude of an input signal level, for example, used in a receiver such as a communication device.
FIG. 5 is a diagram illustrating a configuration example of a limiter circuit and a detection circuit in a general FM receiver. An RSSI circuit is used as the detection circuit in FIG.

  The limiter circuit in the figure includes a capacitor for cutting a DC component with respect to the differential input voltages Vp and Vn input to the IF signal input terminals 18 and 19, and the differential input voltages Vp and Vn via the capacitors. This is a circuit in which a first-stage limiter circuit 15 having a limiter amplifier for performing rectification on an input signal to which a bias VCM is applied is made up of seven stages. Further, the output signals (for example, V1p and V1n) of the limiter amplifiers at the respective stages in FIG. The input signal is rectified and output by the detection circuit (for example, Vr1), and the sum of the output signals Vr1 to Vr7 from the detection circuits at each stage appears at the RSSI circuit output terminal, and the output signal becomes Vrssi.

  FIG. 6 shows a configuration example of the detection circuit at each stage. This figure shows a differential amplifier circuit used for general purposes. For example, when the output signal V1n at the first stage of the limiter amplifier and the output signal V1p in which the phase of V1n is inverted by 180 degrees are input to the differential amplifier circuit, only the signal having a high potential is output as the output signal Vr1. The input signal is full-wave rectified.

The output signal Vrssi of the RSSI circuit obtained by the above configuration is output through a capacitor having an appropriate capacity. The output signal is ideally required to be a signal having linearity.
Patent Document 1 discloses an RSSI circuit that corrects an RSSI output characteristic that is impaired by the loss of a band limiting filter and obtains an RSSI output with good linearity. Patent Document 2 discloses an RSSI circuit that eliminates a non-engageable range portion by freely changing the RSSI output range when the RSSI output range and the input range of an A / D converter connected to the subsequent stage do not mesh. Is disclosed.
Japanese Patent Laid-Open No. 06-350468 Japanese Patent Laid-Open No. 10-336063

However, the RSSI voltage characteristic with respect to the amplitude of the input signal to the RSSI circuit has a problem that it is greatly influenced by the mutual conductance of the MOS transistor generated at the time of manufacturing the circuit and the resistance variation due to temperature change.
The present invention has been made in view of the above-mentioned problems, and the problem to be solved is to provide an RSSI circuit that is not affected by variations in mutual conductance and the like of MOS transistors constituting the RSSI circuit. is there.

  The invention according to claim 1 controls a differential amplifier circuit for amplifying a received signal, a bias circuit for supplying a bias voltage to the differential amplifier circuit, and an output current of the differential amplifier circuit. A transconductance gm of a MOS transistor constituting the differential amplifier circuit, and a resistance value R of a resistor connected to the MOS transistor constituting the differential amplifier circuit. It is an RSSI circuit characterized by having a relationship of 1 / gm << R.

  According to the first aspect of the present invention, the mutual conductance gm of the MOS transistor constituting the differential amplifier circuit and the resistance R have a relationship of 1 / gm << R, whereby the resistance component of the MOS transistor ( 1 / gm) is negligibly small with respect to the resistance value R of the resistor connected to the MOS transistor, so that the output current of the RSSI circuit is not affected by the variation in the mutual conductance gm generated during manufacturing, and the resistance R The effect that can be determined by.

According to a second aspect of the present invention, the resistors connected to the MOS transistors constituting the differential amplifier circuit are configured with resistors having the same shape and the same impurity concentration. This is an RSSI circuit.
According to the invention described in claim 2, in addition to the effect described in claim 1, the resistors inserted into the MOS transistors constituting the differential amplifier circuit are configured with resistors having the same shape and the same impurity concentration. As a result, there is an effect of eliminating variation in resistance value that occurs during manufacturing.

  The invention according to claim 3 further includes a bias cancel circuit for canceling an offset voltage generated in the differential amplifier circuit, and the same resistor as the resistor is connected to the MOS transistor constituting the bias cancel circuit. The RSSI circuit according to claim 1, wherein the RSSI circuit is provided.

According to the invention described in claim 3, in addition to the effect described in claim 1 or 2, the input amplitude to the RSSI circuit is reduced to 0 by the action of canceling the offset voltage generated in the differential amplifier circuit by the bias cancel circuit. In this case, the output current is 0.
The invention according to claim 4 is the RSSI circuit according to any one of claims 1 to 3, wherein the resistors are resistors arranged in the vicinity of each other.

According to the invention described in claim 4, in addition to the same effect as that of the invention described in claim 1 or 2, the resistances are arranged in the vicinity of each other, thereby eliminating variations in resistance values during manufacturing. Can be further enhanced.
The invention according to claim 5 controls a differential amplifier circuit for amplifying a received signal, a MOS transistor for supplying a bias voltage to the differential amplifier circuit, and an output current of the differential amplifier circuit. Therefore, the mutual conductance gm of the MOS transistor that has at least a current mirror circuit and that constitutes the differential amplifier circuit, and the resistance value R of the resistor connected to the MOS transistor that constitutes the differential amplifier circuit is 1 It is an RSSI circuit characterized by having a relationship of / gm << R.

  According to the fifth aspect of the present invention, since the mutual conductance gm of the MOS transistor constituting the differential amplifier circuit and the resistance R have a relationship of 1 / gm << R, the output current of the RSSI circuit is There is an effect that can be determined by the resistance R without being affected by variations in the mutual conductance gm generated during manufacturing.

The invention described in claim 6 is characterized in that the resistors connected to the MOS transistors constituting the differential amplifier circuit are configured with resistors having the same shape and the same impurity concentration. RSSI circuit.
According to the invention described in claim 6, in addition to the effect described in claim 5, the resistors inserted into the MOS transistors constituting the differential amplifier circuit are configured with resistors having the same shape and the same impurity concentration. As a result, there is an effect of eliminating variation in resistance value that occurs during manufacturing.

The invention according to claim 7 is the RSSI circuit according to any one of claims 1 to 4, wherein the resistor is made of polysilicon.
According to the seventh aspect of the present invention, the use of a resistor made of polysilicon has the effect of eliminating variations in resistance values that occur during manufacturing, similar to the first to fourth aspects of the present invention.

The invention according to claim 8 controls a differential amplifier circuit for amplifying a received signal, a bias circuit for supplying a bias voltage to the differential amplifier circuit, and an output current of the differential amplifier circuit. Current mirror circuit for,
And the mutual conductance gm of the MOS transistor constituting the differential amplifier circuit and the resistance value R of the resistor connected to the MOS transistor constituting the differential amplifier circuit are 1 / gm << R. The circuits having the relationship are connected in multiple stages, and the output terminals of the current mirror circuits, which are the output terminals of the circuits connected in multiple stages, are connected to each other, and the MOS transistor and the RSSI circuit output constituting the differential amplifier circuit The resistor connected to the output end of the current mirror circuit, which is the end, is an RSSI circuit characterized in that it is composed of resistors having the same shape and the same impurity concentration.

  As described above, according to any aspect of the present invention, it is possible to provide an RSSI circuit that is not affected by variations in the mutual conductance and the like of the MOS transistors constituting the RSSI circuit.

Hereinafter, embodiments of the present invention will be described with reference to FIGS. 1 to 5. The RSSI circuit according to the present embodiment is formed on a semiconductor circuit board by a CMOS process that can manufacture p-channel and n-channel MOS transistors.
FIG. 1 is a diagram showing a circuit configuration of an RSSI circuit according to the first embodiment of the present invention.

  The RSSI circuit according to this embodiment is connected to the output side of the limiter amplifier in each stage with respect to the limiter circuit connected in multiple stages, and for example, with respect to the outputs V1p and V1p of the first-stage limiter amplifier shown in FIG. A differential amplifier circuit composed of MOS transistors Q1 and Q2 having an output V1n whose phase is inverted by 180 degrees, a MOS transistor Q3 for supplying a bias voltage to the differential amplifier circuit, and a MOS transistor A current mirror circuit configured by Q4 and Q5 and controlling output current based on currents flowing through the MOS transistors Q1 and Q2 in accordance with input voltages V1p and V1n; and a current mirror circuit configured by MOS transistors Q6 and Q7 MOS transistor Q8 is used to cancel the offset voltage generated in the differential amplifier circuit. A multi-stage detection circuit including at least a cancel circuit, resistors R1, R2, R3, R8 connected to the source sides of the transistors Q1, Q2, Q3, and Q8 and a resistor Rrssi connected to the RSSI circuit output terminal 6 It is a circuit formed by connection.

  2A and 2B show the input signal V1n whose phase is inverted by 180 degrees with respect to the signals V1p and V1p from the first-stage limiter amplifier shown in FIG. When input signals V1p and V1n are input to the input terminals 3 and 4 to the first-stage detection circuit of the detection circuit in FIG. 1 to the transistors Q1 and Q2 to which a predetermined bias voltage is applied to the gate by the current source I, respectively. The input signals (V1p, V1n) are superimposed on the bias voltage. When an input signal is input to the transistor Q1, a current corresponding to the input signal flows through the transistor Q4 of the current mirror circuit composed of the MOS transistors Q4 and Q5, so that the output current of the first-stage detection circuit is the transistor Q5. Flows to the side.

Similarly, when an input signal is input to the transistor Q2, a current corresponding to the input signal flows through the transistor Q4 of the current mirror circuit composed of the MOS transistors Q4 and Q5, so that the output of the first-stage detection circuit Current flows to the transistor Q5 side.
Here, the bias voltage is adjusted by a resistor connected to the gate side of the transistors Q1 and Q2. The capacitors connected to the gate sides of the transistors Q1 and Q2 are used to cut the DC component of the input signals (V1p, V1n).

With the above operation, the waveform appearing at the output terminal 5 of the first-stage detection circuit is the waveform shown in FIG.
Here, the resistance of the output terminal of the RSSI circuit is Rrssi, and the resistance connected to each of the transistors Q1, Q2, Q3, and Q8 is the voltage of the input signal to the first-stage detection circuit, R1, R2, R3, R8, respectively. Is ΔV1 and the transconductance of the transistor is gm, the current I1 flowing through the output terminal 5 of the first-stage detection circuit is expressed by the following equation.
I1 = ΔV1 * (1 / (1 / gm + R))
Here, the resistors R1, R2, R3, R8 are resistors having the same shape and the same impurity concentration as the resistor Rrssi, and the resistance values of the resistors R1, R2, R3, R8, Rrssi are respectively set to r1, r2, When r3, r8, and rrssi, R = r1 = r2 = r3 = r8 and rrssi = K * R (where K is a constant). The mutual conductances of the transistors Q1, Q2, Q3, and Q8 are the same, and the value thereof is gm.

  In this embodiment, the mutual conductance gm is appropriately adjusted and determined so as to have a relationship of 1 / gm << R. Alternatively, the resistance value R may be appropriately adjusted and determined so as to have a relationship of 1 / gm << R, or may be determined by adjusting both the mutual conductance gm and the resistance value R. As a result, I1≈ΔV / R, and the current I1 flowing through the transistor Q1 is determined by the resistance value R, so that it is possible to prevent the transistor from being affected by variations in mutual conductance of the transistor.

Here, in order to obtain a relationship of 1 / gm << R, adjustment is made so that the value of 1 / gm is within a range of several% to 20% with respect to the resistance value R. Desirably, the value of 1 / gm is adjusted to a range of several% to 5% with respect to the resistance value R.
Further, the resistance value R may be adjusted according to the number of the same size (shape) and the concentration resistance of the implanted impurity, such as the concentration of the implanted impurity and the vertical / horizontal / depth of the resistance. The size (shape) may be adjusted as appropriate. Further, the mutual conductance of each of the transistors is adjusted by the channel width, the channel length, or the like.

In this embodiment, since the detection circuit has a seven-stage configuration, the voltage of the input signal to each stage is ΔV1, ΔV2, ΔV3, ΔV4, ΔV5, ΔV6, ΔV7, and the output current of each stage is I1, I2, I3, I4. , I5, I6, and I7, the output current Irssi and the output voltage Vrssi at the RSSI circuit output terminal 6 are expressed by the following equations.
Irssi = I1 + I2 + ... + I7
= ΔV1 * (1 / (1 / gm + R)) +... + ΔV7 * (1 / (1 / gm + R))
Vrssi = Rrssi * Irssi
Here, in this embodiment, as described above, the transconductance gm of the transistor is determined so as to have a relationship of 1 / gm << R. Therefore, the resistance value R is canceled, and Vrssi is expressed by the following equation. It becomes.
Vrssi = K * (ΔV1 + ΔV2 +... + ΔV7)
As shown in the above equation, Vrssi output to the RSSI circuit output terminal 6 according to the present embodiment is determined by the constant K (relative ratio K) of the resistance value K * R (= Rrssi) connected to the RSSI circuit output terminal 6. Will be.

  Further, the resistances R1, R2, R3, R8, and Rrssi are made to have the same shape and the same impurity concentration so as to eliminate variations in resistance during manufacturing, whereby the resistance values of the resistors R1, R2, R3, R8, and Rrssi are set to r1, r2, respectively. , R3, r8, rrssi, it is possible to have a relationship of R = r1 = r2 = r3 = r8 and rrssi = K * R, and the relative ratio K can be prevented from varying.

  Furthermore, in this embodiment, a current mirror circuit composed of MOS transistors Q6 and Q7 and a bias cancel circuit composed of MOS transistor Q8 are provided. When the current I flows through the transistor Q8, the current I flows through the transistor Q6 side of the current mirror circuit having a current ratio of 1: 2 composed of the transistors Q6 and Q7. When the current I flows on the transistor Q6 side, the current 2I flows on the transistor Q7 side. Here, since the transistors Q3, Q1, and Q2 have the configuration of a current mirror circuit, even when the input amplitude to the detection circuit is 0, the current I flows through the transistors Q1 and Q2. However, when the input amplitude to the detection circuit is 0, all of the current 2I flowing through the transistor Q7 flows through the transistors Q1 and Q2, so that the current flowing through the transistor Q4 is 0 and the current of the transistor Q5 is also 0.

  With the above operation, in this embodiment, the current mirror circuit composed of the MOS transistors Q6 and Q7 and the bias cancel circuit composed of the MOS transistor Q8 cause a current twice that of the original current source I to flow. It is possible to cancel the offset voltage generated at the output terminal 5 of the detection circuit. That is, even when the input amplitude to the detector circuit is zero, the output current of the detector circuit at each stage can be zero, and the offset voltage appearing at the RSSI circuit output terminal can be zero.

  FIG. 3 is a diagram illustrating an outline of the output characteristics of RSSI according to the present embodiment. The horizontal axis indicates the change in input voltage (dB) by logarithmic display, and the vertical axis indicates the differential output voltage (V) with respect to the input voltage. Although the conventional RSSI output characteristic 7 has an offset voltage, the offset voltage of the output characteristic 8 of the RSSI of this embodiment becomes 0 by having the above-described bias cancel circuit.

As described above, it is possible to eliminate the offset voltage of the RSSI output voltage even when the input amplitude is 0 by eliminating the offset of the output current in the detection circuit of each stage, and the RSSI output characteristics in the weak electric field can be eliminated. Variation can be drastically reduced.
FIG. 4 is a diagram showing a circuit configuration of an RSSI circuit according to the second embodiment of the present invention.

  The RSSI circuit according to this embodiment is connected to the output side of the limiter amplifier in each stage with respect to the limiter circuit connected in multiple stages, and for example, with respect to the outputs V1p and V1p of the first-stage limiter amplifier shown in FIG. A differential amplifier circuit composed of MOS transistors Q9 and Q10 having an output V1n whose phase is inverted 180 degrees, a MOS transistor Q11 for supplying a bias voltage to the differential amplifier circuit, and a MOS transistor A current mirror circuit configured by Q12 and Q13 that controls output current based on currents flowing through the MOS transistors Q9 and Q10 according to the input voltages V1p and V1n, and resistors connected to the source side of the transistors Q9 and Q10, respectively. This is a circuit formed by connecting a detection circuit having at least R9 and R10 in multiple stages.

  As in the first embodiment, the input signals V1p and V1n are signals shown in FIGS. 2 (a) and 2 (b), respectively. When the input signals V1p and V1n are input to the first-stage detection circuit 9 in the transistors Q9 and Q10 to which a predetermined bias voltage is applied to the gate by the current source I, the input signals (V1p and V1n) are applied to the bias voltage. Are superimposed. When an input signal is input to the transistor Q9, a current corresponding to the input signal flows through the transistor Q12 of the current mirror circuit composed of the MOS transistors Q12 and Q13, so that the output current of the first-stage detection circuit 9 is the transistor It flows to the Q13 side.

Similarly, when an input signal is input to the transistor Q10, a current corresponding to the input signal flows through the transistor Q12 of the current mirror circuit composed of the MOS transistors Q12 and Q13. An output current flows to the transistor Q13 side.
With the above operation, the waveform appearing at the output terminal of the first-stage detection circuit is the waveform shown in FIG.

Here, as in the first embodiment, the resistance of the output terminal of the RSSI circuit is Rrssi, and the resistance connected to each of the transistors Q9 and Q10 is R9, R10, and the voltage of the input signal to the first-stage detection circuit, respectively. ΔV′1, the transconductance of the transistor is gm, and the resistors R9 and R10 are resistors having the same shape and the same impurity concentration as the resistor Rrssi, and R = R9 = R10 and Rrssi = K * R (provided that Assuming that K is a constant), the current I13 flowing through the transistor Q13 is expressed by the following equation.
I13 = ΔV′1 * (1 / (1 / gm + R))
Also in this embodiment, by determining the mutual conductance gm so as to have a relationship of 1 / gm << R, the current I13 flowing through the transistor Q13 is determined by the resistance value R because I13≈ΔV′1 / R. Thus, it is possible to prevent the transistor from being affected by variations in mutual conductance.

Therefore, in this embodiment, since the detection circuit has a seven-stage configuration, the voltages of the input signals to each stage are ΔV′1, ΔV′2, ΔV′3, ΔV′4, ΔV′5, ΔV′6, ΔV. '7, assuming that the output current of each stage is I'1, I'2, I'3, I'4, I'5, I'6, I'7, the output current Irssi and output of the RSSI circuit output terminal 14 The voltage Vrssi is expressed by the following equation.
Irssi = I′1 + I′2 +... + I′7
= ΔV′1 * (1 / (1 / gm + R)) +... + ΔV′7 * (1 / (1 / gm + R))
Vrssi = Rrssi * Irssi
Further, since the mutual conductance gm of the transistor is determined so as to have a relationship of 1 / gm << R, the resistance value R is canceled, and Vrssi becomes K * (ΔV′1 + ΔV′2 + ·· + ΔV′7). The Vrssi output to the RSSI circuit output terminal 6 according to the embodiment is determined by the constant K (relative ratio K) of the resistor K * R (= Rrssi) connected to the RSSI circuit output terminal 14.

  In addition, when the resistance values of the resistors R9, R10, and Rrssi are set to r9, r10, and rsrssi by making the resistors R9, R10, and Rrssi have the same shape and the same impurity concentration, and thereby eliminating variations in resistance at the time of manufacture, R = It is possible to have a relationship of r9 = r10 and rrssi = K * R, and the relative ratio K can be prevented from varying.

In the above description, an embodiment of the RSSI circuit in which the detection circuit is composed of seven stages is shown in the present embodiment, but the present invention is not limited to this and is applied to an RSSI circuit in which the detection circuit is composed of one or more stages. Can be adapted.
The resistors R1, R2, R3, R8, and Rrssi used in the first embodiment and the resistors R9, R10, and Rrssi used in the second embodiment use the same material (for example, polysilicon) and have the same concentration. It is desirable to use the ones that are close together and to use close resistors that are produced in the same process. As a result, variations due to material, concentration, etching, and the like when forming a resistor on a semiconductor circuit board by a CMOS process become the same level of resistance, and the influence of variations during the process can be eliminated.

  Further, the RSSI circuit according to the present invention is not limited to the circuit configuration shown in the embodiment, and can be applied to an AGC (Automatic Gain Controller) or the like.

It is a figure which shows the circuit structure of the RSSI circuit which concerns on 1st embodiment of this invention. FIG. 2 is a diagram illustrating waveforms of input terminals V1p and V1n and an output terminal of the first-stage detection circuit illustrated in FIG. It is a figure which shows the outline | summary of the output characteristic of the RSSI circuit which concerns on 1st embodiment of this invention. It is a figure which shows the circuit structure of the RSSI circuit which concerns on 2nd embodiment of this invention. It is a figure which shows the structural example of the limiter circuit in a FM receiver, and a detection circuit. It is a figure which shows the prior art example of the detection circuit which comprises an RSSI circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Detection circuit of the 1st stage 2 ... Detection circuit of the 7th stage 3 ... Input terminal to the detection circuit of the 1st stage 4 ... Input terminal to the detection circuit of the 1st stage 5 .. Output terminal 6 of the first stage detection circuit 6... RSSI circuit output terminal 7... Conventional RSSI output characteristics 8... RSSI output characteristics according to this embodiment 9. DESCRIPTION OF SYMBOLS 10 ... 7th-stage detection circuit 11 ... Input terminal 12 to 1st-stage detection circuit ... Input terminal 13 to 1st-stage detection circuit ... Output of 1st-stage detection circuit Terminal 14 ... RSSI circuit output terminal 15 ... First stage limiter circuit 16 ... First stage detector circuit 17 ... Detector circuit 18 ... IF signal input terminal 19 ... IF signal input Terminal 20 ... RSSI circuit output terminal 21 ... Input terminal 22 to the first stage detection circuit 22 ... First stage detection Input terminal 23 to the wave circuit ... Output terminal of the first stage detection circuit

Claims (8)

A differential amplifier for amplifying the received signal;
A bias circuit for supplying a bias voltage to the differential amplifier circuit;
A current mirror circuit for controlling the output current of the differential amplifier circuit;
Having at least
The mutual conductance gm of the MOS transistor constituting the differential amplifier circuit and the resistance value R of the resistor connected to the MOS transistor constituting the differential amplifier circuit have a relationship of 1 / gm << R. Characteristic RSSI circuit.   2. The RSSI circuit according to claim 1, wherein the resistors connected to the MOS transistors constituting the differential amplifier circuit are composed of resistors having the same shape and the same impurity concentration. A bias cancel circuit for canceling an offset voltage generated in the differential amplifier circuit;
3. The RSSI circuit according to claim 1, wherein the same resistor as the resistor is connected to a MOS transistor constituting the bias cancel circuit. 4.   The RSSI circuit according to claim 1, wherein the resistors are resistors arranged in the vicinity of each other. A differential amplifier for amplifying the received signal;
A MOS transistor for supplying a bias voltage to the differential amplifier circuit;
A current mirror circuit for controlling the output current of the differential amplifier circuit;
Having at least
The mutual conductance gm of the MOS transistor constituting the differential amplifier circuit and the resistance value R of the resistor connected to the MOS transistor constituting the differential amplifier circuit have a relationship of 1 / gm << R. Characteristic RSSI circuit.   6. The RSSI circuit according to claim 5, wherein the resistors connected to the MOS transistors constituting the differential amplifier circuit are configured with resistors having the same shape and the same impurity concentration.   The RSSI circuit according to claim 1, wherein the resistor is made of polysilicon. A differential amplifier for amplifying the received signal;
A bias circuit for supplying a bias voltage to the differential amplifier circuit;
A current mirror circuit for controlling the output current of the differential amplifier circuit;
Having at least
A circuit in which a mutual conductance gm of a MOS transistor constituting the differential amplifier circuit and a resistance value R of a resistor connected to the MOS transistor constituting the differential amplifier circuit have a relationship of 1 / gm << R. Connected in multiple stages,
The output terminals of the current mirror circuit, which is the output terminal of each circuit connected in multiple stages, are connected to each other,
The resistors connected to the MOS transistor constituting the differential amplifier circuit and the output end of the current mirror circuit, which is the RSSI circuit output end, are composed of resistors having the same shape and the same impurity concentration. RSSI circuit.

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