JP2005236064A - Signal transmission pair wiring and its manufacturing method - Google Patents

Signal transmission pair wiring and its manufacturing method Download PDF

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Publication number
JP2005236064A
JP2005236064A JP2004043819A JP2004043819A JP2005236064A JP 2005236064 A JP2005236064 A JP 2005236064A JP 2004043819 A JP2004043819 A JP 2004043819A JP 2004043819 A JP2004043819 A JP 2004043819A JP 2005236064 A JP2005236064 A JP 2005236064A
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Japan
Prior art keywords
wiring
signal transmission
pair wiring
transmission pair
vias
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Inventor
Yasushi Nakagiri
康司 中桐
Tetsuyoshi Ogura
哲義 小掠
Shozo Ochi
正三 越智
Satoru Tomekawa
悟 留河
Kazuo Tsubouchi
和夫 坪内
Yoji Isoda
陽次 礒田
Hiroyuki Nakase
博之 中瀬
Taku Kameda
卓 亀田
Takashi Fujii
隆司 藤井
Shoichi Oshima
尚一 大嶋
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Tohoku University NUC
Panasonic Holdings Corp
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Tohoku University NUC
Matsushita Electric Industrial Co Ltd
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Priority to JP2004043819A priority Critical patent/JP2005236064A/en
Publication of JP2005236064A publication Critical patent/JP2005236064A/en
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Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that in a conventional signal transmission line using a single line, characteristics depending on the shape of a line are not good, and especially when vias intervene in a longitudinal direction, a high frequency characteristic deteriorates depending on a frequency. <P>SOLUTION: In signal transmission pair wiring wherein its multilayers are connected with vias and a plurality of patternized metal layers and a dielectric layer are laminated, the signal transmission wiring with a good transmission characteristic which does not contain a characteristics error till tens of GHz high frequency region is obtained by controlling the diameter and the gap of the via which connect a plurality of wiring where the metal layers are patternized, and by using the signal transmission pair wiring characterized by arranging so that characteristic impedance may serve as a fixed value. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、数十GHz帯の超高周波信号処理ICを実装するための高密度実装基板の信号伝送配線構造に関する。   The present invention relates to a signal transmission wiring structure of a high-density mounting substrate for mounting an ultrahigh frequency signal processing IC of several tens of GHz band.

図8に、従来の多層基板における配線構造の例を示す。配線は、表面に形成された金属膜配線と、誘電体に挟まれた金属膜配線と、双方の配線を接続する縦方向ビアと、金属膜配線とビアとを接続するビアパッド部から形成される。従来の配線は、グランドに対して信号レベルが決定されるシングルエンド伝送であった。金属膜配線は、表面に形成されるものと誘電体に挟まれた配線とも、特性インピーダンスがある値(通常50Ω)となるように構成される。縦方向ビア構造は、インピーダンス制御の手法が無いため、通常は作製工程のルールに基づき、形成される。また、ビアパッド部は、その接続性を保証する為、縦方向ビアの直径より大きく、約2倍の大きさで形成する必要があった。   FIG. 8 shows an example of a wiring structure in a conventional multilayer substrate. The wiring is formed of a metal film wiring formed on the surface, a metal film wiring sandwiched between dielectrics, a vertical via that connects both wirings, and a via pad portion that connects the metal film wiring and the via. . Conventional wiring is single-ended transmission in which the signal level is determined with respect to the ground. The metal film wiring is configured such that the characteristic impedance of both the wiring formed on the surface and the wiring sandwiched between the dielectrics has a certain value (usually 50Ω). Since there is no impedance control method, the vertical via structure is usually formed based on the rules of the manufacturing process. Further, the via pad portion needs to be formed to be about twice as large as the diameter of the vertical via in order to guarantee the connectivity.

しかしながら、従来の単一線路を用いた信号伝送線路では、線路の形状に依存する特性が良好でなく、特に縦方向のビアが介在する場合、周波数に依存して高周波特性が劣化する問題点があった。   However, in the conventional signal transmission line using a single line, the characteristic depending on the shape of the line is not good, and particularly when a vertical via is interposed, there is a problem that the high frequency characteristic deteriorates depending on the frequency. there were.

この課題を解決するために、本発明では、請求項1に係る手段として、信号伝送線路を、二本の配線で一対とするペア配線構造とし、ペア配線伝送線路及び縦方向ビアにおけるそれぞれの特性インピーダンスが一定の値となるようにビアの直径およびビアの間隔を制御して配置した。   In order to solve this problem, in the present invention, as a means according to claim 1, the signal transmission line has a pair wiring structure in which two wires are paired, and each characteristic in the pair wiring transmission line and the vertical via The via diameter and via interval were controlled so that the impedance was a constant value.

請求項2に係る手段として、上記請求項1の手段に加え、ビアパッドのサイズをビアの断面積形状と同一、もしくは断面積形状の125%以下のサイズとして形成することに特徴がある。   The means according to claim 2 is characterized in that, in addition to the means of claim 1, the via pad is formed to have the same size as the cross-sectional area of the via or a size of 125% or less of the cross-sectional area.

請求項3に係る手段として、上記請求項1の手段に加え、金属層のペア配線の間隔と、ビアのペア配線の間隔を同等にして形成することに特徴がある。   The means according to claim 3 is characterized in that, in addition to the means of claim 1, the distance between the pair wirings of the metal layer and the distance between the pair wirings of the via are formed to be equal.

請求項4に係る手段として、上記請求項1の手段に加え、上記請求項2と請求項3に係る手段を同時に用いて信号伝送ペア配線を形成することに特徴がある。   The means according to claim 4 is characterized in that, in addition to the means of claim 1, the means according to claims 2 and 3 are used simultaneously to form a signal transmission pair wiring.

請求項5に係る手段として、上記1、2、3及び4を実現する手段として、基板に溝および/または穴を形成し、前記溝部および/または穴部を含む基板表面に金属膜を形成し、その後、表面を機械的研磨で平坦加工して配線パターンおよび/またはビアを形成する製造方法を一部に用いたことに特徴がある。   As means according to claim 5, as means for realizing 1, 2, 3 and 4, grooves and / or holes are formed in the substrate, and a metal film is formed on the substrate surface including the grooves and / or holes. Then, the manufacturing method of forming a wiring pattern and / or a via by flattening the surface by mechanical polishing is used in part.

基板上の伝送線路及び縦方向のビアのそれぞれの特性インピーダンスを同一としたペア配線構造により、数十GHzの高周波においても、周波数に依存する特性の劣化の無い伝送線路を形成することが可能となる。   A pair wiring structure with the same characteristic impedance for each of the transmission line on the substrate and the vertical via enables the formation of a transmission line that does not deteriorate in frequency-dependent characteristics even at high frequencies of several tens of GHz. Become.

以下、図面を参照しながら、本発明の実施の形態について説明する。   Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(実施の形態1)
図1に請求項1に係る信号伝送ペア配線の上面図及び断面図を示す。表面の金属薄膜配線のペア構造は、線路の幅と間隔を制御することで特性インピーダンスがZ0(例えば100Ω)となるよう制御する。誘電体に挟まれた金属薄膜配線のペア構造は、線路の幅と間隔を制御することで特性インピーダンスをZ0となるよう制御する。縦方向ビア配線は、ビアの直径と間隔を制御することで特性インピーダンスがZ0となるように制御する。
(Embodiment 1)
FIG. 1 shows a top view and a cross-sectional view of a signal transmission pair wiring according to claim 1. The pair structure of the metal thin film wiring on the surface is controlled so that the characteristic impedance becomes Z0 (for example, 100Ω) by controlling the width and interval of the lines. The pair structure of metal thin film wirings sandwiched between dielectrics controls the characteristic impedance to be Z0 by controlling the width and interval of the lines. The vertical via wiring is controlled so that the characteristic impedance becomes Z0 by controlling the via diameter and interval.

図2に、ビアの直径とビア間隔の比と、線路のインピーダンスの関係を求めたシミュレーション結果を示す。例えば、100umのビア径に、200umの間隔でビアを形成することにより、インピーダンスを100Ωに制御することが可能である。   FIG. 2 shows a simulation result for determining the relationship between the ratio of the via diameter and the via interval and the impedance of the line. For example, it is possible to control the impedance to 100Ω by forming vias at intervals of 200 μm in a via diameter of 100 μm.

(実施の形態2)
図3は、請求項2に係る信号伝送ペア配線の上面図及び断面図を示す。図1の構造に加え、配線とビアを接続するビアパッド部を、縦方向ビア配線のサイズと同じ、もしくは125%以下のサイズで形成することにより、ビア途中にあるビアパッド部による反射によるノイズを無くして、より信号通過特性のよい伝送線路を形成することができる。
(Embodiment 2)
FIG. 3 shows a top view and a cross-sectional view of a signal transmission pair wiring according to claim 2. In addition to the structure shown in FIG. 1, the via pad part connecting the wiring and the via is formed with the size equal to or smaller than 125% of the size of the vertical via wiring, thereby eliminating noise caused by reflection from the via pad part in the middle of the via. Thus, a transmission line with better signal transmission characteristics can be formed.

(実施の形態3)
図4は、請求項3に係る信号伝送ペア配線の上面図及び断面図を示す。図1の構造に加え、金属層で形成するペア配線と、ビアで形成するペア配線の間隔を一定とすることにより、実現する。
(Embodiment 3)
FIG. 4 shows a top view and a cross-sectional view of the signal transmission pair wiring according to claim 3. In addition to the structure of FIG. 1, this is realized by making the interval between the pair wiring formed with the metal layer and the pair wiring formed with the via constant.

(実施の形態4)
図5は、請求項4に係る信号伝送ペア配線の上面図及び断面図を示す。図1の構造に加え、配線とビアを接続するビアパッド部を、縦方向ビア配線のサイズと同じ、もしくは125%以下のサイズで形成すし、縦方向のビアの直径を誘電体に挟まれた金属膜配線の幅と同じ太さに設計することで実現する。
(Embodiment 4)
FIG. 5 shows a top view and a cross-sectional view of a signal transmission pair wiring according to claim 4. In addition to the structure shown in FIG. 1, a via pad portion for connecting a wiring and a via is formed in a size equal to or smaller than 125% of the size of a vertical via wiring, and the metal having a vertical via diameter sandwiched between dielectrics. This is achieved by designing to the same thickness as the width of the membrane wiring.

(実施の形態5)
図6は、請求項5に記載の信号伝送ペア配線を用いた場合の信号伝達特性と従来の構造による信号伝達特性のシミュレーションによる比較の図である。9層の多層基板を用いた場合のビア構造を含めたペア配線の伝送特性を示している。601は本発明における伝送特性、602は従来技術による伝送特性である。本発明の請求項5の構造を用いることで、許容減衰量を-0.1dB/mmとすると、伝送可能な周波数帯域を35GHzから90GHzへと拡大することができた。
(Embodiment 5)
FIG. 6 is a diagram comparing the signal transmission characteristic when the signal transmission pair wiring according to claim 5 is used and the signal transmission characteristic of the conventional structure by simulation. The transmission characteristics of a pair wiring including a via structure when a 9-layer multilayer substrate is used is shown. Reference numeral 601 denotes transmission characteristics according to the present invention, and reference numeral 602 denotes transmission characteristics according to the prior art. By using the structure of claim 5 of the present invention, it was possible to expand the transmittable frequency band from 35 GHz to 90 GHz when the allowable attenuation was −0.1 dB / mm.

(実施の形態6)
図7は、請求項5に係る配線構造の形成方法の一例である。半導体プロセスで多層配線構造を実現するために用いられるダマシン工程を用いる。請求項5におけるダマシン工程とは、金属配線形成方式の1つで、まず基板に溝を形成し、そこに金属を蒸着した後に表面を機械的研磨で平坦加工してパターンを形成する技術である。まず、(1)のコア回路に、(2)のようにパターンを形成する。(3)のように誘電体を積層し、(4)のようにビア及び配線パターンを同時に誘電体上へ形成する。次に、(5)のようにメッキなどで配線用金属を堆積し、不必要な金属配線706を物理的研磨などを用いて(6)のように除去し配線を形成する。次に、再び(7)(8)(9)の工程を繰り返しながら、多層配線基板を形成する。誘電体上へ、ビアと配線パターンを同時に形成することにより、請求項1,2,3、及び4に示す構造を作り挙げることが可能となる。
(Embodiment 6)
FIG. 7 is an example of a method for forming a wiring structure according to claim 5. A damascene process used to realize a multilayer wiring structure in a semiconductor process is used. The damascene process in claim 5 is one of metal wiring forming methods, in which a groove is first formed on a substrate, a metal is deposited thereon, and then the surface is flattened by mechanical polishing to form a pattern. . First, a pattern is formed on the core circuit of (1) as shown in (2). Dielectrics are stacked as in (3), and vias and wiring patterns are simultaneously formed on the dielectric as in (4). Next, wiring metal is deposited by plating or the like as in (5), and unnecessary metal wiring 706 is removed as in (6) using physical polishing or the like to form wiring. Next, a multilayer wiring board is formed by repeating the steps (7), (8), and (9) again. By simultaneously forming the via and the wiring pattern on the dielectric, it is possible to create the structure shown in claims 1, 2, 3, and 4.

以上のように、本発明によると数十GHzの高周波領域まで特性誤差の無い伝送特性の良好な信号伝送配線の提供が可能となる。   As described above, according to the present invention, it is possible to provide a signal transmission wiring having a good transmission characteristic with no characteristic error up to a high frequency region of several tens of GHz.

本発明請求項1に係る信号伝送ペア配線の上面図及び断面図Top view and sectional view of signal transmission pair wiring according to claim 1 of the present invention 縦方向ビア配線のビア径とビア間隔の比と特性インピーダンスの関係を示したシミュレーション結果の図Simulation results showing the relationship between the via diameter and via spacing ratio and the characteristic impedance of the vertical via wiring 本発明請求項2に係る信号伝送ペア配線の上面図及び断面図Top view and sectional view of signal transmission pair wiring according to claim 2 of the present invention 本発明請求項3に係る信号伝送ペア配線の上面図及び断面図Top view and sectional view of signal transmission pair wiring according to claim 3 of the present invention 本発明請求項4に係る信号伝送ペア配線の上面図及び断面図Top view and sectional view of signal transmission pair wiring according to claim 4 of the present invention 従来の配線構造と本発明による請求項4の構造を用いた場合の伝送特性の比較図Comparison diagram of transmission characteristics when using the conventional wiring structure and the structure of claim 4 according to the present invention 請求項5に係るペア配線構造作製工程の説明図Explanatory drawing of the pair wiring structure preparation process which concerns on Claim 5 背景技術における従来の典型的な信号伝送配線の上面図及び断面図A top view and a cross-sectional view of a conventional typical signal transmission wiring in the background art

符号の説明Explanation of symbols

101 表層の金属層配線
102 誘電体に挟まれた金属層配線
103 配線とビアを接続するビアパッド部
104 縦方向ビア配線
105 誘電体層
601 本発明による伝送特性のグラフ
602 従来技術を用いた配線の伝送特性のグラフ
701 金属配線層
702 誘電体層
703 配線用溝
704 ビアホール
705 ビア配線
706 不必要な金属層

DESCRIPTION OF SYMBOLS 101 Metal layer wiring of surface layer 102 Metal layer wiring pinched | interposed between dielectrics 103 Via pad part which connects wiring and a via 104 Longitudinal via wiring 105 Dielectric layer 601 Graph of transmission characteristic by this invention 602 Wiring using conventional technology Transmission characteristic graph 701 Metal wiring layer 702 Dielectric layer 703 Wiring groove 704 Via hole 705 Via wiring 706 Unnecessary metal layer

Claims (5)

複数のパターニングされた金属層と、誘電体層とを積層し、その層間をビアにより接続して構成する多層基板の信号伝送ペア配線において、
金属層のパターニングされた複数の配線と相互を接続するビアの直径およびビアの間隔を制御し、特性インピーダンスが一定の値となるように配置することを特徴とした信号伝送ペア配線。
In a signal transmission pair wiring of a multilayer substrate in which a plurality of patterned metal layers and dielectric layers are stacked and the layers are connected by vias,
A signal transmission pair wiring characterized by controlling the diameter of vias and the interval between vias interconnecting a plurality of wirings patterned on a metal layer so that the characteristic impedance becomes a constant value.
配線パターンとビアとの接続部における接触面積をビア断面積と同じ大きさもしくはその125%の大きさ以下で形成することを特徴とした請求項1記載の信号伝送ペア配線。 2. The signal transmission pair wiring according to claim 1, wherein a contact area at a connection portion between the wiring pattern and the via is formed to be equal to or smaller than 125% of the via cross-sectional area. 金属層にパターニングされた平面方向ペア配線と、縦方向ビアによるペア配線の間隔が一定になるように形成することを特徴とした請求項1に記載の信号伝送ペア配線。 2. The signal transmission pair wiring according to claim 1, wherein the pair of wirings in the planar direction patterned on the metal layer and the pair wiring by the vertical via are formed so as to have a constant interval. 請求項2及び請求項3に記載の特徴を同時に有することを特徴とした請求項1記載の信号伝送ペア配線。 4. The signal transmission pair wiring according to claim 1, which has the characteristics of claim 2 and claim 3 at the same time. 基板に溝および/または穴を形成し、前記溝部および/または穴部を含む基板表面に金属膜を形成し、その後、表面を機械的研磨で平坦加工して配線パターンおよび/またはビアを形成する製造工程を含むことを特徴とする請求項1〜4のいずれかに記載の信号伝送ペア配線の製造方法。
Grooves and / or holes are formed in the substrate, a metal film is formed on the substrate surface including the grooves and / or holes, and then the surface is flattened by mechanical polishing to form wiring patterns and / or vias. The method for manufacturing a signal transmission pair wiring according to claim 1, further comprising a manufacturing process.
JP2004043819A 2004-02-20 2004-02-20 Signal transmission pair wiring and its manufacturing method Pending JP2005236064A (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100864468B1 (en) * 2006-06-01 2008-10-22 후지쯔 가부시끼가이샤 Buildup board, and electronic component and apparatus having the buildup board
US8104013B2 (en) 2008-05-13 2012-01-24 Renesas Electronics Corporation Design method of semiconductor package substrate to cancel a reflected wave
US8957325B2 (en) 2013-01-15 2015-02-17 Fujitsu Limited Optimized via cutouts with ground references
KR20170080202A (en) * 2015-12-31 2017-07-10 엘지디스플레이 주식회사 Printed circuit board and display device having the same

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100864468B1 (en) * 2006-06-01 2008-10-22 후지쯔 가부시끼가이샤 Buildup board, and electronic component and apparatus having the buildup board
US8304662B2 (en) 2006-06-01 2012-11-06 Fujitsu Limited Buildup board, and electronic component and apparatus having the buildup board
US8104013B2 (en) 2008-05-13 2012-01-24 Renesas Electronics Corporation Design method of semiconductor package substrate to cancel a reflected wave
US8957325B2 (en) 2013-01-15 2015-02-17 Fujitsu Limited Optimized via cutouts with ground references
KR20170080202A (en) * 2015-12-31 2017-07-10 엘지디스플레이 주식회사 Printed circuit board and display device having the same
KR102554093B1 (en) * 2015-12-31 2023-07-10 엘지디스플레이 주식회사 Printed circuit board and display device having the same

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