JP2005236018A - Minute wiring structure and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a minute wiring structure and a manufacturing method of the minute wiring structure capable of high density wiring by simple means. <P>SOLUTION: The minute wiring structure comprises a sheet-shaped insulator 2, a plurality of first line conductors 3... embedded in the side of one surface 2a side of the insulator 2, and a plurality of second line conductors 4...embedded in the side of the other surface 2b of the insulator 2. In the insulator 2, the first line conductors 3... and the second line conductors 4... are repeatedly alternately arranged, and the first line conductors 3... are disposed in the thickness direction of the insulator 2, biassed to the one surface 2a while the second line conductors 4... are disposed, biassed to the other surface 2b. Further, the first and second line conductors 3... and 4... are overlapped mutually partly in the thickness direction of the insulator 2. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a fine wiring structure and a method for manufacturing the fine wiring structure, and more particularly, to a fine wiring structure and a fine wiring structure manufacturing method capable of achieving high-density wiring by simple means.

  Conventionally, a semiconductor manufacturing process such as a thin film forming process has been applied to the formation of a fine wiring structure required for a high-density mounting substrate. In other words, the formation of the conventional fine wiring structure requires expensive equipment such as a vacuum sputtering apparatus, i-line stepper, G-line stepper, etc., and a clean room for installing these apparatuses and operations accompanying these operations. Expense was necessary. On the other hand, the mounting wiring board must be kept as low as possible in capital investment for manufacturing on the premise of low cost. Therefore, realization of a manufacturing method of a fine wiring structure at low cost is demanded.

Recently, a number of proposals related to the manufacture of fine wiring structures have been made. For example, Patent Document 1 below discloses a method for manufacturing a multilayer wiring board in which the interval between wiring circuit patterns is made narrow by combining electrolytic plating and formation of a permanent resist layer.
JP 2003-264368 A

  However, in the method described in Patent Document 1 as well, as is clear from each step shown in FIG. 2 of the same document, the pitch between wirings in one circuit layer is about 5 μm at the minimum and the wiring width is about 5 μm at the minimum. In order to manufacture such a narrow-pitch wiring structure, there is a problem that expensive equipment is required as described above, and the number of processes is large and the manufacturing of the wiring structure is extremely complicated.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a fine wiring structure capable of forming a high-density wiring by a simple means and a method for manufacturing the fine wiring structure.

In order to achieve the above object, the present invention employs the following configuration.
The fine wiring structure of the present invention includes a sheet-like insulator, a plurality of first line conductors embedded on one surface side of the insulator, and a plurality of second line conductors embedded on the other surface side of the insulator. The first line conductor and the second line conductor are repeatedly and alternately arranged inside the insulator, and along the thickness direction of the insulator, the first line conductor Is disposed near the one surface, the second line conductor is disposed near the other surface, and the first and second line conductors partially overlap each other along the thickness direction of the insulator. It is characterized by.

  According to the above configuration, since the first line conductor is embedded from one side of the insulator and the second line conductor is embedded from the other side, the first and second line conductors are formed from both sides of the insulator. Can be made close to each other, and the pitch between the line conductors can be narrowed. Further, since the first and second line conductors overlap each other, the entire first and second line conductors can be regarded as one wiring structure.

  Further, the method for manufacturing a fine wiring structure according to the present invention includes a step of forming a plurality of first line conductors on the first substrate at regular intervals, and a plurality of second line conductors on the second substrate at regular intervals. And forming the first substrate and the second substrate on one side and the other side of the sheet-like insulator, respectively, and arranging the first and second line conductors on the one side and the other, respectively. The first line conductor and the second line conductor are repeatedly and alternately arranged inside the insulator by pressing the first and second substrates against the insulator after facing each other. And a step of embedding the first and second line conductors in the insulator.

  According to the above configuration, since the line conductors are alternately arranged inside the insulator, the interval between the first line conductors may be slightly larger than the conductor width of the second line conductor. The same applies to the second line conductor. Therefore, a highly accurate semiconductor manufacturing process is not required for forming the first and second line conductors, and the manufacturing process can be simplified.

  According to the fine wiring structure and the manufacturing method of the fine wiring structure of the present invention, high density wiring can be realized by simple means.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a schematic cross-sectional view of the fine wiring structure of the present embodiment, and FIG. 2 is a perspective view of the main part of the fine wiring structure.
As shown in FIGS. 1 and 2, the fine wiring structure 1 of the present embodiment includes a sheet-like insulator 2 and a plurality of first line conductors 3 embedded on one surface 2 a side of the insulator 2. A plurality of second line conductors 4 embedded in one surface 1a of the insulator 2 and the other surface 2b side opposite to the one surface 1a are schematically configured. The first line conductors 3 and the second line conductors 4 are formed in a line shape from the near side to the far side in FIGS. 1 and 2. Further, the insulator 2 is interposed between the first line conductors 3... And the second line conductors 4... In addition to insulating the first and second line conductors 3, 4, the insulator 2 integrally holds the line conductors 3, 4,. For example, the insulator 2 is preferably a thermoplastic resin such as an epoxy resin, a polyacrylic resin, or a polyester resin. Further, adhesive layers 104 and 204 are interposed between the insulator 2 and the first and second line conductors 3. Note that the adhesive layers 104 and 204 may be omitted.

As shown in FIG. 1, the first line conductors 3 are embedded in the insulator 2 with their one surface 3 a exposed from the one surface 2 a side of the insulator 2. The first line conductors 3 are arranged in parallel to each other, and the second line conductor 4 is arranged between the first line conductors 3 and 3.
The second line conductors 4 are embedded in the insulator 2 in a state where one surface 4a of the second line conductors 4 is exposed from the other surface 2b side of the insulator 2 in the same manner as the first line conductors 3. The second line conductors 4 are arranged in parallel to each other, and the first line conductor 3 is arranged between the second line conductors 4, 4.
The first and second line conductors 3..., 4... Are made of, for example, a metal such as Cu or Ni. However, any metal may be used as long as it can be electroplated and has excellent conductivity.

Next, as shown in FIG. 2, the first and second line conductors 3, 4,... Are repeatedly and alternately arranged inside the insulator 2. In FIG. 2, the insulator is not shown for ease of explanation, but in FIG. 2, the insulator 2 is each of the wall surfaces defining the first and second line conductors 3, 4,. One surface 3a ... is arranged so as to cover surfaces other than 4a. An interval w ₁ between the first line conductors 3 and 3 or the second line conductors 4 and 4 is set in a range of 40 μm to 200 μm, for example. The first adjacent spacing _{w 2} of the second line conductor 3, 4 is set in a range of less than 100μm example 20μm or more. Further, the conductor width w ₃ of the first and second line conductors 3... 4 is set in a range of, for example, 10 μm to 90 μm. The interval w ₁ may be changed according to the interval w ₂ and the conductor width w ₃ . The conductor width w ₃ may be changed for each conductor may be aligned conductor width w ₂ to the same value for all the conductors. However, the spacings w ₁ and w ₂ and the conductor width w ₃ need to be adjusted so that the first and second line conductors 3... 4. That is, the distance between the first line conductors 3 and 3 may be slightly larger than the conductor width of the second line conductor 4. The same applies to the second line conductors 4. Furthermore, the distances w ₁ and w ₂ and the conductor width w ₃ may be adjusted in consideration of the material, thickness and the like of the insulator 2.

As shown in FIG. 2, the first line conductors 3 are arranged near the one surface 2a of the insulator 2 along the thickness direction of the insulator 2 (the direction of the arrow D in the figure), and the second line conductors 4. Is disposed closer to the other surface 2b. Then, the first and second line conductors 3, 4,... Partially overlap each other along the thickness direction D of the insulator 2. That is, as shown in FIG. 2, the distance between the one surface 3a of the first line conductor 3 and the one surface 4a of the second line conductor 4 is d, and the conductor thicknesses of the first and second line conductors 3 and 4 are d _1. , D ₂ , the first and second line conductors are arranged so that d <(d ₁₊ d ₂ ). With this configuration, the thickness of the fine wiring structure itself can be reduced. In addition, when the first and second line conductors 3... 4 completely overlap each other, that is, when d = d ₁ or d = d ₂ , the insulator 2 is divided as described later, which is preferable. Absent.

Further, by arranging the first line conductors 3 near the one surface 2a and arranging the second line conductors 4 near the other surface 2b and exposing the one surface 3a, 4a of each conductor from the insulator 2, for example, When other elements are connected to the first and second line conductors 3... 4, the elements can be directly connected to the respective surfaces 3 a and 4 a, thereby facilitating circuit formation. it can.
Further, since the insulator 2 is interposed between the first line conductors 3 ... and the second line conductors 4 ..., the first and second line conductors 3, 4 are not likely to be short-circuited with each other, and the first, second Current leakage between the two-line conductors 3 and 4 can also be prevented.

  FIG. 3 shows an example in which the fine wiring structure 1 is applied to a circuit board. The circuit board 10 shown in FIG. 3 forms the wiring structures 1 and 1 of this embodiment on both surfaces of the epoxy resin plate 11, respectively, and a passive element 12 is connected to one of the fine wiring structures. Insulators 2 and 2 constituting each fine wiring structure 1 and 1 are laminated with insulating resist layers 13 and 13. The passive element 12 is electrically connected to the first line conductors 3 and 3 provided in one fine wiring structure 1 via solder balls 12a. Further, the epoxy resin plate 11 is provided with a through hole 11a, and the first line conductor 3 and the second line conductor 4 provided in each of the fine wiring structures 1 and 1 are connected to each other through the through hole 11a. Has been.

  According to the fine wiring structure 1 of the present embodiment, a circuit board 10 having a multilayer structure as shown in FIG. 3 can be easily formed. Moreover, since the 2nd line conductor 4 is arrange | positioned between the 1st line conductors 3 and 3, the space | interval of 1st line conductors 3 and 3 spreads, and attachment of the passive element 12 etc. can be performed easily. it can.

  Next, the manufacturing method of the fine wiring structure of this embodiment is demonstrated with reference to drawings. 4 and 5 show process drawings of a method for manufacturing a fine wiring structure. The method for manufacturing the fine wiring structure includes a step of forming first and second line conductors as shown in FIG. 4, and a step of embedding the first and second line conductors in an insulator as shown in FIG. , Is roughly composed.

  First, in the step of forming the first and second line conductors, the first and second line conductors are formed on the first and second substrates, respectively, with a certain interval. FIG. 4 shows only the step of forming the first line conductor on the first substrate, and the step of forming the second line conductor is the same as the step of forming the first line conductor, so that the description thereof is omitted.

First, as shown in FIG. 4A, a first substrate 101 and a conductive seed layer 102 laminated on the first substrate 101 are prepared. The first substrate 101 is a substrate made of, for example, glass or the like with extremely high flatness, whose surface roughness is set to 0.1 to 0.3 μm or less. Further, for example, a copper sputtered film having a thickness of about 2 μm can be used for the conductive seed layer 102.
Next, as shown in FIG. 4B, a plating resist 103 made of a high resolution photoresist is formed on the conductive seed layer 102. The plating resist 103 has a pattern portion 103a for forming the first line conductor. The conductive seed layer 102 is exposed on the bottom surface of the pattern portion 103a. In order to form the plating resist 103 having the pattern portion 103a, a resist layer is formed on the first substrate by a spin coat method or the like, and then exposure and development are performed using a photomask, whereby a pattern is formed. It is formed by removing the resist to be a part. The width of the pattern portion 103a may be slightly larger than the width of the second line conductors 4 and may be about several tens of μm to several tens of μm. Specifically, when the width of the second line conductor is set to 10 μm, the width of the pattern portion 103a may be set to about 15 μm. As described above, since the width of the pattern portion 103a is about several tens of μm to several tens of μm, the pattern portion 103a can be formed with conventional accuracy, and it is not necessary to use special equipment.

Next, as shown in FIG. 4C, a plurality of first line conductors 3 made of copper are formed in parallel by electroplating. Specifically, a plating solution containing copper sulfate or the like is brought into contact with the conductive seed layer 102 exposed from the pattern portion 103a, and electrolytic plating is performed using the conductive seed layer 102 as an electrode, whereby the first pattern portion 103a. Line conductors 3 are formed. The thickness of the first line conductors 3 is preferably about 7 μm, for example. The conductor width of the first line conductors 3 is preferably about 10 μm, for example.
Next, as shown in FIG. 4D, after the plating resist 103 is removed, an adhesive layer 104 is applied to the first line conductors 3 and the conductive seed layer 102. The thickness of the adhesive layer 104 is preferably about 0.1 μm. In this way, a plurality of first line conductors 3 are formed on the first substrate 101 at predetermined intervals.

Next, the process of embedding the first and second line conductors in the insulator will be described. First, as shown in FIG. 5A, a sheet-like insulator 2 made of an epoxy resin, a polyester resin, or the like is prepared, the first substrate 101 is disposed on the one surface 2 a side of the insulator 2, and the other surface of the insulator 2 is arranged. The second substrate 201 is disposed on the 2b side. Further, the relative positions of the first and second substrates 101 and 201 are adjusted so that the second line conductor 4 is positioned between the first line conductors 3 and 3. Further, the first and second substrates 101 and 201 are arranged so that the first and second line conductors 3, 4. Further, the insulator 2 at this time preferably has a thickness of about 10 μm to 100 μm.
The second line conductors 4 are formed by sequentially laminating the conductive seed layer 202, the second line conductors 4 and the adhesive layer 204 on the second substrate 201 in the same manner as in FIGS. 4A to 4D. It has been done.

  Next, the first and second substrates 101 and 201 are pressed against the insulator 2 and hot pressed. The insulator 2 is deformed by this heat press and is sandwiched between the first and second line conductors 3... 4, and the first and second line conductors 3. Insulated. The temperature at the time of hot pressing depends on the material of the insulator 2, but is preferably in the range of 140 to 180 ° C. The pressure of the hot press is preferably about 15 to 25 Pa. Further, the pressing time is preferably about 30 to 50 minutes. The first and second line conductors 3, 4,... Are embedded in the insulator 2 by this hot pressing. In this way, the first line conductors 3 and the second line conductors 4 are repeatedly and alternately arranged in the insulator 2. At this time, the pressure of the hot press is adjusted so that the first line conductors 3 ... and the second line conductors 4 ... do not completely overlap in the thickness direction. If the first and second line conductors 3... 4 completely overlap, the insulator 2 is divided and the fine wiring structure 1 itself is destroyed.

  Next, as shown in FIG. 5C, the first and second substrates 101 and 102 sandwiching the insulator 2 are removed, and further, as shown in FIG. 5D, wet etching using a 10% ferric chloride aqueous solution as an etchant solution. Thus, the conductive seed layers 102 and 202 are removed. By removing the conductive seed layers 102 and 202, the first and second line conductors 3, 4, one surface 3 a, 4 a,... Are exposed from the one surface 2 a and the other surface 2 b of the insulator 2. In this way, a fine wiring structure 1 as shown in FIG. 1 is obtained.

  According to said structure, the space | interval of 1st, 2nd line conductors 3 ... 4 ... is adjusted to about several micrometers thru | or several dozen micrometer, and each line conductor 3 ... 4 ... is alternated inside the insulator 2. By arranging them side by side, the distance between the adjacent first and second line conductors 3 and 4 can be reduced to about several μm or less. As described above, the interval between the line conductors 3 and 4 can be set to several μm or less without using expensive equipment such as a stepper device. This eliminates the need for a highly accurate semiconductor manufacturing process when forming the first and second line conductors, and simplifies the manufacturing process.

A copper sputtered film having a thickness of 2 μm was formed on a glass substrate to form a conductive seed layer. A resist layer was laminated on the conductive seed layer, and exposure and development were performed to form a plating resist having a comb-like pattern portion. Next, electrolytic plating was performed to form a comb-shaped first line conductor made of copper in the pattern portion of the plating resist. The resist for plating was removed after forming the first line conductor.
Further, in the same manner as the formation of the first line conductor, a comb-shaped second line conductor was formed on another glass substrate.

  Next, an insulator sheet made of an epoxy resin having a thickness of 20 μm is prepared, and the first line conductor and the second line conductor previously formed on one surface and the other surface of the insulator sheet are opposed to each other. Hot pressing was performed under conditions of a pressing pressure of 2 MPa and a pressing time of 50 minutes, and the first and second line conductors were embedded on one side and the other side of the insulating sheet, respectively. Thereafter, the glass substrate and the conductive seed layer were removed.

In this way, as shown in FIG. 6, a meander line in which a pair of comb-shaped line conductors are arranged in parallel with each other was formed. In addition, as shown in FIG. 6, the conductor width (w ₃ ) of the comb-like conductor is 10 μm, the interval (w ₂ ) between the adjacent first and second line conductors is 10 μm, The interval (w ₁ ) was 30 μm. Moreover, the length of the parallel part of conductors was 150 μm.

The inductance of the obtained meander line was measured and found to be 0.4 nH. In addition, no current leakage was observed between the comb electrodes. Thus, although the distance between the first and second line conductors is very close to 10 μm, the insulation between the first and second line conductors was good.
Further, in this embodiment, the first and second line conductors having a comb-teeth shape with an interval (w ₁ ) of 30 μm are formed, and these line conductors are integrated with the insulator sheet, whereby the first and second A meander line having an interval (w ₂ ) between two line conductors of 10 μm can be easily formed, and can be formed using a film forming apparatus or an exposure apparatus with relatively low accuracy.

FIG. 1 is a schematic cross-sectional view showing an example of a fine wiring structure according to an embodiment of the present invention. FIG. 2 is a perspective view schematically showing a main part of a fine wiring structure according to an embodiment of the present invention. FIG. 3 is a schematic cross-sectional view showing an example of a circuit board provided with the fine wiring structure of the present invention. FIG. 4 is a process diagram illustrating a method for manufacturing a fine wiring structure according to an embodiment of the present invention. FIG. 5 is a process diagram illustrating a method for manufacturing a fine wiring structure according to an embodiment of the present invention. FIG. 6 is a schematic plan view showing the meander line of the example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Fine wiring structure, 2 ... Insulator, 2a ... One side, 2b ... Other side, 3 ... 1st line conductor, 4 ... 2nd line conductor, 101 ... 1st board | substrate, 102 ... 2nd board | substrate

Claims (2)

A sheet-like insulator, a plurality of first line conductors embedded on one side of the insulator, and a plurality of second line conductors embedded on the other side of the insulator;
Inside the insulator, the first line conductor and the second line conductor are repeatedly and alternately arranged, and the first line conductor is arranged closer to the one surface along the thickness direction of the insulator. And the second line conductor is disposed closer to the other surface, and the first and second line conductors partially overlap each other along the thickness direction of the insulator. Fine wiring structure. Forming a plurality of first line conductors on the first substrate at regular intervals;
Forming a plurality of second line conductors on the second substrate at regular intervals; and
After disposing the first substrate and the second substrate on the one surface side and the other surface side of the sheet-like insulator, respectively, the first and second line conductors are respectively opposed to the one surface and the other surface, By pressing the first and second substrates against the insulator, the first line conductor and the second line conductor are repeatedly and alternately arranged inside the insulator. And a step of embedding the two-line conductor in the insulator.

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