JP2005235820A - Method of calculating model formula of circuit simulation - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a model formula of circuit simulation which can be applied even if a channel length is further shortened. <P>SOLUTION: The method of calculating the model formula of circuit simulation comprises steps of calculating first parasitic resistance which is not dependent on a gate voltage from actual measurement data of a semiconductor element; calculating second parasitic resistance which is dependent on a gate voltage from I-V characteristics from which the first parasitic resistance has been removed; and separating the second parasitic resistance from channel resistance and third parasitic resistance formed on both sides below a gate length by using various kinds of diffusion resistors TEG with the same width W but with a different length L. An I-V characteristic formula is obtained by using the third parasitic resistance as an independent characteristic. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  In the present invention, for the purpose of improving the accuracy and speed of a circuit simulator used in designing an integrated circuit, model parameters are extracted by a method of decomposing measured data, and the model parameters are used to be incorporated in the circuit simulator. The present invention relates to a method for calculating a model expression for circuit simulation for obtaining a model expression.

  In the prior art, the LEVEL 1 model was developed at the University of California, Berkeley in the early days. Thereafter, as the channel length becomes shorter, the LEVEL2 and LEVEL3 models have been developed by the same university. The BSIM model, the BSIM2 model, the BSIM3 model, and the BSIM4 model have been developed one after another by the university since the channel length was less than 1 μm. In industry, Fairchild has developed the MOS9 model, which is an improvement of the BSIM model. Recently, a HiSIM model has been developed at Hiroshima University in Japan.

  Conventional models have ignored parasitic resistances to speed up circuit simulators. Furthermore, when the parasitic resistance cannot be ignored, we have developed a model formula that incorporates the parasitic resistance. However, there is a problem that new models must be created one after another as the channel length becomes shorter because no model formula based on physical phenomena has been developed by decomposing from measured data. Furthermore, there is a problem that it is difficult to obtain model parameters from actually measured data. Further, in the case of a special process such as a high breakdown voltage process, there is a problem that another model formula has been developed despite the same Tr structure.

  Accordingly, an object of the present invention is to obtain a model expression of a circuit simulator that can be applied even when the channel length is further shortened.

According to a first aspect of the present invention, there is provided a method for calculating a model equation for circuit simulation according to the present invention, comprising: calculating a first parasitic resistance that does not depend on a gate voltage from actual measurement data of a semiconductor element; The step of calculating the second parasitic resistance depending on the gate voltage from the V characteristic and the use of a plurality of types of diffused resistors TEG having the same width W and different lengths L of the diffused resistors, A step of separating the channel resistance and the third parasitic resistance generated on both sides under the gate length, and obtaining the IV characteristic equation by using the third parasitic resistance as an independent characteristic. It is characterized by.
According to a second aspect of the present invention, in the circuit simulation model formula calculation method according to the first aspect, in the MOSFET, the drain-source voltage is V _DS , the current flowing through the channel is I _DS , and the drain-source voltage is When the resistance is R _OUT , the drain end and source end contact resistance is R _CON , the drain diffusion resistance is RD, the source diffusion resistance is RS, the LDD resistance under the gate is R _LDD , and the channel resistance under the gate is _RC From the I ' _DS -V _GS characteristics without parasitic resistance (2 · R _CON + RD + RS) independent of the gate voltage, the following formula (1)

As the diffusion resistance TEG, if the output resistance of the gate length L1 is R _OUT 1 and the output resistance of the gate length L2 is R _OUT 2, then R _OUT 1 = 2 · R _LDD + _RC 1, R _OUT Since 2 = 2 · R _LDD + _RC 2, the following formula (2) is obtained from R _OUT , R _OUT 1 and R _OUT 2.

And using R _OUT 1 and R _OUT 2, the third parasitic resistance (2 · R _LDD ) generated on both sides under the gate length L is _expressed by the following equation (3).

It is characterized by.
According to a third aspect of the present invention, in the MOSFET simulation model formula calculation method according to the first aspect, in the MOSFET, the drain-source voltage is V _DS , the drain-source resistance is R _OUT , the drain end, When the source end contact resistance is R _CON , the drain diffusion resistance is RD, the source diffusion resistance is RS, the X axis is V _DS , and the Y axis is R _OUT , the coordinates (0, b) and V _DS voltage intersect at one point The error between the straight line passing through the two points with the coordinate (X, Y ₁ ) on the high voltage side and the coordinates (x ₁ , y ₁₁ ), (x ₂ , y ₂₁ ), Λ, and the coordinates (0, From the error between the straight line passing through the two points b) and the coordinates (X, Y ₁ ) on the high voltage side of the V _DS voltage and the coordinates (x ₁ , y ₁₂ ), (x ₂ , y ₂₂ ), Λ The error of the following equation (4)

(However, if (Y ₁ −b) is greater than or equal to a predetermined value, this coordinate is removed.) B of the coordinate (0, b) that minimizes the overall error is defined as a parasitic resistance (independent of the gate voltage) RD + RS + 2 · R _CON ).

  In the present invention, model parameters can be obtained by decomposing actual measurement data, and a model equation is constructed from the resistance data of the decomposed three regions. Therefore, all the gate lengths from the long channel to the short channel are one model equation. In the case of a special process such as a high voltage process, it is not necessary to develop another model formula and it can be applied to a process that will be developed in the future. Is fundamentally different.

Embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a structural diagram showing a cross section along a channel of a MOSFET.
As shown in FIG. 1, when the drain-source voltage of the MOSFET is V _DS and the current flowing through the channel is I _DS , the drain-source resistance is R _OUT . R _OUT is composed of drain end, source end contact resistance R _CON , drain diffusion resistance RD, source diffusion resistance RS, LDD resistance R _LDD under the gate, and channel resistance R _C under the gate. The internal voltage V ′ _DS generated at both ends of the channel is a potential difference of the channel resistance R _C and is clearly lower than V _DS by a voltage drop of (2 · R _CON + RD + RS + 2 · R _LDD ) × I _DS .
From FIG. 1, the following three formulas are established.
V _DS = R _OUT · I _DS (5)
R _OUT = 2 · R _CON + RD + RS + 2 · R _LDD + R _C (6)
V ′ _DS = (2 · R _LDD + R _C ) · I _DS (7)
If the level 3 model is used for the channel current equation of the MOSFET, it can be expressed by the following three equations.

L _eff = L-2 · LD (9)
W _eff = W−2 · WD (10)

FIG. 2 shows an I _DS -V _GS characteristic diagram of the MOSFET, and FIG. 3 shows an I _DS -V _DS characteristic diagram of the MOSFET.
Figure 4 is calculated to obtain the R _OUT -V _DS characteristics from I _DS -V _DS characteristics of the MOSFET shown in FIG. 3, the R _OUT -V _DS characteristics, the parasitic resistance that is independent of the gate voltage _{(2 · R CON + RD +} RS) Shows how to do. In other words, the MOSFET gate current I _DS is reduced in flowing current due to the influence of the parasitic resistance (2 · R _CON + RD + RS) independent of the gate voltage. Therefore, the parasitic resistance (2 · R _CON + RD + RS) independent of the gate voltage common to all the MOSFETs is obtained from the R _OUT -V _DS characteristics of the plurality of MOSFETs.
From Expression (7) and Expression (8), Expression (11) is obtained.

  Substituting equation (11) into equation (6) yields equation (11).

From the equation (12), the term of R _C is a straight line in which the slope of the resistance changes depending on the gate voltage V _GS , and the intersection is a parasitic resistance (2 · R _CON + RD + RS) that does not depend on the gate voltage.

FIG. 5 is a characteristic diagram showing an embodiment of the present invention, and specifically explains a method for calculating a parasitic resistance independent of the gate voltage of FIG.
First, assuming that the coordinates intersecting at one point are (0, b) and the coordinates on the high voltage side of the V _DS voltage are (X, Y ₁ ), the straight line passing through these two points is expressed by equation (13).

When the error between this straight line and the coordinates (x ₁ , y ₁₁ ), (x ₂ , y ₂₁ ), Λ is obtained, the error from the coordinates (x ₁ , y ₁₁ ) is expressed by equation (14).

At this time, if the relative error = error / (Y ₁ −b) ≧ 0.001, this coordinate is removed. Further, the error from the coordinates (x ₂ , y ₂₁ ) is expressed by equation (15).

At this time, if the relative error = error / (Y ₁ −b) ≧ 0.001, this coordinate is removed.
Thereafter, the same operation is repeated.

  The error is generally expressed by equation (16).

Next, assuming that the coordinates intersecting at one point are (0, b) and the coordinates on the high voltage side of the V _DS voltage are (X, Y ₂ ), the straight line passing through these two points is expressed by equation (17).

When the error between this straight line and the coordinates (x ₁ , y ₁₂ ), (x ₂ , y ₂₂ ), Λ is determined, the error from the coordinates (x ₁ , y ₁₂ ) is expressed by equation (18).

At this time, if the relative error = error / (Y ₁ −b) ≧ 0.001, this coordinate is removed. Further, an error from the coordinates (x ₂ , y ₂₂ ) is expressed by Expression (19).

At this time, if the relative error = error / (Y ₁ −b) ≧ 0.001, this coordinate is removed.
Thereafter, the same operation is repeated.

  The error is generally expressed by equation (20).

  Therefore, the overall error is as shown in the following equation (21).

The b of the coordinate (0, b) that minimizes the overall error is the parasitic resistance (2 · R _CON + RD + RS) independent of the gate voltage.

In other words, the IV characteristics excluding the parasitic resistance that does not depend on the gate voltage are obtained as follows.
First, in _{R OUT = V DS / I DS} , calculates the R _{OUT.
Next, 2 · R LDD + R C} = R OUT - in _{(2 · R CON + RD +} RS), and calculates the 2 · R _LDD + R _C.
Further, I ′ _DS is recalculated by the following equation (22).

Here, the parasitic resistance that does not depend on the gate voltage is 2 · R _CON + RD + RS, and the parasitic resistance that depends on the gate voltage is 2 · R _LDD + _RC .

FIG. 6 is a configuration diagram showing a cross section perpendicular to the channel of the MOSFET. As shown in FIG. 6, the cross-sectional diffusion length (WD) of the MOSFET is the length of the anti-inversion layer that has entered under the gate width W, and the cross-sectional diffusion length (2WD) of the MOSFET generated on both sides of the gate width W. Is the effective channel width W _eff . Considering WD is important in order to reduce the error between the actual measurement and the simulation.

FIG. 7 is an I _DS -W characteristic diagram showing how to obtain 2WD. The drain current I _{DS of the} MOSFET is less current flowing due to the influence of 2WD. Therefore, the cross-sectional diffusion length (2WD) of the MOSFETs generated on both sides of the gate width W shown in FIG. 3 is obtained from the I ′ _DS −V _GS characteristics with the parasitic resistance independent of the gate voltage removed for a plurality of MOSFETs. Ask.
Substituting equation (9) into equation (8) yields equation (23).

(23) from the equation, the gate length L of the MOSFET are the same, the gate width W with a plurality of different MOSFET, as shown in FIG. 7, takes the gate width W in the X-axis drain current I _DS in the Y-axis 2 · WD can be obtained from the intersection of the straight line connecting the same gate voltages V _GS and the X axis.

FIG. 8 is a diagram showing an embodiment of the present invention. The I ′ _DS −V _GS characteristic obtained by removing the parasitic resistance independent of the gate voltage is used to generate the I ′ _DS −W characteristic, and the gate width W A specific method for obtaining the cross-sectional diffusion length (2WD) of MOSFETs generated on both sides is described.
First, assuming that the coordinates that intersect at one point are (a, 0) and the coordinates of the long width are (X, Y ₁ ), the straight line passing through these two points is expressed by equation (24).

When the error between this straight line and the coordinates (x ₁ , y ₁₁ ), (x ₂ , y ₂₁ ), Λ is obtained, the error between the coordinates (x ₁ , y ₁₁ ) is expressed by equation (25).

The error from the coordinates (x ₂ , y ₂₁ ) is expressed by equation (26).

  Thereafter, the same operation is repeated.

  The error is generally expressed by equation (27).

Next, assuming that the coordinates that intersect at one point are (a, 0) and the coordinates of the long width are (X, Y ₂ ), the straight line passing through these two points is expressed by equation (28).

When the error between this straight line and the coordinates (x ₁ , y ₁₂ ), (x ₂ , y ₂₂ ), Λ is obtained, the error between the coordinates (x ₁ , y ₁₂ ) is expressed by equation (29).

Further, an error from the coordinates (x ₂ , y ₂₁ ) is expressed by Expression (30).

  Thereafter, the same operation is repeated.

  The error is generally expressed by equation (31).

  Therefore, the overall error is as shown in the following equation (32).

  The a of the coordinate (a, 0) that minimizes the overall error is the cross-sectional diffusion length (2WD) of the MOSFET generated on both sides of the gate width W.

FIG. 9 is a diagram showing an embodiment of the present invention. The length of the parasitic resistance generated on both sides under the gate length L from the I ′ _DS −V _GS characteristic obtained by removing the parasitic resistance independent of the gate voltage. Explains how to obtain (2LD).
When the parasitic resistance (2 · R _CON + RD + RS) that does not depend on the gate voltage is removed from Expression (12), Expression (33) is obtained.

From Equation (33), using a plurality of TEGs having the same MOSFET gate width W and different gate lengths L, the external resistance R _OUT is taken as the Y axis and the gate length L as the X axis as shown in FIG. 2 · LD can be obtained from the intersection of the straight line connecting the same gate voltages V _GS and the X axis.

FIG. 11 is a diagram showing an embodiment of the present invention. The R ′ _OUT −L characteristic is generated using the I ′ _DS −V _GS characteristic from which the parasitic resistance independent of the gate voltage is removed. A specific method for obtaining the length (2LD) of the parasitic resistance generated on both sides of the circuit is described.
First, assuming that the coordinates that intersect at one point are (a, 0) and the coordinates of the long length are (X, Y ₁ ), the straight line passing through these two points is expressed by equation (34).

When the error between this straight line and the coordinates (x ₁ , y ₁₁ ), (x ₂ , y ₂₁ ), Λ is obtained,
The error from the coordinates (x ₁ , y ₁₁ ) is expressed by Equation (35).

Further, an error from the coordinates (x ₂ , y ₂₁ ) is expressed by Expression (36).

  Thereafter, the same operation is repeated.

  The error is generally expressed by equation (37).

Next, assuming that the coordinates intersecting at one point are (a, 0) and the long-length coordinates are (X, Y ₂ ), the straight line passing through these two points is expressed by equation (38).

When the error between this straight line and the coordinates (x ₁ , y ₁₂ ), (x ₂ , y ₂₂ ), Λ is determined, the error from the coordinates (x ₁ , y ₁₂ ) is expressed by Equation (39).

Further, the error from the coordinates (x ₂ , y ₂₁ ) is expressed by equation (40).

  Thereafter, the same operation is repeated.

  The error is generally expressed by equation (41).

  Therefore, the overall error is as shown in the following equation (42).

  The a of the coordinate (a, 0) that minimizes the overall error is the length (2LD) of the parasitic resistance generated on both sides under the gate length L.

FIG. 12 is a diagram for explaining the basic principle for _obtaining the parasitic resistance (2 · R _LDD ) generated on both sides under the gate length L. The contact resistance R _CON always exists in the diffusion resistance TEG. Therefore, when the diffusion resistance is measured with one TEG, a resistance including the contact resistance R _CON is obtained. Therefore, the contact resistance (R _CON ) and the diffusion resistance (RD or RS) can be separated by using two types of diffusion resistances TEG having the same width W and different length L.
From (a) of FIG. 12, the output resistance R _OUT 1 is
R _OUT 1 = 2 ・ R _CON + R _D1 (43)
From (b) of FIG. 12, the output resistance R _OUT 2 is
R _OUT 2 = 2 ・ R _CON + R _D2 (44)
It is.
When the diffusion resistance is expressed using the diffusion sheet resistance R _SH , the expressions (43) and (44) are rewritten as the following expressions (45) and (46), respectively.

By removing the contact resistance (R _CON ) from the equations (45) and (46), the diffusion sheet resistance (R _SH ) is obtained.

Substituting equation (47) into equation (45) gives the contact resistance (R _CON ).

  When Expression (47) and Expression (48) are substituted into Expression (45) and Expression (46), respectively, Expression (49) and Expression (50) are obtained.

FIG. 13 is a diagram for explaining the separation of the channel resistance (R _C ) and the parasitic resistance (2 · R _LDD ) generated on both sides under the gate length L. By applying the method described in FIG. 12, the channel resistance (R _C ) and the parasitic resistance (2 · R _LDD ) generated on both sides under the gate length L can be separated.
From FIG. 13 (a), the output resistance (R _OUT 1) is
R _OUT 1 = 2 ・ R _LDD + R _C1 (51)
From FIG. 13 (b), the output resistance (R _OUT 2) is
R _OUT 2 = 2 ・ R _LDD + R _C2 (52)
It becomes.
When Expression (33) is simplified, Expression (53) is obtained.

When the output resistance (R _OUT 1) of FIG. 13 (a) is expressed using the equation (53), the equation (54) is obtained.

When the output resistance (R _OUT 2) in FIG. 13B is expressed using the equation (53), the equation (55) is obtained.

  From Equation (54) and Equation (55),

  From FIG. 13 (a), equation (57) is obtained.

  From FIG. 13 (b), equation (58) is obtained.

From the equations (57) and (58), the channel resistance (R _C ) is expressed by the following equation (59).

Substituting Equation (57) and Equation (58) into Equation (54) and Equation (55), respectively, the parasitic resistance (2 · R _LDD ) generated on both sides under the gate length L is expressed by the following equation (60 ).

However, 2 · R _LDD is inversely proportional to W _eff · (V _GS −V _TH −1 / 2 · V ′ _DS ), and can be regarded as a sheet resistance (R _SHLDD ) proportional to 2 · LD. When this is expressed by an equation, the equation (61) is obtained.

  When Expression (59) and Expression (61) are combined, Expression (62) is obtained.

Hereinafter, a method for extracting model parameters by decomposing actual measurement data of an integrated circuit according to the present invention will be described.
FIG. 14 is a flowchart showing a method of extracting MOSFET model parameters.
First, a method for calculating the parasitic resistance that does not depend on the gate voltage in the MOSFET will be described.
The R _OUT -V _DS characteristic is obtained using the I _DS -V _DS characteristic of the MOSFET (step 1), and this R _OUT -V _DS characteristic is stored (step 2). Then, using the R _OUT -V _DS characteristic stored in step 2, a parasitic resistance (2 · R _CON + RD + RS) independent of the gate voltage is calculated (step 3).
From the above equation (12), the term R _C is a straight line in which the slope of the resistance changes depending on the gate voltage V _GS , and the intersection is a parasitic resistance (2 · R _CON + RD + RS) that does not depend on the gate voltage (FIGS. 5).
In step 4, the calculated parasitic resistance ( _2.RCON + RD + RS) is stored.
On the other hand, the R _OUT -V _GS characteristic is obtained using the I _DS -V _GS characteristic of the MOSFET (step 5), and the R _OUT -V _GS characteristic is stored (step 6).
The parasitic resistance (2 · R _CON + RD + RS) independent of the gate voltage stored in step 4 is used to recalculate the I _DS -V _GS characteristics of the MOSFET (step 7). The recalculated I _{DS ′} -V _GS characteristic and R _{OUT ′} -V _GS characteristic are stored (step 8).
Further, the I _DS -V _DS characteristics of the MOSFET are recalculated using the parasitic resistance (2 · R _CON + RD + RS) independent of the gate voltage stored in step 4 (step 9). The recalculated I _{DS ′} -V _DS characteristic and R _{OUT ′} -V _DS characteristic are stored (step 10).

Next, the cross-sectional diffusion length (WD) of the MOSFET generated on both sides of the gate width W is obtained.
The I _{DS ′} -V _GS characteristic stored in step 8 is converted into an I _{DS ′} -W characteristic (step 11). Then, using the I _{DS ′} -W characteristic stored in step 12 (see FIGS. 7 and 8), 2WD is obtained from the intersection of the straight line connecting the same gate voltages V _GS and the X axis (step 13). In step 14, the WD is stored.
Next, the length (LD) of the parasitic resistance generated on both sides under the gate length L is obtained.
The R _{OUT ′} -V _GS characteristic stored in step 8 is converted into the R _{OUT ′} -L characteristic (step 15). Then, using the R _{OUT ′} -L characteristic stored in step 16 (see FIGS. 10 and 11), 2LD is obtained from the intersection of the straight line connecting the same gate voltages V _GS and the X axis (step 17). In step 18, the LD is stored.
Then, by using two types of diffused resistors TEG having the same diffused resistor width W and different lengths L, they are generated on both sides under the channel resistance (R _C ) (formula (59)) and the gate length L. The parasitic resistance (2 · R _LDD ) (formula (60)) is separated (step 19).
2 · R _LDD can be regarded as a sheet resistance (R _SHLDD ) that is inversely proportional to W _eff · (V _GS −V _TH −1 / 2 · V ′ _DS ) and proportional to 2 · LD. (Expression (61))
The R _LDD characteristic and the R _C characteristic thus obtained are stored (step 20), and the channel resistance R _C characteristic under the gate, the parasitic resistance depending on the gate voltage (R _LDD characteristic), and independent of the gate voltage. A parasitic resistance (RD + RS + 2 · R _CON ) is synthesized (step 21) to obtain an IV characteristic equation (step 22).

FIG. 15 is a flowchart showing a method for extracting model parameters of BJT.
First, a method for calculating parasitic resistance in BJT will be described.
The I _C -V _CE characteristic of the BJT is converted into an R _CE -V _CE characteristic (step 1), and this R _CE -V _CE characteristic is stored (step 2). Then, the parasitic resistance (RC + RE) is calculated using the R _CE -V _CE characteristic stored in step 2 (step 3). In step 4, the calculated parasitic resistance (RC + RE) is stored.
On the other hand, the R _BE -V _BE characteristic is obtained using the I _B -V _BE characteristic of the BJT (step 5), and this R _BE -V _BE characteristic is stored (step 6). Then, the parasitic resistance (RB + RE) is calculated using the R _BE -V _BE characteristic stored in step 6 (step 7). In step 8, the calculated parasitic resistance (RB + RE) is stored.
Using the parasitic resistance (RC + RE) stored in Step 4, the I _C -V _CE characteristic of BJT is recalculated (Step 9). The I _C -V _CE characteristics are recalculated and stored as I _C '-V _CE characteristic (Step 10).
Further, the I _B -V _BE characteristic of BJT is recalculated using the parasitic resistance (RB + RE) stored in step 8 (step 11). The I _B -V _BE characteristic recalculated and stored as I _B '-V _BE characteristic (Step 12).
Then, the remaining parameters of the BJT are extracted from the I _{C ′} -V _CE characteristic stored in Step 10 and the I _{B ′} -V _BE characteristic stored in Step 12 (Step 13). The parameters extracted in step 13 are stored (step 14).
Further, the (I _B + I _C ) −V _BE characteristic is converted into the R _OUT −V _BE characteristic by using the I _C −V _CE characteristic and the I _B −V _BE characteristic of the BJT (step 15). The converted R _OUT -V _BE characteristic is stored (step 16), and the parasitic resistance (RE) is separated using the R _OUT -V _BE characteristic (step 17). The separated parasitic resistance (RE) is stored (step 18).
The parasitic resistances (RB, RC) are separated using the parasitic resistance (RC + RE) stored in step 4, the parasitic resistance (RB + RE) stored in step 8, and the parasitic resistance (RE) stored in step 18 (step 19). ) And store the separated parasitic resistance (RB) and parasitic resistance (RC) (step 20).
The characteristic equations are obtained by synthesizing the parasitic resistances thus obtained.

FIG. 16 is a flowchart showing a method for extracting diode model parameters.
First, a method for calculating the parasitic resistance in the diode will be described.
The I _D -V _D characteristic of the diode is converted into a R _OUT -V _D characteristic (step 1), and this R _OUT -V _D characteristic is stored (step 2). Then, the parasitic resistance (RS) is calculated using the R _OUT -V _D characteristic stored in Step 2 (Step 3). In step 4, the calculated parasitic resistance (RS) is stored.
Using the parasitic resistance (RS) stored in Step 4, the I _D -V _D characteristic of the diode is recalculated (Step 5). The I _D -V _D characteristic recalculated and stored as I _D '-V _D characteristic (Step 6).
Then, the I _{D ′} -V _D characteristic stored in Step 6 is converted into an I _N (I _{D ′} ) -V _DS characteristic (Step 7). The parasitic resistance (IS) and the parasitic resistance (VTE) are separated from the converted I _N (I _{D ′} ) −V _DS characteristic and stored (step 8).
Then, the characteristic equations are obtained by synthesizing the parasitic resistances thus obtained.
FIG. 17 is a flowchart showing a method for extracting JFET model parameters.
Note that the method of extracting the JFET model parameters is the same as that of the MOSFET, so the same steps as those in FIG.

  The present invention relates to a method for calculating a model equation for circuit simulation in which model parameters are extracted by a method of decomposing actual measurement data and a model equation to be incorporated into a circuit simulator is obtained by using the model parameter. MOSFET, JFET, BJT, diode It can be applied to semiconductor elements such as.

1 is a structural diagram showing a cross section along a channel of a MOSFET according to an embodiment of the present invention; MOSFET I _DS -V _GS characteristics I _DS -V _DS characteristics of MOSFET R _OUT -V _DS characteristic diagram of MOSFET showing a method of calculating parasitic resistance (2 · R _CON + RD + RS) independent of general gate voltage R _OUT -V _DS characteristic diagram of MOSFET showing a method of calculating parasitic resistance (2 · R _CON + RD + RS) independent of specific gate voltage Configuration diagram showing a cross section perpendicular to the channel of the MOSFET I _DS -W characteristics diagram showing how to obtain general 2WD I _DS -W characteristics diagram showing how to obtain specific 2WD The figure explaining how to obtain the length (2LD) of the parasitic resistance generated on both sides under the gate length L from the I ′ _DS −V _GS characteristic with the parasitic resistance independent of the gate voltage removed. R _OUT -L characteristic diagram showing how to obtain general 2LD R _OUT -L characteristic diagram showing how to obtain a specific 2WD The figure explaining the basic principle for _calculating the parasitic resistance ( _{2.R LDD} ) generated on both sides under the gate length L The figure explaining isolation of the channel resistance (R _C ) and the parasitic resistance (2 · R _LDD ) generated on both sides under the gate length L Flowchart showing a method for extracting MOSFET model parameters Flowchart showing a method for extracting BJT model parameters Flowchart showing how to extract diode model parameters Flowchart showing a method for extracting JFET model parameters

Claims (3)

  A step of calculating a first parasitic resistance that does not depend on the gate voltage from actual measurement data of the semiconductor element, and a step of calculating a second parasitic resistance that depends on the gate voltage from the IV characteristics obtained by removing the first parasitic resistance. By using a plurality of types of diffused resistors TEG having the same diffused resistor width W and different lengths L, the second parasitic resistors are generated on both sides under the channel resistance and the gate length. And a step of separating the parasitic resistance, and using the third parasitic resistance as an independent characteristic to obtain an IV characteristic equation. In MOSFET, drain-source voltage is V _DS , channel current is I _DS , drain-source resistance is R _OUT , drain end, source end contact resistance is R _CON , drain diffusion resistance is RD, source When the diffusion resistance is RS, the LDD resistance under the gate is R _LDD , and the channel resistance under the gate is _RC , the I ′ _DS −V _GS characteristic is obtained by removing the parasitic resistance ( _{2.R CON} + RD + RS) independent of the gate voltage. From the following formula (1)

To calculate
As the diffusion resistor TEG, assuming that the output resistance of the gate length L1 is R _OUT 1 and the output resistance of the gate length L2 is R _OUT 2, R _OUT 1 = 2 · R _LDD + _RC 1, R _OUT 2 = 2 · Since R _LDD + _RC 2, the following formula (2) is obtained from R _OUT , R _OUT 1 and R _OUT 2.

And using R _OUT 1 and R _OUT 2, the third parasitic resistance (2 · R _LDD ) generated on both sides under the gate length L is _expressed by the following equation (3).

The circuit simulation model formula calculation method according to claim 1, wherein: In the MOSFET, the drain-source voltage is V _DS , the drain-source resistance is R _OUT , the drain end, the source end contact resistance is R _CON , the drain diffusion resistance is RD, the source diffusion resistance is RS, and the X axis is When V _DS , Y axis is R _OUT ,
A straight line passing through two points of coordinates (0, b) intersecting at one point and coordinates (X, Y ₁ ) on the high voltage side of the V _DS voltage, and coordinates (x ₁ , y ₁₁ ), (x ₂ , y ₂₁ ), The error from Λ, and the straight line passing through two points, the coordinate (0, b) intersecting at one point and the coordinate (X, Y ₁ ) on the high voltage side of the V _DS voltage, and the coordinate (x ₁ , y ₁₂ ), ( x ₂ , y ₂₂ ), from the error with Λ, the total error is expressed by the following equation (4)

In
However, if (Y ₁ −b) is greater than or equal to a predetermined value, this coordinate is removed.
2. The model equation for circuit simulation according to claim 1, wherein b of the coordinate (0, b) that minimizes the overall error is a parasitic resistance (RD + RS + 2 · R _CON ) independent of the gate voltage. Calculation method.

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