JP2001119017A - Method and system for extracting model parameter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To extract a model parameter with high precision by simply setting the border of a bin. SOLUTION: An Rd-L characteristics is calculated against the gate length of a channel resistor, based on the measurement value for the channel resistor and threshold value calculated from a DC current/voltage characteristics provided by measuring an MOSFET of different gate lengths. When the Rd-L characteristic is linearly approximated against the gate length to provide a straight line for a model parameter for each effective gate bias voltage, a hold straight line inclination calculating part 31 calculates the inclination of the hole straight line which is linearly approximated for the hole gate length, and a section straight line inclination calculating part 32 calculates each inclination of a section straight line, connecting adjacent measuring points of a channel resistor. An inclination intersection detecting part 33 detects a gate length, where an adjoining inclination value of the section straight line crosses the inclination value of the hole straight line as a gate length, where a measurement value of the channel resistor deviates, and a border gate length deciding part 34 decides a border gate length of a bin based on that gate length. A model parameter is extracted for each bin.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for extracting model parameters of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) used in a circuit simulation in designing an LSI (Large Scale Integration) circuit, and more particularly to a method for extracting the model parameter. The present invention relates to a model parameter extraction method and a model parameter extraction method capable of extracting model parameters by simpler region setting with higher accuracy when measuring DC current-voltage characteristics of different MOSFETs to extract model parameters.

[0002]

2. Description of the Related Art In designing an LSI circuit, a circuit simulation is used to verify the circuit operation of each function in an integrated circuit. In general, many MOS transistors forming an integrated circuit have substantially the same elements other than the gate length L and the gate width W of the MOS transistors, and are different from each other only in the gate length L and the gate width W.

Accordingly, the electrical characteristics of a MOS transistor vary depending on the dimensions of the gate length L and the gate width W. Therefore, in an integrated circuit including MOSFETs having various element shapes, the electrical characteristics of the circuit are determined using model parameters. In order to simulate the characteristics, the MO
It is necessary to prepare model parameters for every combination of the gate length L and the gate width W of the SFET.

Conventionally, this type of model parameter extraction method and its method have been disclosed in, for example, Japanese Patent Publication No. 269984.
No. 4 is disclosed. In this patent publication, MOSFE
Utilizing a known characteristic that the channel resistance Rd of T shows linearity with respect to the gate length L, a highly accurate model formula has been proposed in a wider range.

For example, as shown in a flowchart of FIG. 10 and a functional block diagram of FIG. 11, the drain current measuring unit 10 measures a current-voltage characteristic (step S101).
That is, for each of the MOSFETs having a plurality of gate lengths L to be modeled, the drain current Id is measured by changing the drain-source voltage Vds, and Id is measured.
While the voltage is stored in the −Vds characteristic holding unit 11, the drain current Id is measured by holding the drain-source voltage Vds near zero volts and changing the gate-source voltage Vgs.
It is stored in the d-Vgs characteristic holding unit 12.

Next, based on the characteristics stored in the Id-Vgs characteristics holding unit 12, the threshold voltage measuring unit 13
Of the threshold voltage Vth with respect to (Step S102)
And stored in the Vth-L characteristic holding unit 14. On the other hand, the channel resistance measuring unit 15 measures the characteristic of the channel resistance Rd with respect to the gate-source voltage Vgs for each sample of each gate length (step S103) and stores the characteristic in the Rd-Vgs characteristic holding unit 16.

Next, the channel resistance characteristic calculating section 17
Calculates the channel resistance Rd for the gate length L for each effective gate bias voltage Vge from the Vth-L characteristic and the Rd-Vgs characteristic (step S104), and stores it in the Rd-L characteristic holding unit 18.

From the Rd-L characteristic, the channel resistance characteristic linear approximation unit 20 calculates the slope ρ of the channel resistance with respect to the gate length and the channel resistance γ when the gate length becomes zero.
Are extracted as data for the effective gate bias voltage Vge, respectively, to perform the overall linear approximation calculation (step S105).

Next, the model parameter extracting unit 21
The diffusion layer resistance γ is defined as the channel resistance γ when the slope ρ becomes zero based on the effective gate bias voltage Vge dependency data of the slope ρ and the channel resistance γ obtained in the above procedure.
0 is determined, the parameter of the analytical model of the effective mobility is determined based on the reciprocal 1 / ρ of the slope ρ and the Vge dependency, and the V of the amount represented by the equation of (γ−γ0) Vge / ρ is determined.
The parameters of the analysis model of the gate diffusion layer overlap length are determined and extracted with the ge dependency (step S10).
6) Yes.

On the other hand, parameters relating to mobility and parasitic resistance, which are general basic model parameters for MOS, can be obtained by fitting measured values of channel resistance to a model equation. For example, in a model called BSIM3, the gate length L, the gate width W, the gate oxide capacitance Cox, the effective gate bias voltage Vge, the effective mobility μe, and the channel resistance Rd based on the parasitic resistance Rds are approximated by the following equation (1). it can.

[0011]

(Equation 1) From this equation 1, the effective mobility μe and the parasitic resistance Rd
It can be understood that each s can be obtained from the slope or intercept of the Rd-L characteristic.

However, in practice, the measured value of the channel resistance Rd is calculated based on the effective gate bias voltage Vg with respect to the gate length L.
e, the measured values of the effective mobility μe and the parasitic resistance Rds are obtained for each effective gate bias voltage Vge from the slope and intercept of the obtained straight line, and the μe-Vge characteristics and the Rds-Vge characteristics are measured. Values are obtained, and each of them is fitted to a model equation of mobility and parasitic resistance to extract model parameters related to mobility and parasitic resistance.

On the other hand, to accurately simulate a circuit constituted by a MOSFET having a large gate length L size region, model parameters of the MOSFET extracted with high accuracy in a wide gate length L size region are used. There is a need. However, at present, there is no model capable of expressing the current-voltage characteristics with high accuracy using a set of model parameters obtained from one entire straight line obtained by linear approximation for all the shapes of the gate length L.

That is, as shown in FIG. 12, for example, in the Rd-L characteristic, the measurement point of the channel resistance Rd with respect to one effective gate bias voltage Vge is a linear approximation in a region where the gate length is shorter than the gate length L4. May deviate significantly from the entire straight line. Therefore, in such a case, the measured values of the mobility and the parasitic resistance, which are obtained from the linearly approximated whole straight line, cannot be said to have high accuracy in the region of the gate length L4 or less. As described above, the parameters such as the mobility and the parasitic resistance extracted using the measured values of the mobility and the parasitic resistance obtained from the linearly approximated whole straight line have poor accuracy in a region shorter than a certain gate length.

Therefore, as shown in FIG. 13, for a device having a gate length L and a gate width W, binning in which a region having a gate length L and a gate width W is divided into regions called bins (containers) by a lattice. Is performed.
The device prepares model parameters for each bin by extracting the model parameters from the current-voltage characteristic data in the area of the bin. At the time of circuit simulation, the plurality of model parameters are used to determine the gate length L corresponding to the bin. Highly accurate current-voltage characteristics can be reproduced by properly applying to each region.

[0016]

The conventional model parameter extraction method described above has a problem that it is not possible to expect a highly accurate parameter over the entire gate length region.

The reason is that, due to the fact that the channel resistance characteristic with respect to the gate length of the MOSFET has linearity, the model parameters are extracted from the entire straight line obtained by measuring the channel resistance over the entire gate length region by linear approximation. However, this is because there is a gate length region where the measured value of the channel resistance deviates significantly from the overall straight line, and the accuracy is reduced in this region.

Although a plurality of parameter sets have been used as means for solving such problems, at present, there is no effective means for setting bins by binning, so that an optimum bin boundary is set. Because it is difficult to do so, high-precision parameters cannot be expected.

An object of the present invention is to solve such a problem, and to measure DC current-voltage characteristics of MOSFETs having different gate lengths and to extract model parameters when extracting model parameters with higher accuracy and simpler area. An object of the present invention is to provide a model parameter extraction method and a method that can be extracted by setting.

[0020]

A model parameter extracting method according to the present invention measures DC current-voltage characteristics of MOSFETs having different gate lengths, and measures a threshold voltage and a channel resistance value from the DC voltage characteristics. And extracting a model parameter by calculating a measured value of the characteristic of the channel resistance value with respect to the gate length from the channel resistance value and performing a linear process on the gate length for each effective gate bias voltage. The gate length at a point where the measured value of the channel resistance deviates greatly from the entire straight line obtained by linearly approximating the channel resistance with respect to all gate lengths for at least one preselected effective gate bias voltage is detected as a boundary gate length, and this boundary is detected. Regions with boundaries based on gate length are determined as bins, and It is extracted model parameters by performing a linear process.

The model parameter extraction method according to the present invention comprises a current-voltage characteristic measuring section for measuring DC current-voltage characteristics of MOSFETs having different gate lengths, and a threshold voltage for calculating a measured value of the threshold voltage from the measured DC voltage characteristics. A measuring unit, a channel resistance measuring unit that calculates a measured value of channel resistance from the measured DC voltage characteristic, and a channel that calculates a measured value of the characteristic of the channel resistance value with respect to the gate length from the measured threshold voltage and the channel resistance value. A resistance characteristic calculation unit, and a channel resistance characteristic linear approximation unit for performing a linear process on a gate length for each effective gate bias voltage to obtain a linearly approximated straight line, and extracting a model parameter from the obtained straight line And
The gate length at a point where the measured value of the channel resistance deviates greatly from the entire straight line obtained by linearly approximating the channel resistance with respect to all gate lengths for each effective gate bias voltage is defined as a boundary gate length, and a boundary based on this boundary gate length is defined as a boundary gate length. A binning boundary determining unit that determines a region having the bin as a bin,
A bin-by-bin model parameter extraction unit that performs the linear process for each determined bin to extract model parameters.

As described above, the boundary gate length is automatically set by the user by actually visually observing or calculating the value by presetting the measured value of the channel resistance out of the linear approximation. In addition, it can be easily determined or determined.

Further, since the at least one preselected effective gate bias voltage is one effective gate bias voltage having the highest voltage, the measurement error can be reduced, and the determination or the determination can be made more easily. Can be calculated.

One of the specific means is to calculate a boundary gate length, an effective gate bias voltage, and a slope value of a section straight line connecting measurement points of channel resistance at adjacent gate lengths. The gate length is based on a measurement point at which the slope value of the straight line crosses the slope value of the entire straight line obtained by linearly approximating the entire effective gate bias voltage. Another is that the bin is a region where the measurement point of the channel resistance changes lower than the overall linear line that is linearly approximated at each effective gate bias voltage.

[0025]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a flowchart showing an embodiment of the main procedure of the model parameter extracting method according to the present invention.

In FIG. 1, in the measurement of the current-voltage characteristics (step S1), the characteristics of the drain current Id and the drain-source voltage Vds (hereinafter, Id-Vds characteristics) are measured by a measuring device for each device having a different gate length L. ) And the characteristics of the drain current Id and the gate-source voltage Vgs (hereinafter, Id-Vgs characteristics) are measured.

Next, from the measured value data of the Id-Vgs characteristic, the characteristic of the threshold Vth (Vth-L
Characteristics (procedure S2) and the measured value of the channel resistance Rd are calculated (procedure S3), and the characteristics (hereinafter Rd) of the channel resistance Rd and the gate bias voltage Vg are calculated.
-Vg characteristic).

Next, the measured value of the Vth-L characteristic and Rd
From the measured value of the -Vg characteristic, the effective gate bias voltage Vge
The characteristic of the channel resistance Rd (R
The measured value (dL characteristic) is calculated (step S4).
The calculated Rd for each effective gate bias voltage Vge
The measured value of the -L characteristic is calculated by the least square method for each effective gate bias voltage Vge with respect to the gate length L (procedure S
5) Then, a linearly approximated overall straight line is obtained. This entire straight line is used to determine the boundary gate length at the time of binning in the subsequent process, and does not require high accuracy unlike the model parameter extraction.

Next, the boundary gate length is determined by binning which is a feature of the present invention (step S6), and model parameters are extracted for each bin determined in this step (step S7).
Is done. Details of the procedure S6 will be described later with reference to FIG.

Next, a system configuration according to the present invention will be described with reference to FIG. 1 and FIG.

As shown in FIG. 1, the drain current measuring section 10 applies a drain-source voltage Vds to each of the MOSFETs having a plurality of gate lengths L to be modeled in accordance with the procedure S1. The drain current Id is measured and stored in the Id-Vds characteristic holding unit 11, while the drain-source voltage Vds is held near zero volt, the gate-source voltage Vgs is changed, and the drain current Id is measured to measure Id-Vgs. It is stored in the characteristic holding unit 12.

Next, in step S2, the threshold voltage measuring unit 1 is determined from the characteristics stored in the Id-Vgs characteristics holding unit 12.
3 obtains the characteristic of the threshold voltage Vth with respect to each gate length L and stores the characteristic in the Vth-L characteristic holding unit 14. On the other hand, in step S3, the channel resistance measuring unit 15 measures the characteristics of the channel resistance Rd with respect to the gate-source voltage Vgs for each sample of each gate length, and stores the characteristics in the Rd-Vgs characteristic holding unit 16.

Next, in the above procedure 4, the channel resistance characteristic calculator 17 calculates the Vth-L characteristic and the Rd-Vgs
From the characteristics, the gate length L for each effective gate bias voltage Vge
Is calculated and stored in the Rd-L characteristic holding unit 18.

In step S5, the channel resistance characteristic linear approximation unit 20 calculates a measured value for the gate length of the channel resistance from the Rd-L characteristic based on the effective gate bias voltage V
An overall straight line that is linearly approximated using the least squares method is obtained for each ge.

FIG. 3 is a graph showing a linear approximation for each effective gate bias voltage Vge with respect to a graph of the measured value of the channel resistance Rd with respect to the gate length L for each effective gate bias voltage Vge stored in the Rd-L characteristic holding unit 18. 5 is a graph in which an example of the entire straight line is entered.

In the above step S6, the binning boundary gate length determination unit 30 determines the boundary gate length L by binning because the value of the channel resistance Rd deviates from the linearly approximated overall straight line by a value less than the gate length L3. I have.

In step S6, the Rd-L characteristic and the linearly approximated whole straight line are graphically displayed on a screen.
By reading the value of the channel resistance Rd, which deviates significantly from the entire straight line, the user can make a determination.

In the example shown in FIG. 3, the measured value of the channel resistance Rd with respect to the gate length L for each effective gate bias voltage Vge is significantly different from the entire straight line linearly approximated by the gate length L 3, so that the binning boundary gate The length determining unit 30 determines the boundary gate length of the binning to be the gate length L4, and sets a bin in an area between the gate length L4 and the gate length L4 for each effective gate bias voltage Vge.

Therefore, in step S7, the bin-by-bin linear approximation unit 41 obtains a straight line that linearly approximates the measured value of the Rd-L characteristic for each bin set by the binning boundary gate length determination unit 30. Next, a bin-based model parameter extraction unit 4
2 obtains the measured values of the mobility and the parasitic resistance from the slope value (slope) and intercept of the straight line linearly approximated for each bin, and the related parameters are obtained by applying the measured values of these characteristics to the model formula. Therefore, a highly accurate model parameter can be obtained for each bin by a relatively simple model formula.

Next, another embodiment in which the boundary gate length can be automatically calculated by referring to FIG. 2 will be described with reference to FIGS.

As shown in FIG. 4, for convenience of automatic calculation, here, one of the highest voltage values of the effective gate bias voltage Vge is selected as a measured value to be obtained in the above-described Rd-L characteristic. I have. The reason for setting the highest voltage value is that the measurement error of the channel resistance at this voltage is smaller than that at other lower voltage values.
As a result, the amount of measurement value calculation or linear approximation calculation is reduced, and the process is simplified.

Therefore, the Rd-L characteristic holding section 18 in FIG. 2 needs to correspond to only one effective gate bias voltage Vge. The channel resistance characteristic linear approximation unit 20 calculates the total gate length L with respect to the maximum effective gate bias voltage Vge.
Are linearly approximated by the least squares method, and the slope value of the entire straight line is obtained.

FIG. 5 shows the inclination value of the entire straight line obtained here by a solid line.

Next, the binning boundary gate length determining unit 3
0 determines the boundary gate length for setting the bin.

The details of the procedure S6 of FIG. 1 and the binning boundary gate length determining unit 30 in this embodiment will be described with reference to FIGS. 6 and 7 and FIGS.

As shown in FIG. 7, the binning boundary gate length determination unit 30 automatically determines the binning boundary gate length, and as shown in FIG. And a boundary gate length determination unit 34.

First, the overall straight line slope value calculator 31 receives the overall straight line data for the highest effective gate bias voltage Vge from the channel resistance characteristic linear approximation unit 20 and calculates the overall straight line slope value (step S11). On the other hand, the section linear slope value calculation unit 32 calculates the channel resistance Rd of each gate length L from the measured value of the Rd-L characteristic held by the Rd-L characteristic holding unit 19 as shown in FIG. The slope value of the section straight line obtained by connecting the values for each adjacent point is obtained as a middle gate length L by calculation (step S12).

FIG. 4 shows the maximum effective gate bias voltage V
The entire straight line that is linearly approximated to ge is indicated by a solid line, and the section straight lines in the sections connecting the measured values of the channel resistances Rd at adjacent gate lengths L are indicated by dotted lines.

FIG. 5 is a broken line connecting a straight line connecting all the gate lengths L with the slope values of the whole straight line and connecting the slope values of the section straight lines at the gate length L in the middle of the section straight lines with dotted lines. Are shown.

When the measured channel resistance value of the Rd-L characteristic is a smooth curve, the portion forming a straight line is a wide area, and the channel resistance value drops sharply only in the portion having a small gate length. Therefore, as in the example shown in FIG. 4, the slope value in a region larger than the gate length L5 is almost the same as the slope value of the whole straight line. On the other hand, in a region smaller than the gate length L5, the inclination value gradually increases. As described above, the slope value of the entire straight line, which is linearly approximated, tends to increase as the amount of decrease in the measured value of the channel resistance gradually increases in the small portion of the gate length L.

For this reason, as a typical state, as shown in FIG. 4 and FIG. 5, as compared with the inclination value of the whole straight line, the inclination value is smaller in the region longer than the gate length L5. Below L4, it gradually increases.

Therefore, returning to the flowchart of FIG.
The inclination value intersection detection unit 33 includes an overall straight line inclination value calculation unit 31.
In the example of FIG. 5, the gate length L5 of the measurement point at which the section linear inclination value crosses the entire inclination value is detected (step S1).
3) will do.

As shown in the example of FIG. 5, if the location crossing the slope value is one location of the gate length L5 (YES in step S14), the boundary gate length determination unit 34 sets the binning boundary to this gate length L5. It can be determined (procedure S15). Therefore,
The bin-by-bin model parameter extracting unit 40 receives the binning boundary gate length L5, and based on the gate length L5, can extract a model parameter for each bin, that is, a gate length L4 equal to or larger than the next lower gate length L4. As a result, high accuracy of the model parameters can be expected.

However, as shown in FIGS. 8 and 9, when the inclination value of the adjacent point varies with respect to the inclination value of the whole straight line, it is necessary to add another condition in the automatic calculation. . In such a case, that is, the procedure S14
Is “NO”, the binning may be left to the user's judgment, so that the binning boundary gate length determining unit 30 can output “user left”.

As described above, in contrast to the well-known characteristic that the channel resistance Rd of the MOSFET shows linearity with respect to the gate length L, the channel resistance Rd has a linearity with respect to the entire gate length in a region where the gate length L is small. By taking advantage of the fact that it deviates from the linearity, simply binning the region deviating from the linearity, it is possible to extract highly accurate model parameters. After binning, since linear approximation can be performed for each bin, there is no need to use a complicated model formula, and automatic calculation can be simplified.

Further, in the above description, linear approximation is performed for each bin as a new bin even in a region longer than the detected boundary gate length to ensure high accuracy. However, a linear approximation formula for the entire gate length is obtained. If high accuracy can be ensured for the above region, an entire straight line that is linearly approximated with the entire gate length may be applied as it is to simplify the calculation process.

In the above description, the functional blocks or flowcharts have been illustrated and described. However, the functions can be freely distributed or merged, or the procedures can be interchanged by changing the order of the procedures or parallel operations as long as the above functions are satisfied. It does not limit the invention.

[0059]

As described above, according to the present invention, it is possible to obtain an effect that highly accurate model parameters can be extracted by simply setting a binning boundary.

The reason is that a straight line used for extracting parameters relating to the mobility and the parasitic resistance, which are basic parameters, linearly approximates the characteristics of the channel resistance Rd with respect to the gate length L.
Based on the gate length L where the measured value of the channel resistance Rd deviates greatly from the overall straight line obtained by linearly approximating the characteristic with respect to
This is because the binning boundary gate length can be determined.

Specifically, the boundary of the bin area can be determined based on the gate length L of the measurement point where the slope value of the section straight line connecting adjacent measured values of the channel resistance Rd exceeds the slope value of the entire straight line. Since the measured values of the mobility and the parasitic resistance can be accurately fitted to the model formula from the measured values of the channel resistance for each determined bin, the MOSFE
This is because parameters relating to mobility and parasitic resistance, which are basic parameters of T, can be extracted with high accuracy.

[Brief description of the drawings]

FIG. 1 is a flowchart illustrating an embodiment of a processing procedure according to the present invention.

FIG. 2 is a system configuration diagram showing an embodiment of the present invention.

FIG. 3 is a graph showing one form of Rd-L characteristics.

FIG. 4 shows that the boundary gate length L of a bin is Rd−
9 is a graph illustrating an embodiment determined from L characteristics.

FIG. 5 is a graph illustrating an embodiment of the present invention in which a boundary gate length L of a bin is determined based on an inclination value of an entire straight line obtained by linearly approximating the boundary gate length L.

FIG. 6 is a flowchart showing an embodiment of a processing procedure for realizing FIG. 5;

FIG. 7 is a system configuration diagram showing one embodiment of FIG. 6;

FIG. 8 is a graph illustrating an embodiment for determining a boundary gate length L of another bin different from FIG. 4;

FIG. 9 is a graph illustrating an embodiment for determining a boundary gate length L of another bin different from FIG. 5;

FIG. 10 is a flowchart showing an example of the related art.

FIG. 11 is a system configuration diagram showing an example of the related art.

FIG. 12 is a graph showing an example in which a straight line linearly approximated to the Rd-L characteristic is entered.

FIG. 13 is a graph illustrating an example of binning.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Drain current measurement part 11 Id-Vds characteristic holding part 12 Id-Vgs characteristic holding part 13 Threshold voltage measuring part 14 Vth-L characteristic holding part 15 Channel resistance measuring part 16 Rd-Vgs characteristic holding part 17 Channel resistance characteristic calculating part 18 Rd-L characteristic holding unit 20 Channel resistance characteristic linear approximation unit 30 Binning boundary gate length determination unit 31 Overall linear inclination value calculation unit 32 Section linear inclination value calculation unit 33 Inclination value intersection detection unit 34 Boundary gate length determination unit 41 Bin-by-bin linear Approximator 42 Model parameter extractor for each bin

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 29/00

Claims (8)

[Claims] A DC current-voltage characteristic of MOSFETs having different gate lengths is measured, a threshold voltage and a channel resistance value are measured from the DC voltage characteristic, and a characteristic of the channel resistance value with respect to the gate length is determined from the threshold voltage and the channel resistance value. In the model parameter extraction method of extracting the model parameters by calculating the measured value of and performing the linear processing on the gate length for each effective gate bias voltage, the measured value of the channel resistance is obtained by converting the channel resistance to all gate lengths. On the other hand, a gate length at a location that deviates greatly from the whole straight line that is linearly approximated for each of at least one effective gate bias voltage selected in advance is detected as a boundary gate length, and a region having a boundary based on this boundary gate length is defined as a bin. Is determined, and linear processing is performed for each bin to extract model parameters. A method for extracting model parameters, which comprises: 2. The method according to claim 1, wherein the at least one preselected effective gate bias voltage is a single effective gate bias voltage having the highest voltage. 3. The boundary gate length according to claim 1, wherein the slope value of a section straight line connecting measurement points of channel resistance at adjacent gate lengths is calculated with one effective gate bias voltage. A model parameter extraction method, characterized in that the gate length is based on a measurement point that crosses a slope value of an overall straight line that is linearly approximated to a measurement point of a channel resistance in the entire gate length of the effective gate bias voltage. 4. The model parameter extracting method according to claim 1, wherein the bin is an area where the measurement point of the channel resistance changes lower than a linear approximation with one effective gate bias voltage. 5. A current-voltage characteristic measuring section for measuring DC current-voltage characteristics of MOSFETs having different gate lengths, a threshold voltage measuring section for calculating a measured value of a threshold voltage from the measured DC voltage characteristics, and a measured DC voltage characteristic. A channel resistance measurement unit that calculates a measured value of the channel resistance from the channel resistance; a channel resistance characteristic calculation unit that calculates a measured value of the characteristic of the channel resistance value with respect to the gate length from the measured threshold voltage and the channel resistance value; A channel resistance characteristic linear approximation unit for performing a linear process on each effective gate bias voltage to obtain a linearly approximated straight line, and measuring a channel resistance in a model parameter extraction method of extracting a model parameter from the obtained straight line. The value is a channel resistance that is at least one preselected for all gate lengths. A binning boundary determining unit that determines a gate length at a location that deviates greatly from an entire straight line that is linearly approximated for each effective gate bias voltage as a boundary gate length, and determines a region having a boundary based on the boundary gate length as a bin, A bin-by-bin model parameter extraction unit for extracting the model parameters by performing the linear processing for each bin. 6. The model parameter extraction method according to claim 5, wherein the at least one preselected effective gate bias voltage is one effective gate bias voltage having the highest voltage. 7. The binning boundary determination unit according to claim 5, wherein the slope value of a section straight line connecting measurement points of channel resistance at adjacent gate lengths at each effective gate bias voltage is calculated, and the slope value of the adjacent section straight line is calculated. Determining a gate length based on a measurement point crossing a slope value of an entire straight line linearly approximated to each of the effective gate bias voltages as a boundary gate length. 8. The binning boundary determination unit according to claim 5, wherein the measured value of the characteristic of the channel resistance value with respect to the gate length calculated by the channel resistance characteristic calculation unit is obtained by the channel resistance characteristic linear approximation unit. A model parameter extraction method, wherein an area having a gate length that changes lower than a straight line is determined as the bin.