JP2013089696A - High breakdown voltage mosfet circuit simulation model creation method, device and program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain drain current accuracy over a wide bias range in a high breakdown voltage MOSFET model, thereby improving the accuracy of simulation.SOLUTION: A model is created which comprises: first and second MOSFETs 1 and 2 having drains are connected in common, gates connected in common, and back gates connected in common, and respectively corresponding to the width of a source diffusion layer and the width of a well contact diffusion layer in the source region thereof; and a first variable resistance element 3 which is connected at one end to the source of the second MOSFET 2. In this model, a junction point at which the source of the second MOSFET 2 and the other end of the first variable resistance element 3 are connected is defined as a source terminal S, while the common connected drains, the common connected gates, and the common connected back gates of the first and the second MOSFETs are respectively defined as a drain terminal D, a gate terminal G, and a back gate terminal B, and the resistance value of the first variable resistance element 3 is adjusted on the basis of electrical characteristic data of a high breakdown voltage MOSFET which is the object of modeling.

Description

  The present invention relates to a circuit simulation technique for a high voltage MOSFET, and more particularly, to a circuit simulation model creation method, apparatus, and program.

  In order to increase the accuracy of a circuit simulation model of a high voltage MOSFET (Metal Oxide Semiconductor Field Effect Transistor), a technique using a macro model in which a variable resistor is combined with an element model representing a normal MOSFET is disclosed in, for example, Patent Document 1 Etc. are described. Examples are shown in FIGS. 19A and 19B.

  In FIG. 19A, a circuit block in which the variable resistor 101 is connected to the drain side of the MOSFET 102 is used as a macro model expressing one high voltage MOSFET. The terminal on the side not connected to the drain of the MOSFET 102 among the terminals of the variable resistor 101 is defined as a macro model drain terminal (D). The gate terminal (G), source terminal (S), and back gate terminal (also referred to as “bulk terminal”) (B) of the macro model are the same as the gate terminal, source terminal, and back gate terminal (bulk terminal) of the MOSFET 102, respectively. is there. This macro model allows the gate-source voltage (also referred to simply as “gate voltage”) and drain-source caused by the low-concentration drain diffusion layer located between the channel region and the drain electrode (high-concentration drain diffusion layer). A parasitic resistance component depending on voltage (also simply referred to as “drain voltage”) can be expressed.

  FIG. 19B is obtained by replacing the variable resistor 101 in FIG. 19A with a junction transistor (JFET) 103. The macro model shown in FIG. 19B also has the same effect as the macro model shown in FIG.

  Further, Chapter 14 of Non-Patent Document 1 discloses a technique for including a parasitic resistance component of a low-concentration drain diffusion layer located between a channel region and a drain electrode in a model equation of a transistor model. In this case, the macro model shown in FIGS. 19A and 19B is replaced with a single MOSFET 104 as shown in FIG. 19C, for example. In FIG. 19C, the variable resistor 101 of FIG. 19A or the JFET 103 of FIG. 19B is incorporated in the model in advance. Therefore, the drain of the MOSFET 104 is the macro model drain terminal (D).

JP 2005-190328 A JP 2001-189449 A Japanese Patent No. 3120389

Hiroshima University & STARC, "HiSIM_HV 1.2.0 User's Manual" (2009) [Search September 12, 2011] <Internet URL: http://home.hiroshima-u.ac.jp/usdl/HiSIM_HV/C- Code / HiSIM_HV_C.html>

  The following is an analysis of related technology.

  Even if the related technique described in Patent Document 1 and Non-Patent Document 1 is used for the high breakdown voltage MOSFET having the layout structure shown in FIG. 20, an accurate circuit simulation model cannot be obtained. The inventors have found it completely unique. Note that, for example, the descriptions of Patent Literature 2, Patent Literature 3 and the like are referred to as related technologies relating to transistors having the layout structure shown in FIG. 20 in the source region.

As shown in FIG. 20, the high breakdown voltage MOSFET has a special structure on the source side, that is, a well for supplying a source voltage to the source diffusion layer 112 (high concentration N ⁺ diffusion layer) and a P well (not shown). A contact diffusion layer (also referred to as a “well electrode diffusion layer”) 111 (high-concentration P ⁺ diffusion layer) is provided on the source region side of the gate electrode 115 (disposed on the silicon substrate via a gate insulating film). And a layout structure arranged alternately adjacent to each other. In such a high breakdown voltage MOSFET, when the MOSFET model described with reference to FIG. 19 or the like is used, the drain current cannot be accurately obtained in a wide bias range (this will be described in detail later). .

  As a result of analyzing and examining the cause, the present inventors have developed a completely new macro model that solves the above problems and verified the simulation accuracy of the macro model. That is, the object of the present invention is to obtain the drain current accuracy in a wide bias range in a high breakdown voltage MOSFET model having a structure in which a source diffusion layer and a well contact diffusion layer are arranged adjacent to each other in a source region. Another object is to provide an apparatus, a method, a program, and a recording medium that improve simulation accuracy.

  In order to solve at least one of the above-mentioned problems, the present invention is generally configured as follows (however, it is of course not limited to the following).

According to one aspect of the present invention, there is provided a high breakdown voltage MOSFET having a source region in which a source diffusion layer and a well contact diffusion layer having a conductivity type opposite to that of the source diffusion layer are disposed adjacent to each other along a channel width direction. As a MOSFET model for circuit simulation, drains are connected in common, gates are connected in common, and back gates are connected in common, corresponding to the width of the source diffusion layer and the width of the well contact diffusion layer in the source region, respectively. First and second MOSFETs having first and second channel widths, and a first variable resistance element having one end connected to the source of the second MOSFET, the source of the first MOSFET And the other end of the first variable resistance element as a source terminal, the commonly connected gates of the first and second MOSFETs are connected. Inn, gate and the common connection, the back gate and the common connection, respectively, a drain terminal, a gate terminal, means for creating a model of a back gate terminal,
Storage means for storing electrical characteristic data of the high breakdown voltage MOSFET to be modeled;
Means for reading out electrical characteristic data of the high withstand voltage MOSFET from the storage means, and adjusting a resistance value of the first variable resistance element of the MOSFET model for circuit simulation based on the electrical characteristic data. A model creation device is provided.

According to another aspect of the present invention, there is provided a high breakdown voltage MOSFET having a source region in which a source diffusion layer and a well contact diffusion layer having a conductivity type opposite to that of the source diffusion layer are disposed adjacent to each other along a channel width direction. In creating a MOSFET model for circuit simulation with an information processing device,
The drains are connected in common, the gates are connected in common, the back gates are connected in common, and the first and second channel widths corresponding to the width of the source diffusion layer and the width of the well contact diffusion layer in the source region, respectively. First and second MOSFETs having:
A first variable resistance element having one end connected to the source of the second MOSFET;
With
Using the connection point between the source of the first MOSFET and the other end of the first variable resistance element as a source terminal, the commonly connected drain, the commonly connected gate, and the common connection of the first and second MOSFETs Processing to create a model with the back gate as a drain terminal, a gate terminal, and a back gate terminal,
Processing for reading electrical characteristic data of the high breakdown voltage MOSFET from a storage device that stores electrical characteristic data of the high breakdown voltage MOSFET to be modeled, and adjusting a resistance value of the first variable resistance element based on the electrical characteristic data The
A program to be executed by the information processing apparatus is provided.

According to yet another aspect of the present invention, a high breakdown voltage MOSFET having a source region in which a source diffusion layer and a well contact diffusion layer having a conductivity type opposite to that of the source diffusion layer are disposed adjacent to each other in the channel width direction. In creating a MOSFET model for circuit simulation in an information processing device,
The drains are connected in common, the gates are connected in common, the back gates are connected in common, and the first and second channel widths corresponding to the width of the source diffusion layer and the width of the well contact diffusion layer in the source region, respectively. First and second MOSFETs having:
A first variable resistance element having one end connected to the source of the second MOSFET;
With
A connection point between the source of the first MOSFET and the other end of the first variable resistance element is used as a source terminal, and the commonly connected drain, the commonly connected gate, and the common of the first and second MOSFETs Create models that use the connected back gates as the drain terminal, gate terminal, and back gate terminal, respectively.
The electrical characteristic data of the high breakdown voltage MOSFET is read out from the storage means for storing the electrical characteristic data of the high breakdown voltage MOSFET to be modeled, and the first variable of the model of the MOSFET for circuit simulation is based on the electrical characteristic data A model generation method for adjusting the resistance value of the resistance element is provided.

  According to the present invention, in a high breakdown voltage MOSFET model having a structure in which a source diffusion layer and a well contact diffusion layer are disposed adjacent to each other in a source region, the accuracy of drain current can be obtained in a wide bias range, and simulation is performed. Accuracy can be improved.

It is a figure explaining the outline | summary of this invention. It is a figure explaining the 1st Embodiment of this invention. It is a figure explaining the 1st Embodiment of this invention. It is a figure explaining the system of the 2nd Embodiment of this invention. It is a figure explaining the operation | movement of the 2nd Embodiment of this invention. It is a figure explaining the principle of this invention. It is a figure explaining the effect of this invention. It is a figure explaining the effect of this invention. It is a figure explaining the 3rd Embodiment of this invention. It is a figure explaining the 3rd Embodiment of this invention. It is a figure explaining the 4th Embodiment of this invention. It is a figure explaining the operation | movement of the 4th Embodiment of this invention. It is a figure explaining the 2nd Embodiment of this invention. It is a figure explaining the 5th Embodiment of this invention. It is a figure explaining the 6th Embodiment of this invention. It is a figure explaining the 6th Embodiment of this invention. It is a figure explaining the 7th Embodiment of this invention. It is a figure explaining the 7th Embodiment of this invention. (A), (B), (C) is a figure explaining related technology. It is a figure explaining related technology. It is a figure explaining the problem of related technology. It is a figure explaining the problem of related technology. It is a figure explaining the problem of related technology. It is a figure explaining the problem of related technology.

  According to the present invention, one of the first and second diffusion regions disposed opposite to the semiconductor substrate surface with a gate electrode disposed on the semiconductor substrate with a gate insulating film interposed therebetween. The first diffusion region includes a first conductivity type first diffusion layer (for example, 12 in FIG. 2) and a channel contact width between the first diffusion layer and the opposite conductivity type well contact diffusion layer (11 in FIG. 2). As a model of a MOSFET for circuit simulation of MOSFETs arranged adjacent to each other in the direction, the second diffusion regions (for example, the drain in FIG. 1) are connected in common, the gates are connected in common, and the back gates are connected. Are connected in common and correspond to the width of the first diffusion layer (12 in FIG. 2) and the width of the well contact diffusion layer (11 in FIG. 2) of the first diffusion region, respectively. And one end of the first and second MOSFETs (1 and 2 in FIG. 1) having the following channel width and the first diffusion region (for example, the source in FIG. 1) of the second MOSFET (2 in FIG. 1). A first variable resistance element (3 in FIG. 1) connected, the first diffusion region of the first MOSFET (1 in FIG. 1), and the first variable resistance element (FIG. 1). 3) is used as the first terminal (S) as a connection point with the other end of the first and second MOSFETs (1 and 2 in FIG. 1), the second diffusion region connected in common, and the common A model is used in which the connected gate and the commonly connected back gate are the second terminal (D), the gate terminal (G), and the back gate terminal (B), respectively. Based on the electrical characteristic data of the high breakdown voltage MOSFET to be modeled, the resistance value (Rs) of the first variable resistance element (3 in FIG. 1) of the model of the MOSFET for circuit simulation is adjusted.

  In the following, the basic principle of the above-described present invention will be described, and then embodiments will be described.

  As described above, even if the related techniques described in Patent Document 1, Non-Patent Document 1, etc. are used, an accurate circuit simulation model cannot be obtained for the MOSFET having the layout structure shown in FIG. Since it became clear from examination of this time by the present inventors, it demonstrates below.

In FIG. 20, an N ⁺ type source diffusion layer 112 and a P ⁺ type well contact diffusion layer 111 (P ⁺ diffusion layer) are arranged adjacent to each other in the channel width direction on the source side on the left side of the gate electrode 115. ing. In the example of FIG. 20, P ⁺ -type well contact diffusion layers (P ⁺ diffusion layers) 111 and N ⁺ -type source diffusion layers (N ⁺ diffusion layers) 112 are alternately arranged adjacent to each other. In FIG. 20, three P ⁺ -type well contact diffusion layers (P ⁺ diffusion layers) 111 are arranged, and two N ⁺ -type source diffusion layers (N ⁺ diffusion layers) 112 are arranged therebetween. Note that the layout configuration of FIG. 20 is simply illustrated for the sake of explanation, and includes a P ⁺ type well contact diffusion layer (P ⁺ diffusion layer) 111 and an N ⁺ type source diffusion layer (N ⁺ diffusion). The number and arrangement of the layers) 112 are not limited to the configuration shown in FIG. The N ⁺ -type source diffusion layer 112 and the P ⁺ -type well contact diffusion layer 111 are usually formed so as to be electrically connected.

In FIG. 20, on the drain side on the right side of the gate electrode 115, an N ⁻ type low concentration drain diffusion layer 114 adjacent to the gate electrode 115 and an N ⁺ type drain diffusion layer 113 adjacent to the low concentration drain diffusion layer 114. (N ⁺ diffusion layer for drain contact) is provided.

  In FIG. 20, when a voltage is applied to the gate electrode 115, an inversion layer (channel) is formed on the surface of the silicon substrate below the gate electrode 115, and the source and the drain are electrically connected.

In the example shown in FIG. 20, the N-channel MOSFET is formed in the P-type well. However, when the N-channel MOSFET is formed on the surface of the P-type silicon substrate, the P ⁺ -type well contact diffusion layer 111 is P ^+. It becomes a type of substrate contact (Substrate Contact) diffusion layer. Therefore, hereinafter, the P ⁺ type well contact diffusion layer 111 may be a P ⁺ type substrate contact diffusion layer. The well contact diffusion layer (substrate contact diffusion layer) is also simply referred to as well contact (substrate contact). Note that the P ⁺ -type well contact diffusion layer (substrate contact) of the N-channel MOSFET is connected to a power supply VSS (0 V), for example. In FIG. 20, the layout configuration of the N-channel MOSFET is illustrated. However, the P-channel MOSFET is the same except that the polarity is inverted.

In FIG.
Wn is a width per source diffusion layer 112 of N ⁺ type,
Wp is the width per P ⁺ -type well contact diffusion layer 111,
W is the total channel width. This W is a value obtained by adding the sum (= ΣWn) of the widths Wn of the source diffusion layers 112 and the sum (= ΣWp) of the widths Wp of the well contact diffusion layers 111 (W = ΣWn + ΣWp).

Note that Wn may have the same value for all the N ⁺ type source diffusion layers 112 in the source region, or may differ for each source diffusion layer 112. The same applies to Wp. In other words, all the P ⁺ -type well contact diffusion layers 111 in the source region may have the same width, or the P ⁺ -type well contact diffusion layers 111 may have different widths.

In FIG. 20, the ends of the P ⁺ -type well contact diffusion layer 111 and the N ⁺ -type source diffusion layer 112 opposite to the gate electrode 115 are aligned with each other. Absent. For example, the N ⁺ type source diffusion layer 112 further extends on the side opposite to the side facing the gate electrode 115 and is connected to the adjacent N ⁺ type source diffusion layer 112, and the P ⁺ type well contact diffusion layer 111 therebetween is formed You may make it surround. The layout structure shown in FIG. 20 is also called a “source substrate connection structure” because the P ⁺ type well contact diffusion layer 111 and the N ⁺ type source diffusion layer 112 are connected.

FIG. 21A and FIG. 21B are diagrams respectively showing results of modeling drain current-drain voltage characteristics (Id-Vd characteristics) and actual measurement values for different Wnratio of the high breakdown voltage MOSFET of FIG. (Analysis result made by the present inventors). Here, Wnratio is the ratio of the total width Wn of each N ⁺ -type source diffusion layer 112 (= ΣWn) to the total channel width W (= ΣWn + ΣWp) in FIG. Given below.

  Wnratio = {(ΣWn) / (ΣWn + ΣWp)} × 100

  In FIG. 21A, Wnratio = 48%, and in FIG. 21B, Wnratio = 40%. 21A and 21B, the horizontal axis represents drain voltage (drain-to-source voltage) Vds (unit: voltage (Voltage)), and the vertical axis represents drain current (drain-to-source current) Id. An Id-Vd characteristic curve in which the gate voltage (gate-source voltage) Vgs is changed from 0 to 5 V in 1 V step is shown. When the gate-source voltage Vgs = 0V, the N-channel MOSFET is in the off state, and the drain current Id = 0.

  In the example of FIG. 21A, the actual measurement value indicated by the ▲ mark and the modeling result (conventional model) by the related technique indicated by the broken line are over the entire range (0 to 20 V) of the drain-source voltage Vds. The gate-source voltages Vgs = 0, 1, 2,...

  On the other hand, in the example of FIG. 21B in which the same model is compared with an actual measurement value (indicated by a ▲ mark) when Wnratio is 40%, an actual measurement value (▲) and a modeling result indicated by a broken line ( The previous model) does not match. In particular, in the region where the drain current Id is substantially constant without depending on the drain-source voltage Vds, the difference from the actually measured value (▲) becomes remarkable in the region where the gate-source voltage Vgs is high.

  This is presumably because the drain current-drain-source voltage (Id-Vds) characteristics of the MOSFET change due to the difference in the Wnratio value in the layout configuration shown in FIG.

  The inventors of the present application tried to adjust model parameters of the related-art MOSFET model shown in FIG. 19, but the drain current-drain-source voltage (Id) due to the difference in Wnratio value of 40% and 48%. -Vds) The change in characteristics could not be expressed by the MOSFET model shown in FIG.

  The inventors of the present application have made a more detailed examination on the fitting error of such a MOSFET model (for example, the model shown in FIG. 19), and the result will be described below.

  22 (A) and 22 (B) show a comparison of drain-source current Ids in a state where the N-channel MOSFET having the layout structure shown in FIG. 20 is turned on between elements (MOSFETs) having different Wnratio. Yes (analysis result made by the present inventors). In FIG. 22, the vertical axis represents the drain-source current Ids normalized by the total channel width W (= ΣWn + ΣWp), which is Ids / W. In FIG. 22, the Wnratio of the element (MOSFET) A on the horizontal axis is 40%, and the Wnratio of the elements (MOSFETs) B and C are both 48% (note that the elements B and C have the same Wnratio, but MOSFET).

  In FIG. 22 (A) and FIG. 22 (B), the mark ● represents an actual measurement value. Further, the conventional model (intersection of the elements A, B, and C and the broken line) indicated by a broken line uses, for example, the MOSFET model of FIG. 19A and its parameters (for example, the resistance of the variable resistance element 101 of FIG. 19A). A simulation is performed on the MOSFET model obtained by fitting values and other parameters) to obtain Ids / W. The broken line is a line obtained by connecting the modeling results of the elements A, B, and C with straight lines (not each dot of the broken line... Represents the modeling result, but the intersection of the elements A, B, and C and the broken line. Is the Ids / W of the elements A, B, and C. The same applies to FIG.

  In the linear region (drain-source voltage Vds = 0.1 V, gate voltage Vg = 5 V) shown in FIG. 22A, the measured value (●) of the drain current Ids / W normalized by the total channel width W is It is shown that the element A with Wnratio = 40% and the elements B and C with Wnratio = 48% are almost equal and hardly depend on Wnratio. Further, as shown in FIG. 22A, the modeling result Ids / W using the related technology model (conventional model) such as FIG. 19 is Wnratio = 40% of the element A, the elements B and C in the linear region. It intersects with any measured value (●) of Wnratio = 48% of FIG.

  On the other hand, in the saturation region shown in FIG. 22B (drain-source voltage Vds = 12 V, gate-source voltage Vg = 5 V), the measured drain current Ids / W normalized by the total channel width W ( ) Changes depending on Wnratio. That is, in the element A with Wnratio = 40%, the modeling result using the measured value of Ids / W (indicated by ●) and the related technology model (conventional model) such as FIG. 19 (intersection of the broken line and the element A) Does not match (there is a difference). However, for elements B and C with Wnratio = 48%, the measured value of Ids / W (indicated by ●) is almost the same as the modeling result (conventional model) that is the intersection of the broken line and elements B and C. , Wnratio = 40% as in the device A, no significant difference is recognized.

  In the related technology shown in FIG. 19 and the like, the Wnratio dependency can increase or decrease the overall current level by adjusting, for example, a resistance component (resistance value of the variable resistor 101 in FIG. 19A). .

  However, as seen in FIGS. 22A and 22B, depending on the drain voltage (drain-source voltage), a different Wnratio dependency appears in the drain-source current Ids. It cannot be modeled well.

In particular, as shown in FIGS. 22 (A) and 22 (B),
In the linear region, the drain-source current Ids does not depend on Wnratio,
Only in the saturation region, the drain-source current Ids depends on Wnratio.
This tendency is recognized.

  In a MOSFET having a normal structure (for example, refer to a high breakdown voltage MOSFET in FIG. 3 described later), the characteristics of the linear region do not change depending on the layout structure of the element, and only the characteristics of the saturation region have the layout structure of the element. It does not change depending on.

  The characteristic of the linear region does not change depending on the layout structure of the element, and only the characteristic of the saturation region changes depending on the layout structure of the element. This is unique to the MOSFET having the layout structure shown in FIG. (Analysis result made by the inventors of the present application).

  For this reason, it is extremely difficult to express it by modeling the related technique (variable resistance connected to the drain of the MOSFET) shown in FIGS.

をゲート幅Ｗで規格化した値Ｇｍ／Ｗを、Ｗｎｒａｔｉｏ＝４０％（破線）とＷｎｒａｔｉｏ＝４８％（実線）で比較した結果である（本願発明者らによって為された分析結果である）。 FIG. 23A and FIG. 23B show the mutual conductance which is a differential value of the drain-source current Ids with respect to the gate-source voltage Vgs in the linear region and the saturation region, respectively.

The value Gm / W normalized by the gate width W is compared with Wnratio = 40% (broken line) and Wnratio = 48% (solid line) (analysis result made by the present inventors).

  In FIGS. 23A and 23B, the horizontal axis represents the gate-source voltage Vgs (0 to 5 V), and the vertical axis represents Gm / W (actually measured value). The characteristic polarity of Wnratio = 40% (broken line) and Wnratio = 48% (solid line) is a predetermined voltage step (1V or less step, for example, 0.25V step) with the gate-source voltage Vgs in the range of 0-5V. And Gm / W of a plurality of points measured and measured by curve fitting.

  As in the case of the drain current Ids shown in FIG. 22A, in the linear region Vds = 0.1 V, Gm / W does not depend on Wnratio as shown in FIG. That is, Wnratio = 40% (broken line) and Wnratio = 48% (solid line) almost coincide in the range of Vgs = 0 to 5V (the broken line and the solid line almost overlap). Although the cause is unknown, a difference appears in a partial section near 1 V <Vgs <1.25 V.

  On the other hand, in the saturation region Vds = 12 V, Gm / W depends on Wnratio as shown in FIG. That is, the characteristics differ between Wnratio = 40% (solid line) and Wnratio = 48% (broken line) (the broken line and the solid line do not overlap in a wide range of 1V <Vgs ≦ 5V).

  This cause was examined by focusing attention on the formation conditions of the inversion layer, which is a region where carriers contributing to electrical conduction are induced. The results will be described below with reference to FIGS. 24 (A) and 24 (B).

  Both FIG. 24A and FIG. 24B exemplify and schematically illustrate the layout of a high voltage MOSFET to be modeled, and explain the analysis results made by the inventors of the present application. FIG. In FIGS. 24A and 24B, a region denoted by reference numeral 117 is a region where the inversion layer is not formed (or the inversion layer is difficult to form).

FIG. 24A schematically illustrates how the inversion layer is formed when the drain-source voltage (drain voltage) Vds is low and the N-channel MOSFET operates in the linear region. When the gate voltage is applied to the gate electrode 115, the inversion layer 116 induced near the silicon substrate surface under the gate electrode 115 (just below the gate oxide film) spreads to the drain side because the potential difference from the source to the drain is small. It is thought that it is formed in a shape. In the vicinity of the P ⁺ type well contact diffusion layer 111, it is considered that no inversion layer is formed on the silicon substrate surface under the gate electrode 115. This is shown as a region 117 in which an inversion layer is hardly formed in FIG.

However, as shown in FIG. 24A, since the inversion layer 116 is formed over a wide range up to the end on the drain 114 side below the gate electrode 115, considering the total amount of charges in the inversion layer 116, P The influence of the inversion layer not being formed in the vicinity of the ⁺ type well contact diffusion layer 111 is small.

Therefore, in the linear region, the ratio Wpatio (= ΣWp / (ΣWn + ΣWp) × 100) of the total width (= ΣWp) of the P ⁺ -type well contact diffusion layer 111 to the total channel width W is the drain-source current. It is considered that the influence on Ids is small.

Further, since the ratio Wnratio (% notation) of the total width (= ΣWn) of the N ⁺ diffusion layer 112 that is the source diffusion layer to the total channel width W is Wnratio = (100−Wpatio)%, the linear region Then, it is considered that the influence of Wnratio on the total charge amount of the inversion layer 116 is small and the influence of Wnratio on the drain current Ids is small. For this reason, the drain-source current-drain-source voltage characteristic (Ids-Vds characteristic) and Gm / W in the linear region do not depend on the channel width ratio Wnratio of the N ⁺ diffusion layer.

  FIG. 24B schematically illustrates how the inversion layer is formed when the drain-source voltage Vds is high and the N-channel MOSFET operates in the saturation region. In the saturation region, the potential difference from the source to the drain is large, and the inversion layer 116 has a property of being formed in a region where the potential of the silicon substrate surface is low. Therefore, it is assumed that the inversion layer 116 is formed only in the vicinity of the source having a low channel potential (pinch-off: a reverse voltage is applied to the pn junction between the drain diffusion layer and the well (substrate), and the depletion layer expands. , The channel becomes narrower).

In this case, the fact that the inversion layer is not formed in the vicinity of the P ⁺ -type well contact diffusion layer 111 greatly affects the charge amount of the entire inversion layer 16. As a result, in the saturation region, the ratio Wnratio of the width ΣWn of the N ⁺ diffusion layer 112 to the total channel width W is considered to increase the influence on the drain current Ids.

Then, as shown in FIG. 24B, the inversion layer 16 is formed in a limited range on the source side of the surface of the silicon substrate immediately below the gate electrode 115 (in FIG. 24B, the inversion layer 116 is formed). The tip is limited to a region closer to the source side than the middle of the gate electrode 115), and the total charge amount of the inversion layer 116 is the ratio Wnratio of the total width (= ΣWn) of the N ⁺ diffusion layer 112 to the total channel width W Sensitive to differences in values. In other words, in the saturation region of FIG. 24B, an inversion layer is formed in the area surrounded by the drain side edge and the source side edge (N + diffusion layer 112) of the inversion layer 115 immediately below the gate electrode 115. The ratio of the area occupied by the region 117 that is difficult to be increased is larger than that in the linear region of FIG. 24A, and the total width (= ΣWp) of the P ⁺ -type well contact diffusion layer 111 is larger than the total channel width W. It is thought that the influence of the ratio Wpatio on the drain-source current (drain current) Ids increases.

  The effects (Gm / W dependence on Wnratio) as shown in FIGS. 23A and 23B are not considered in the related technology MOSFET model shown in FIG. I can't. This is considered to be the reason (cause) that it is difficult to create an accurate circuit simulation model for the high voltage MOSFET of FIG.

  As described above, in the high breakdown voltage MOSFET in which the source diffusion layers 112 and the well contact diffusion layers 111 are alternately arranged adjacently along the side of the gate electrode in the source region, the widths of the source diffusion layers 112 and the well contact diffusion layers 111 are as follows. There is no MOSFET model for circuit simulation that can express the characteristics of the electrical characteristics that change depending on the ratio (Wnratio), and thus the necessity for its implementation has been described.

  That is, the implementation of a MOSFET model for circuit simulation that can express the feature that the drain-source current Ids is highly dependent on Wnratio in the saturation region and the drain-source current Ids is less dependent on Wnratio in the linear region. is necessary.

  As a MOSFET model, it is desirable to realize a MOSFET model that can express these characteristics of electrical characteristics using as few modeling parameters as possible.

  Further, a mechanism for transferring the Wnratio value to the circuit simulator for the MOSFET model for circuit simulation or a mechanism for determining the Wnratio value in the MOSFET model is desired.

  It is also desirable to establish a procedure for extracting MOSFET models that express these features.

  In particular, it is desirable to establish a model extraction procedure including a structure of a TEG (Test Element Group) used for model extraction, an extraction algorithm, and an extraction tool.

According to the present invention, in the source region, a source diffusion layer (N ⁺ diffusion layer in the case of an N-channel MOSFET, P ⁺ diffusion layer in the case of a P-channel MOSFET) and a well contact diffusion layer (in the case of an N-channel MOSFET, A circuit of a high voltage MOSFET (lateral power MOS transistor) having an LDMOS (Laterally Diffused MOS) structure (lateral diffusion MOS structure) in which N + layers in the case of a P ⁺ layer and a P channel MOSFET are alternately arranged adjacent to each other. A model for simulation, a method for creating the model, and a model creation device are provided.

  FIG. 1A is a diagram showing a macro model configuration of a high voltage MOSFET (N-channel MOSFET) according to one embodiment of the present invention. As shown in FIG. 1A, the first MOSFET (1), the second MOSFET (2), and the variable resistance element (3) are configured, and the drain, gate, and back gate of the first MOSFET (1). (Bulk) is connected to the drain, gate, and back gate (bulk) of the second MOSFET (2), respectively, and the drain terminal D, gate terminal G, and back gate (bulk) terminal B of the high voltage MOSFET macro model, respectively. One end of the variable resistance element (3) is connected to the source of the second MOSFET (2), and the other end of the variable resistance element (3) is connected in parallel with the source of the first MOSFET (1). Connect to the source terminal S of the breakdown voltage MOSFET macro model. Although not particularly limited, both the first MOSFET (1) and the second MOSFET (2) are N-channel MOSFETs.

The channel width of the first MOSFET (1) is the sum (= ΣWn) of the width Wn (see FIG. 2) of the N ⁺ diffusion layer 12 of the source region of the high breakdown voltage MOSFET to be modeled,
The channel width of the second MOSFET (2) is the sum (= ΣWp) of the width Wp (see FIG. 2) of the P ⁺ diffusion layer 11 in the source region of the high breakdown voltage MOSFET to be modeled.

The variable resistance element (3) connected to the source of the second MOSFET (2) has a parasitic resistance component in the vicinity of the well contact diffusion layer (11 in FIG. 2; P ⁺ diffusion layer), and the drain current (drain) of the high breakdown voltage MOSFET. Equivalent resistance for expressing the effect on the current between sources).

  The resistance value Rs of the variable resistance element (3) in FIG. 1A typically has a dependency on the gate voltage (gate-source voltage) Vg as shown in FIG. The drain-source voltage is set so as to reflect the dependency of Vd. Note that when the source is GND (ground potential), the gate-source voltage is equal to the gate voltage, and the drain-source voltage is equal to the drain voltage. In FIG. 1B, the horizontal axis represents the drain voltage, and the vertical axis represents the resistance value Rs of the variable resistance element (3). In FIG. 1B, the Rs-Vd characteristic under the condition of constant gate voltage is plotted with respect to several different gate voltages Vg.

As shown in FIG. 1B, the bias dependence of the resistance value Rs of the variable resistance element (3) is
A first region 4 that increases as the drain voltage Vd increases;
A second region 5 in which the resistance value Rs does not depend on the drain voltage;
It consists of two areas.

  In the MOSFET model of FIG. 1A, the resistance value Rs is set to be smoothly connected at the boundary between the first region 4 and the second region 5.

  In the MOSFET model of FIG. 1A, the resistance value Rs of the variable resistance element (3) is set so as to decrease as the gate voltage Vg increases. That is, when the drain voltage Vd is constant, the resistance value Rs of the variable resistance element (3) decreases as the gate voltage Vg increases.

In the first MOSFET (1) and the second MOSFET (2), the high breakdown voltage MOSFET 7 (see FIG. 3) having a normal structure in which the source regions are all composed of the N ⁺ diffusion layer 12 (source diffusion layer), Apply the extracted model parameters as they are or with some modifications.

  Although the N-channel MOSFET has been described above, the present invention can also be applied to the P-channel MOSFET by inverting the polarity.

  According to the present invention, it is possible to obtain a circuit simulation model that accurately represents the characteristics of a source substrate connection type high voltage MOSFET based on a simple and clear procedure. Hereinafter, some embodiments will be described.

<Embodiment 1>
FIG. 1 is a diagram for explaining Embodiment 1 of the present invention. FIG. 1A shows an equivalent circuit of a macro model for circuit simulation of a high voltage MOSFET. In FIG. 1 (A),
Reference symbol D is a drain terminal of a macro model for high voltage MOSFET simulation,
Reference symbol G is the gate terminal of the macro model,
Reference symbol S is a source terminal of the macro model,
Reference symbol B is a back gate (bulk) terminal of the macro model.

  As shown in FIG. 1B, the MOSFET macro model includes a first MOSFET (1), a second MOSFET (2), and a variable resistance element (3), and the drain of the first MOSFET (1). , Gate and back gate (bulk) are commonly connected to the drain, gate and back gate (bulk) of the second MOSFET (2), respectively, and the drain terminal, gate terminal and back gate (back gate ( A bulk terminal, one end of the variable resistance element (3) is connected to the source of the second MOSFET (2), and the other end of the variable resistance element (3) together with the source of the first MOSFET (1) has a high breakdown voltage. It is connected to the source terminal of the MOSFET macro model.

  The variable resistance element (3) has a bias dependency of the high breakdown voltage macro model to be modeled, for example, a gate-source voltage dependency (gate voltage dependency) and a drain-source voltage dependency (drain voltage dependency). Have.

FIG. 2 is a diagram schematically showing a layout of a high breakdown voltage N-channel MOSFET corresponding to the macro model of the first embodiment. In FIG. 2, 11 is a well contact diffusion layer (P ⁺ diffusion layer) in the source region, 12 is a source diffusion layer (N ⁺ diffusion layer), and 13 is an N ⁺ diffusion layer (drain contact N ⁺ diffusion layer) in the drain region. , 14 are drain N ^- diffusion layers, and 15 is a gate electrode (formed on a gate insulating film on a silicon substrate). The N ⁺ diffusion layer represents a high concentration N type diffusion layer, the N ⁻ diffusion layer represents a low concentration N type diffusion layer, and the P ⁺ diffusion layer represents a high concentration P type diffusion layer.

In FIG. 2, the N-channel MOSFET is formed in the P-type well. However, when the N-channel MOSFET is formed on the surface of the P-type silicon substrate, for example, the P ⁺ -type well contact diffusion layer 111 is P It becomes a ⁺ type substrate contact diffusion layer. In this case, the following embodiment is applied as it is by replacing the well contact with the substrate contact.

In order to increase the breakdown voltage, a low concentration N ⁻ diffusion layer 14 is arranged between the N ⁺ diffusion layer 13 on the drain side and the gate electrode 15 on the surface of the silicon semiconductor substrate. On the source side, a P ⁺ -type well contact diffusion layer (P ⁺ diffusion layer) 11 and an N ⁺ -type source diffusion layer (N ⁺ diffusion layer) 12 are alternately arranged at regular intervals. . The structure on the source side illustrated in FIG. 2 is referred to as a “source substrate connection structure” as in FIG. A plurality of well contact diffusion layers (P ⁺ diffusion layers) 11 in the source region are connected in common to the back gate terminal (B), and a plurality of source diffusion layers (N ⁺ diffusion layers) 12 are shared in the source terminal (S). The N ⁺ diffusion layer 13 (drain contact) in the drain region is connected to the drain terminal (D).

In the MOSFET model of FIG. 1A, the channel width of the first MOSFET (1) is the sum (= ΣWn) of the width Wn of the N ⁺ diffusion layer 12 in the source region of FIG. ) Is the sum (= ΣWp) of the width Wp of the P ⁺ diffusion layer 11 (well contact) in the source region of FIG.

  In the MOSFET model of FIG. 1A, the resistance value Rs of the variable resistance element (3) is dependent on the dependency of the gate voltage (gate-source voltage) Vg and the drain voltage (as shown in FIG. 1B). The drain-source voltage is set so as to reflect the dependency of Vd. That is, as shown in FIG. 1B, the resistance value Rs of the variable resistance element 3 includes the first region 4 in which the resistance value Rs of the variable resistance element (3) depends on the drain voltage Vd, and the variable resistance element ( The resistance value Rs of 3) has the second region 5 that does not depend on the drain voltage Vd, and is set so that the first region 4 and the second region 5 are smoothly connected to each other at the boundary of the region 5.

  Further, as shown in FIG. 1B, the resistance value Rs of the variable resistance element 3 is set so as to reflect the characteristic that the resistance value Rs decreases (rises) as the gate voltage Vg increases (decreases).

  FIG. 3 schematically shows the layout of a high-voltage MOSFET having a normal structure used for extracting initial values of model parameters of the first MOSFET (1) and the second MOSFET (2) in the macro model of the first embodiment. FIG.

As shown in FIG. 3, the layout of the normal structure 7 is different from the structure of the source substrate connection structure 6 of FIG. 2 in that the source side structure is only the N ⁺ diffusion layer 12 (channel width = W) and the well contact. The layer (P ⁺ diffusion layer) 11 is disposed in a region on the opposite side to the side facing the gate electrode 15 of the N ⁺ diffusion layer 12.

<Embodiment 2>
Next, a second embodiment of the present invention will be described. FIG. 4 is a diagram showing a configuration of a model creating apparatus according to the second embodiment for creating the MOSFET model (referred to as “macro model”) of the first embodiment described with reference to FIGS. 1 and 2. It is.

  In FIG. 4, a wafer 21 having MOSFETs having two types of layout patterns, the source substrate connection structure 6 in FIG. 2 and the normal structure 7 in FIG. 3, is prepared.

  In the electrical characteristic measuring apparatus 22, the Id-Vg characteristic (drain current-gate voltage characteristic) and Id of the high breakdown voltage MOSFET (FIG. 2) having the source substrate connection structure on the wafer 21 and the high breakdown voltage MOSFET having the normal structure (FIG. 3) Measure electrical characteristics such as -Vd characteristics (drain current-drain voltage characteristics).

  The recording medium 23 records source substrate connection structure and normal structure electrical characteristic data 41/42, MOSFET extraction program 43, MOSFET model 44, macro model extraction program 45, macro model 48, model verification program 49, and the like. The recording medium 23 may be a storage device (for example, a magnetic disk storage device such as a HDD (Hard Disk Drive) or an optical disk storage device such as a DVD (Digital Versatile Disk)) provided with the recording medium. Of course.

  The information processing device 24 reads various measurement data and various models from the recording medium 23 and performs processing such as model extraction and model verification. Although not particularly limited, the information processing device 24 may execute a circuit simulation or the like using a SPICE simulator or the like, for example, using the macro model created in the present embodiment. Alternatively, circuit simulation may be executed by another information processing apparatus.

  FIG. 5 is a flowchart showing a procedure for creating a macro model by the apparatus shown in FIG. With reference to FIG.4 and FIG.5, the creation process of the macro model in Embodiment 1 is demonstrated.

  In process 31, the electrical characteristics of the wafer 21 are measured using the electrical characteristics measuring device 22, and electrical characteristics data is stored in the recording medium 23. At this time, electrical characteristics (drain current-gate voltage characteristics (Id-Vg characteristics), drain current-drain voltage characteristics) necessary for model extraction with respect to two types of high breakdown voltage MOSFETs having a source substrate connection structure and high breakdown voltage MOSFETs having a normal structure. (Id-Vd characteristic) etc.) is measured, and electric characteristic data 41 and 42 (normal structure electric characteristic data, source substrate connection structure electric characteristic data) are stored.

Next, in process 32, the electrical characteristic data of the recording medium 23 and the MOSFET extraction program 43 are read into the information processing device 24, and the MOSFET extraction program 43 is executed by the information processing device 24, whereby a high-voltage MOSFET model having a normal structure is obtained. Is stored in the MOSFET model 44 of the recording medium 23. MOSFET model used at this time, the high-voltage-only model that can express the bias dependence of the drain resistance (HiSIM_HV: Hi roshima University S tarc I GFET M odel H igh V oltage / large current) such as FIG. 19 (C )), And the dependency of the drain current on the channel length L is adjusted to some extent.

  Next, in processing 33, the MOSFET model 44 and the macro model extraction program 45 of the recording medium 23 are read into the information processing apparatus 24, and the macro model extraction program 45 is executed, whereby the source substrate shown in FIG. A macro model of a high breakdown voltage MOSFET having a connection structure is created and stored as a macro model 48 in the storage medium 23. At this time, only the variable resistance element 3 in FIG. 1A is adjusted without changing the contents of the MOSFET model (44 in FIG. 4). That is, the variable resistance element 3 incorporates the gate voltage Vg dependency and the drain voltage Vd dependency.

  Next, in process 34, the macro model 48 of the high breakdown voltage MOSFET of the source substrate connection structure is readjusted (the macro model 48 and the macro model extraction program 45 of the recording medium 23 are read into the information processing device 24 as necessary). In the process 34, adjustment is performed by paying particular attention to a parameter related to the drain resistance of the MOSFET. In FIG. 1A, parameters relating to the drain resistance (see the variable resistance element 101 in FIG. 19A) are incorporated in the model, and in the process 34, the parameters relating to the drain resistance are adjusted.

  Next, in process 35, the macro model 48 and the model verification program 49 of the recording medium 23 are read into the information processing apparatus 24, and the model verification program 49 is executed to verify the macro model 48.

  Next, in processing 36, the verification result of the macro model executed by the model verification program 49 is determined (for example, even if the user determines by looking at the verification result of the macro model output to the output device of the information processing device 24). It may be automatically determined by the information processing device 24), and if there is no problem, the process ends (OK branch of process 36). If there is a problem (NG branch of process 36), the process returns to process 34. It repeats until the verification result in the process 36 becomes OK.

  Next, a procedure for creating a macro model by the apparatus of the second embodiment shown in FIG. 4 will be described in detail with reference to FIG.

  The electrical characteristics measuring device 22 is used to measure the electrical characteristics of two types of patterns, a high breakdown voltage MOSFET (FIG. 2) having a source substrate connection structure mounted on the wafer 21 and a high breakdown voltage MOSFET having a normal structure (FIG. 3). The measurement data of the high-voltage MOSFET with the normal structure (FIG. 3) and the high-voltage MOSFET with the source substrate connection structure (FIG. 2) are the normal structure electrical characteristic data 41 and the source substrate connection structure electrical characteristic data 42, respectively. 4 of 23).

  Next, the information processing device 24 (FIG. 4) reads the normal structure electrical characteristic data 41 using the MOSFET extraction program 43, and the MOSFET threshold voltage and drain current characteristics (for example, Id-Vg characteristics, Id-Vd characteristics). However, model extraction is performed so as to coincide with the normal structure electrical characteristic data 41, and the resultant is stored as a MOSFET model 44 in a recording medium (23 in FIG. 4).

  The MOSFET model uses a high breakdown voltage dedicated model (HiSIM_HV, see FIG. 19C) that can express the bias dependence of the drain resistance, and the channel length dependence of the drain current is adjusted to some extent.

  Next, the information processing apparatus 24 (FIG. 4) uses the macro model extraction program 45 to read the MOSFET model 44 and the source substrate connection structure electrical characteristic data 42 from the recording medium 23 (FIG. 4), and to obtain the source substrate connection structure. The model is extracted so that the threshold voltage and drain current characteristics (for example, Id-Vg characteristic, Id-Vd characteristic) of the MOSFET match the source substrate connection structure electrical characteristic data 42, and a temporary macro is created. The model 46 is stored in a recording medium.

  At this time, the macro model extraction program 45 of the information processing device 24 (FIG. 4) adjusts only the variable resistance element 3 without changing the contents of the MOSFET model 44.

  The resistance value Rs of the variable resistance element 3 incorporates the gate voltage Vg dependency and the drain voltage Vd dependency. An example is shown below.

Rs' = (Rs0 + Rs1 * Vg + Rs2 * Vg 2) / W (1)

  Rs = Rs' * (f (Vd, δ) * 0.5 + 0.5) (2)

f (Vd, δ) = (Vg-0.5 * (Vg-Vd -δ + sqrt ((Vg-Vd -δ) ² + 4 * δ * Vg))) / Vg (3)

  δ = 0.01 (4)

  Here, Vg is a gate voltage (gate-source voltage), and Vd is a drain voltage (drain-source voltage). W is the total channel width (W = ΣWn + ΣWp). Rs is the resistance value of the variable resistance element 3.

  Further, the function f (Vd, δ) in the equation (3) is a smoothing function, and a straight line (0 ≦ Vd <) having a slope 1 / Vg passing through the origin (0, 0) at the coordinates (Vd, f (Vd)). Vg) and Vd> Vg, f (Vd) = 1, and the drain voltage Vd = Vg is smoothly connected before and after. When the value of δ is increased, it gradually changes around Vd = Vg.

  Therefore, Rs (resistance value of the variable resistance element 3) in the equation (2) is Rs when Vd = 0, 0 <Vd <Vg and a slope of 1 / Vg, Vs> Vg, Rs ′, and Vd = Vg Connect smoothly before and after.

  Further, another example of the variable resistance element 3 is shown in the following expressions (1 ′) to (3 ′).

R _s = ((R _s0 + R _s1 * V _g + R _s2 * V _g ² ) * f (V _d ) + R _s3 ) / W (1 ')

f (V _d , δ) = (V _dsat -0.5 * (V _dsat -V _d -δ + ((V _dsat -V _d -δ) ² + 4 * δ * V _dsat ) ^0.5 )) / V _dsat (2 ')

V _dsat = (V _g -V _t ) ^fac1 / fac2 (3 ')

  The parameters fac1 and fac2 in the saturation drain voltage Vdsat of equation (3 ') are for correcting the difference between the measured apparent saturation voltage and the pinch-off voltage in the MOSFET (transistor) caused by the voltage drop effect on the drift resistor. Are fitting parameters. Vt is the threshold voltage of the MOSFET. The pinch-off voltage of the MOSFET does not depend much on the presence or absence of the drift region, but the pinch-off of the MOSFET occurs at an apparently higher voltage in the high breakdown voltage MOSFET due to the voltage drop due to the parasitic resistance of the drift region than when there is no voltage drop. Is to correct. This correction is particularly necessary for a transistor with a short gate length.

  Next, the information processing apparatus 24 (FIG. 4) uses the macro model adjustment program 47 to read the temporary macro model 46 and the source substrate connection structure electrical characteristic data 42 from the recording medium 23 (FIG. 4), and particularly Id. The parameter of the drain resistance relationship of the MOSFET model in the temporary macro model 46 is adjusted so that the vicinity of the boundary between the linear region and the saturation region of the −Vd characteristic is matched, and is stored as the macro model 48 in the recording medium 23 (FIG. 4).

  Next, the information processing apparatus 24 (FIG. 4) uses the macro model verification program 49 to read the macro model 48 and the source substrate connection structure electrical characteristic data 42 from the recording medium 23 (FIG. 4), and verify the macro model. I do.

  Here, with respect to measurement data of various channel lengths and channel widths, the matching accuracy of electrical characteristics, channel length dependency, and channel width dependency are verified, and the results are recorded as a macro model verification result 50 on the recording medium 23. (FIG. 4).

  Next, the macro model verification result 50 is judged, and if there is no problem, the macro model 48 is terminated as a final result. If there is a problem, the process returns to the macro model adjustment process (the macro model adjustment program 47) and verified. Repeat until the result is OK. As input data at this time, instead of the temporary macro model 46, the macro model 48 is read from the recording medium 23 (FIG. 4).

  The effects of the first and second embodiments will be described.

In a high voltage MOSFET having a source substrate connection structure to be modeled,
The current in the region adjacent to the N ⁺ diffusion layer (12 in FIG. 2) is represented by the first MOSFET (1 in FIG. 1).
The current in the region adjacent to the P ⁺ diffusion layer (well contact diffusion layer, 11 in FIG. 2) is represented by a series connection circuit of the variable resistance element (3 in FIG. 1) and the second MOSFET (2 in FIG. 1).
The channel width Wn (total) of the N ⁺ diffusion layer (12 in FIG. 2) and the channel width Wp (total) of the P ⁺ diffusion layer (well contact diffusion layer, 11 in FIG. 2) are respectively determined in the first MOSFET 1 By incorporating the channel width and the channel width of the second MOSFET 2 into the macro model, the ratio of the channel widths of the N ⁺ diffusion layer (12 in FIG. 2) and the P ⁺ diffusion layer (11 in FIG. 2) (for example, Wnratio = ΣWn) The MOSFET characteristics that change depending on / (ΣWn + ΣWp)) could be fitted with high accuracy.

Regarding the carrier flow depending on the bias in the vicinity of the P ⁺ diffusion layer (well contact diffusion layer, 11 in FIG. 2) peculiar to the high breakdown voltage MOSFET of the source substrate connection structure, the drain-source current Ids of the high breakdown voltage MOSFET The equivalent resistance that can express the influence exerted is solved by connecting the variable resistance element 3 (see FIG. 1) in series with the source of the second MOSFET (2).

In the high breakdown voltage MOSFET having the source substrate connection structure, as described with reference to FIGS. 24A and 24B, the inversion layer 116 is formed in the channel region in the vicinity of the P ⁺ diffusion layer 111 (well contact diffusion layer). Is difficult to be formed (see region 117), and apparently a resistance is added, and the vicinity of the P ⁺ diffusion layer 11 is covered with the gate electrode 115, so that the resistance value is equal to the gate voltage. (Gate-source voltage) Vgs dependence.

In this embodiment, the resistance component (parasitic resistance) in the vicinity of the P ⁺ diffusion layer (11 in FIG. 2) is expressed by a resistance (variable resistance element 3 in FIG. 1) whose resistance value Rs depends on the gate-source voltage Vgs. doing. More specifically, when the gate-source voltage Vgs is high, the channel region around the P ⁺ diffusion layer 11 (11 in FIG. 2) is relatively less than when the gate-source voltage Vgs is low. In addition, it is considered that the inversion layer is easily formed, and the resistance value of the parasitic resistance is lowered. For this reason, the parasitic resistance has dependency on the gate-source voltage Vgs such that the resistance value decreases as the gate-source voltage Vgs increases (see Rs in FIG. 1B).

  In addition, in order to express characteristics peculiar to the high breakdown voltage MOSFET of the source substrate connection structure (see FIGS. 22 to 24 and their related explanations), the variable resistance element 3 (see FIG. 1) has a drain-source voltage (see FIG. (Drain voltage) Vds dependence was given. The typical form is demonstrated with reference to FIG.

  FIG. 6A is a diagram schematically showing an equivalent circuit of channels formed on the surface of the silicon semiconductor substrate immediately below the gate electrode 15 of the MOSFET having the layout structure of FIG. FIG. 6B is a diagram showing the drain-source voltage (drain voltage) dependence characteristics of the resistance value Rs of the variable resistance element 3 of FIG. 6A. The horizontal axis represents the drain voltage, and the vertical axis represents the variable resistance. This is the resistance value Rs of the element 3.

As shown in FIG. 6A, there is a gap between the N ⁺ diffusion layer 12 and the drain (low-concentration drain diffusion layer (N ⁻ diffusion layer) 14 and drain diffusion layer (N ⁺ diffusion layer) 13) in the source region. 1 is connected, and the second MOSFET 2 of FIG. 1 is connected between the P ⁺ diffusion layer 11 which is a well contact diffusion layer and the drains (14, 13), and the source of the second MOSFET 2 A variable resistance element 3 having a variable resistance value Rs is connected between the P ⁺ diffusion layers 11 (terminal S in FIG. 1). In FIG. 6A, two first MOSFETs 1 are arranged between the drain and the N ⁺ diffusion layer 12, and three series circuits of the second MOSFET 2 and the variable resistance element 3 are arranged in parallel between the drain and the P ⁺ diffusion layer 11. It is connected to the. The gates of these first and second MOSFETs 1 and 2 (five in total) are connected in common, connected to the gate terminal (G in FIG. 1) of the MOSFET model, the drains are connected in common, and the drain terminal (see FIG. 1 D). Two N ⁺ diffusion layers 11 are commonly connected and connected to a source terminal (S in FIG. 1) of the MOSFET model, and three P ⁺ diffusion layers 11 are commonly connected and a back gate (bulk) terminal of the MOSFET model. (B in FIG. 1).

  In FIG. 6B, the drain voltage dependency of the resistance value Rs of the variable resistance element 3 is that the first region 4 in which the resistance value Rs increases as the drain voltage Vd increases, and the resistance value Rs becomes the drain voltage Vd. The second area 5 is independent of the second area 5.

  More typically, at the boundary between the first region 4 and the second region 5, the resistance value Rs is configured to be smoothly connected by the smoothing function f (Vd, δ) of Expression (3). .

More typically, the boundary between the first region 4 and the second region 5 is set at or near the boundary between the linear region and the saturation region of the high voltage MOSFET to be modeled. As shown in FIG. 24A, in the region where the drain voltage Vd is low (linear region), the influence of the presence of the P ⁺ diffusion layer 111 on the drain current Id (drain-source current Ids) is small. As shown in FIG. 24B, in the region where the drain voltage Vd is high (saturation region), the presence of the P ⁺ diffusion layer 111 greatly affects the drain current Id (drain-source current Ids). It is a thing.

  According to this embodiment, the bias voltage dependence peculiar to the high voltage MOSFET having the source substrate connection structure can be expressed with high accuracy by the above-described operation.

Further, in FIG. 6A, the influence of the region where the inversion layer adjacent to the P ⁺ diffusion layer 11 is not sufficiently formed (117 in FIGS. 24A and 24B) on the drain current Id is expressed as the drain voltage Vd. And the variable resistance element 3 depending on the gate voltage Vg. For this reason, the parameters that need to be added when creating the macro model are a small number of parameters related to the variable resistance element 3 (for example, Rs0, Rs1, Rs2, etc. in the equation (1)).

  That is, according to the present embodiment, there is no significant increase in the fitting target parameter expected when the adjustment or improvement of the MOSFET model is performed, and the high-voltage MOSFET model having a normal structure in which the fitting method is established is the starting point. By fitting a small number of modeling parameters relating to the variable resistance element 3 (Rs0, Rs1, Rs2, etc. in the formulas (1), (2), etc.), a macro model with high accuracy could be formed.

Further, according to the configuration of the macro model of the present embodiment, when executing the circuit simulation, for the MOSFET model,
Pass the Wnratio value as an instance parameter (a parameter set for the element specified by the instance name), or
2 and 6, channel widths Wn and Wp respectively corresponding to the N ⁺ diffusion layer 12 and the P ⁺ diffusion layer 11 are passed, or
Calculate the value of Wnratio as a function of channel width W in the model,
Thus, the value of Wnratio used in the macro model can be specified.

In addition, a characteristic measurement pattern of a high-voltage MOSFET (see FIG. 3) having a normal structure in which the source regions are all formed of the N ⁺ diffusion layer 12 is prepared, and an electric characteristic is measured. Once the breakdown voltage MOSFET model is created, a macro model of a high breakdown voltage MOSFET model composed of a high breakdown voltage MOSFET model having a normal structure and the variable resistance element 3 is created, and a small number of parameters of the variable resistance element 3 are adjusted. Thus, a model for circuit simulation can be created by a method with a clear procedure.

  In the present embodiment, as shown in FIG. 6B, the variable resistance element 3 includes the first region 4 in which the resistance value increases as the drain voltage Vd increases, and the resistance value does not depend on the drain voltage. Although the example comprised from two area | regions of the 2nd area | region 5 was shown, when the request | requirement with respect to accuracy is low, you may represent the variable resistive element 3 with the model which consists of a single area | region. However, when the accuracy of the model is required, the variable resistance element 3 is a model composed of two regions as described above or a model composed of three or more regions as described in the fourth embodiment. Is preferably expressed.

  As the boundary between the first region 4 and the second region 5 in the model of the variable resistance element 3, for example, the drain voltage Vd near the boundary between the linear region and saturation region of the MOSFET to be modeled is selected. Alternatively, the drain voltage Vd higher than the boundary between the linear region and the saturation region of the MOSFET to be modeled, typically, a value about 1 to 2.5 times the drain voltage Vd serving as the boundary between the linear region and the saturation region. It is good. The drain voltage at the boundary between the linear region and the saturation region of the MOSFET is called “saturation voltage”.

  Although the N-channel MOSFET has been described in the first and second embodiments, the present invention can be similarly applied to the P-channel MOSFET by inverting the polarity of the first embodiment (P-channel MOSFET). In this case, the source terminal voltage is higher than the drain terminal voltage, and the gate-source voltage Vgs is a negative value or 0).

FIG. 7A and FIG. 7B show the results of modeling drain current-drain voltage characteristics (Id-Vd characteristics) with respect to different Wnratio (high line) and measured values ( FIG. 20 is a diagram comparing the conventional model of FIG. 19 (broken line, corresponding to FIG. 21). Here, Wnratio is the ratio (% notation) of the total ΣWn of the width Wn of each N ⁺ -type source diffusion layer (N ⁺ diffusion layer) 12 to the total channel width W (= ΣWn + ΣWp) in FIG. .

  Wnratio = {(ΣWn) / (ΣWn + ΣWp)} × 100

  In FIG. 7A, Wnratio = 48%, and in FIG. 7B, Wnratio = 40%. 7A and 7B, the horizontal axis represents drain voltage (drain-to-source voltage) Vds (unit: Voltage), and the vertical axis represents drain current (drain-to-source current) Id ( An Id-Vd curve is shown in which the gate voltage (gate-to-source voltage) Vgs is changed from 0 to 5V in 1V steps. At Vgs = 0V, the MOSFET is off and the drain current Id = 0.

  In FIG. 7A, the actual measurement value indicated by the ▲ mark, the embodiment indicated by the solid line, and the modeling result (conventional model) by the related technology indicated by the broken line indicate the entire range of Vds, the gate-source voltage (gate Voltage) Vgs = 0, 1, 2,...

  In FIG. 7B, the actual measurement value (▲) and the modeling result of the embodiment indicated by the solid line almost coincide with each other in both the linear region and the saturation region.

  On the other hand, in the conventional model shown by the broken line in FIG. 7B, the saturation region does not match (particularly, the difference from the actual measurement value (▲) becomes remarkable in the saturation region where the gate voltage Vgs is high).

  FIG. 8A and FIG. 8B compare the drain current (drain-source current) Ids in a state where the N-channel MOSFET is turned on between elements (MOSFETs) having different Wnratio. In FIG. 8, the drain current on the vertical axis is normalized by the total channel width W and is set to Ids / W. The Wnratio of the element (MOSFET) A on the horizontal axis is 40%, and the Wnratio of the elements (MOSFETs) B and C is 48% (Note that the elements B and C are common MOSFETs but are different MOSFETs). . As shown in FIG. 8A, the embodiment of the present invention indicated by a solid line and the actually measured value indicated by ● are substantially matched (the conventional model indicated by a broken line is also substantially matched).

  In the linear region (drain-source voltage Vds = 0.1 V, gate voltage Vg = 5 V) shown in FIG. 8A, the measured value (●) of the drain current Ids / W normalized by the total channel width W is , Wnratio = 40% of the element A and Wnratio = 48% of the elements B and C are substantially the same and hardly depend on Wnratio. Further, the modeling result Ids / W using the embodiment shown in FIGS. 2 and 6 is, as shown in FIG. 8A, in the linear region, Wnratio = 40% for the element A, Wnratio = for the elements B and C = It intersects with any actual measurement value (●) of 48%. As described with reference to FIG. 22A, the modeling result Ids / W using the model (conventional model) of the related technology such as FIG. 19 is a linear region as shown in FIG. In FIG. 5, the measured values (●) of the element A with Wnratio = 40% and the elements B and C with Wnratio = 48% intersect with each other and are almost the same.

  In the saturation region (drain-source voltage Vds = 12 V, gate voltage Vg = 5 V) shown in FIG. 8B, the measured value (●) of the drain current Ids / W normalized by the total channel width W (= ΣWn + ΣWp). ) Changes depending on Wnratio.

  In the saturation region shown in FIG. 8B, in the element A with Wnratio = 40%, the measured value of Ids / W (indicated by ●) and the modeling result Ids using the embodiment shown in FIGS. / W matches. On the other hand, in the modeling result using the related technology model (conventional model) such as FIG. 19 (intersection of the broken line and the element A), Ids / W is different from the measured value for the element A with Wnratio = 40%. It is remarkable.

  In FIG. 8B, the elements (solid lines) of the elements B and C with Wnratio = 48% agree with the actually measured values (●). It should be noted that the conventional model indicated by the broken line also substantially matches the actual measurement value (●) for the elements B and C with Wnratio = 48%.

<Embodiment 3>
FIG. 9 is a diagram showing a macro model for circuit simulation of a high voltage MOSFET in an equivalent circuit in the third embodiment of the present invention.

In FIG.
Reference symbol D is a drain terminal of a macro model for high voltage MOSFET simulation,
Reference symbol G is a gate terminal of the macro model,
Reference symbol S denotes a source terminal of the macro model,
Reference symbol B is a well terminal of the macro model.

Referring to FIG. 9, this macro model is
First MOSFET (151),
A second MOSFET (152),
A first variable resistance element (153),
A second variable resistance element (154),
Third variable resistance element (155)
It is composed of

  The gate and bulk (back gate) of the first MOSFET (151) are connected in common to the gate and bulk of the second MOSFET (152), respectively, and the gate terminal (G) and bulk terminal (B) of the high voltage MOSFET macro model, respectively. ).

  One end of the first variable resistance element (153) is connected to the drain of the first MOSFET (151), and one end of the second variable resistance element (154) is connected to the drain of the second MOSFET (152), The other end of the first variable resistance element (153) and the other end of the second variable resistance element (154) are both connected to the drain terminal (D) of the high voltage MOSFET macro model.

  One end of the third variable resistance element (155) is connected to the source of the second MOSFET (152), and the other end of the third variable resistance element (155) is connected to the source of the first MOSFET (151). It is connected to the source terminal (S) of the high voltage MOSFET macro model.

  The first and second variable resistance elements (153, 154) have dependency on the drain voltage of the high breakdown voltage macro model.

  The third variable resistance element (155) corresponds to the variable resistance element (3) of FIG. 1, and has a dependency on the gate voltage Vg and a dependency on the drain voltage Vd of the high voltage macro model.

  The difference between the first and second embodiments and the present embodiment is that the first variable resistance element (153) and the second variable resistance are connected to the drains of the first MOSFET (151) and the second MOSFET (152), respectively. The element (154) is inserted in series.

In the embodiments 1 and 2 requires a high withstand voltage only model (HiSIM_HV etc.) that can represent the drain voltage dependence of the drain resistor, in the third embodiment, ordinary MOSFET model (BSIM3 (B erkley S hort- channel I GFET (I nsulated G ate FET ) M odel), able to use BSIM4 etc.).

<Embodiment 4>
Next, a fourth embodiment of the present invention will be described. This embodiment is an embodiment relating to an apparatus for creating the macro model of the third embodiment shown in FIG. FIG. 11 is a diagram illustrating a configuration of the fourth embodiment. In FIG. 11, the same or equivalent elements as those in FIG.

  Referring to FIG. 11, the wafer 21 is prepared by mounting two types of patterns of MOSFETs, a source substrate connection structure (FIG. 2) and a normal structure (FIG. 3).

  The electrical characteristic measuring device 22 measures electrical characteristics such as Id-Vg and Id-Vd characteristics of the MOSFET (source substrate connection structure and normal structure) of the wafer 21.

  The recording medium 25 (or storage device) includes the electrical characteristic data 41/42, the MOSFET extraction program 43, the MOSFET model 44, the macro model 1 extraction program 45-1, the macro model 1 (48-1), and the macro model 2 extraction program 45. -2, macro model 2 (48-2), model verification program 49, etc. are recorded.

  The information processing device 24 reads various measurement data and various models, and performs model extraction and model verification.

  The difference between the present embodiment and the second embodiment is that the creation of the macro model is divided into two types.

  FIG. 12 is a flowchart showing a procedure for creating a macro model in the apparatus of FIG. In FIG. 12, processes that perform the same or equivalent processes as those in FIG. 5 are given the same reference numerals.

  First, in the process 31, the electrical characteristics of the wafer 21 are measured using the electrical characteristics measuring device 22, and the electrical characteristics data 41/42 is stored in the recording medium 25. At this time, electrical characteristics (drain current-gate voltage characteristics (Id-Vg characteristics), drain current-drain voltage characteristics (Id-Vd characteristics), etc.) required for model extraction with two types of patterns of the source substrate connection structure and the normal structure ) Is measured and recorded as electrical characteristic data 41 and 42.

  Next, in process 32, the electrical characteristic data 41/42 of the recording medium 25 and the MOSFET extraction program 43 are read into the information processing device 24, and a high voltage MOSFET model 44 having a normal structure is created. The model used at this time is a normal MOSFET model (BSIM3, BSIM4, etc.), and the channel length dependence of the drain current is adjusted to some extent. In the drain current-drain voltage characteristics (Id-Vd characteristics), the region where the gate voltage Vg is high may not match, but the process proceeds to the next.

  Next, in the process 37, the electrical characteristic data 41/42 of the recording medium 25, the MOSFET model 44, and the macro model 1 extraction program 45-1 are read into the information processing device 24, and the macro model of the high voltage MOSFET having the normal structure shown in FIG. 1 (48-1) is created.

  As shown in FIG. 10, a variable resistance element (153) is connected between the drain of the MOSFET (151) and the drain terminal D of the macro model. At this time, the parameters of the MOSFET are not changed as much as possible, and are adjusted only by the variable resistance element (153) of FIG. The variable resistance element (153) is dependent on the drain voltage Vd.

  Next, in the process 33, the macro model 1 (48-1) and the macro model 2 extraction program 45-2 of the recording medium 25 are read into the information processing apparatus 24, and the macro model 2 extraction program 45-2 is executed. A macro model 2 (48-2) of a high voltage MOSFET having a substrate connection structure is created.

  In the equivalent circuit of FIG. 9, the first MOSFET (151) and the second MOSFET (152) are the same model, and the first variable resistance element (153) and the second variable resistance element (154) are also the same. . At this time, only the variable resistance element (155) is adjusted without changing the contents of the macro model 1. The variable resistance element (155) includes the dependency of the gate voltage Vg and the drain voltage as in, for example, the expressions (1) to (4) (or the expressions (1 ′) to (3 ′)) of the first embodiment. Vd dependency is provided.

  Next, in process 34, the macro model 2 (48-2) and the macro model 2 extraction program (45-2) of the recording medium 25 are read into the information processing apparatus 24, and the macro model 2 extraction program (45-2) is executed. Thus, the macro model 2 (48-2) of the high breakdown voltage MOSFET having the source substrate connection structure is readjusted. At this time, the adjustment is performed by paying particular attention to parameters relating to drain resistance (152 and 153 in FIG. 9).

  Next, in process 35, the macro model 2 (48-2) and the model verification program 49 of the recording medium 25 are read into the information processing apparatus 24, and the macro model 2 (48-2) is verified.

  In the process 36, the model verification result is determined. If there is no problem, the process ends. If there is a problem (NG branch in the process 36), the process returns to the process 34 and is repeated until the verification result becomes OK.

  Regarding the detailed flow, the adjustment of the variable resistance element 153 is only added between the MOSFET model 44 and the macro model extraction program 45 in FIG. 13 referred to in the description of the second embodiment. Is omitted. In the fourth embodiment, the same effects as in the first and second embodiments are obtained.

<Embodiment 5>
Next, a fifth embodiment of the present invention will be described. FIG. 14 is a diagram illustrating a procedure for creating a macro model according to the fifth embodiment. The difference from the second embodiment is that a difference data generation program 52 and electrical characteristic difference data 53 are added. The procedure of this embodiment will be described below with reference to FIGS.

  The electrical characteristics measuring device 22 is used to measure the electrical characteristics of two types of patterns, a high breakdown voltage MOSFET (FIG. 2) having a source substrate connection structure mounted on the wafer 21 and a high breakdown voltage MOSFET having a normal structure (FIG. 3). The measurement data of the high-voltage MOSFET having the normal structure (FIG. 3) and the high-voltage MOSFET having the source substrate connection structure (FIG. 2) are transferred to the recording medium 23 as the normal structure electric characteristic data 41 and the source substrate connection structure electric characteristic data 42, respectively. Store.

  Next, the information processing apparatus 24 reads the normal structure electrical characteristic data 41 from the recording medium 23 using the MOSFET extraction program 43, and the threshold voltage and drain current characteristics of the MOSFET match the normal structure electrical characteristic data 41. The model is extracted as described above and stored in the recording medium 23 as the MOSFET model 44.

  As the MOSFET model, a high breakdown voltage dedicated model (for example, HiSIM_HV) that can express the bias dependency of the drain resistance is used, and the channel length dependency is adjusted to some extent.

  Next, the information processing apparatus 24 reads the normal structure electrical property data 41 and the source substrate connection structure electrical property data 42 from the recording medium 23 using the difference data generation program 52, and the normal structure electrical property data 41 is read. Then, the electrical characteristic difference data 53 obtained by subtracting the value obtained by multiplying the ratio of the width of the source diffusion layer (12) to the total channel width (ΣWn / W: FIG. 2) from the electrical characteristic data 42 of the source substrate connection structure is recorded. Store in the medium 23.

  In the information processing device 24, when the measurement points of the normal structural electrical property data 41 and the source substrate connection structural electrical property data 42 are different, for example, interpolation is performed by performing interpolation or extrapolation.

  Next, the information processing device 24 reads the MOSFET model 44 and the electrical characteristic difference data 53 using the macro model extraction program 45, and calculates the total channel width W of the MOSFET as the sum of the widths of the well contact diffusion layers (ΣWp 2), the variable resistance element 3 (see FIG. 1) is inserted into the source of the MOSFET model 44, and the variable resistance element 3 is adjusted in the same manner as in the second embodiment.

  Thereafter, the information processing apparatus 24 creates a macro model (FIG. 1 or FIG. 9) of the source substrate connection structure and stores it as the temporary macro model 46 in the recording medium 23. Subsequent steps are the same as those in the second embodiment, and a description thereof will be omitted.

  The macro model extraction program 45 of the present embodiment performs fitting (for example, curve fitting using the least squares method) on the waveform (data value) of the electrical characteristic difference data 53, so that the variable resistance element 3 in the macro model is obtained. Determine the modeling parameters.

  In addition, as a modification of the present embodiment, the macro model extraction program 45 uses the first value based on the waveform (data value) of the electrical characteristic difference data 53 when modeling the resistance value Rs of the variable resistance element 3. A function of detecting a boundary between the region 4 (see FIG. 1B) and the second region 5 (see FIG. 1B) may be provided.

  Further, the macro model extraction program 45 has a function of determining a parameter in a mathematical expression expressing the resistance value Rs of the variable resistance element 3 in the macro model or an initial value of the parameter based on the detected boundary. Also good.

  Alternatively, the macro model extraction program 45 allows the model creator to refer to the macro model extraction so that the first area 4 (see FIG. 1B) and the second area 5 (see FIG. 1B). A function of detecting and displaying the boundary may be provided.

  In addition, the macro model extraction program 45 sets the boundary between the first region 4 (see FIG. 1B) and the second region 5 (see FIG. 1B) in the electrical characteristics represented by the macro model as electrical characteristics. A function of comparing and verifying with the boundaries in the difference data 53 and displaying the verification result may be provided.

  For example, the macro model extraction program 45 detects the drain voltage Vd_gds0 at which the differential value of the drain current Id with respect to the drain voltage Vd becomes zero at each gate voltage using the electrical characteristic difference data 53, and the value is detected in the first region. 4 may be a boundary between the second region 5 and the second region 5.

  Alternatively, the macro model extraction program 45 is used as an initial value when fitting a parameter in a mathematical expression expressing the resistance value Rs of the variable resistance element 3. When there are a plurality of drain voltages Vd_gds0 at which the derivative value of the drain current by the drain voltage becomes zero, one or two intermediate points may be used as the boundary between the first region 4 and the second region 5. .

  Furthermore, as an example of the case where only one of a plurality of Vd_gds0 is used, the macro model extraction program 45 can include a region with a small drain bias in the characteristics in which Rs changes with the drain voltage Vd. The larger value of Vd_gds0 may be used as the boundary.

  This embodiment has the same effects as the first and second embodiments.

  Further, in the present embodiment, by creating the electrical characteristic difference data 53, the model parameter of the variable resistance element 3 in the macro model is determined with higher accuracy than when the electrical characteristic difference data 53 is not created. be able to.

This electrical characteristic difference data 53, which has extracted the P ⁺ strongly receive current component the influence of the parasitic resistance due to the presence of the diffusion layer 11 (see FIG. 1 (A)), by the P ⁺ diffusion layer 11 This is because the influence of the parasitic resistance appears more conspicuously, and the fitting of the model parameters of the variable resistance element 3 becomes easy.

  In addition, by creating the electrical characteristic difference data 53, the boundary between the first region 4 and the second region 5 necessary for modeling the resistance value Rs of the variable resistance element 3 with high accuracy (FIG. 1B). , FIG. 6B) becomes easy to detect.

Furthermore, according to this embodiment, the program executed by the information processing apparatus 24 is
The third electrical property data (by the calculation using the first electrical property measurement data (electrical property data 41 of the normal structure) and the second electrical property measurement data (the electrical property data 42 of the source substrate connection structure) Processing (function) for generating electrical characteristic difference data 53);
Processing (function) for generating a circuit simulation element model for the third electrical characteristic;
When the model parameter of the variable resistance element 3 is fitted or modeled, the first region 4 and the first area 4 required for modeling the resistance value Rs of the variable resistance element 3 with high accuracy are provided. 2 is easy to detect the boundary of the region 5 (see FIGS. 1B and 6B).

  In the present embodiment, the MOSFET is virtually divided into a plurality in the channel width W direction (see FIG. 6A), and the electrical characteristics of a specific virtual region out of the divided channel widths. , The current flowing through the series connection of the second MOSFET 2 and the variable resistance element 3 (Rs), the first electric characteristic actual measurement data (normal structure electric characteristic data 41) and the second electric characteristic actual measurement data (source substrate connection) It is obtained by calculation using the structural electrical characteristic data 42). Accordingly, the first region 4 and the second region 5 which are required for modeling the resistance value Rs of the variable resistance element 3 with high accuracy when fitting or modeling the model parameter of the variable resistance element 3. Detecting the boundaries of

<Embodiment 6>
Next, a sixth embodiment of the present invention will be described. The present embodiment is an example in which the region division of the resistance value Rs of the variable resistance element 3 is changed from two to three or more in the first to fifth embodiments.

In the present embodiment, the resistance value Rs of the variable resistance element 3 is
A bias region independent of the drain-source voltage Vds on the low voltage side;
A bias region depending on the drain-source voltage Vds;
It consists of three regions, a bias region that does not depend on the drain-source voltage Vds on the high voltage side. Further, the adjacent regions of the three regions are smoothly connected to each other.

  FIG. 15 is a diagram illustrating an example in which the resistance value Rs of the variable resistance element 3 is divided into three regions. In FIG. 15, the horizontal axis represents the drain voltage Vd, and the vertical axis represents the resistance value Rs of the variable resistance element 3.

In the present embodiment, the first region 4 in which the resistance value Rs in FIG. 1B depends on the drain voltage Vd is used as the first region 4 in which the resistance value Rs does not depend on the drain voltage Vd on the low drain voltage side. It is divided into two regions, the V _D side region (8) and the high V _D side region (9) of the first region where the resistance value Rs depends on the drain voltage Vd.

The boundary between the low V _D side region (8) of the first region and the high V _D side region (9) of the first region; and
The boundary between the high V _D side region (9) of the first region and the second region 5 is
Typically, in both cases, when the gate voltage Vg is high, the drain voltage Vd moves to the higher side.

More typically, the boundary between the low V _D side region (8) of the first region and the high V _D side region (9) of the first region, and
The boundary between the high V _D side region (9) of the first region and the third region (8);
Both are connected smoothly.

  The resistance value Rs of the variable resistance element 3 can be expressed using, for example, Expressions (5) to (13), for example.

    Voffset01 = Vg + Voffset1 (5)

    Voffset02 = Vg + Voffset2 (6)

Rs01 = (Rs0 + Rs1 * Vg + Rs2 * Vg ² ) / W (7)

    Rs02 = Rs01 * Voffset02 / Voffset01 (8)

    Rs10 = Rs01 * Rs3 (9)

Rs11 = Rs01 * (Voffset01-0.5 * (Voffset01-Vd-δ + sqrt ((Voffset01- Vd-δ) ² + 4 * δ * Voffset01))) / Voffset01 (10)

Rs12 = Rs02 * (Voffset02-0.5 * (Voffset02-Vd-δ + sqrt ((Voffset02-Vd-δ) ² + 4 * δ * Voffset02))) / Voffset02 (11)

    Rs = Rs10 + (Rs01 / (Rs02 − Rs01)) * (Rs12 − Rs11) (12)

    δ = 0.01 (13)

here,
Voffset1 is a fitting parameter for expressing the boundary between the low drain voltage side region (8) of the first region and the high drain voltage side region (9) of the first region,
Voffset2 is a fitting parameter for expressing the boundary between the high drain voltage side region (9) of the first region and the second region (5),
Rs1, Rs2, Rs3, and Rs4 are fitting parameters for expressing the gate bias dependence of the resistance value Rs.

Further, in a more preferable form of the macro model extraction program 45 in the sixth embodiment, in the macro model extraction program 45 of the third embodiment, the first area 4 (see FIG. 1B) and the second area 5 ( In place of the procedure for detecting the boundary in FIG.
The boundary between the low V _D side region (8) of the first region and the high V _D side region (9) of the first region; and
High V _D side region of the first region (9) to detect the boundary between the second region (5), it has a function of executing the same processing as the third embodiment.

In the sixth embodiment, the macro model extraction program 45 uses the electrical characteristic difference data 53 to detect two drain voltages Vd_gds0 at which the differential value of the drain current by the drain voltage becomes zero at each gate voltage,
Let Vd_gds0 on the low drain bias side be the boundary between the low V _D side region (8) of the first region and the high V _D side region (9) of the first region,
The high drain bias side Vd_gds0, the boundary between the high _{V D} side region of the first region (9) the second region (5),
Is provided in the macro model extraction program 45.

  The reason why the resistance value Rs of the variable resistance element 3 in FIG. 1 or FIG. 9 is divided into three regions in the sixth embodiment will be described with reference to FIG.

FIG. 16 (A) shows an embodiment in which an inversion layer is formed at a lower V _D side region of the first region (8). Low V _D side region of the first region (8), the MOSFET drain voltage Vd is at a low region is operated in the linear region, the inversion layer 116 extends to the drain end near the gate power.

For this reason, the region 117 where the inversion layer formed in the vicinity of the P ⁺ diffusion layer (well contact diffusion layer) 11 is not formed (therefore, the region having a small channel charge) has little influence on the charges of all inversion layers. . Therefore, the value of the parasitic resistance Rs modeled as the variable resistance element 3 of FIG. 1 or FIG. 9 is small.

  Further, since the inversion layer always extends to the vicinity of the drain of the 116 gate electrode 115, the drain voltage dependency of the parasitic resistance Rs modeled as the variable resistance element 3 in FIG. 1 or FIG. 9 is small.

FIG. 16 (B) shows a configuration in which an inversion layer is formed in the high V _D side region of the first region (9). This is the form in intermediate drain bias conditions lower V _D side region (8) and a second region of the first region (5). The drain voltage Vd is higher than the low V _D side region (8) of the first region, and the transistor operates in the saturation region or the transition region from the linear region to the saturation region.

  Since the range where the inversion layer 116 is formed is wider on the drain side than the region 117 where the inversion layer is not yet formed, the influence of the region 117 where the inversion layer is not formed on the total inversion layer charge is Compared to the case where it is formed in a very narrow range near the drain region, it is small.

Further, the high V _D side region of the first region (9), the range boundaries of the drain region side of which is formed of the inversion layer 116, with increasing drain voltage Vd, the ends of the drain region side of the gate electrode 115 To move closer to the source area.

Therefore, as the drain voltage Vd increases, the influence of the region 117 where the inversion layer is not formed on the total inversion layer charge increases. Therefore, the high V _D side region of the first region (9), with increasing drain voltage Vd, the value of the parasitic resistance Rs which is modeled as a variable resistance element 3 of FIG. 1 or FIG. 9 is increased.

FIG. 16C shows a mode in which an inversion layer is formed in the second region (5). Second region (5) is a state higher drain voltage Vd than the high V _D side region (9) of the first region, MOS transistors operating in the saturation region. At this time, the inversion layer 116 is formed in a narrow range near the source region. For this reason, the region 117 where the inversion layer is not formed (therefore, the region where the channel charge is small) has a large influence on the total inversion layer charge, and the value of the parasitic resistance Rs modeled as the variable resistance element 3 in FIG. large.

Further, in this state, the boundary on the drain region side of the inversion layer 116 is closer to the source region than the boundary on the drain side of the region where the region 117 where the inversion layer is not already formed is present. The change in the influence of the region 117 where the inversion layer is not formed due to the change on the total inversion layer charge is also reduced. For this reason, the value of the parasitic resistance Rs modeled as the variable resistance element 3 in FIG. 1 or FIG. 9 does not depend on the drain voltage, or the dependence on the drain voltage depends on the high V _D side region of the first region. It is smaller than the case of (9).

The boundary between the low V _D side region (8) of the first region and the high V _D side region (9) of the first region is a drain voltage Vd that is a boundary between the linear region and saturation region of the MOSFET to be modeled, That is, it is approximately the same as the saturation voltage. Alternatively, the value is slightly lower than the saturation voltage, for example, typically a value about 0.2 to 1 times the saturation voltage.

The boundary between the high V _D side region (9) of the first region and the second region (5) is set to the same level as the saturation voltage of the MOSFET to be modeled. Alternatively, the value is higher than the saturation voltage, for example, typically about 1 to 2.5 times the saturation voltage.

In addition, the drain voltage serving as the boundary between the high V _D side region (9) and the second region (5) of the first region is equal to the low V _D side region (8) of the first region and the first region. It is higher than the drain voltage which becomes the boundary of the high V _D side region (9).

  In the present embodiment, the example in which the resistance value Rs (representing the parasitic resistance Rs) of the variable resistive element 3 is divided into three regions has been shown. However, if necessary, the resistance value Rs is further divided into four or more regions. Also good.

  In the present embodiment, in the extraction procedure of the first to fifth embodiments, the resistance value Rs of the variable resistance element 3 is determined in the procedure of modeling the resistance value Rs of the variable resistance element 3 so as to be composed of two regions. A model is extracted by modeling so as to be composed of three regions or four or more regions.

  In the present embodiment, the resistance value Rs of the variable resistance element 3 is modeled in a region divided more than the two regions described in the first embodiment and the like. Modeling accuracy can be improved. As a result, the accuracy of the macro model for circuit simulation is improved, and the accuracy of the circuit simulation using this macro model is improved.

Further, in the present embodiment, by creating the electrical characteristic difference data 53 described in the fifth embodiment, the first region required for modeling the resistance value Rs of the variable resistance element 3 with high accuracy is reduced. The boundary between the V _D side region (8) and the high V _D side region (9) of the first region, and the boundary between the high V _D side region (9) of the first region and the second region (5) Is easier to detect.

<Embodiment 7>
Next, a seventh embodiment of the present invention will be described. In the present embodiment, the following forms, or some of the following forms, are added to the macro model extraction program 45 in the fifth and sixth embodiments. In the present embodiment, a model and a macro model of the variable resistance element 3 are generated by obtaining parasitic resistance sensitivity data 61 representing the current sensitivity of the MOSFET with respect to the parasitic resistance added to the source side of the MOSFET. The seventh embodiment will be described with reference to FIGS. 17 and 18.

  FIG. 18 is obtained by replacing a part of the procedure using the MOSFET model 44 in FIG. 17 with a procedure using the normal structural electrical characteristic data 41.

  In the seventh embodiment, the MOSFET for the parasitic resistance added to the source side of the MOSFET by the parasitic resistance sensitivity analysis program 64 using the normal structure electrical characteristic data 41 or the MOSFET model 44 corresponding to the normal structure electrical characteristic data 41 is used. Parasitic resistance sensitivity data 61 representing the current sensitivity is obtained. The parasitic resistance sensitivity data is data representing how much the drain current of the MOSFET fluctuates when a certain amount of parasitic resistance is attached on the source side under each bias condition.

  When the parasitic resistance sensitivity data 61 is obtained using the normal structural electrical characteristic data 41 instead of the MOSFET model 44, the normal structural electrical characteristic data 41 is treated as a table model to obtain the parasitic resistance sensitivity data 61. Here, the table model is a mechanism for obtaining the MOSFET current (drain current) under a given bias condition from a collection of MOSFET current value data at each bias point, unlike the MOSFET model expressed by mathematical formulas. Say.

  Next, the parasitic resistance component extraction program is obtained by using the normal structure electrical characteristic data 41 or the normal structure MOSFET model 44 corresponding to the normal structure electrical characteristic data, the electrical characteristic difference data 53, and the obtained parasitic resistance sensitivity data 61. 65, Rs bias dependency estimation data 62, which is data in which the bias dependency of the resistance value Rs of the variable resistance element 3 (155 in FIG. 9) of FIG. 1 is estimated, is created. That is, normal structure electrical characteristic data 41 that is an electrical characteristic that does not have a parasitic resistance Rs on the source side, and electrical characteristic difference data 53 that is an electrical characteristic that has a parasitic resistance Rs on the source side (corresponding to the current flowing through the second MOSFET 2) ) To obtain the current fluctuation amount due to the parasitic resistance per unit channel width under each bias condition.

  Then, using the obtained current fluctuation amount and the parasitic resistance sensitivity data 61 indicating the influence of the parasitic resistance on the current under each bias condition, the resistance value Rs bias dependency estimation data 62 which is the parasitic resistance under each bias condition. Specifically, this is a procedure for obtaining the Rs bias dependency estimation data 62 for the resistance value Rs of the variable resistance element 3 (155 in FIG. 9) under each bias condition. The Rs bias dependency estimation data is characteristic data as shown in FIGS. 1B, 6B, and 15, for example.

  Also, the macro model extraction program 45 in FIG. 17 uses the bias dependency estimation data 62 of Rs and the bias dependency of the resistance value Rs of the variable resistance element 3 (155 in FIG. 9) by the variable resistance model parameter extraction program 66. Create a variable resistance model 63 that is a parameter representing the sexiness,

  Then, the macro model extraction program 45 uses the Rs bias dependency estimation data 62 to create an initial value model for creating a parameter representing the bias dependency of the resistance value Rs of the variable resistance element 3 (155 in FIG. 9). The variable resistance model 63 is created by using the variable resistance model 63.

  The variable resistance model parameter extraction program 66 may automatically generate the variable resistance model 63. Alternatively, the variable resistance model parameter extraction program 66 is appropriately selected in the information processing apparatus (24 in FIG. 4) that executes the variable resistance model parameter extraction program 66 according to the operation / instruction from the operator. May be generated.

  In addition, the temporary macro model 46 having the same configuration as that in FIG. 1A is generated by the temporary macro model creation program 67 using the obtained variable resistance model 63 and the MOSFET model 44 corresponding to the normal structure electrical characteristic data. Is done. As described above, the seventh embodiment makes it possible to extract a parameter representing the bias dependence of the resistance value Rs of the variable resistance element 3 with high accuracy.

  It should be noted that the disclosures of the above-mentioned patent documents and non-patent documents are incorporated herein by reference. Within the scope of the entire disclosure (including claims) of the present invention, the embodiments and examples can be changed and adjusted based on the basic technical concept. Various disclosed elements (including each element of each claim, each element of each embodiment, each element of each drawing, etc.) can be combined or selected within the scope of the claims of the present invention. . That is, the present invention of course includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the technical idea.

1, 151 First MOSFET
2, 152 Second MOSFET
3, 155 Variable resistance element 6 Source substrate connection structure 7 Normal structure 11, 111 P ⁺ diffusion layer (well contact diffusion layer)
12, 112 N ⁺ diffusion layer (source diffusion layer)
13, 113 Drain diffusion layers 14, 114 Low-concentration drain diffusion layers 15, 115 Gate electrode 21 Wafer 22 Electrical property measuring device 23, 25 Recording medium 24 Information processing device 31-37 Processing 41, 42 Electrical property data 43 MOSFET extraction program 44 MOSFET model 45, 45-1, 45-2 Macro model extraction program 46 Temporary macro model 47 Macro model adjustment program 48, 48-1, 48-2 Macro model 49 Model verification program 50 Model verification result 51 Result determination 52 Difference data generation Program 53 Electrical characteristic difference data 61 Parasitic resistance sensitivity data 62 Rs bias dependency estimation data 63 Variable resistance model 64 Parasitic resistance sensitivity analysis program 65 Parasitic resistance component extraction program 66 Variable resistance model parameter extraction program 7 Provisional macro model creating program 101 a variable resistor 102, 104 MOSFET
103 JFET
116 Inversion layer 117 Region where inversion layer is hard to be formed (region where inversion layer is not formed)
153, 154, 155 variable resistance element

Claims (26)

As a model of a MOSFET for circuit simulation of a high breakdown voltage MOSFET having a source diffusion layer and a source region in which the source diffusion layer and a well-contact diffusion layer of opposite conductivity type are disposed adjacent to each other in the channel width direction,
The drains are connected in common, the gates are connected in common, the back gates are connected in common, and the first and second channel widths corresponding to the width of the source diffusion layer and the width of the well contact diffusion layer in the source region, respectively. First and second MOSFETs having:
A first variable resistance element having one end connected to the source of the second MOSFET;
With
A connection point between the source of the first MOSFET and the other end of the first variable resistance element is used as a source terminal, and the commonly connected drain, the commonly connected gate, and the common of the first and second MOSFETs Means for creating a model in which the connected back gate is a drain terminal, a gate terminal, and a back gate terminal, respectively;
Storage means for storing electrical characteristic data of the high breakdown voltage MOSFET to be modeled;
Means for reading out the electrical characteristic data of the high withstand voltage MOSFET from the storage means, and adjusting a resistance value of the first variable resistance element of the model of the MOSFET for circuit simulation based on the electrical characteristic data;
A model creation device characterized by comprising: In the source region, the channel width of the first MOSFET in the MOSFET model for circuit simulation of the high breakdown voltage MOSFET, in which the source diffusion layer and the well contact diffusion layer are alternately arranged in the channel width direction. Is the sum of the widths of the source diffusion layers in the source region of the modeling target MOSFET, and the channel width of the second MOSFET is the sum of the widths of the well contact diffusion layers in the source region of the modeling target MOSFET The model creation apparatus according to claim 1, further comprising:   The model of the circuit simulation MOSFET includes a second variable resistance element and a third variable resistance element between a drain of the first and second MOSFETs and a drain terminal of the model, respectively. Item 3. The model creation device according to item 1 or 2.   A first region in which a resistance value of the first variable resistance element of the MOSFET model for circuit simulation depends on a drain-source voltage; and a second region that does not depend on the drain-source voltage; 4. The model according to claim 1, further comprising a unit configured to smoothly connect the first region and the second region. 5. Creation device.   The boundary between the first region and the second region of the resistance value of the first variable resistance element of the MOSFET model for circuit simulation is defined as the boundary between the linear region and the saturation region of the high voltage MOSFET to be modeled. Means for setting a value corresponding to a value within a voltage range having a lower limit as a drain-source voltage and a voltage obtained by multiplying the drain-source voltage at the boundary by a predetermined number of times as an upper limit. The model creation apparatus according to claim 4. In the MOSFET model for circuit simulation, the first variable resistance element corresponds to an equivalent resistance for expressing the influence of the parasitic resistance near the well contact diffusion layer on the drain current of the MOSFET,
A first region in which the resistance value of the first variable resistance element increases as the drain-source voltage increases; and a second region in which the resistance value does not depend on the drain-source voltage. The resistance value is smoothly connected at the boundary between the first region and the second region, and the resistance value of the first variable resistance element has a characteristic of decreasing as the gate-source voltage increases. The model creation device according to any one of claims 1 to 3, wherein In the MOSFET model for circuit simulation,
The resistance value of the first variable resistance element is
A first region that depends on the drain-source voltage; and a second region that does not depend on the drain-source voltage;
Dividing the first region into at least two regions corresponding to the drain-source voltage characteristics of the resistance value;
2. The apparatus according to claim 1, further comprising: a unit configured to smoothly connect the first and second regions and adjacent regions of a region obtained by dividing the first region. 4. The model creation device according to any one of items 3. Using the electrical characteristics data of a normal structure high voltage MOSFET having a source region composed of the source diffusion layer without including the well contact diffusion layer, a normal structure MOSFET model is created,
In the MOSFET model composed of the normal structure MOSFET model and the first variable resistance element, the first variable resistance element of the first variable resistance element is matched with the electrical characteristic data of the high breakdown voltage MOSFET to be modeled. The model creating apparatus according to claim 1, further comprising a parameter adjusting unit. Generating a first model comprising a MOSFET model composed of the normal-structure MOSFET model and the first variable resistance element;
Based on the first model, a second model including the second and third variable resistance elements between the drain terminals of the modeling target MOSFET is generated as a model of the circuit simulation MOSFET. 4. The model creation according to claim 3, further comprising means for adjusting a resistance value of the second and third variable resistance elements after adjusting a resistance value of the first variable resistance element. apparatus. The electrical characteristic data of the normal structure MOSFET is multiplied by a value obtained by dividing the sum of the widths of the source diffusion layers in the source region of the high breakdown voltage MOSFET to be modeled by the channel width of the high breakdown voltage MOSFET to be modeled. Means for subtracting the calculated value from the electrical characteristic data of the high breakdown voltage MOSFET to be modeled to obtain electrical characteristic difference data;
A portion corresponding to the sum of the widths of the well contact diffusion layers in the source region of the high breakdown voltage MOSFET to be modeled is defined as a model of the normal structure MOSFET, a model of the normal structure MOSFET, and a model of the normal structure MOSFET. Means for adjusting a resistance value of the first variable resistance element connected to a source;
The model creation device according to claim 1, wherein the model creation device includes: Means for obtaining parasitic resistance sensitivity data representing the current sensitivity of the MOSFET with respect to the parasitic resistance added to the source side of the high breakdown voltage MOSFET to be modeled;
Means for creating a variable resistance model depending on the bias of the first variable resistance element;
The model creation device according to claim 1, wherein the model creation device includes: As a model of a MOSFET for circuit simulation of a high breakdown voltage MOSFET having a source diffusion layer and a source region in which the source diffusion layer and a well-contact diffusion layer of opposite conductivity type are disposed adjacent to each other in the channel width direction,
The drains are connected in common, the gates are connected in common, the back gates are connected in common, and the first and second channel widths corresponding to the width of the source diffusion layer and the width of the well contact diffusion layer in the source region, respectively. First and second MOSFETs having:
A first variable resistance element having one end connected to the source of the second MOSFET;
With
The connection point between the source of the first MOSFET and the other end of the first variable resistance element is used as a source terminal, the drain connected in common, the gate connected in common, and the back gate connected in common between the first and second MOSFETs. Are the drain terminal, the gate terminal, and the back gate terminal, respectively, and the resistance element of the first variable resistance element is a drain-source voltage dependence characteristic and a gate-source voltage dependence characteristic of the high breakdown voltage MOSFET to be modeled. A computer-readable recording medium on which a MOSFET model set to have characteristics is recorded. A MOSFET model for circuit simulation of a high breakdown voltage MOSFET having a source diffusion layer and a source region in which the source diffusion layer and a well-contact diffusion layer of opposite conductivity type are disposed adjacent to each other in the channel width direction In creating with the device,
The drains are connected in common, the gates are connected in common, the back gates are connected in common, and the first and second channel widths corresponding to the width of the source diffusion layer and the width of the well contact diffusion layer in the source region, respectively. First and second MOSFETs having:
A first variable resistance element having one end connected to the source of the second MOSFET;
With
Using the connection point between the source of the first MOSFET and the other end of the first variable resistance element as a source terminal, the commonly connected drain, the commonly connected gate, and the common connection of the first and second MOSFETs Processing to create a model with the back gate as a drain terminal, a gate terminal, and a back gate terminal,
A process of reading electrical characteristic data of the high breakdown voltage MOSFET from storage means for storing electrical characteristic data of the high breakdown voltage MOSFET to be modeled, and adjusting a resistance value of the first variable resistance element based on the electrical characteristic data The
A program to be executed by the information processing apparatus. A MOSFET model for circuit simulation of a high breakdown voltage MOSFET having a source diffusion layer and a source region in which the source diffusion layer and a well-contact diffusion layer of opposite conductivity type are disposed adjacent to each other in the channel width direction In creating with the device,
The drains are connected in common, the gates are connected in common, the back gates are connected in common, and the first and second channel widths corresponding to the width of the source diffusion layer and the width of the well contact diffusion layer in the source region, respectively. First and second MOSFETs having:
A first variable resistance element having one end connected to the source of the second MOSFET;
With
A connection point between the source of the first MOSFET and the other end of the first variable resistance element is used as a source terminal, and the commonly connected drain, the commonly connected gate, and the common of the first and second MOSFETs Create models that use the connected back gates as the drain terminal, gate terminal, and back gate terminal, respectively.
The electrical characteristic data of the high breakdown voltage MOSFET is read out from the storage means for storing the electrical characteristic data of the high breakdown voltage MOSFET to be modeled, and the first variable of the model of the MOSFET for circuit simulation is based on the electrical characteristic data A model creation method characterized by adjusting a resistance value of a resistance element. In the source region, the channel width of the first MOSFET in the MOSFET model for circuit simulation of the high breakdown voltage MOSFET in which the source diffusion layer and the well contact diffusion layer are alternately arranged in the channel width direction. , The sum of the widths of the source diffusion layers of the source region of the modeling target MOSFET,
15. The model creation method according to claim 14, wherein the channel width of the second MOSFET is a sum of widths of the well contact diffusion layers in the source region of the modeling target MOSFET.   The second and third variable resistance elements are respectively inserted between the drains of the first and second MOSFETs and the drain terminals of the model as models of the MOSFETs for circuit simulation. Item 16. A model creation method according to item 14 or 15.   A first region in which a resistance value of the first variable resistance element of the MOSFET model for circuit simulation depends on a drain-source voltage; and a second region that does not depend on the drain-source voltage; 17. The model creation method according to claim 14, wherein the first region and the second region are set so as to be smoothly connected.   The boundary between the first region and the second region of the resistance value of the first variable resistance element of the MOSFET model for circuit simulation is defined as the boundary between the linear region and the saturation region of the high voltage MOSFET to be modeled. The drain-source voltage is set to correspond to a value within a voltage range having a lower limit, and a voltage obtained by multiplying the drain-source voltage at the boundary by a predetermined number of times as an upper limit. Item 18. A model creation method according to Item 17. In the MOSFET model for circuit simulation, the first variable resistance element corresponds to an equivalent resistance for expressing the influence of the parasitic resistance near the well contact diffusion layer on the drain current of the MOSFET,
A first region in which the resistance value of the first variable resistance element increases as the drain-source voltage increases; and a second region in which the resistance value does not depend on the drain-source voltage. The resistance value is smoothly connected at the boundary between the first region and the second region, and the resistance value of the first variable resistance element has a characteristic of decreasing as the gate-source voltage increases. The model creation method according to any one of claims 14 to 16. In the MOSFET model for circuit simulation,
The resistance value of the first variable resistance element is
A first region that depends on the drain-source voltage; and a second region that does not depend on the drain-source voltage;
Dividing the first region into at least two regions corresponding to the drain-source voltage characteristics of the resistance value;
17. The device according to claim 14, wherein the first and second regions and adjacent regions of the region obtained by dividing the first region are set so as to be smoothly connected to each other. The model creation method described in the section. Using the electrical characteristics data of a normal structure high voltage MOSFET having a source region composed of the source diffusion layer without including the well contact diffusion layer, a normal structure MOSFET model is created,
In the MOSFET model composed of the normal structure MOSFET model and the first variable resistance element, the first variable resistance element of the first variable resistance element is matched with the electrical characteristic data of the high breakdown voltage MOSFET to be modeled. 21. The model creation method according to claim 14, wherein a parameter is adjusted. Generating a first model comprising a MOSFET model of the normal structure and a MOSFET model comprising the first variable resistance element;
Based on the first model, a second model including the second and third variable resistance elements between the drain terminals of the modeling target MOSFET is generated as a model of the circuit simulation MOSFET. The model creation method according to claim 16, wherein the resistance values of the second and third variable resistance elements are adjusted after adjusting the resistance values of the first variable resistance elements. The electrical characteristic data of the normal structure MOSFET is multiplied by a value obtained by dividing the sum of the widths of the source diffusion layers in the source region of the high breakdown voltage MOSFET to be modeled by the channel width of the high breakdown voltage MOSFET to be modeled. The value obtained by subtracting the value from the electrical property data of the high breakdown voltage MOSFET to be modeled to obtain electrical property difference data,
A portion corresponding to the sum of the widths of the well contact diffusion layers in the source region of the high breakdown voltage MOSFET to be modeled is defined as a model of the normal structure MOSFET, a model of the normal structure MOSFET, and a model of the normal structure MOSFET. The model creation method according to claim 14, wherein a resistance value of the first variable resistance element connected to a source is adjusted. Obtain parasitic resistance sensitivity data representing the current sensitivity of the MOSFET with respect to the parasitic resistance added to the source side of the high breakdown voltage MOSFET to be modeled,
The model creation method according to claim 14, wherein a variable resistance model depending on a bias of the first variable resistance element is created.   A simulation apparatus that executes a circuit simulation using a MOSFET model created by the model creation apparatus according to claim 1.   25. A simulation method for executing a circuit simulation using a MOSFET model created by the model creation method according to claim 14.

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