JP2005227435A - Display device - Google Patents

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JP2005227435A
JP2005227435A JP2004034658A JP2004034658A JP2005227435A JP 2005227435 A JP2005227435 A JP 2005227435A JP 2004034658 A JP2004034658 A JP 2004034658A JP 2004034658 A JP2004034658 A JP 2004034658A JP 2005227435 A JP2005227435 A JP 2005227435A
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circuit board
terminals
display device
terminal
along
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JP4413637B2 (en
JP2005227435A5 (en
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Yuichi Takenaka
雄一 竹中
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Japan Display Inc
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Hitachi Displays Ltd
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<P>PROBLEM TO BE SOLVED: To prevent a connection failure, due to warpage of a printed circuit board (PCB), in which, on a main face formed by extending to one direction, the plurality of terminals are arranged in parallel to the direction, between a plurality of terminals of the PCB and terminals of the other printed circuit board and to prevent a short circuit between the plurality of terminals. <P>SOLUTION: In a display device which is equipped with a display panel PNL, a first circuit board PCB1 having the main face along an x-axis direction and a y-axis direction crossing the x-axis and a second circuit board FPC1 which is electrically connected to a plurality of terminals d(p) arranged to the x-axis direction in line on the main face of the first circuit board, and in which the main face of the first circuit board PCB1 is formed by extending long to the x-axis direction, each terminal d(p) of the first circuit board PCB1 is extended longer to the y-direction than connection terminals TERa connected to d(p), of the second circuit board FPC1 and spacings Sp, Sp' and Sp" with which each adjoining pair of the terminals d(p) is separated are expanded at both ends of the terminals d(p). <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、液晶表示装置、エレクトロルミネセンス表示装置、電界放出型表示装置等の如き所謂平面型の表示装置(Flat Panel Display,FPDと略される)に関わり、特に表示パネルに複数の印刷回路基板を直列的に接続し、これらの印刷回路基板を通して当該表示パネルに電力又は信号を供給する表示装置に好適な当該印刷回路基板間の接続構造に関する。   The present invention relates to a so-called flat display device (abbreviated as Flat Panel Display, FPD) such as a liquid crystal display device, an electroluminescence display device, a field emission display device, and the like, and in particular, a plurality of printed circuits on a display panel. The present invention relates to a connection structure between printed circuit boards suitable for a display device in which substrates are connected in series and power or signals are supplied to the display panel through the printed circuit boards.

液晶表示装置、エレクトロルミネセンス表示装置、電界放出型表示装置等の所謂平面型表示装置として知られる表示装置(表示モジュール)の一例を図1に示す。この表示装置の一例は、後述の特許文献1に開示される液晶表示装置に準じて図1に描かれる。   An example of a display device (display module) known as a so-called flat display device such as a liquid crystal display device, an electroluminescence display device, or a field emission display device is shown in FIG. An example of this display device is depicted in FIG. 1 according to a liquid crystal display device disclosed in Patent Document 1 described later.

図1に示される表示パネルPNLは、一対の基板SUB1,SUB2(その少なくとも一方は、光を十分に透過し得る材料からなる透明基板)を夫々の主面を対向させて貼り合わせ、この基板SUB1,SUB2間に液晶組成物を封入して形成される。表示パネルPNLは、対向する一対の辺(図1に示された直交座標のx軸沿いに延びる)とこの一対の辺の一つに交差する方向(図1に示された直交座標のy軸方向)に延びる他の一対の辺とを有する所謂矩形状に成形される。当該表示パネルPNLの当該一対の辺の一つ(図1では上辺)及び当該他の一対の辺の一つ(図1では右辺)の各々には、印刷回路基板PCB1,PCB2(Printed Circuit Board,PCBと略される,以下、第1回路基板とも記す)の一つから複数の可撓印刷回路基板FPC1,FPC2(Flexible Printed Circuit Board,FPCと略される,以下、第の回路基板とも記す)を介して信号(画像データやその表示を制御する信号)や電力が供給される。   The display panel PNL shown in FIG. 1 has a pair of substrates SUB1 and SUB2 (at least one of which is a transparent substrate made of a material that can sufficiently transmit light) bonded to each other, and the substrate SUB1. , SUB2 is formed by sealing a liquid crystal composition. The display panel PNL has a pair of opposing sides (extending along the x-axis of the orthogonal coordinates shown in FIG. 1) and a direction intersecting one of the pair of sides (the y-axis of the orthogonal coordinates shown in FIG. 1). And a pair of other sides extending in a direction). Each of one of the pair of sides (upper side in FIG. 1) and one of the other pair of sides (right side in FIG. 1) of the display panel PNL includes printed circuit boards PCB1, PCB2 (Printed Circuit Board, One of a plurality of flexible printed circuit boards FPC1, FPC2 (abbreviated as Flexible Printed Circuit Board, FPC, hereinafter also referred to as a first circuit board). A signal (a signal for controlling image data and its display) and electric power are supplied via.

第1回路基板PCB1には、表示制御回路Tcon(タイミング・コントローラ(Timing Controller)とも呼ばれる集積回路素子)や種々の電子部品Ecomが搭載された制御回路基板CTB(Control Circuit Board)がジャンパ(Jumper)JMP1を通して接続される。制御回路基板CTBは、コンピュータやテレビジョン・システムという所謂表示装置の外部から映像データ及びその表示に必要な制御信号を受けるため、インターフェース回路基板(Interface Circuit Board)とも呼ばれる。第1回路基板PCB1から表示パネルPNLの上辺に至る信号又は電力の供給は、複数の第2回路基板FPC1の各々の一端を表示パネルPNLの上辺に形成された入力部SIGIN1に電気的に接続し、当該第2回路基板FPC1の各々の他端を第1回路基板PCB1の主面の接続領域CNA1に形成された複数の端子に電気的に接続して行われる。第1回路基板PCB1の主面はx方向及びy方向に沿って拡がる。   On the first circuit board PCB1, a control circuit board CTB (Control Circuit Board) on which a display control circuit Tcon (an integrated circuit element also called a timing controller) and various electronic components Ecom are mounted is a jumper. Connected through JMP1. The control circuit board CTB is also called an interface circuit board because it receives video data and a control signal necessary for displaying the video data from outside a so-called display device such as a computer or a television system. Supply of a signal or power from the first circuit board PCB1 to the upper side of the display panel PNL is performed by electrically connecting one end of each of the plurality of second circuit boards FPC1 to an input unit SIGIN1 formed on the upper side of the display panel PNL. The other end of each second circuit board FPC1 is electrically connected to a plurality of terminals formed in the connection area CNA1 on the main surface of the first circuit board PCB1. The main surface of the first circuit board PCB1 extends along the x direction and the y direction.

第1回路基板PCB1はジャンパJMP2を通して第2回路基板PCB2にも接続され、制御回路基板CTBから受けた信号や電力を第2回路基板PCB2に分配する。第2回路基板PCB2から表示パネルPNLの右辺に至る信号又は電力の供給は、複数の第2回路基板FPC2の各々の一端を表示パネルPNLの右辺に形成された入力部SIGIN2に電気的に接続し、当該第2回路基板FPC2の各々の他端を第1回路基板PCB2の主面の接続領域CNA2に形成された複数の端子に電気的に接続して行われる。第1回路基板PCB1と複数の第2回路基板FPC1との電気的な接続は、第1回路基板PCB1の主面に形成されたアラインメント・マーク(Alignment Mark)ALM1を基準に当該第2回路基板FPC1の各々の他端と接続領域CNA1に形成された端子との位置を合わせて行う。これと同様に、第1回路基板PCB2と複数の第2回路基板FPC2との電気的な接続も、第1回路基板PCB2の主面に形成されたアラインメント・マークALM2を基準に当該第2回路基板FPC2の各々の他端と接続領域CNA2に形成された端子との位置を合わせて行う。  The first circuit board PCB1 is also connected to the second circuit board PCB2 through the jumper JMP2, and distributes signals and power received from the control circuit board CTB to the second circuit board PCB2. To supply a signal or power from the second circuit board PCB2 to the right side of the display panel PNL, electrically connect one end of each of the plurality of second circuit boards FPC2 to an input part SIGIN2 formed on the right side of the display panel PNL. The other end of each second circuit board FPC2 is electrically connected to a plurality of terminals formed in the connection area CNA2 on the main surface of the first circuit board PCB2. The electrical connection between the first circuit board PCB1 and the plurality of second circuit boards FPC1 is based on an alignment mark ALM1 formed on the main surface of the first circuit board PCB1. This is performed by aligning the other end of each and the terminals formed in the connection region CNA1. Similarly, the electrical connection between the first circuit board PCB2 and the plurality of second circuit boards FPC2 is also based on the alignment mark ALM2 formed on the main surface of the first circuit board PCB2. This is performed by matching the positions of the other ends of the FPC 2 and the terminals formed in the connection area CNA2.

第1回路基板PCB1(その接続領域CNA1)と複数の第2回路基板FPC1との電気的な接続及び第1回路基板PCB2(その接続領域CNA2)と複数の第2回路基板FPC2との電気的な接続の詳細を、図1の領域2aに示された第2回路基板FPC1の他端と第1回路基板PCB1との接続構造を例に図2を参照して説明する。図2(A)に示される第2回路基板FPC1は、所謂TAB(Tape Automated Bonding)の手法により表示パネルの駆動素子(Driver Element)IC1を搭載したTCP(Tape Carrier Package)やCOF(Chip On Film)として知られる実装構造を有する。   Electrical connection between the first circuit board PCB1 (its connection area CNA1) and the plurality of second circuit boards FPC1 and electrical connection between the first circuit board PCB2 (its connection area CNA2) and the plurality of second circuit boards FPC2 Details of the connection will be described with reference to FIG. 2, taking as an example a connection structure between the other end of the second circuit board FPC1 and the first circuit board PCB1 shown in the region 2a of FIG. A second circuit board FPC1 shown in FIG. 2A is a TCP (Tape Carrier Package) or COF (Chip On Film) on which a display panel driver element IC1 is mounted by a so-called TAB (Tape Automated Bonding) technique. ).

図2(A)とこれに示される領域2bの断面が描かれた図2(B)とから明らかなように、第2回路基板FPC1は、絶縁性のベースフィルム(Base Film)BSF(f)、その主面(第2回路基板FPC1の主面ともなる)に形成された導体膜からなる複数の配線d(f)、及びこの複数の配線d(f)を覆う絶縁膜INS(f)を含む。複数の配線d(f)は、第2回路基板FPC1の一端及び他端にて絶縁膜INS(f)から露出されて上述の接続端子TERa、TERbとして用いられる。  As is clear from FIG. 2A and FIG. 2B in which the cross section of the region 2b shown therein is drawn, the second circuit board FPC1 is made of an insulating base film (Base Film) BSF (f). A plurality of wirings d (f) made of a conductor film formed on the main surface (also serving as a main surface of the second circuit board FPC1), and an insulating film INS (f) covering the plurality of wirings d (f) Including. The plurality of wirings d (f) are exposed from the insulating film INS (f) at one end and the other end of the second circuit board FPC1 and used as the connection terminals TERa and TERb.

一方、第1回路基板PCB1は、図2(B)に示されるように、絶縁性の基材(Base Member)BSF(p)、その主面(第1回路基板PCB1の主面ともなる)に形成された導体膜からなる複数の配線d(p)、及びこの複数の配線d(p)を覆う絶縁膜INS(p)を含む。樹脂のみで成形される第2回路基板FPC1のベースフィルムBSF(f)に対して、第1回路基板PCB1の基材BSF(p)は樹脂に浸漬されたガラス繊維等により堅牢に成形される。絶縁膜INS(p)は、第2回路基板FPC1の絶縁膜INS(f)と同様に樹脂や無機材料の薄膜で形成してもよいが、これよりも厚い半田レジスト(Solder Resist)の膜に代えてもよい。上述の接続領域CNA1にて、絶縁膜INS(p)にはx方向に延びる開口が形成され、この開口から露出される複数の配線d(p)は第1回路基板PCB1の複数の端子として第2回路基板FPC1の他端に設けられた接続端子TERaに電気的に接続される。第1回路基板PCB1の複数の端子と第2回路基板FPC1の接続端子TERaとは、図2(B)に示されるように、異方性導電膜(Anisotropic Conductive Film)ACFにより電気的に接続される。   On the other hand, as shown in FIG. 2B, the first circuit board PCB1 has an insulating base member (Base Member) BSF (p) on its main surface (which also serves as the main surface of the first circuit board PCB1). A plurality of wirings d (p) made of the formed conductor film and an insulating film INS (p) covering the plurality of wirings d (p) are included. In contrast to the base film BSF (f) of the second circuit board FPC1 molded only with the resin, the base material BSF (p) of the first circuit board PCB1 is firmly molded with glass fiber or the like immersed in the resin. The insulating film INS (p) may be formed of a thin film of a resin or an inorganic material like the insulating film INS (f) of the second circuit board FPC1, but a thicker solder resist (Solder Resist) film is used. It may be replaced. In the connection region CNA1, an opening extending in the x direction is formed in the insulating film INS (p), and a plurality of wirings d (p) exposed from the opening are used as a plurality of terminals of the first circuit board PCB1. It is electrically connected to a connection terminal TERa provided at the other end of the two-circuit board FPC1. The plurality of terminals of the first circuit board PCB1 and the connection terminals TERa of the second circuit board FPC1 are electrically connected by an anisotropic conductive film ACF as shown in FIG. The

なお、図2(A)において、第1回路基板PCB1に形成される複数の配線d(p)の輪郭は、接続領域CNA1にて第2回路基板FPC1に、それ以外の領域にて絶縁膜INS(p)に夫々覆われるため、破線で示される。図2(C)は、第1回路基板PCB1の別の断面構造を図2(B)に倣って示す。図2(C)に示された第1回路基板PCB1では、絶縁性の基材BSF(p)の裏面(上述の第1回路基板PCB1の主面に対向する別の主面)に複数の配線d(p)が形成され、絶縁性の基材BSF(p)の主面には、接続端子TERaに電気的に接続される複数の端子として別の導体層d2(p)が形成される。複数の配線d(p)の各々は、接続領域CNA1にて、基材BSF(p)を貫通するスルーホール(Through Hole)THにより対応する導体層d2(p)に導通される。絶縁性の基材BSF(p)の裏面に形成された複数の配線d(p)は、絶縁膜INS(p)により覆われる。  In FIG. 2A, the outlines of the plurality of wirings d (p) formed on the first circuit board PCB1 are formed on the second circuit board FPC1 in the connection area CNA1 and on the insulating film INS in the other areas. Since they are respectively covered by (p), they are indicated by broken lines. FIG. 2C shows another cross-sectional structure of the first circuit board PCB1 following FIG. In the first circuit board PCB1 shown in FIG. 2C, a plurality of wirings are provided on the back surface of the insulating base material BSF (p) (another main surface facing the main surface of the first circuit board PCB1). d (p) is formed, and another conductor layer d2 (p) is formed on the main surface of the insulating base material BSF (p) as a plurality of terminals electrically connected to the connection terminal TERa. Each of the plurality of wirings d (p) is electrically connected to the corresponding conductor layer d2 (p) through a through hole TH that penetrates the base material BSF (p) in the connection region CNA1. The plurality of wirings d (p) formed on the back surface of the insulating base material BSF (p) are covered with the insulating film INS (p).

以上に説明した表示装置は、下記特許文献1に開示される液晶表示装置に基づき、これに幾つかの改良を含めて構成されるが、その構成要素はエレクトロルミネセンス表示装置、電界放出型表示装置等の如き液晶表示装置以外の表示装置にも転用可能である。
特開平05-257142号(対応米国特許第5432626号公報)
The display device described above is based on the liquid crystal display device disclosed in Patent Document 1 described below, and includes some improvements. The components are an electroluminescence display device and a field emission display. The present invention can also be used for display devices other than liquid crystal display devices such as devices.
JP 05-257142 (corresponding US Pat. No. 5,432,626)

図1、図2(B)、及び図2(C)を参照して説明した如く、第1回路基板PCB1は第1方向(例えば、x軸)及び第1方向に交差する第2方向(例えば、x軸と直交するy軸)に沿う主面を有し、この主面には第2回路基板FPC1に電気的に接続される複数の端子が第1方向(例えば、x軸)に並設されて接続領域CNA1をなす。第1回路基板PCB1は、当該第1方向(例えば、x軸)沿いに延びる。また、第1回路基板PCB1の厚みは、当該第1方向(例えば、x軸)及び当該第2方向(例えば、y軸)の夫々に交差する第3方向(例えば、x軸及びy軸と直交するz軸)に沿う。このため、図3(A)に示す如く、第1回路基板PCB1の第1方向に沿う寸法(長さ)Px、第2方向に沿う寸法(幅)Py、及び第3方向に沿う寸法(厚さ)Pz(図示されず)は、Px>Py>Pzの関係にある。   As described with reference to FIGS. 1, 2B, and 2C, the first circuit board PCB1 has a first direction (for example, an x-axis) and a second direction (for example, an x-axis) that intersects the first direction (for example, , A main surface along the y-axis orthogonal to the x-axis), and a plurality of terminals electrically connected to the second circuit board FPC1 are arranged in parallel in the first direction (for example, the x-axis) on the main surface. Thus, the connection area CNA1 is formed. The first circuit board PCB1 extends along the first direction (for example, the x axis). Further, the thickness of the first circuit board PCB1 is orthogonal to the third direction (for example, the x-axis and the y-axis) that intersects each of the first direction (for example, the x-axis) and the second direction (for example, the y-axis). Along the z axis). Therefore, as shown in FIG. 3A, the dimension (length) Px along the first direction, the dimension (width) Py along the second direction, and the dimension (thickness along the third direction) of the first circuit board PCB1. P) Pz (not shown) has a relationship of Px> Py> Pz.

一方、第1方向(例えば、x軸)沿いに延びた接続領域CNA1に並設される複数の端子は、第1方向(例えば、x軸)沿いに延ばされた異方性導電膜ACFで覆われ、この異方性導電膜ACFを介して第2回路基板FPC1の接続端子TERaが熱圧着される。第1回路基板PCB1が、第1方向、第2方向、及び第3方向に僅かな突起や凹みを有する場合、上述のPxは最大長さ、Pyは最大幅、Pzは最大厚さとして記される。なお、第1回路基板PCB2の形状及び第2回路基板FPC2との接続形態についても、上記第1方向をy軸と、上記第2方向をx軸と読み替えることにより、第1回路基板PCB1と同様に説明される。  On the other hand, the plurality of terminals arranged in parallel in the connection region CNA1 extending along the first direction (for example, the x-axis) are anisotropic conductive films ACF extending along the first direction (for example, the x-axis). The connection terminal TERa of the second circuit board FPC1 is covered with the anisotropic conductive film ACF and is thermocompression bonded. When the first circuit board PCB1 has slight protrusions and depressions in the first direction, the second direction, and the third direction, the above Px is described as the maximum length, Py is the maximum width, and Pz is the maximum thickness. The The shape of the first circuit board PCB2 and the connection form with the second circuit board FPC2 are the same as those of the first circuit board PCB1 by replacing the first direction with the y-axis and the second direction with the x-axis. Explained.

本発明者は、第1回路基板PCB1の中心が図3(B)及び図3(C)に示す如く、第2方向(y軸として示す)に反る問題を発見した。この問題は、第1回路基板PCB1の第3方向に沿う寸法(厚さ)Pzが他の寸法Px(長さ)及びPy(幅)に対して小さくなる、換言すれば、第1回路基板PCB1が薄くなるにつれて顕在化し、第2方向(y軸)沿いの寸法Py(幅)に対して第1方向(x軸として示す)沿いに長くなる程、生じる。図3(B)に示す(1)の場合は、第1回路基板PCB1の中心がy軸の正方向に反る。図1に示したように、接続領域CNA1に接続された第2回路基板FPC1がy軸の負方向に延びて表示パネルPNLに接続されるため、(1)の場合における第1回路基板PCB1の反りは、「表示パネルPNLとは反対向きの反り」とも記される。図3(C)に示す(2)の場合は、第1回路基板PCB1の中心がy軸の負方向に反るため、「表示パネルPNL向きの反り」とも記される。   The inventor has found a problem that the center of the first circuit board PCB1 is warped in the second direction (shown as the y-axis) as shown in FIGS. 3B and 3C. The problem is that the dimension (thickness) Pz along the third direction of the first circuit board PCB1 is smaller than the other dimensions Px (length) and Py (width), in other words, the first circuit board PCB1. Becomes more apparent as it becomes thinner, and becomes longer along the first direction (shown as the x-axis) with respect to the dimension Py (width) along the second direction (y-axis). In the case of (1) shown in FIG. 3B, the center of the first circuit board PCB1 is warped in the positive direction of the y-axis. As shown in FIG. 1, since the second circuit board FPC1 connected to the connection area CNA1 extends in the negative direction of the y axis and is connected to the display panel PNL, the first circuit board PCB1 in the case of (1) The warp is also described as “a warp opposite to the display panel PNL”. In the case of (2) shown in FIG. 3C, since the center of the first circuit board PCB1 is warped in the negative direction of the y-axis, it is also referred to as “warping toward the display panel PNL”.

第1回路基板PCB1の接続領域CNA1に第2回路基板FPC1の接続端子TERaを接続する工程において、第1方向(x軸)沿いに延びたテープ状の異方性導電膜ACFをアラインメント・マークALM1を参照しながら接続領域CNA1に配置するとき、場合(1)の第1回路基板PCB1の反りが生じると、接続領域CNA1の中心において、異方性導電膜ACFは接続領域CNA1からy軸の負方向(表示パネルPNL向き)にずれる。また、場合(2)の第1回路基板PCB1の反りが生じると、接続領域CNA1の中心において、異方性導電膜ACFは接続領域CNA1からy軸の正方向(表示パネルPNLとは反対向き)にずれる。いずれの場合においても、接続領域CNA1の中心部にて、第1回路基板PCB1に設けられた複数の端子は異方性導電膜ACFで十分に覆われない。  In the step of connecting the connection terminal TERa of the second circuit board FPC1 to the connection area CNA1 of the first circuit board PCB1, the tape-like anisotropic conductive film ACF extending along the first direction (x-axis) is aligned with the alignment mark ALM1. When the warp of the first circuit board PCB1 in the case (1) occurs when arranging in the connection region CNA1 with reference to FIG. 6, the anisotropic conductive film ACF is negative in the y-axis from the connection region CNA1 in the center of the connection region CNA1. The direction is shifted (toward the display panel PNL). Further, when the warp of the first circuit board PCB1 in the case (2) occurs, the anisotropic conductive film ACF is in the positive direction of the y axis from the connection region CNA1 in the center of the connection region CNA1 (the direction opposite to the display panel PNL). Sneak away. In any case, the plurality of terminals provided on the first circuit board PCB1 are not sufficiently covered with the anisotropic conductive film ACF at the center of the connection region CNA1.

更に、図3(B)に示す場合(1)の第1回路基板PCB1の反り(表示パネルPNLとは反対向きの反り)が生じた状態で、第1回路基板PCB1の接続領域CNA1に第2回路基板FPC1の接続端子TERaが熱圧着されたときの問題を図4(A)を参照して説明する。図4(A)に示される第1回路基板PCB1の中心部(領域4bとして例示)において、第2回路基板FPC1の接続端子TERaが第1回路基板PCB1の接続領域CNA1に対してy軸の負方向(表示パネルPNL向き)にずれる。この領域4bにおける接続端子TERaと接続領域CNA1(第1回路基板PCB1の端子となるd(p))との接続面積(x軸とy軸とからなる平面に沿う面積)は、図4(B)に示す如く、図2(B)を参照して説明されたそれと比較して狭まる。   Further, in the state shown in FIG. 3B, the second circuit board PCB1 is warped (the warp in the direction opposite to the display panel PNL) in the first circuit board PCB1 in the case (1), and the second circuit area is connected to the connection area CNA1 of the first circuit board PCB1. A problem when the connection terminal TERa of the circuit board FPC1 is thermocompression bonded will be described with reference to FIG. 4A, the connection terminal TERa of the second circuit board FPC1 is negative in the y axis with respect to the connection area CNA1 of the first circuit board PCB1. The direction is shifted (toward the display panel PNL). The connection area (area along the plane consisting of the x-axis and the y-axis) between the connection terminal TERa and the connection region CNA1 (d (p) serving as the terminal of the first circuit board PCB1) in this region 4b is shown in FIG. As shown in FIG. 2, it is narrower than that described with reference to FIG.

例えば、接続領域CNA1の両端で第1回路基板PCB1の端子d(p)と第2回路基板FPC1の接続端子TERaとが図2(B)の如く電気的に接続され、その中央で第1回路基板PCB1の端子d(p)と第2回路基板FPC1の接続端子TERaとが図4(B)の如く電気的に接続されるとすると、第1回路基板PCB1から第2回路基板FPC1へ伝送される信号が経験する電気的な抵抗は、接続領域CNA1の両端とその中央部で相違する。このため、接続領域CNA1の両端とその中央部とで同じ信号を第1回路基板PCB1から第2回路基板FPC1へ出力する場合、接続領域CNA1の中心に接続された接続端子TERaで受け取られた当該信号は、接続領域CNA1の端部に接続された接続端子TERaで受け取られた当該信号とは異なるものとして、第2回路基板FPC1に搭載された駆動素子IC1やこれから信号を受ける表示パネルPNLの回路にて認識される。  For example, the terminal d (p) of the first circuit board PCB1 and the connection terminal TERa of the second circuit board FPC1 are electrically connected at both ends of the connection area CNA1 as shown in FIG. If the terminal d (p) of the board PCB1 and the connection terminal TERa of the second circuit board FPC1 are electrically connected as shown in FIG. 4B, they are transmitted from the first circuit board PCB1 to the second circuit board FPC1. The electrical resistance experienced by the signal differs between both ends of the connection region CNA1 and the central portion thereof. Therefore, when the same signal is output from the first circuit board PCB1 to the second circuit board FPC1 at both ends and the center of the connection area CNA1, the signal received by the connection terminal TERa connected to the center of the connection area CNA1. The signal is different from the signal received at the connection terminal TERa connected to the end of the connection region CNA1, and the circuit of the driving element IC1 mounted on the second circuit board FPC1 and the display panel PNL receiving the signal therefrom Is recognized.

本発明者は、上述した第1回路基板PCB1の反り及びこれに起因する種々の問題を解決するために、以下に示す如き表示装置を提供する。本発明による表示装置は、上記第1回路基板に形成され且つ第2回路基板FPC1の接続端子に接続される端子を、当該接続端子より長く形成される形状に特徴付けられる。その代表的な構造は、以下に記すとおりである。   The present inventor provides a display device as described below in order to solve the above-described warpage of the first circuit board PCB1 and various problems caused by the warp. The display device according to the present invention is characterized in that a terminal formed on the first circuit board and connected to the connection terminal of the second circuit board FPC1 is formed longer than the connection terminal. The typical structure is as follows.

表示装置1は:表示パネル、第1方向(例えば、x軸)及び第1方向に交差する第2方向(例えば、x軸と直交するy軸)に沿う主面を有し且つ当該主面には第2方向に延びる複数の端子が第1方向に並設されている第1回路基板、及び一端が前記表示パネルに他端が前記第1回路基板の前記複数の端子に夫々電気的に接続される少なくとも一つの第2回路基板とを備え、前記複数の端子の隣接し合う各一対は、夫々の両端にて当該夫々の両端の間よりも互いに広く隔てられる。 The display device 1 has a main surface along a display panel, a first direction (for example, x-axis) and a second direction (for example, y-axis orthogonal to the x-axis) intersecting the first direction, and the main surface Is a first circuit board in which a plurality of terminals extending in the second direction are arranged in parallel in the first direction, and one end is electrically connected to the display panel and the other end is electrically connected to the plurality of terminals of the first circuit board. At least one second circuit board, and the adjacent pairs of the plurality of terminals are separated from each other at both ends more widely than between the both ends.

表示装置2は:表示装置1において、前記第1回路基板の前記主面が、前記第1方向(x)沿いよりも前記第2方向(例えば、y軸)沿いに長く延びる。  Display device 2: In display device 1, the main surface of the first circuit board extends longer along the second direction (for example, the y-axis) than along the first direction (x).

表示装置3は:表示装置1において、前記第1回路基板には複数の前記第2回路基板が前記第1方向沿いに並設され、第1回路基板の前記複数の端子は前記第1方向(例えば、x軸)沿いに複数の第2回路基板の夫々に対応した複数の群に分けられ且つ複数の群の夫々に対応する第2回路基板に電気的に接続されている。  Display device 3: In display device 1, a plurality of second circuit boards are arranged in parallel along the first direction on the first circuit board, and the plurality of terminals of the first circuit board are arranged in the first direction ( For example, it is divided into a plurality of groups corresponding to each of the plurality of second circuit boards along the x-axis) and electrically connected to the second circuit boards corresponding to each of the plurality of groups.

表示装置4は:表示装置3において、前記表示パネルは対向する一対の辺(例えば、前記x軸方向に延びている)とこの一対の辺の一つに交差する方向に延びる他の一対の辺(例えば、前記y軸方向に延びている)とを有する矩形状に成形され、前記複数の第2回路基板は表示パネルの前記一対の辺及び前記他の一対の辺のいずれか一つの辺に並設されている。  Display device 4: In display device 3, the display panel has a pair of opposing sides (for example, extending in the x-axis direction) and another pair of sides extending in a direction intersecting one of the pair of sides. (E.g., extending in the y-axis direction), and the plurality of second circuit boards are formed on any one of the pair of sides and the other pair of sides of the display panel. It is installed side by side.

表示装置5は:表示装置3において、前記複数の第2回路基板の各々には前記表示パネルの駆動回路素子が搭載されている。 Display device 5: In the display device 3, a driving circuit element of the display panel is mounted on each of the plurality of second circuit boards.

表示装置6は:表示装置1において、前記第1回路基板の前記主面において前記複数の端子が前記第1方向(例えば、x軸)に並設された領域(接続領域)は、前記第2方向(例えば、y軸)よりも第1方向沿いに長く延びている。  Display device 6: In display device 1, a region (connection region) in which the plurality of terminals are arranged in parallel in the first direction (for example, the x axis) on the main surface of the first circuit board is the second device. It extends longer along the first direction than the direction (for example, the y-axis).

表示装置7は:表示装置6において、前記複数の端子が並設された領域の前記第2方向(例えば、y軸)沿いの幅は、前記第2回路基板の複数の端子に電気的に接続される前記他端の該第2方向沿いの幅よりも広い。  Display device 7: In display device 6, the width along the second direction (for example, the y-axis) of the region where the plurality of terminals are arranged in parallel is electrically connected to the plurality of terminals of the second circuit board. Wider than the width of the other end along the second direction.

表示装置8は:表示装置7において、前記第1回路基板及びこれに電気的に接続される前記第2回路基板は前記第1方向(例えば、x軸)及び前記第2方向(例えば、y軸)に交差する第3方向(例えば、x軸及びy軸と直交するz軸)沿いに厚みを有し、第2回路基板は可撓である。  Display device 8: In the display device 7, the first circuit board and the second circuit board electrically connected thereto are arranged in the first direction (for example, the x axis) and the second direction (for example, the y axis). ) In the third direction (for example, the z-axis orthogonal to the x-axis and the y-axis), and the second circuit board is flexible.

表示装置9は:表示パネル、第1方向(例えば、x軸)及び第1方向に交差する第2方向(例えば、x軸と直交するy軸)に沿う主面を有し且つこの主面には第2方向に延びる複数の端子が第1方向に並んで形成されている第1回路基板、及び一端が前記表示パネルに他端が前記第1回路基板の前記複数の端子に夫々電気的に接続される少なくとも一つの第2回路基板とを備え、前記第2回路基板の前記他端には前記第1回路基板の前記複数の端子の一つに夫々接続され且つ当該一つの端子に接続された状態で前記第2方向沿いに延びる接続端子が形成され、前記第1回路基板の前記一つの端子が前記第2方向に沿いに延びる長さは前記第2回路基板の前記接続端子のそれより長く、且つ前記一つの端子の前記第1方向に沿う幅は当該一つの端子の両端にて当該両端の間の部分に比べて狭められている。  The display device 9 has: a main surface along a display panel, a first direction (for example, x-axis) and a second direction (for example, y-axis orthogonal to the x-axis) intersecting the first direction, and the main surface Is a first circuit board in which a plurality of terminals extending in the second direction are formed side by side in the first direction, and one end is electrically connected to the display panel and the other end is electrically connected to the plurality of terminals of the first circuit board. At least one second circuit board to be connected, and the other end of the second circuit board is connected to one of the plurality of terminals of the first circuit board and connected to the one terminal. In this state, a connection terminal extending along the second direction is formed, and the length of the one terminal of the first circuit board extending along the second direction is longer than that of the connection terminal of the second circuit board. The width of the one terminal along the first direction is the one terminal It is narrowed as compared with the portion between the ends at both ends of the child.

表示装置10は:表示装置9において、前記第1回路基板の前記主面に形成された前記複数の端子は、第1回路基板主面に導体層として形成された複数の配線の一部であり、且つ当該第1回路基板主面にて複数の配線を覆う絶縁膜に形成された開口から露出されている。  Display device 10: In display device 9, the plurality of terminals formed on the main surface of the first circuit board are a part of a plurality of wirings formed as a conductor layer on the first circuit board main surface. And it is exposed from the opening formed in the insulating film which covers a some wiring in the said 1st circuit board main surface.

表示装置11は:表示装置10において、前記絶縁膜の前記開口は前記第2方向(例えば、y軸)よりも前記第1方向(例えば、x軸)沿いに長く延びて形成され、この開口に並設された前記複数の端子の第2方向に沿う長さは当該開口の第2方向に沿う幅により決められている。  Display device 11: In the display device 10, the opening of the insulating film is formed to extend longer along the first direction (for example, the x axis) than the second direction (for example, the y axis). The length along the second direction of the plurality of terminals arranged side by side is determined by the width along the second direction of the opening.

表示装置12は:表示装置11において、前記第2回路基板の前記他端には、前記絶縁膜の前記開口内に並ぶ前記第1回路基板の前記複数の端子に夫々に接続される複数の前記接続端子が並設される。  The display device 12: In the display device 11, the other end of the second circuit board is connected to the plurality of terminals of the first circuit board arranged in the opening of the insulating film, respectively. Connection terminals are juxtaposed.

表示装置13は:表示装置9において、前記第1回路基板の前記一つの端子の前記両端に挟まれて形成された前記部分(即ち、当該両端より第1方向(例えば、x軸)に沿う幅の広い部分)の前記第2方向(例えば、y軸)沿いの長さは、当該一つの端子に接続される前記第2回路基板の前記接続端子のそれに比べて短い。  Display device 13: In display device 9, said portion formed between said both ends of said one terminal of said first circuit board (that is, a width along a first direction (eg, x-axis) from said both ends) The length along the second direction (for example, the y-axis) of the wide portion of the second circuit board is shorter than that of the connection terminal of the second circuit board connected to the one terminal.

表示装置14は:表示装置9において、前記第2回路基板の前記接続端子は、第2回路基板の主面に形成された導体層の第2回路基板の前記他端にて導体層を覆う絶縁膜から露出した一部分である。  Display device 14: In display device 9, the connection terminal of the second circuit board is an insulation covering the conductor layer at the other end of the second circuit board of the conductor layer formed on the main surface of the second circuit board. The part exposed from the film.

上述した表示装置1及び表示装置9のいずれにおいても、前記第1回路基板に形成される複数の端子の各々が、これに接続される前記第2回路基板の接続端子よりも前記第2方向(例えば、y軸)沿いに長く延びるため、この第1回路基板の中心が当該第2方向沿いに反れても、第1回路基板の中心とその両端とにおける当該複数の端子の各々と当該接続端子との電気的な接続状態の相違は充分に抑えられる。さらに、表示装置1において、当該複数の端子の隣接する一対を前記第1方向(例えば、x軸)沿いに離間する寸法を当該端子の両端にて広げ、表示装置9において、当該複数の端子の各々の第1方向沿いの寸法(換言すれば、当該端子の幅)をこの端子の両端にて狭めることにより、当該複数の端子を第2方向沿いに長く延ばすことに伴う、新たな問題も解決される。この新たな問題は、この複数の端子の隣接する一対の端部が第2回路基板の接続端子に接続されないときに生じる端子間の短絡であり、その詳細は、本発明の比較例として後述する。   In both the display device 1 and the display device 9 described above, each of the plurality of terminals formed on the first circuit board is in the second direction (more than the connection terminal of the second circuit board connected thereto). For example, since it extends long along the y-axis), even if the center of the first circuit board is warped along the second direction, each of the plurality of terminals and the connection terminals at the center of the first circuit board and both ends thereof The difference in the electrical connection state is sufficiently suppressed. Furthermore, in the display device 1, the dimension of separating adjacent pairs of the plurality of terminals along the first direction (for example, the x axis) is widened at both ends of the terminal, and the display device 9 Narrowing the dimension along each first direction (in other words, the width of the terminal) at both ends of the terminal solves a new problem associated with extending the plurality of terminals along the second direction. Is done. This new problem is a short circuit between terminals that occurs when a pair of adjacent ends of the plurality of terminals are not connected to the connection terminals of the second circuit board, and details thereof will be described later as a comparative example of the present invention. .

本発明による表示装置は、以上に例示した14種類の構造に限定されるものではなく、その技術思想を逸脱しない範囲において、多様に変形され得る。   The display device according to the present invention is not limited to the 14 types of structures exemplified above, and can be variously modified without departing from the technical idea thereof.

以下、本発明による表示装置の最良の形態を説明する前に、本発明者が当該表示装置を着想する過程で検討したされた表示装置を比較例として、これに採用された第1回路基板に起因する当該第1回路基板の端子間の短絡の問題も含めて説明する。   Hereinafter, before explaining the best mode of the display device according to the present invention, the display device studied in the process of conceiving the display device by the present inventor is used as a comparative example, and the first circuit board employed in the display device is used as a comparative example. Description will be made including the problem of the short circuit between the terminals of the first circuit board.

〔比較例〕
図5(A)に示した第1回路基板PCB1は、背景技術で説明した第1回路基板PCB1をその主面に形成された接続領域CNA1(複数の端子が並設される領域)に第2回路基板FPC1を接続した状態で示し、図5(B)は図5(A)に示した第1回路基板PCB1の中心が図3(B)に示す如く、y軸の正方向(表示パネルPNLとは反対向き)に反った状態を示す。図5(A)に示された接続領域CNA1の幅(x軸方向の寸法):Y(CNA)は、作図の都合上、接続領域CNA1に接続される接続端子TERaが形成された第2回路基板FPC1の端部の幅(換言すれば接続端子TERaの長さ)Y[TERa]をより広めに描かれているが、図4(B)を参照して説明した如く、実質的には幅Y[TERa]に等しい。なお、図4(B)を参照して上述した第1回路基板PCB1の端子d(p)と接続端子TERaとの電気的な接続の問題は、図5(B)において、破線枠で囲んだ領域4bにて生じる。なお、Y(ACF)は異方性導電膜ACFの幅である。
[Comparative Example]
The first circuit board PCB1 shown in FIG. 5A is second in the connection area CNA1 (area where a plurality of terminals are arranged in parallel) formed on the main surface of the first circuit board PCB1 described in the background art. FIG. 5B shows the circuit board FPC1 connected, and the center of the first circuit board PCB1 shown in FIG. 5A is the positive direction of the y-axis (display panel PNL) as shown in FIG. 3B. Is the opposite direction). The width (dimension in the x-axis direction) of the connection region CNA1 shown in FIG. 5A: Y (CNA) is the second circuit in which the connection terminal TERa connected to the connection region CNA1 is formed for the sake of drawing. The width of the end portion of the substrate FPC1 (in other words, the length of the connection terminal TERa) Y [TERa] is drawn wider, but as described with reference to FIG. Equal to Y [TERa]. Note that the problem of electrical connection between the terminal d (p) of the first circuit board PCB1 and the connection terminal TERa described above with reference to FIG. 4B is surrounded by a broken line frame in FIG. 5B. It occurs in region 4b. Y (ACF) is the width of the anisotropic conductive film ACF.

本発明者は図5(C)に示す如く、第1回路基板PCB1の主面に第2回路基板FPC1の端部の幅Y[TERa]より広い幅Yb(CNA)を有する接続領域CNA1を形成して、上述の問題の解決を試みた。本発明者が試作した第1回路基板PCB1に形成された接続領域CNA1の幅Yb(CNA)は、第2回路基板FPC1の端部の幅(接続端子の長さ)Y[TERa]に第1回路基板PCB1がy軸沿いに反る大きさの2倍で求められた長さを加えた値か、それ以上にする。例えば、少なくとも第2回路基板FPC1の端部の幅Y[TERa]の1.2倍以上(望ましくは1.5倍以上)に広げる。例えば、図2(B)に示される如き断面構造を有する第1回路基板PCB1の試作品においては、Y[TERa]=1.2mmに合わせて決められた幅Y(CNA)を有する図5(A)に示された接続領域CNA1に対して、図5(C)に示された接続領域CNA1は、その両端が夫々0.4mmづつ、y軸方向沿いに延ばされている。従って、その幅Yb(CNA)は2.0mmとなり、図5(A)に示される1.2mmの幅Y(CNA)に比べて約1.7倍になる。   As shown in FIG. 5C, the inventor forms a connection region CNA1 having a width Yb (CNA) wider than the width Y [TERa] of the end of the second circuit board FPC1 on the main surface of the first circuit board PCB1. Then, an attempt was made to solve the above problem. The width Yb (CNA) of the connection region CNA1 formed on the first circuit board PCB1 prototyped by the present inventor is the first width (connection terminal length) Y [TERa] of the second circuit board FPC1. The value obtained by adding the length obtained by double the size of the circuit board PCB1 warping along the y-axis is set to be larger than that. For example, at least 1.2 times the width Y [TERa] of the end portion of the second circuit board FPC1 (preferably 1.5 times or more). For example, in the prototype of the first circuit board PCB1 having a cross-sectional structure as shown in FIG. 2B, FIG. 5 () having a width Y (CNA) determined in accordance with Y [TERa] = 1.2 mm. In contrast to the connection area CNA1 shown in A), the connection area CNA1 shown in FIG. 5C is extended along the y-axis direction by 0.4 mm at both ends. Therefore, the width Yb (CNA) is 2.0 mm, which is about 1.7 times the width Y (CNA) of 1.2 mm shown in FIG.

この試作品における接続領域CNA1の平面構造及び断面構造は、図6(A)及び図6(C)に拡大されて示される。図5(C)に示された接続領域CNA1は、図6(A)及び図6(C)に示される如く、第1回路基板PCB1の基材BSF(p)に形成された導体層d(p)を覆う絶縁膜INS(p)の開口として形成され、この開口から露出された導体層d(p)が「第1回路基板PCB1に形成された複数の端子」として、第2回路基板FPC1の接続端子との接続に供される。絶縁膜INS(p)の開口から露出された導体層d(p)、即ち「第1回路基板PCB1に形成された複数の端子」の各々の幅(x軸方向の寸法)Wpは0.5mmであり、その隣接する一対をx軸方向に離す間隔Spは0.5mmである。  The planar structure and the cross-sectional structure of the connection region CNA1 in this prototype are shown enlarged in FIGS. 6 (A) and 6 (C). As shown in FIGS. 6A and 6C, the connection region CNA1 shown in FIG. 5C has a conductor layer d () formed on the base material BSF (p) of the first circuit board PCB1. p) is formed as an opening of the insulating film INS (p) covering the second circuit board FPC1 with the conductor layer d (p) exposed from the opening as “a plurality of terminals formed on the first circuit board PCB1”. It is used for connection with the connection terminal. The width (dimension in the x-axis direction) Wp of each of the conductor layer d (p) exposed from the opening of the insulating film INS (p), that is, the “plurality of terminals formed on the first circuit board PCB1,” is 0.5 mm. The interval Sp separating the adjacent pairs in the x-axis direction is 0.5 mm.

上述した試作品に限らず、接続領域CNA1の幅Yb(CNA)を第2回路基板FPC1の端部の幅Y[TERa]より広げた図5(C)に示す第1回路基板PCB1を採用することにより、第1回路基板PCB1の中心が図5(D)に示す如くy軸の正方向に反った場合も、その端部(破線で囲まれた領域6a)とその中央(破線で囲まれた領域6b)とにおける第1回路基板PCB1の端子と第2回路基板FPC1の接続端子との電気的な接続状態の相違を解消できた。このような効果は、第1回路基板PCB1の中心がy軸の負方向に反った場合でも、得られる。しかしながら、第1回路基板PCB1の端子に第2回路基板FPC1の接続端子と接続されない部分が生じることで、新たな問題が生じた。図5(D)の領域6aに生じる新たな問題を図6(A)及び図6(C)を参照して、図5(D)の領域6bに生じる新たな問題を図6(B)及び図6(D)を参照して、夫々説明する。   The first circuit board PCB1 shown in FIG. 5C in which the width Yb (CNA) of the connection region CNA1 is wider than the width Y [TERa] of the end portion of the second circuit board FPC1 is adopted, not limited to the prototype described above. As a result, even when the center of the first circuit board PCB1 is warped in the positive direction of the y-axis as shown in FIG. 5D, its end (the region 6a surrounded by a broken line) and its center (enclosed by a broken line). The difference in the electrical connection state between the terminal of the first circuit board PCB1 and the connection terminal of the second circuit board FPC1 in the region 6b) can be eliminated. Such an effect can be obtained even when the center of the first circuit board PCB1 is warped in the negative direction of the y-axis. However, a new problem arises because the portion of the terminal of the first circuit board PCB1 is not connected to the connection terminal of the second circuit board FPC1. The new problem that occurs in the region 6a of FIG. 5D is described with reference to FIGS. 6A and 6C, and the new problem that occurs in the region 6b of FIG. Each will be described with reference to FIG.

図5(D)の領域6aでは、図6(A)に示す如く、第2回路基板FPC1の端部に形成された長さ(y軸方向の寸法)がY[TERa]の接続端子d(f)が、接続領域CNA1において、長さ(y軸方向の寸法)がYb(CNA)の第1回路基板PCB1の端子d(p)に接続される位置はy軸の正方向(表示パネルPNLとは反対方向)に偏る。従って、第1回路基板PCB1の端子d(p)の表示パネルPNL側は、接続端子d(f)に接続されないが、第2回路基板FPC1で覆われる。しかしながら、第2回路基板FPC1の端部を第1回路基板PCB1の接続領域CNA1に接続する工程において、その雰囲気中に漂う導電性の粒子PARが第1回路基板PCB1の端子d(p)の表示パネルPNL側に付着し、第2回路基板FPC1の熱圧着により第1回路基板PCB1の隣接する一対の端子d(p)の間に押さえ込まれる(図6(C)参照)。このため、当該一対の端子d(p)は導電性の粒子PARにより導通される。また、図1の如く組み立てられた表示装置を保持する金属製の部材から生じる塵や、この表示装置が利用される雰囲気に含まれる金属等の微粒子が導電性の粒子PARとして付着することもある。   In the region 6a of FIG. 5D, as shown in FIG. 6A, the length (dimension in the y-axis direction) formed at the end portion of the second circuit board FPC1 is Y [TERa]. f) in the connection area CNA1, the position connected to the terminal d (p) of the first circuit board PCB1 whose length (dimension in the y-axis direction) is Yb (CNA) is the positive direction in the y-axis (display panel PNL). The opposite direction). Accordingly, the display panel PNL side of the terminal d (p) of the first circuit board PCB1 is not connected to the connection terminal d (f), but is covered with the second circuit board FPC1. However, in the step of connecting the end of the second circuit board FPC1 to the connection region CNA1 of the first circuit board PCB1, the conductive particles PAR drifting in the atmosphere are displayed on the terminals d (p) of the first circuit board PCB1. It adheres to the panel PNL side and is pressed between a pair of adjacent terminals d (p) of the first circuit board PCB1 by thermocompression bonding of the second circuit board FPC1 (see FIG. 6C). For this reason, the pair of terminals d (p) are conducted by the conductive particles PAR. In addition, fine particles such as dust generated from a metal member holding the display device assembled as shown in FIG. 1 or metal contained in an atmosphere in which the display device is used may adhere as conductive particles PAR. .

一方、図5(D)の領域6bでは、図6(B)に示す如く、第2回路基板FPC1の端部に形成された長さY[TERa]の接続端子d(f)が、接続領域CNA1において、長さYb(CNA)の第1回路基板PCB1の端子d(p)に接続される位置はy軸の負方向(表示パネルPNL寄り)に偏る。従って、第1回路基板PCB1の端子d(p)の表示パネルPNLとは反対側の部分(図6(B)にて斜線パターンが施された部分)は、第2回路基板FPC1に覆われることなく露出する。従って、第2回路基板FPC1の端部を第1回路基板PCB1の接続領域CNA1に接続する工程や、表示装置を図1に示す如く完成させた後に第1回路基板PCB1を金属製のケース(又は「枠」)に収納する工程において、雰囲気中に漂う導電性の粒子PARが第1回路基板PCB1の端子d(p)の第2回路基板FPC1により覆われない部分に付着し(図6(D)参照)、第1回路基板PCB1の隣接する一対の端子d(p)を電気的に短絡する。   On the other hand, in the region 6b of FIG. 5D, as shown in FIG. 6B, the connection terminal d (f) of length Y [TERa] formed at the end of the second circuit board FPC1 is connected to the connection region. In CNA1, the position connected to the terminal d (p) of the first circuit board PCB1 having the length Yb (CNA) is biased in the negative y-axis direction (close to the display panel PNL). Accordingly, the portion of the terminal d (p) of the first circuit board PCB1 opposite to the display panel PNL (the portion with the hatched pattern in FIG. 6B) is covered with the second circuit board FPC1. It ’s exposed. Accordingly, the process of connecting the end portion of the second circuit board FPC1 to the connection region CNA1 of the first circuit board PCB1 or the display device is completed as shown in FIG. In the process of storing in the “frame”), the conductive particles PAR floating in the atmosphere adhere to a portion of the terminal d (p) of the first circuit board PCB1 that is not covered by the second circuit board FPC1 (FIG. 6D )), And electrically shorting a pair of adjacent terminals d (p) of the first circuit board PCB1.

以上に述べた導電性の粒子PARによる短絡は、表示装置の組立工程のみならず、これが製品として出荷された後にも生じるため、第1回路基板PCB1の接続領域CNA1の設計には、導電性の粒子PARの予期できない付着に備えた配慮が必要となる。このような状況に鑑み、本発明者は以下に記す新規な第1回路基板PCB1を試作し、導電性の粒子PARが第1回路基板PCB1の接続領域CNA1に付着しても、上述した端子d(p)間の短絡の問題を解決した。   The short circuit due to the conductive particles PAR described above occurs not only in the assembly process of the display device but also after it is shipped as a product. Therefore, the design of the connection region CNA1 of the first circuit board PCB1 is not limited to the conductive circuit PAR. Care must be taken in preparation for the unexpected adhesion of the particles PAR. In view of such a situation, the inventor made a prototype of a new first circuit board PCB1 described below, and the terminal d described above even when the conductive particles PAR adhere to the connection region CNA1 of the first circuit board PCB1. Solved the short circuit problem between (p).

図7(A)には、本発明による表示装置を特徴付ける新規な第1回路基板PCB1の接続領域CNA1の平面構造が、図6(A)や図6(B)に倣って模式的に描かれている。図7(A)において、長さLpは、上述した図5(A)の第1回路基板PCB1に形成された接続領域CNA1の幅に相当する。図7(A)において、上述した図5(C)の第1回路基板PCB1における接続領域CNA1の表示パネルPNL側(y軸の負方向)への延伸長さはLp1に、表示パネルPNLとは反対側(y軸の正方向)への延伸長さはLp2に、夫々相当する。従って、図5(C)及び図6(A)乃至図6(D)に示されるYb(CNA)は、Lp,Lp1,及びLp2の総和となる。図7(A)には、第1回路基板PCB1の端子となる導体層d(p)の輪郭が、接続領域CNA1にて実線で、絶縁膜INS(p)に覆われた領域にて破線で夫々示される。また、接続領域CNA1の両端における導体層d(p)の幅(x軸方向の寸法)Wp1,Wp2は、この両端に挟まれた部分(例えば、接続領域CNA1の中央部)の幅Wpに比べて狭められている。従って、接続領域CNA1の両端にて導体層d(p)の隣接する一対を離す間隔Sp’,Sp”は、この両端の間の部分(例えば、接続領域CNA1の中央部)で当該一対の導体層d(p)を離す間隔Spより広い。従って、図6(A)や図6(B)の接続領域CNA1に示される導体層d(p)に比べて、図7(A)に接続領域CNA1に示される導体層d(p)は、そのy軸の正方向に向けて、幅の異なる第1部分、第2部分、及び第3部分が順次形成されていることに特徴付けられる。導体層d(p)における第1部分の幅Wp1、第2部分の幅Wp、及び第3部分の幅Wp2は、Wp>Wp1,及びWp>Wp2なる関係を満たす。隣り合う一対の導体層d(p)に着眼すれば、これらの第1部分がx軸方向に離される間隔(距離)Sp’、これらの第2部分がx軸方向に離される間隔(距離)Sp、及びこれらの第3部分がx軸方向に離される間隔Sp”は、Sp<Sp’,及びSp<Sp”なる関係を満たす。   FIG. 7A schematically illustrates the planar structure of the connection region CNA1 of the novel first circuit board PCB1 that characterizes the display device according to the present invention, following FIGS. 6A and 6B. ing. In FIG. 7A, the length Lp corresponds to the width of the connection region CNA1 formed on the first circuit board PCB1 shown in FIG. In FIG. 7A, the extension length of the connection region CNA1 in the first circuit board PCB1 in FIG. 5C described above toward the display panel PNL side (the negative direction of the y-axis) is Lp1, and what is the display panel PNL? The extending length in the opposite side (positive direction of the y-axis) corresponds to Lp2. Therefore, Yb (CNA) shown in FIGS. 5C and 6A to 6D is the sum of Lp, Lp1, and Lp2. In FIG. 7A, the outline of the conductor layer d (p) serving as the terminal of the first circuit board PCB1 is indicated by a solid line in the connection region CNA1 and by a broken line in a region covered with the insulating film INS (p). Each is shown. Further, the widths (dimensions in the x-axis direction) Wp1 and Wp2 of the conductor layer d (p) at both ends of the connection region CNA1 are larger than the width Wp of the portion sandwiched between the both ends (for example, the central portion of the connection region CNA1). It is narrowed. Therefore, the distances Sp ′ and Sp ″ separating the adjacent pairs of the conductor layers d (p) at both ends of the connection region CNA1 are the portions between the both ends (for example, the central portion of the connection region CNA1). Since the distance Sp is greater than the distance Sp separating the layers d (p), the connection region in FIG.7 (A) is larger than the conductor layer d (p) shown in the connection region CNA1 in FIG.6 (A) and FIG.6 (B). The conductor layer d (p) shown in CNA1 is characterized in that a first portion, a second portion, and a third portion having different widths are sequentially formed in the positive direction of the y-axis. In the layer d (p), the width Wp1 of the first portion, the width Wp of the second portion, and the width Wp2 of the third portion satisfy the relationship of Wp> Wp1, and Wp> Wp2. When focusing on p), the distance (distance) at which these first parts are separated in the x-axis direction. p ′, an interval (distance) Sp at which these second portions are separated in the x-axis direction, and an interval Sp ″ at which these third portions are separated in the x-axis direction are Sp <Sp ′ and Sp <Sp ″. Satisfy the relationship.

先に例示した試作品に対して、本実施例に鑑み試作した第1回路基板PCB1では、上記第1部分の幅Wp1及び上記第3部分の幅Wp2を0.25mmとし、上記第2部分の幅Wpを0.5mmとした。隣り合う一対の導体層d(p)の上記第1部分を隔てる間隔Sp’及び上記第3部分を隔てる間隔Sp”は0.75mmであり、上記第2部分を隔てる間隔Spは0.5mmである。Lp1,Lp,及びLp2の長さは、先述の試作品と同様に0.4mm,1.2mm,0.4mmとしたが、第2部分の長さ(y軸方向の寸法)はLpより短くした。従って、図7(A)の断面構造を示す図7(B)において、第1部分の長さYe1,第2部分の長さYc,及び第3部分の長さYe2は、Ye1>Lp1,Yc<Lp,Ye2>Lp2,Ye1>Yc,及びYe2>Ycの関係を満たす。また、接続領域CNA1の端部から絶縁膜INS(p)に覆われて延びる導体層d(p)の幅は、図7(A)に示す如く、接続領域CNA1の端部に形成された導体層d(p)の幅(例えば、Wp2)より広くしてもよい(例えば、幅Wpに広げる)。   In the first circuit board PCB1 prototyped in consideration of the present embodiment with respect to the prototype illustrated above, the width Wp1 of the first portion and the width Wp2 of the third portion are set to 0.25 mm, and the second portion The width Wp was 0.5 mm. An interval Sp ′ separating the first portion and an interval Sp ″ separating the third portion of a pair of adjacent conductor layers d (p) is 0.75 mm, and the interval Sp separating the second portion is 0.5 mm. The lengths of Lp1, Lp, and Lp2 are 0.4 mm, 1.2 mm, and 0.4 mm, as in the previous prototype, but the length of the second portion (dimension in the y-axis direction) is Lp. Therefore, in Fig. 7B showing the cross-sectional structure of Fig. 7A, the length Ye1 of the first portion, the length Yc of the second portion, and the length Ye2 of the third portion are Ye1. > Lp1, Yc <Lp, Ye2> Lp2, Ye1> Yc, and Ye2> Yc, and a conductor layer d (p) extending from the end of the connection region CNA1 to be covered with the insulating film INS (p). Is formed at the end of the connection region CNA1 as shown in FIG. The conductor layer width d (p) (e.g., Wp2) may be wider than (e.g., spread width Wp).

一方、本実施例の第1回路基板PCB1に形成された端子に接続される第2回路基板の接続端子d(f)の輪郭は、図7(A)に示された4本の端子d(p)の内側2本に重ねて描かれた破線で示され、その端からy軸沿いに延びた長さY[TERa]の部分が接続端子として第1回路基板PCB1の端子d(p)に接続される。また、図7(A)に示された4本の端子d(p)の左端の1本には、y軸の正方向へ最も大きくずれて接続される第2回路基板の接続端子の輪郭が一点鎖線の枠d(f)’で、y軸の負方向へ最も大きくずれて接続される第2回路基板の接続端子の輪郭が二点鎖線の枠d(f)”で、夫々示される。これらの接続端子の輪郭d(f)’,d(f)”は、第1回路基板PCB1の端子d(p)に実際に接続される部分のみを示す。図7(A)に示された4本の端子d(p)の内側2本(その各々の長さLpの部分)に接続される破線で示された接続端子に対し、輪郭d(f)’で示された第2回路基板の接続端子はy軸の正方向に向けて距離TER(+y)だけずれ、輪郭d(f)”で示された第2回路基板の接続端子はy軸の負方向に向けて距離TER(−y)だけずれる。   On the other hand, the outline of the connection terminal d (f) of the second circuit board connected to the terminal formed on the first circuit board PCB1 of the present embodiment is the four terminals d () shown in FIG. The portion of the length Y [TERa], which is indicated by broken lines drawn on two inner sides of p) and extends from the end along the y axis, serves as a connection terminal to the terminal d (p) of the first circuit board PCB1. Connected. In addition, one of the left ends of the four terminals d (p) shown in FIG. 7A has the outline of the connection terminal of the second circuit board that is connected with the largest displacement in the positive direction of the y-axis. The outline of the connection terminal of the second circuit board connected with the largest shift in the negative direction of the y-axis is indicated by a dashed-dotted line frame d (f) ′. The outlines d (f) ′ and d (f) ″ of these connection terminals show only the part that is actually connected to the terminal d (p) of the first circuit board PCB1. Contour d (f) with respect to the connection terminal indicated by the broken line connected to the two inside terminals (parts of the length Lp thereof) of the four terminals d (p) shown in FIG. The connection terminal of the second circuit board indicated by 'is shifted by the distance TER (+ y) in the positive direction of the y axis, and the connection terminal of the second circuit board indicated by the outline d (f) " The distance TER (−y) is shifted in the negative direction.

本実施例に応じて試作された上記第1回路基板PCB1の端子に接続される第2回路基板の接続端子の幅Wfは0.5mmであり、隣り合う一対の接続端子をx軸方向に離す距離(間隔)Sfは0.5mmである。図7(A)に示される第2回路基板の接続端子の長さ(y軸方向の寸法)Y[TERa]は1.2mmであり、第1回路基板PCB1に形成された端子d(p)の当該第1回路基板PCB1の設計にて意図された部分(長さLpに相当する部分,以下、設計領域とも呼ぶ)に接続されている。従って、第2回路基板の接続端子との接続がy軸の正方向にずれたときに対応した長さLp1の延長部分及びy軸の負方向にずれたときに対応した長さLp2の延長部分には、図6(A)や図6(B)に示される導電性粒子PARが付着する可能性を孕む。しかしながら、図7(A)に破線で示した導電性粒子PARに対し、夫々の延長部分にて隣り合う一対の端子d(p)をx軸方向に離す距離Sp’,Sp”が長さLpの部分のそれ(Sp)に比べて大きいため、一対の端子d(p)の一方に接触した導電性粒子PARはその他方に接触できない。また、第1回路基板PCB1の端子に付着し得る導電性粒子PARの大きさには現実的に上限があるため、第1回路基板PCB1の端子d(p)の一対を隔てる距離を夫々の延長部分にて大きくすることで、これらの間に短絡が生じる確率は顕著に下がる。   The width Wf of the connection terminal of the second circuit board connected to the terminal of the first circuit board PCB1 prototyped according to the present embodiment is 0.5 mm, and a pair of adjacent connection terminals are separated in the x-axis direction. The distance (interval) Sf is 0.5 mm. The length (dimension in the y-axis direction) Y [TERa] of the connection terminal of the second circuit board shown in FIG. 7A is 1.2 mm, and the terminal d (p) formed on the first circuit board PCB1 Of the first circuit board PCB1 is connected to a part intended for the design (a part corresponding to the length Lp, hereinafter also referred to as a design area). Therefore, the extension portion corresponding to the length Lp1 when the connection with the connection terminal of the second circuit board is shifted in the positive direction of the y axis and the extension portion corresponding to the length Lp2 when the connection to the connection terminal of the second circuit board is shifted in the negative direction of the y axis. In this case, there is a possibility that the conductive particles PAR shown in FIGS. 6A and 6B adhere. However, the distances Sp ′ and Sp ″ separating the pair of terminals d (p) adjacent to each other at the extended portions with respect to the conductive particles PAR indicated by the broken lines in FIG. Therefore, the conductive particles PAR that are in contact with one of the pair of terminals d (p) cannot be in contact with the other, and the conductive particles that can adhere to the terminals of the first circuit board PCB1. Since there is a practical upper limit to the size of the active particles PAR, a short circuit between the terminals d (p) of the first circuit board PCB1 is increased by increasing the distance separating the pair of terminals d (p) at each extension portion. The probability of occurrence is significantly reduced.

本実施例では、図7(A)に示す如く、第1回路基板PCB1の接続領域CNA1に並設される端子d(p)の幅は、その設計領域においても狭められる。従って、第2回路基板の接続端子が設計者の意図どおりに設計領域にて端子d(p)に接続された場合、これらの間における電気抵抗が高くなることが予想される。しかしながら、図7(B)に示す如く、y軸方向の長さがY[TERa]の接続端子d(f)(導体層の一部)は、y軸方向の長さがLpの設計領域を中心にy軸の正方向及びy軸の負方向のいずれかにずれる。従って、y軸の正方向へのずれ量TER(+y)やy軸の負方向へのずれ量TER(−y)がLpの半分以下である場合、設計領域に形成される端子d(p)の幅が広い部分(上記第2部分)の長さYcをLpより小さくすると、y軸の正方向にずれた接続端子d(f)及びy軸の負方向にずれた接続端子d(f)のいずれも当該端子d(p)の第2部分に接続される。このため、本実施例の第1回路基板PCB1が図5(D)に示す如く反っても、これに形成された端子d(p)と第2回路基板の接続端子d(f)との領域6a及び領域6bにおける電気的な接続条件と、これらの領域以外における端子d(p)の設計領域と第2回路基板の接続端子d(f)との電気的な接続状態とを揃えやすくなる。また、端子d(p)の第2部分がその設計領域内に収まることにより、接続端子d(f)がy軸の正方向及び負方向のいずれに大きくずれても、上述した第1回路基板PCB1の端子d(p)の間に短絡が生じる可能性はより低く抑えられる。   In the present embodiment, as shown in FIG. 7A, the width of the terminal d (p) arranged in parallel with the connection region CNA1 of the first circuit board PCB1 is also reduced in the design region. Therefore, when the connection terminal of the second circuit board is connected to the terminal d (p) in the design area as intended by the designer, it is expected that the electrical resistance between them will increase. However, as shown in FIG. 7B, the connection terminal d (f) (a part of the conductor layer) whose length in the y-axis direction is Y [TERa] (part of the conductor layer) has a design region whose length in the y-axis direction is Lp. The center is shifted to either the positive direction of the y-axis or the negative direction of the y-axis. Accordingly, when the displacement amount TER (+ y) in the positive direction of the y axis and the displacement amount TER (−y) in the negative direction of the y axis are equal to or less than half of Lp, the terminal d (p) formed in the design region. When the length Yc of the wide part (the second part) is smaller than Lp, the connection terminal d (f) shifted in the positive direction of the y axis and the connection terminal d (f) shifted in the negative direction of the y axis Are connected to the second portion of the terminal d (p). Therefore, even if the first circuit board PCB1 of this embodiment is warped as shown in FIG. 5D, the region between the terminal d (p) formed on the first circuit board PCB1 and the connection terminal d (f) of the second circuit board. It becomes easy to make the electrical connection conditions in 6a and 6b and the electrical connection state of the design region of the terminal d (p) and the connection terminal d (f) of the second circuit board outside these regions. In addition, since the second portion of the terminal d (p) is within the design area, the first circuit board described above can be used regardless of whether the connection terminal d (f) is greatly displaced in the positive or negative direction of the y-axis. The possibility of a short circuit occurring between the terminals d (p) of the PCB 1 is further suppressed.

この効果を、本実施例に応じて試作された上記第1回路基板PCB1とこれに形成された端子(接続領域CNA)に接続される上記第2回路基板FPC1との接続を例にあげて説明すると、y軸方向に、長さLb=1.2mmの部分、その一端からy軸の負方向に延びる長さLp1=0.4mmの延長部分、及びその他端からy軸の正方向に延びる長さLp2=0.4mmの延長部分からなる端子d(p)は、これに接続される長さY[TERa]=1.2mmの接続端子d(f)がy軸の負方向に沿って最大TER(−y)=0.4mmだけずれることと、y軸の正方向に沿って最大TER(+y)=0.4mmだけずれることとを許容する。この場合を図7(A)を参照して説明すると、y軸の正方向に向けて最も大きくずれた(シフトした)第2回路基板の接続端子輪郭d(f)’及びy軸の負方向に向けて最も大きくずれた第2回路基板の接続端子d(f)”のいずれも端子d(p)の設計領域に0.8mm重なる。このため、当該設計領域にて、前者の接続端子d(f)’と後者の接続端子d(f)”とは互いに0.4mmの長さで重なる。従って、この端子d(p)の第2部分の長さYcを0.4mmとし、第1部分の長さYe1及び第3部分の長さYe2を夫々0.8mmとすれば、端子d(p)の設計領域に正確に接続される第2回路基板の接続端子d(f)における当該端子d(p)と当該接続端子d(f)との導通条件を、y軸方向に大きくずれて端子d(p)に接続される接続端子d(f)’や接続端子d(f)”におけるそれに合わせられる。本実施例の第1回路基板PCB1は、その端子d(p)に接続される第2回路基板の接続端子d(f)の位置がy軸の正方向及び負方向の各々に同じ程度でずれてもよいように設計されているが、第2回路基板の接続端子d(f)の位置がy軸の正方向及び負方向のいずれか一方に向けてずれ易い場合は、第1部分の長さYe1と第3部分の長さYe2とを違えることが望ましい。   This effect will be described with reference to the connection between the first circuit board PCB1 prototyped according to the present embodiment and the second circuit board FPC1 connected to the terminal (connection area CNA) formed thereon. Then, in the y-axis direction, a portion having a length Lb = 1.2 mm, an extending portion having a length Lp1 = 0.4 mm extending from one end thereof in the negative direction of the y-axis, and a length extending from the other end in the positive direction of the y-axis. The terminal d (p) consisting of an extension of length Lp2 = 0.4 mm has a maximum length of Y [TERa] = 1.2 mm connecting terminal d (f) connected thereto along the negative direction of the y-axis. It is allowed to deviate by TER (−y) = 0.4 mm and to deviate by maximum TER (+ y) = 0.4 mm along the positive direction of the y-axis. This case will be described with reference to FIG. 7A. The connection terminal contour d (f) ′ of the second circuit board that is most greatly shifted (shifted) in the positive direction of the y-axis and the negative direction of the y-axis. Any of the connection terminals d (f) ″ of the second circuit board that is displaced the most toward the terminal overlaps the design area of the terminal d (p) by 0.8 mm. For this reason, in the design area, the former connection terminal d (F) ′ and the latter connection terminal d (f) ″ overlap each other with a length of 0.4 mm. Therefore, if the length Yc of the second portion of the terminal d (p) is 0.4 mm, the length Ye1 of the first portion and the length Ye2 of the third portion are 0.8 mm, respectively, the terminal d (p ) In the connection terminal d (f) of the second circuit board that is accurately connected to the design area of the second circuit board, the conduction condition between the connection terminal d (p) and the connection terminal d (f) is greatly shifted in the y-axis direction. The first circuit board PCB1 of the present embodiment is connected to the terminal d (p) connected to the connection terminal d (f) ′ connected to d (p) and the connection terminal d (f) ″. The connection terminal d (f) of the second circuit board is designed so that the position of the connection terminal d (f) of the two circuit boards may be shifted by the same degree in each of the positive and negative directions of the y-axis. When the position of the first portion is likely to be shifted toward either the positive direction or the negative direction of the y-axis, the length Y of the first portion It is desirable made different 1 and the third portion length of Ye2.

なお、本実施例で説明した第1回路基板PCB1の端子d(p)の寸法を第2回路基板の接続端子d(f)の寸法と比較すると、端子d(p)の第2部分の長さYc(y軸方向の寸法)は接続端子d(f)の長さY[TERa]より小さくすることが望ましく、その幅(x軸方向の寸法)Wpは、隣り合う一対の接続端子d(f)をx軸方向に離間する距離(間隔)Sfに合わせ、誤差を含めて0.8Sf乃至1.2Sfの範囲に納めるとよい。また、隣り合う一対の第2部分をx軸方向に離間する距離(間隔)Spは、接続端子d(f)の幅Wfに合わせる。端子d2(p)の第1部分の幅Wp1及び第3部分の幅Wp2は、これを狭めたことにより拡がる隣り合う一対の第1部分をx軸方向に離す距離S’や隣り合う一対の第3部分をx軸方向に離す距離S”との釣り合いに応じて決めることが望ましい。、第1部分の幅Wp1はその隣り合う一対をx軸方向に離す距離S’の半分以下とし、第3部分の幅Wp2はその隣り合う一対をx軸方向に離す距離S”の半分以下とする。距離S’及び距離S”に好適な絶対値は、例えば0.5mm未満に抑えるとよい。第1回路基板PCB1の端子d(p)自体の長さ(換言すれば、接続領域CNA1の幅)Yb(CNA)は、比較例で述べたような目安で決め、例えば、第2回路基板FPC1の端部の幅(換言すれば、接続端子の長さ)Y[TERa]の1.2倍以上(更に望ましくは1.5倍以上)にするとよい。第1回路基板PCB1の端子d(p)に導電性粒子PARを余計に付着させないために、第1回路基板PCB1の端子d(p)の長さYb(CNA)はy軸方向に延ばし過ぎないことが望ましい。第1回路基板PCB1の端子d(p)の長さは、例えば、Y[TERa]の2倍以下に抑えるとよい。   When the dimension of the terminal d (p) of the first circuit board PCB1 described in this embodiment is compared with the dimension of the connection terminal d (f) of the second circuit board, the length of the second portion of the terminal d (p) The length Yc (dimension in the y-axis direction) is preferably smaller than the length Y [TERa] of the connection terminal d (f), and its width (dimension in the x-axis direction) Wp is a pair of adjacent connection terminals d ( It is preferable that f) be matched with the distance (interval) Sf that is separated in the x-axis direction and be included in the range of 0.8 Sf to 1.2 Sf including the error. Further, the distance (interval) Sp separating the pair of adjacent second portions in the x-axis direction is set to the width Wf of the connection terminal d (f). The width Wp1 of the first portion and the width Wp2 of the third portion of the terminal d2 (p) are the distance S ′ separating the pair of adjacent first portions that are expanded by narrowing the first portion in the x-axis direction and the pair of adjacent first portions. It is desirable to determine it according to the balance with the distance S ″ that separates the three portions in the x-axis direction. The width Wp1 of the first portion is less than half of the distance S ′ that separates the adjacent pair in the x-axis direction. The width Wp2 of the part is set to be not more than half of the distance S ″ that separates the adjacent pair in the x-axis direction. The absolute values suitable for the distance S ′ and the distance S ″ are preferably less than 0.5 mm, for example. The length of the terminal d (p) itself of the first circuit board PCB1 (in other words, the width of the connection region CNA1). Yb (CNA) is determined by the standard as described in the comparative example. For example, the width of the end portion of the second circuit board FPC1 (in other words, the length of the connection terminal) is 1.2 times or more Y [TERa]. (More preferably, 1.5 times or more.) In order to prevent the conductive particles PAR from adhering excessively to the terminal d (p) of the first circuit board PCB1, the terminal d (p) of the first circuit board PCB1 The length Yb (CNA) is preferably not excessively extended in the y-axis direction, and the length of the terminal d (p) of the first circuit board PCB1 is preferably, for example, less than twice Y [TERa].

以上に述べた本実施例における第1回路基板PCB1及び第2回路基板FPC1のその他の構造や材質は、背景技術の欄にて図2(A)乃至図2(C)を参照して説明したとおりである。第2回路基板FPC1は、TAB(Tape Automated Bonding)の手法により表示パネルの駆動素子IC1を搭載したTCP(Tape Carrier Package)やCOF(Chip On Film)として知られる実装構造を有する。また、第2回路基板FPC1は、絶縁性のベースフィルムBSF(f)、その主面(第2回路基板FPC1の主面ともなる)に形成された金属、合金、導電性酸化物等の導体膜からなる複数の配線d(f)、及びこの複数の配線d(f)を覆う絶縁膜INS(f)を含む。一方、第1回路基板PCB1は、絶縁性の基材BSF(p)、その主面(第1回路基板PCB1の主面ともなる)に形成された金属、合金、導電性酸化物等の導体膜からなる複数の配線d(p)、及びこの複数の配線d(p)を覆う絶縁膜INS(p)を含む。樹脂のみで成形される第2回路基板FPC1のベースフィルムBSF(f)に対して、第1回路基板PCB1の基材BSF(p)は樹脂に浸漬されたガラス繊維等により堅牢に成形するとよい。絶縁膜INS(p)は、第2回路基板FPC1の絶縁膜INS(f)と同様に樹脂や無機材料の薄膜で形成してもよいが、これらの材料より厚い膜を形成し易い半田レジストに代えてもよい。   The other structures and materials of the first circuit board PCB1 and the second circuit board FPC1 in the present embodiment described above have been described with reference to FIGS. 2A to 2C in the background art section. It is as follows. The second circuit board FPC1 has a mounting structure known as TCP (Tape Carrier Package) or COF (Chip On Film) on which the display panel drive element IC1 is mounted by a TAB (Tape Automated Bonding) method. The second circuit board FPC1 includes an insulating base film BSF (f), a conductor film such as a metal, an alloy, or a conductive oxide formed on the main surface thereof (which also serves as the main surface of the second circuit board FPC1). A plurality of wirings d (f) and an insulating film INS (f) covering the plurality of wirings d (f). On the other hand, the first circuit board PCB1 is made of an insulating base material BSF (p), a conductor film such as a metal, an alloy, or a conductive oxide formed on the main surface (also the main surface of the first circuit board PCB1). A plurality of wirings d (p) and an insulating film INS (p) covering the plurality of wirings d (p). In contrast to the base film BSF (f) of the second circuit board FPC1 molded only with the resin, the base material BSF (p) of the first circuit board PCB1 may be molded firmly with glass fiber or the like immersed in the resin. The insulating film INS (p) may be formed of a thin film of a resin or an inorganic material as in the case of the insulating film INS (f) of the second circuit board FPC1, but a solder resist that can easily form a film thicker than these materials is used. It may be replaced.

図8(A)には、本発明による表示装置を特徴付ける新規な第1回路基板PCB1の接続領域CNA1の平面構造が、図7(A)に準じて模式的に描かれている。実施例1の第1回路基板PCB1に形成された端子d(p)が、これに接続される第2回路基板の接続端子d(f)の位置のy軸の正方向及び負方向のいずれにも同じ程度のずれを許容するように設計されているのに対し、本実施例の第1回路基板PCB1に設けられた端子d2(p)は、これに接続される第2回路基板の接続端子d(f)の位置がy軸の負方向のずれを優先させて設計されている。このため、図8(A)に示す端子d2(p)を実施例1にて定義した設計領域(長さLp)と2つの延長部分(長さLp1,Lp2)に分けると、これらの長さはLp>Lp1>Lp2の関係を満たす。接続端子d(f)がy軸の負方向にずれることを優先させるために、y軸の負方向に延びる延長部分(Lp1)がy軸の正方向に延びる延長部分(Lp2)より長く形成される。なお、本実施例の端子d2(p)と実施例1の端子端子d(p)との参照符号の相違に関しては後述する。   FIG. 8A schematically illustrates the planar structure of the connection region CNA1 of the novel first circuit board PCB1 that characterizes the display device according to the present invention, according to FIG. The terminal d (p) formed on the first circuit board PCB1 of Example 1 is in either the positive or negative direction of the y axis at the position of the connection terminal d (f) of the second circuit board connected to the terminal d (p). Is designed to allow the same degree of deviation, whereas the terminal d2 (p) provided on the first circuit board PCB1 of this embodiment is the connection terminal of the second circuit board connected thereto. The position of d (f) is designed with priority given to the negative displacement of the y-axis. Therefore, when the terminal d2 (p) shown in FIG. 8A is divided into the design region (length Lp) and the two extended portions (lengths Lp1, Lp2) defined in the first embodiment, these lengths are divided. Satisfies the relationship Lp> Lp1> Lp2. In order to give priority to shifting the connection terminal d (f) in the negative direction of the y-axis, the extension portion (Lp1) extending in the negative direction of the y-axis is formed longer than the extension portion (Lp2) extending in the positive direction of the y-axis. The The difference in reference numerals between the terminal d2 (p) of the present embodiment and the terminal d (p) of the first embodiment will be described later.

図8(A)に示す如く設計される本実施例の第1回路基板PCB1は、例えば図5(C)に示す如く成形される。この第1回路基板PCB1の両端及びその近傍に形成された端子d2(p)の設計領域に、アラインメント・マークALM1を基準にして、第2回路基板の接続端子d(f)を合わせて接続するとき、図8(A)に示す本実施例の端子d2(p)の形状は、第1回路基板PCB1の中央がy軸の正方向(表示パネルPNLの反対方向)に反ることに起因する問題を解決する。この問題とは、実施例1でも述べた、隣り合う端子d2(p)間の短絡と、第1回路基板PCB1(端子d2(p))と第2回路基板(接続端子d(f))との電気的な接続条件のx軸沿いに生じるばらつきである。見方を変えれば、本実施例の第1回路基板PCB1の中心に形成された端子d2(p)の設計領域に第2回路基板の接続端子d(f)を合わせる場合、図8(A)に示す本実施例の端子d2(p)の形状は、第1回路基板PCB1の中央がy軸の負方向(表示パネルPNL向き)に反ることに起因する上述の諸問題を解決する。   The first circuit board PCB1 of this embodiment designed as shown in FIG. 8A is formed as shown in FIG. 5C, for example. The connection terminal d (f) of the second circuit board is connected to the design region of the terminal d2 (p) formed at both ends of the first circuit board PCB1 and in the vicinity thereof with the alignment mark ALM1 as a reference. At this time, the shape of the terminal d2 (p) in this embodiment shown in FIG. 8A is caused by the center of the first circuit board PCB1 being warped in the positive direction of the y-axis (the direction opposite to the display panel PNL). Solve a problem. This problem is the short circuit between the adjacent terminals d2 (p) described in the first embodiment, the first circuit board PCB1 (terminal d2 (p)), and the second circuit board (connection terminal d (f)). The variation that occurs along the x-axis of the electrical connection conditions. In other words, when the connection terminal d (f) of the second circuit board is aligned with the design region of the terminal d2 (p) formed at the center of the first circuit board PCB1 of this embodiment, FIG. The shape of the terminal d2 (p) of the present embodiment shown solves the above-mentioned problems caused by the center of the first circuit board PCB1 being warped in the negative y-axis direction (toward the display panel PNL).

本実施例においても、実施例1と同様に、これに鑑み、以下に如き第1回路基板PCB1を試作した。この試作品において、上述のLp1,Lp,及びLp2の長さは、夫々0.5mm,1.2mm,0.2mmとなる。また、端子d2(p)を、図8(B)に示す如く、y軸沿いに実施例1と同様に定義される第1部分(長さYe1),第2部分(長さYc),及び第3部分(長さYe2)に分けると、夫々の長さは0.5mm,1.0mm,0.4mmになる。換言すれば、長さYe1,Yc,及びYe2は、Yc>Ye1>Ye2,Ye1=Lp1,Yc<Lp,及びYe2>Lp2の関係を満たす。端子d2(p)における第1部分の幅Wp1及び第3部分の幅Wp2は0.25mmであり、第2部分の幅Wpは0.5mmである。隣り合う一対の導体層d2(p)の第1部分を隔てる間隔Sp’及び第3部分を隔てる間隔Sp”は0.75mmであり、第2部分を隔てる間隔Spは0.5mmである。また、この試作された第1回路基板PCB1に接続される第2回路基板には、実施例1にて用いたものと同様に、幅Wfが0.5mmの接続端子d(f)が0.5mmの間隔Sfでx軸方向に並設される。この接続端子は、第2回路基板に形成された導体層d(f)の端を、1.2mmの長さ(y軸方向の寸法)Y[TERa]で絶縁膜INS(f)から露出させて形成される。   In the present embodiment as well, in the same manner as in the first embodiment, in view of this, a first circuit board PCB1 as described below was prototyped. In this prototype, the lengths of Lp1, Lp, and Lp2 described above are 0.5 mm, 1.2 mm, and 0.2 mm, respectively. Further, as shown in FIG. 8B, the terminal d2 (p) has a first part (length Ye1), a second part (length Yc), If it divides into the 3rd part (length Ye2), each length will be 0.5 mm, 1.0 mm, and 0.4 mm. In other words, the lengths Ye1, Yc, and Ye2 satisfy the relationship of Yc> Ye1> Ye2, Ye1 = Lp1, Yc <Lp, and Ye2> Lp2. In the terminal d2 (p), the width Wp1 of the first portion and the width Wp2 of the third portion are 0.25 mm, and the width Wp of the second portion is 0.5 mm. The interval Sp ′ separating the first portions of the pair of adjacent conductor layers d2 (p) and the interval Sp ″ separating the third portions are 0.75 mm, and the interval Sp separating the second portions is 0.5 mm. The second circuit board connected to the prototyped first circuit board PCB1 has a connection terminal d (f) of 0.5 mm in width Wf of 0.5 mm, similar to that used in the first embodiment. This connection terminal is connected to the end of the conductor layer d (f) formed on the second circuit board with a length Y of 1.2 mm (dimension in the y-axis direction). [TERa] is exposed from the insulating film INS (f).

本実施例の第1回路基板PCB1では、図8(B)に示す如く、基材BSF(p)の主面に導体層d2(p)からなる端子が形成され、この基材BSF(p)の裏面(当該主面とは反対側に位置する他の主面)に導体層d(p)からなる回路が形成される。この2つの導体層d2(p),d(p)は、基材BSF(p)を貫通するスルーホールTHにて電気的に接続される。図8(A)において、導体層d(p)及びスルーホールTHは細い破線で示される。スルーホールTHは、幅の広い第2部分にて端子d2(p)に接続されるとよい。図8(A)及び図8(B)に示される第1回路基板PCB1では、端子となる導体層d2(p)とこれから第1回路基板PCB1内に延びる配線をなす導体層d(p)とが別の層(Level)に形成されるため、導体層d2(p)は、実施例1の導体層d(p)如く接続領域CNA1の外側へ延びない。しかし、本実施例の第1回路基板PCB1が、実施例1で例示した第1回路基板PCB1と同様な断面構造をもつ場合、図7(A)に示される接続領域CNA1内の導体層d(p)の輪郭を図8(A)に示す端子d2(p)のそれに倣って成形される。また、接続領域CNA1の外側へ延びる導体層d(p)の幅は実施例1と同様に端子の第1部分又は第3部分より広くしても良い。   In the first circuit board PCB1 of this embodiment, as shown in FIG. 8B, a terminal made of the conductor layer d2 (p) is formed on the main surface of the base material BSF (p), and this base material BSF (p) A circuit composed of the conductor layer d (p) is formed on the back surface (the other main surface opposite to the main surface). The two conductor layers d2 (p) and d (p) are electrically connected through a through hole TH penetrating the base material BSF (p). In FIG. 8A, the conductor layer d (p) and the through hole TH are indicated by thin broken lines. The through hole TH is preferably connected to the terminal d2 (p) at the second wide portion. In the first circuit board PCB1 shown in FIGS. 8A and 8B, a conductor layer d2 (p) serving as a terminal and a conductor layer d (p) forming a wiring extending into the first circuit board PCB1 from the conductor layer d2 (p). Is formed in another layer (Level), the conductor layer d2 (p) does not extend outside the connection region CNA1 like the conductor layer d (p) of the first embodiment. However, when the first circuit board PCB1 of the present embodiment has the same cross-sectional structure as the first circuit board PCB1 illustrated in the first embodiment, the conductor layer d (in the connection region CNA1 shown in FIG. The contour of p) is formed following that of the terminal d2 (p) shown in FIG. Further, the width of the conductor layer d (p) extending outside the connection region CNA1 may be wider than the first portion or the third portion of the terminal, as in the first embodiment.

一方、本実施例の第1回路基板PCB1に形成された端子に接続される第2回路基板の接続端子d(f)の輪郭は、図8(A)に示された4本の端子d2(p)の内側2本に重ねて描かれた破線で示され、その端からy軸沿いに延びた長さY[TERa]の部分が接続端子として、端子d2(p)の設計領域(長さLpの部分)に接続される。上述のとおり、本実施例の第1回路基板PCB1は、端子d2(p)に接続される第2回路基板の接続端子d(f)の位置がy軸の負方向にずれ易いことを考慮して設計される。従って、y軸の負方向に最も大きくずれて図8(A)の左端の端子d2(p)に接続される第2回路基板の接続端子の輪郭を、二点鎖線の枠d(f)”で示す。この輪郭d(f)”は、第2回路基板の導体層d(f)の端子d2(p)に実際に接続される部分のみを示し、その位置は端子d2(p)の設計領域からy軸の負方向に距離TER(−y)だけずれている。   On the other hand, the outline of the connection terminal d (f) of the second circuit board connected to the terminals formed on the first circuit board PCB1 of the present embodiment is the four terminals d2 ( The design area (length) of a terminal d2 (p) is indicated by a broken line drawn on two inner sides of p) and has a length Y [TERa] extending from the end along the y-axis as a connection terminal. Lp portion). As described above, the first circuit board PCB1 of this embodiment takes into account that the position of the connection terminal d (f) of the second circuit board connected to the terminal d2 (p) is likely to shift in the negative direction of the y-axis. Designed. Therefore, the outline of the connection terminal of the second circuit board connected to the terminal d2 (p) at the left end in FIG. 8A with the largest deviation in the negative direction of the y-axis is represented by a two-dot chain line d (f) ". This outline d (f) ″ indicates only a portion that is actually connected to the terminal d2 (p) of the conductor layer d (f) of the second circuit board, and its position is the design of the terminal d2 (p). The region is deviated by a distance TER (−y) in the negative direction of the y-axis.

このような技術的背景で設計される本実施例の第1回路基板PCB1は、図8(A)に示す如く、端子d2(p)の第2部分の第1部分に接する端が、当該端子d2(p)の設計領域の端(y軸の負側,所謂表示パネルPNL寄り)と重なる。換言すれば、y軸の負側に形成された延長部分の長さLp1は第1部分の長さYe1に等しい。このため、実施例1に比べて端子d2(p)の第2部分を長く形成でき、端子d2(p)と接続端子d(f)との接続抵抗を低減できる。また、図8(A)の内側2本の端子d2(p)の第2部分と接続端子d(f)の長さY[TERa]の部分の輪郭(太い破線)との重なりと、左端に示す端子d2(p)の第2部分と接続端子の輪郭d(f)”(二点鎖線)との重なりとの比較から明らかなように、端子d2(p)と接続端子d(f)との電気的な接続条件は、第1回路基板PCB1のx軸方向に生じる接続端子d(f)と端子d2(p)設計領域との位置合わせの相違の影響を受けることなく、一定に保たれる。また、端子d2(p)の第2部分が延びただけ第1部分は短くなるも、この第1部分及び第3部分が形成されたことにより端子d2(p)間の短絡が防がれることは、実施例1で述べたとおりである。   As shown in FIG. 8A, the first circuit board PCB1 of this embodiment designed with such a technical background has an end in contact with the first part of the second part of the terminal d2 (p). It overlaps with the end of the design area d2 (p) (the negative side of the y-axis, close to the so-called display panel PNL). In other words, the length Lp1 of the extended portion formed on the negative side of the y-axis is equal to the length Ye1 of the first portion. For this reason, compared with Example 1, the 2nd part of terminal d2 (p) can be formed long, and the connection resistance of terminal d2 (p) and connecting terminal d (f) can be reduced. Also, the overlap between the second portion of the two inner terminals d2 (p) in FIG. 8A and the outline (thick dashed line) of the length Y [TERa] portion of the connection terminal d (f) As apparent from a comparison between the second portion of the terminal d2 (p) shown and the overlap of the outline d (f) ″ (two-dot chain line) of the connection terminal, the terminal d2 (p) and the connection terminal d (f) The electrical connection conditions are kept constant without being affected by the difference in alignment between the design area of the connection terminal d (f) and the terminal d2 (p) generated in the x-axis direction of the first circuit board PCB1. Further, although the first portion becomes shorter as the second portion of the terminal d2 (p) extends, the short circuit between the terminals d2 (p) is prevented by forming the first portion and the third portion. This is as described in the first embodiment.

以上の説明からすると、本実施例の第1回路基板PCB1に形成された端子d2(p)の第1部分及び第3部分は必要以上に長く形成されるように見える。しかしながら、接続端子d(f)の不測のずれ(y軸の正方向も含む)を考慮すると、このように端子d2(p)の第1部分及び第3部分を冗長に形成することが望ましい。また、斯様な冗長部分は、上述した第1部分及び第3部分の定義のとおり、第2部分より幅を狭めて、その隣り合う一対をx軸方向により広く離すことが望ましい。   From the above description, it appears that the first and third portions of the terminal d2 (p) formed on the first circuit board PCB1 of this embodiment are formed longer than necessary. However, considering an unexpected shift of the connection terminal d (f) (including the positive direction of the y-axis), it is desirable to form the first part and the third part of the terminal d2 (p) redundantly in this way. In addition, as described above, the redundant part is preferably narrower than the second part, and the adjacent pairs are more widely separated in the x-axis direction as defined in the first part and the third part.

なお、本実施例においても実施例1と同様に、端子d2(p)の第2部分の長さYcを接続端子d(f)の長さY[TERa]より小さくすることが望ましく、その幅Wpは、接続端子d(f)の幅Wfに合わせ、その幅(x軸方向の寸法)Wpは、隣り合う一対の接続端子d(f)をx軸方向に離間する距離(間隔)Sfに合わせ、誤差を含めて0.8Sf乃至1.2Sfの範囲に納めるとよい。また、隣り合う一対の第2部分をx軸方向に離間する距離(間隔)Spは、接続端子d(f)の幅Wfに合わせる。端子d2(p)の第1部分の幅Wp1及び第3部分の幅Wp2は、これを狭めたことにより拡がる隣り合う一対の第1部分をx軸方向に離す距離S’や隣り合う一対の第3部分をx軸方向に離す距離S”との釣り合いに応じて決めることが望ましい。例えば、第1部分の幅Wp1はその隣り合う一対をx軸方向に離す距離S’の半分以下とし、第3部分の幅Wp2はその隣り合う一対をx軸方向に離す距離S”の半分以下とする。距離S’及び距離S”に好適な絶対値は、例えば0.5mm未満に抑えるとよい。第1回路基板PCB1の端子d(p)自体の長さ(換言すれば、接続領域CNA1の幅)Yb(CNA)は、比較例で述べたような目安で決め、例えば、第2回路基板FPC1の端部の幅(換言すれば、接続端子の長さ)Y[TERa]の1.2倍以上(更に望ましくは1.5倍以上)にするとよい。また、第1回路基板PCB1の端子d(p)に導電性粒子PARを余計に付着させないために、第1回路基板PCB1の端子d(p)の長さは、例えば、Y[TERa]の2倍以下に抑えるとよい。   In the present embodiment, similarly to the first embodiment, it is desirable that the length Yc of the second portion of the terminal d2 (p) be smaller than the length Y [TERa] of the connection terminal d (f), and its width Wp matches the width Wf of the connection terminal d (f), and its width (dimension in the x-axis direction) Wp is a distance (interval) Sf that separates a pair of adjacent connection terminals d (f) in the x-axis direction. In addition, it is preferable that the error is included in the range of 0.8 Sf to 1.2 Sf. Further, the distance (interval) Sp separating the pair of adjacent second portions in the x-axis direction is set to the width Wf of the connection terminal d (f). The width Wp1 of the first portion and the width Wp2 of the third portion of the terminal d2 (p) are the distance S ′ separating the pair of adjacent first portions that are expanded by narrowing the first portion in the x-axis direction and the pair of adjacent first portions. It is desirable to determine according to the balance with the distance S ″ that separates the three portions in the x-axis direction. For example, the width Wp1 of the first portion is less than half of the distance S ′ that separates the adjacent pair in the x-axis direction. The width Wp2 of the three portions is set to be not more than half of the distance S ″ that separates the adjacent pairs in the x-axis direction. The absolute values suitable for the distance S ′ and the distance S ″ are preferably less than 0.5 mm, for example. The length of the terminal d (p) itself of the first circuit board PCB1 (in other words, the width of the connection region CNA1). Yb (CNA) is determined by the standard as described in the comparative example. For example, the width of the end portion of the second circuit board FPC1 (in other words, the length of the connection terminal) is 1.2 times or more Y [TERa]. (More preferably, 1.5 times or more.) In order to prevent the conductive particles PAR from adhering to the terminals d (p) of the first circuit board PCB1, the terminals d (p) of the first circuit board PCB1 are used. ) May be suppressed to, for example, not more than twice Y [TERa].

本実施例で説明した第1回路基板PCB1は、絶縁性の基材BSF(p)は、樹脂のみで成形してもよいが、樹脂に浸漬されたガラス繊維等により第2回路基板FPC1のベースフィルムBSF(f)より堅牢に成形してもよい。導体層d(p),d2(p)は、例えば金属、合金、又は導電性酸化物で形成される。絶縁膜INS(p)は、第2回路基板FPC1の絶縁膜INS(f)と同様に樹脂や無機材料の薄膜で形成してもよいが、これらの材料より厚い膜を形成し易い半田レジストに代えてもよい。第1回路基板PCB1に形成された複数の端子d2(p)と第2回路基板FPC1の接続端子d(f)とは、異方性導電膜ACFにより電気的に接続される。   In the first circuit board PCB1 described in this embodiment, the insulating base material BSF (p) may be formed of only a resin, but the base of the second circuit board FPC1 is made of glass fiber or the like immersed in the resin. The film may be formed more firmly than the film BSF (f). The conductor layers d (p) and d2 (p) are formed of, for example, a metal, an alloy, or a conductive oxide. The insulating film INS (p) may be formed of a thin film of a resin or an inorganic material as in the case of the insulating film INS (f) of the second circuit board FPC1, but a solder resist that can easily form a film thicker than these materials is used. It may be replaced. The plurality of terminals d2 (p) formed on the first circuit board PCB1 and the connection terminals d (f) of the second circuit board FPC1 are electrically connected by an anisotropic conductive film ACF.

本実施例では、実施例1及び実施例2で例示した第1回路基板PCB1の全体の形状及びこれが適用される表示装置の構造について述べる。
図9(A)に示された表示装置は、表示パネルPNLの基板SUB1に多結晶シリコン又は擬似単結晶シリコンで垂直駆動回路VDR(例えば、アクティブ駆動における走査信号出力回路、パッシブ駆動におけるセグメント信号出力回路)及び水平駆動回路HDR(例えば、アクティブ駆動における画像信号出力回路、パッシブ駆動におけるセグメント信号出力回路)が形成される。このため、第2回路基板FPC1は図1等に示されたそれと異なり、駆動素子IC1が搭載されない単なるコネクタ(Connector)として用いられる。また、第1回路基板PCB1は、表示制御回路Tconが搭載された図1に示す制御回路基板CTBの如き、インタフェース回路基板として用いられる。
In this embodiment, the overall shape of the first circuit board PCB1 exemplified in Embodiments 1 and 2 and the structure of a display device to which the first circuit board PCB1 is applied will be described.
In the display device shown in FIG. 9A, a vertical drive circuit VDR (for example, a scanning signal output circuit in active drive, a segment signal output in passive drive) is formed on a substrate SUB1 of a display panel PNL with polycrystalline silicon or pseudo single crystal silicon. Circuit) and a horizontal drive circuit HDR (for example, an image signal output circuit in active drive, a segment signal output circuit in passive drive). For this reason, the second circuit board FPC1 is different from that shown in FIG. 1 and the like and is used as a simple connector (Connector) on which the drive element IC1 is not mounted. The first circuit board PCB1 is used as an interface circuit board such as the control circuit board CTB shown in FIG. 1 on which the display control circuit Tcon is mounted.

第1回路基板PCB1の接続領域CNAには、x軸方向に延びる一枚の第2回路基板FPC1の端部が接続されるが、第1回路基板PCB1が図9(B)に示す如く、x軸方向に長く延びて成形されるため、その領域6a,6bにおいては、比較例で説明したような問題が生じる。従って、複数の第2回路基板FPC1を一体化して、x軸方向に長く延びた第1回路基板PCB1に接続したときも、第1回路基板PCB1の端子を実施例1や実施例2に示す如く形成するとよい。   An end portion of one second circuit board FPC1 extending in the x-axis direction is connected to the connection area CNA of the first circuit board PCB1. As shown in FIG. Since it is formed to extend long in the axial direction, the problems described in the comparative example occur in the regions 6a and 6b. Therefore, even when the plurality of second circuit boards FPC1 are integrated and connected to the first circuit board PCB1 extending in the x-axis direction, the terminals of the first circuit board PCB1 are connected as shown in the first and second embodiments. It is good to form.

また、図9(B)に示す第1回路基板PCB1は、x軸方向の最大寸法Pmax(x)がy軸方向の最大寸法Pmax(y)より大きく、x軸方向にPext(x)及びy軸方向にPext(y)だけ延びた延伸部が形成される。第1回路基板PCB1において、この延伸部は上述の如く反り易い。従って、その上述の最大寸法がPmax(x)≦Pmax(y)の関係を満たす第1回路基板PCB1でも、Pext(x)>Pext(y)なる条件を満たし且つ接続部CNAが形成される延伸部を有する場合は、その接続部CNAに並設される複数の端子の形状を実施例1や実施例2に示す如く形成するとよい。   Further, in the first circuit board PCB1 shown in FIG. 9B, the maximum dimension Pmax (x) in the x-axis direction is larger than the maximum dimension Pmax (y) in the y-axis direction, and Pext (x) and y in the x-axis direction. An extending portion extending in the axial direction by Pext (y) is formed. In the first circuit board PCB1, the extending portion is easily warped as described above. Therefore, even in the first circuit board PCB1 whose maximum dimension satisfies the relationship of Pmax (x) ≦ Pmax (y), the extension satisfying the condition of Pext (x)> Pext (y) and the connection portion CNA is formed. In the case of having a portion, a plurality of terminals arranged in parallel to the connection portion CNA may be formed as shown in the first and second embodiments.

なお、図9(A)において、破線の枠で囲まれた領域PIXは、表示パネルの主面に二次元的に配置された複数の画素領域の一つを示す。各々の画素領域PIXには、画像表示に直接寄与する画素回路PX(容量で示されているが、EL表示装置ではダイオードに代えてもよい)と、この画素回路の制御に係る制御回路SW(例えば、スイッチング素子)が形成される。図示された画素領域PIXは、アクティブ駆動される表示装置に合わせて示されるが、パッシブ駆動される表示装置においては画素領域PIXから制御回路SWが取り除かれる。   In FIG. 9A, an area PIX surrounded by a broken-line frame indicates one of a plurality of pixel areas arranged two-dimensionally on the main surface of the display panel. In each pixel region PIX, a pixel circuit PX (indicated by a capacitor, which directly contributes to image display, may be replaced by a diode in an EL display device), and a control circuit SW ( For example, a switching element) is formed. The illustrated pixel region PIX is shown in accordance with a display device that is actively driven, but the control circuit SW is removed from the pixel region PIX in a display device that is passively driven.

本発明の背景技術となる表示装置(液晶表示装置)の表示パネル周辺の構造を模式的に説明する平面図である。It is a top view which illustrates typically the structure of the display panel periphery of the display apparatus (liquid crystal display device) used as the background art of this invention. 図1に示された表示装置に用いられる第1回路基板PCB1と第2回路基板FPC1の接続形態を示す拡大図であり、(A)は接続部分の平面図、(B)及び(C)は接続部分の断面構造を夫々示す。It is an enlarged view which shows the connection form of 1st circuit board PCB1 and 2nd circuit board FPC1 used for the display apparatus shown by FIG. 1, (A) is a top view of a connection part, (B) and (C) are FIG. The cross-sectional structure of the connecting portion is shown. 図1及び図2(A)乃至2(C)に示された第1回路基板PCB1に生じる「反り」の問題を説明する平面図である。FIG. 3 is a plan view for explaining a problem of “warping” occurring in the first circuit board PCB1 shown in FIGS. 1 and 2A to 2C. (A)は図1に示された表示装置において、第1回路基板PCB1が図3(B)に示す如く反ったときを示す平面図であり、(B)はこのときの第1回路基板PCB1と第2回路基板FPC1との接続部分を示す断面図である。1A is a plan view showing a state in which the first circuit board PCB1 is warped as shown in FIG. 3B in the display device shown in FIG. 1, and FIG. 3B is a first circuit board PCB1 at this time. It is sectional drawing which shows the connection part of 2nd and 2nd circuit board FPC1. (A)は従来の第1回路基板PCB1をその接続領域CNA1に接続された第2回路基板FPC1とともに示す平面図、(B)は(A)に示す第1回路基板PCB1の中心がy軸の負方向に沿った状態を示す平面図、(C)は本発明者が検討した比較例における第1回路基板PCB1をその接続領域CNA1に接続された第2回路基板FPC1とともに示す平面図、及び(D)は(C)に示す第1回路基板PCB1の中心がy軸の負方向に沿った状態を示す平面図である。(A) is a plan view showing a conventional first circuit board PCB1 together with a second circuit board FPC1 connected to the connection area CNA1, and (B) is a center of the first circuit board PCB1 shown in FIG. (C) is a plan view showing the first circuit board PCB1 in the comparative example examined by the present inventors together with the second circuit board FPC1 connected to the connection region CNA1, and (C). (D) is a plan view showing a state in which the center of the first circuit board PCB1 shown in (C) is along the negative direction of the y-axis. (A)は図5(D)の領域6aに生じる端子d(p)間の短絡を説明する平面図、(B)は図5(D)の領域6bに生じる端子d(p)間の短絡を説明する平面図、(C)は(A)で説明される端子d(p)間の短絡箇所を示す断面図、及び(D)は(B)で説明される端子d(p)間の短絡箇所を示す断面図である。FIG. 5A is a plan view for explaining a short circuit between terminals d (p) occurring in the region 6a of FIG. 5D, and FIG. 5B is a short circuit between the terminals d (p) occurring in the region 6b of FIG. (C) is sectional drawing which shows the short circuit location between terminal d (p) demonstrated by (A), (D) is between terminal d (p) demonstrated by (B) It is sectional drawing which shows a short circuit location. (A)は本発明の実施例1の表示装置における第1回路基板PCB1と第2回路基板FPC1の接続形態を模式的に且つ拡大して示す平面図であり、(B)は(A)に示された第1回路基板PCB1と第2回路基板FPC1との接続部分を示す断面図である。(A) is the top view which shows typically and expanded the connection form of 1st circuit board PCB1 and 2nd circuit board FPC1 in the display apparatus of Example 1 of this invention, (B) is (A). It is sectional drawing which shows the connection part of 1st circuit board PCB1 shown and 2nd circuit board FPC1. (A)は本発明の実施例2の表示装置における第1回路基板PCB1と第2回路基板FPC1の接続形態を模式的に且つ拡大して示す平面図であり、(B)は(A)に示された第1回路基板PCB1と第2回路基板FPC1との接続部分を示す断面図である。(A) is the top view which shows typically and expanded the connection form of 1st circuit board PCB1 and 2nd circuit board FPC1 in the display apparatus of Example 2 of this invention, (B) is (A). It is sectional drawing which shows the connection part of 1st circuit board PCB1 shown and 2nd circuit board FPC1. (A)は本発明の実施例3の表示装置における表示パネルとその周辺の構造を模式的に説明する平面図であり、(B)は(A)に示される表示装置に用いられた第1回路基板PCB1の形状を説明する平面図である。(A) is a top view which illustrates typically the structure of the display panel and its periphery in the display apparatus of Example 3 of this invention, (B) is the 1st used for the display apparatus shown by (A). It is a top view explaining the shape of circuit board PCB1.

符号の説明Explanation of symbols

PNL・・・・表示パネル、PCB1, PCB2・・・・第1回路基板、FPC1, FPC2・・・・第2回路基板、CNA1,CNA2・・・・第1回路基板の接続領域、TERa、TERb・・・・第2回路基板の端部(接続端子)。

PNL ... Display panel, PCB1, PCB2 ... First circuit board, FPC1, FPC2, ... Second circuit board, CNA1, CNA2, ... Connection area of the first circuit board, TERa, TERb .... The end (connection terminal) of the second circuit board.

Claims (14)

表示パネルと、
第1方向及び該第1方向に交差する第2方向に沿う主面を有し且つ該主面には該第2方向に延びる複数の端子が該第1方向に並設されている第1回路基板と、
一端が前記表示パネルに他端が前記第1回路基板の前記複数の端子に夫々電気的に接続される少なくとも一つの第2回路基板とを備え、
前記複数の端子の隣接し合う各一対は、夫々の両端にて該夫々の両端の間よりも互いに広く隔てられる表示装置。
A display panel;
A first circuit having a main surface along a first direction and a second direction intersecting the first direction, and a plurality of terminals extending in the second direction arranged in parallel in the first direction on the main surface A substrate,
And at least one second circuit board having one end electrically connected to the display panel and the other end electrically connected to the plurality of terminals of the first circuit board,
Each pair of adjacent terminals of the plurality of terminals is separated from each other at both ends more widely than between both ends.
前記第1回路基板の前記主面は、前記第1方向沿いよりも前記第2方向沿いに長く延びている請求項1に記載の表示装置。   The display device according to claim 1, wherein the main surface of the first circuit board extends longer along the second direction than along the first direction. 前記第1回路基板には複数の前記第2回路基板が前記第1方向沿いに並設され、該第1回路基板の前記複数の端子は前記第1方向沿いに該複数の第2回路基板の夫々に対応した複数の群に分けられ且つ該複数の群の夫々に対応する該第2回路基板に電気的に接続されている請求項1に記載の表示装置。   The first circuit board includes a plurality of second circuit boards arranged along the first direction, and the plurality of terminals of the first circuit board are arranged along the first direction with respect to the plurality of second circuit boards. 2. The display device according to claim 1, wherein the display device is divided into a plurality of groups corresponding to each of the plurality of groups and electrically connected to the second circuit board corresponding to each of the plurality of groups. 前記表示パネルは対向する一対の辺と該一対の辺の一つに交差する方向に延びる他の一対の辺とを有する矩形状に成形され、前記複数の第2回路基板は該表示パネルの該一対の辺及び該他の一対の辺のいずれか一つの辺に並設されている請求項3に記載の表示装置。   The display panel is formed in a rectangular shape having a pair of opposite sides and another pair of sides extending in a direction intersecting one of the pair of sides, and the plurality of second circuit boards are formed on the display panel. The display device according to claim 3, wherein the display device is juxtaposed along one of the pair of sides and the other pair of sides. 前記複数の第2回路基板の各々には前記表示パネルの駆動回路素子が搭載されている請求項3に記載の表示装置。   The display device according to claim 3, wherein a driving circuit element of the display panel is mounted on each of the plurality of second circuit boards. 前記第1回路基板の前記主面において前記複数の端子が前記第1方向に並設された領域は、前記第2方向よりも該第1方向沿いに長く延びている請求項1に記載の表示装置。   2. The display according to claim 1, wherein a region where the plurality of terminals are arranged in parallel in the first direction on the main surface of the first circuit board extends longer in the first direction than in the second direction. apparatus. 前記複数の端子が並設された領域の前記第2方向沿いの幅は、前記第2回路基板の該複数の端子に電気的に接続される前記他端の該第2方向沿いの幅よりも広い請求項6に記載の表示装置。   The width along the second direction of the region where the plurality of terminals are arranged side by side is larger than the width along the second direction of the other end electrically connected to the plurality of terminals of the second circuit board. The display device according to claim 6, which is wide. 前記第1回路基板及びこれに電気的に接続される前記第2回路基板は前記第1方向及び前記第2方向に交差する第3方向沿いに厚みを有し、該第2回路基板は可撓である請求項7に記載の表示装置。   The first circuit board and the second circuit board electrically connected to the first circuit board have a thickness along a third direction intersecting the first direction and the second direction, and the second circuit board is flexible. The display device according to claim 7. 表示パネルと、
第1方向及び該第1方向に交差する第2方向に沿う主面を有し且つ該主面には該第2方向に延びる複数の端子が該第1方向に並んで形成されている第1回路基板と、
一端が前記表示パネルに他端が前記第1回路基板の前記複数の端子に夫々電気的に接続される少なくとも一つの第2回路基板とを備え、
前記第2回路基板の前記他端には前記第1回路基板の前記複数の端子の一つに夫々接続され且つ該一つの端子に接続された状態で前記第2方向沿いに延びる接続端子が形成され、
前記第1回路基板の前記一つの端子が前記第2方向に沿いに延びる長さは前記第2回路基板の前記接続端子のそれより長く、且つ前記一つの端子の前記第1方向に沿う幅は該一つの端子の両端にて該両端の間の部分に比べて狭まっている表示装置。
A display panel;
A first surface having a main surface along a first direction and a second direction intersecting the first direction, and a plurality of terminals extending in the second direction are formed side by side in the first direction on the main surface. A circuit board;
And at least one second circuit board having one end electrically connected to the display panel and the other end electrically connected to the plurality of terminals of the first circuit board,
At the other end of the second circuit board, a connection terminal is formed which is connected to one of the plurality of terminals of the first circuit board and extends along the second direction while being connected to the one terminal. And
The length of the one terminal of the first circuit board extending along the second direction is longer than that of the connection terminal of the second circuit board, and the width of the one terminal along the first direction is A display device in which both ends of the one terminal are narrower than a portion between the both ends.
前記第1回路基板の前記主面に形成された前記複数の端子は、該第1回路基板主面に導体層として形成された複数の配線の一部であり、該第1回路基板主面にて該複数の配線を覆う絶縁膜に形成された開口から露出されている請求項9に記載の表示装置。   The plurality of terminals formed on the main surface of the first circuit board are a part of a plurality of wirings formed as a conductor layer on the first circuit board main surface. The display device according to claim 9, wherein the display device is exposed from an opening formed in an insulating film covering the plurality of wirings. 前記絶縁膜の前記開口は前記第2方向よりも前記第1方向沿いに長く延びて形成され、該開口に並設された前記複数の端子の該第2方向に沿う長さは該開口の該第2方向に沿う幅により決められている請求項10に記載の表示装置。   The opening of the insulating film is formed to extend longer along the first direction than the second direction, and the length along the second direction of the plurality of terminals arranged in parallel with the opening is the length of the opening. The display device according to claim 10, which is determined by a width along the second direction. 前記第2回路基板の前記他端には、前記絶縁膜の前記開口内に並ぶ前記第1回路基板の前記複数の端子に夫々に接続される複数の前記接続端子が並設される請求項11に記載の表示装置。   The plurality of connection terminals respectively connected to the plurality of terminals of the first circuit board arranged in the opening of the insulating film are arranged in parallel at the other end of the second circuit board. The display device described in 1. 前記第1回路基板の前記一つの端子の前記両端に挟まれて形成された該両端より第1方向に沿う幅の広い前記部分の前記第2方向沿いの長さは、該一つの端子に接続される前記第2回路基板の前記接続端子のそれに比べて短い請求項9に記載の表示装置。   The length along the second direction of the portion that is formed between the both ends of the one terminal of the first circuit board and that is wider than the both ends along the first direction is connected to the one terminal. The display device according to claim 9, wherein the display device is shorter than that of the connection terminal of the second circuit board. 前記第2回路基板の前記接続端子は、該第2回路基板の主面に形成された導体層の該第2回路基板の前記他端にて該導体層を覆う絶縁膜から露出した一部分である請求項9に記載の表示装置。


The connection terminal of the second circuit board is a part exposed from an insulating film covering the conductor layer at the other end of the second circuit board of a conductor layer formed on the main surface of the second circuit board. The display device according to claim 9.


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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009084138A1 (en) * 2007-12-28 2009-07-09 Panasonic Corporation Electronic device
KR101789237B1 (en) 2011-01-19 2017-10-24 삼성디스플레이 주식회사 Liquid crystal display apparatus

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104143294A (en) * 2014-07-24 2014-11-12 捷星显示科技(福建)有限公司 Nanometer water ion display device

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5658594U (en) * 1979-10-09 1981-05-20
JPS6443390U (en) * 1987-09-09 1989-03-15
JPH0381982U (en) * 1989-12-08 1991-08-21
JPH08316590A (en) * 1995-05-19 1996-11-29 Hitachi Ltd Printed board, production thereof, apparatus and liquid crystal display having printed board
JP2002232098A (en) * 2001-01-31 2002-08-16 Seiko Epson Corp Wiring board, optoelectric device, and electronic apparatus
JP2002328620A (en) * 2001-04-27 2002-11-15 Advanced Display Inc Liquid crystal display
JP2003167269A (en) * 2001-11-29 2003-06-13 Sharp Corp Display device
JP2003218492A (en) * 2002-01-28 2003-07-31 Mitsubishi Electric Corp Terminal connecting structure and matrix type flat display apparatus
JP2003287767A (en) * 2002-03-27 2003-10-10 Optrex Corp Liquid crystal display device

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5658594U (en) * 1979-10-09 1981-05-20
JPS6443390U (en) * 1987-09-09 1989-03-15
JPH0381982U (en) * 1989-12-08 1991-08-21
JPH08316590A (en) * 1995-05-19 1996-11-29 Hitachi Ltd Printed board, production thereof, apparatus and liquid crystal display having printed board
JP2002232098A (en) * 2001-01-31 2002-08-16 Seiko Epson Corp Wiring board, optoelectric device, and electronic apparatus
JP2002328620A (en) * 2001-04-27 2002-11-15 Advanced Display Inc Liquid crystal display
JP2003167269A (en) * 2001-11-29 2003-06-13 Sharp Corp Display device
JP2003218492A (en) * 2002-01-28 2003-07-31 Mitsubishi Electric Corp Terminal connecting structure and matrix type flat display apparatus
JP2003287767A (en) * 2002-03-27 2003-10-10 Optrex Corp Liquid crystal display device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009084138A1 (en) * 2007-12-28 2009-07-09 Panasonic Corporation Electronic device
US8223294B2 (en) 2007-12-28 2012-07-17 Panasonic Corporation Electronic device
KR101789237B1 (en) 2011-01-19 2017-10-24 삼성디스플레이 주식회사 Liquid crystal display apparatus

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