JP2005224095A - Boosting circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a boosting circuit wherein a perfect discharge is performed within a fixed period, and stable operation is obtained, without giving adverse effects at the next starting. <P>SOLUTION: The boosting circuit includes p-channel transistors 2, 3, 5 and an n-channel transistor 6, capacitance 4 connected between a connecting side of the transistors 2, 3 and a connecting side of the transistors 5, 6, capacitance 1 connected to the opposite side of the capacitance 4 of the transistor 2, and a discharge resistor 7 for discharging which is connected to a side of the transistor 2 of the capacitance 1. The capacitance 4 is charged by turning on the transistor 3, 4 and connecting to power supply VCC at charging, then a voltage of the capacitance 4 is applied to the capacitance 1, by turning on the transistors 2, 5 and connecting to the power supply VCC, and the transistors 2, 3 are turned on at discharging of the capacitance 1. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a booster circuit, and more particularly to a discharge method thereof.

  Usually, the booster circuit is composed of four transistors and two capacitors when performing a double boosting of the boost reference voltage VCI having a lower potential than the power supply VCC generated by a regulator or the like from the power supply VCC and the ground VSS, for example. A desired voltage is generated by a charge pump operation based on a given clock.

  The configuration of FIG. 2, which is a prior art booster circuit that generates a voltage (Vout) that is twice the boost reference voltage VCI, will be described below.

  The P-channel transistor 5 has a source connected to the boosted reference voltage VCI, a drain connected to the drain of the N-channel transistor 6 and one end of the capacitor 4, and the gate shown in FIG. Yes.

  The N-channel transistor 6 has a source connected to the ground VSS, a drain connected to the drain of the P-channel transistor 5 and one end of the capacitor 4, and a signal B in FIG. 3 is input to the gate.

  The P-channel transistor 3 has a drain connected to the boost reference voltage VCI, a source connected to the drain of the P-channel transistor 2 and the other end of the capacitor 4, and a gate to which the signal C in FIG. 3 is input. ing.

  The P-channel transistor 2 has a source connected to one end of the capacitor 1, a drain connected to the source of the P-channel transistor 3 and the other end of the capacitor 4, and a signal D in FIG. 3 is input to the gate. ing.

  One end of the capacitor 4 is connected to the drain of the P channel transistor 5 and the drain of the N channel transistor 6, and the other end is connected to the source of the P channel transistor 3 and the drain of the P channel transistor 2.

  The other end of the capacitor 1 is connected to the ground VSS, and one end is connected to the source of the P-channel transistor 2. As a result, a voltage (Vout) that is twice the boost reference voltage VCI is output at this location. The capacitor 1 has a role of holding a voltage (Vout) that is twice the boost reference voltage VCI.

  2 will be described below with reference to FIGS. 4 and 5 which are equivalent circuits of FIG. 2, with respect to the operation when the booster circuit shown in FIG. 2 generates a voltage (Vout) twice the boost reference voltage VCI. explain.

  In the booster circuit shown in FIG. 2, the signal shown in FIG. 3 is inputted to the P-channel transistor 5, the N-channel transistor 6, the P-channel transistor 3, and the P-channel transistor 2, which are four transistors constituting the booster circuit. Thus, it is possible to generate a voltage (Vout) twice the boost reference voltage VCI in the capacitor 1.

  First, as in the equivalent circuit of FIG. 4, the switch S6 and the switch S3 are turned on, and the switch S5 and the switch S2 are turned off. In this state, the boosted reference voltage VCI is stored in the capacitor 4.

  Next, as in the equivalent circuit of FIG. 5, the switch S5 and the switch S2 are turned on, and the switch S6 and the switch S3 are turned off. In this state, the capacitor 4 and the capacitor 1 are connected, and the charge stored in the capacitor 4 is charged into the capacitor 1. At this time, since the potential at one end of the capacitor 4 is the boost reference voltage VCI, the potential of the capacitor 1 is raised.

  By repeating the operations of FIG. 4 and FIG. 5, a voltage (Vout) twice the boost reference voltage VCI is generated in the capacitor 1.

  Next, a method for discharging the booster circuit shown in FIG. 2 for performing the double boosting of the boost reference voltage VCI according to the prior art will be described with reference to the drawings.

  To discharge the booster circuit shown in FIG. 2, signal inputs to the gates of the four transistors shown in FIG. 2 are fixed, the P-channel transistor 5 is turned off, the N-channel transistor 6 is turned on, and the P-channel transistor 3 is turned on. The P channel transistor 2 is turned on. By doing so, a voltage (Vout) twice the boosted reference voltage VCI stored in the capacitor 1 is discharged to the boosted reference voltage VCI via the P-channel transistor 2 and the P-channel transistor 3.

At this time, the gate signal for operating the P-channel transistor 2 and the P-channel transistor 3 is a voltage (Vout) twice the boost reference voltage VCI generated by the self-boosting circuit. Transistor 2 and P-channel transistor 3 can no longer exceed the threshold and will not operate. However, in the steps so far, discharge can be instantaneously performed up to the voltage corresponding to the respective threshold values of the P-channel transistor 2 and the P-channel transistor 3 rather than the boost reference voltage VCI. Thereafter, the voltage remaining in the capacitor 1 can be discharged by free discharge of the capacitor 1.
JP-A-6-327236

  The capacitor 1 of the booster circuit shown in FIG. 2 is connected to the boost reference voltage VCI via the P-channel transistor 2 and the P-channel transistor 3. For this reason, when discharging is performed, charges corresponding to the threshold values of the P channel transistor 2 and the P channel transistor 3 remain, and in order to completely discharge the voltage twice the stored boost reference voltage VCI, the capacitor 1 Rely on free discharge. For this reason, it is difficult to completely discharge the capacitor 1 of the booster circuit within a certain period.

  Further, if the charge remains in the capacitor 1 after the discharge, when starting up the voltage of the booster circuit, there is a possibility of a start-up failure due to the charge that could not be completely discharged at the previous start-up. There was a problem.

  SUMMARY OF THE INVENTION The present invention solves the above-described problems of the prior art, and an object of the present invention is to provide a booster circuit that can be discharged in a certain period and can operate stably.

  In order to solve the above-described problem, a booster circuit according to the present invention includes a boosting target capacitor for accumulating charges corresponding to a supplied voltage, and a control switch element connected to the boosting target capacitor. A boost voltage generating means for supplying a voltage to the boost target capacitor via the switch element; and a first discharge means for discharging the charge accumulated in the boost target capacitor via the control switch element. The generating means is a booster circuit that generates a desired voltage by a charge pump operation based on a given clock, and is connected to the boosting target capacitor to discharge the charge accumulated in the boosting target capacitor. It has the discharge means.

  In the above configuration, the boost voltage generating means includes a voltage application capacitor connected to the boost target capacitor via the control switch element, and a first switch element connected to the control switch element side of the voltage application capacitor. The voltage application capacitor can be charged by being turned on when the first switch element is turned on while the control switch element is turned off and connected to the opposite side of the voltage application capacitor with the first switch element. The second switch element to be connected to the second switch element side of the voltage application capacitor, and the voltage application capacitor via the control switch element when the first switch element and the second switch element are off. And a third switch element that allows the voltage stored in the capacitor to be applied to the boosting target capacitor, and the first discharge means includes a control switch element and a first switch element. It is intended.

  In the above configuration, the second discharge means includes, for example, a resistor or a transistor.

  The boost voltage generating means includes, for example, a voltage application capacitor connected to the boost target capacitor via the control switch element, and a first switch element connected to the control switch element side of the voltage application capacitor. The voltage application capacitor can be charged by being turned on when the first switch element is turned on while the control switch element is turned off and connected to the opposite side of the voltage application capacitor with the first switch element. The second switch element to be connected to the second switch element side of the voltage application capacitor, and the voltage application capacitor via the control switch element when the first switch element and the second switch element are off. And a third switch element that allows the voltage stored in the capacitor to be applied to the boosting target capacitor, and the first discharge means includes the control switch element and the first switch element.

  Here, the first switch element is a P-channel transistor having a drain connected to the reference voltage supply line and a source connected to a connection point between one electrode of the voltage application capacitor and the control switch, The switch element is an N-channel transistor having a source connected to the ground and a drain connected to the other electrode of the voltage application capacitor. The third switch element has a source connected to the reference voltage supply line and a drain. Is a P-channel transistor connected to the other electrode of the voltage application capacitor, and the second discharge means includes a resistor provided between one end of the boost target capacitor and the ground, and for a predetermined period, By fixing the reference voltage supply line to the ground potential and turning on the control switch element and the first switch element, the first discharge is performed. Via a step and second discharge means, it is preferable to discharge the charge stored in the capacitor boosting a subject. In this booster circuit, the ground potential is supplied to the gate of the first switch element in a predetermined period, and the reference voltage supply line is supplied to the gates of the second switch element and the third switch element in a period other than the predetermined period. Is supplied with a booster circuit operating voltage having a higher potential than the reference voltage supplied from.

  The first switch element is a P-channel transistor having a drain connected to the reference voltage supply line and a source connected to a connection point between one electrode of the voltage application capacitor and the control switch. The switch element is an N-channel transistor having a source connected to the ground and a drain connected to the other electrode of the voltage application capacitor. A third switch element has a source connected to the reference voltage supply line and a drain connected to the other electrode. A P-channel transistor connected to the other electrode of the voltage application capacitor, wherein the second discharge means includes a discharge N-channel transistor provided between one end of the boost target capacitor and the ground, for a predetermined period In this case, the reference voltage supply line is fixed to the ground potential, and the control switch element, the first switch element, By the N-channel transistors for the charge on, via the first discharge means and second discharge means, it is preferable to discharge the charge stored in the capacitor boosting a subject. In this booster circuit, the ground potential is supplied to the gate of the first switch element in a predetermined period, and the gates of the second switch element, the third switch element, and the discharge N-channel transistor are in a predetermined period. In other cases, a booster circuit operating voltage having a higher potential than the reference voltage supplied from the reference voltage supply line is supplied.

  The first switch element is an N-channel transistor having a drain connected to the ground and a source connected to a connection point between one electrode of the voltage application capacitor and the control switch, and the second switch element , A P-channel transistor having a source connected to the reference voltage supply line and a drain connected to the other electrode of the voltage application capacitor. The third switch element has a source connected to the ground and a drain applied to the voltage application. An N-channel transistor connected to the other electrode of the capacitor, wherein the second discharge means includes a resistor provided between one end of the boost target capacitor and the ground, and for a predetermined period, a reference voltage supply line Is fixed to the ground potential and the control switch element and the first switch element are turned on, so that the first discharge means and Via the second discharge means, it is preferable to discharge the charge stored in the capacitor boosting a subject. In this booster circuit, the ground potential is supplied to the gate of the first switch element in a predetermined period, and the reference voltage supply line is supplied to the gates of the second switch element and the third switch element in a period other than the predetermined period. Is supplied with a booster circuit operating voltage having a higher potential than the reference voltage supplied from.

  The first switch element is an N-channel transistor having a drain connected to the ground and a source connected to a connection point between one electrode of the voltage application capacitor and the control switch, and the second switch element , A P-channel transistor having a source connected to the reference voltage supply line and a drain connected to the other electrode of the voltage application capacitor. The third switch element has a source connected to the ground and a drain applied to the voltage application. An N-channel transistor connected to the other electrode of the capacitor, wherein the second discharge means includes a discharge N-channel transistor provided between one end of the boost target capacitor and the ground, and for a predetermined period, The reference voltage supply line is fixed to the ground potential, the control switch element, the first switch element, and the disc By turning on the over-di for N-channel transistor, through the first discharge means and second discharge means, it is preferable to discharge the charge stored in the capacitor boosting a subject. In this booster circuit, the ground potential is supplied to the gate of the first switch element in a predetermined period, and the gates of the second switch element, the third switch element, and the discharge N-channel transistor are in a predetermined period. In other cases, a booster circuit operating voltage having a higher potential than the reference voltage supplied from the reference voltage supply line is supplied.

  According to the booster circuit of the present invention, since the boosting target capacitor has a resistor or transistor for the purpose of discharging, it is possible to discharge in a certain period with a time constant between the capacitor and the resistor or transistor.

  As a result, it is possible to completely discharge the electric charge accumulated in the boosting target capacitor during a certain period, and it is possible to stably start up the power source every time the booster circuit is activated.

  Hereinafter, a booster circuit according to an embodiment of the present invention will be described with reference to the drawings.

(Embodiment 1)
FIG. 1 is a diagram illustrating a booster circuit according to the first embodiment. As shown in FIG. 1, the booster circuit according to the first embodiment is provided with a discharge resistor 7 for discharge purpose in the prior art booster circuit.

  The configuration of the booster circuit according to the first embodiment is shown below.

  The P-channel transistor 5 (third switch) has a source connected to the boost reference voltage VCI, a drain connected to the drain of the N-channel transistor 6 and one end of the capacitor 4, and a gate connected to A in FIG. Signal is being input.

  The N-channel transistor 6 (second switch) has a source connected to the ground VSS, a drain connected to the drain of the P-channel transistor 5 and one end of the capacitor 4, and a gate shown in FIG. Is entered.

  In the P-channel transistor 3 (first switch), the boosted reference voltage VCI is connected to the drain, the source is connected to the drain of the P-channel transistor 2 and the other end of the capacitor 4, and the gate is shown in FIG. C signal is input.

  The P-channel transistor 2 (control switch) has a source connected to one end of the capacitor 1, a drain connected to the source of the P-channel transistor 3 and the other end of the capacitor 4, and a gate connected to D in FIG. Signal is being input.

  One end of the capacitor 4 (voltage application capacitor) is connected to the drain of the P-channel transistor 5 and the drain of the N-channel transistor 6, and the other end is connected to the source of the P-channel transistor 3 and the drain of the P-channel transistor 2. Has been.

  The other end of the capacitor 1 (capacitor for boosting) is connected to the ground VSS, and one end is connected to the source of the P-channel transistor 2. As a result, a voltage (Vout) that is twice the boost reference voltage VCI is output at this location. The capacitor 1 has a role of holding a voltage (Vout) that is twice the boost reference voltage VCI.

  The above is the configuration of the booster circuit that generates a voltage (Vout) twice the boost reference voltage VCI of the prior art. The booster circuit of the first embodiment is different from the booster circuit of the prior art in the following configuration. .

  One end of the discharge resistor 7 is connected to the ground VSS, and the other end is connected to one end of the capacitor 1 and the source of the P-channel transistor 2.

  A method for discharging the booster circuit shown in FIG. 1 will be described below.

  As in the prior art booster circuit, signal inputs to the gates of the four transistors shown in FIG. 1 are fixed, the P-channel transistor 5 is turned off, the N-channel transistor 6 is turned on, the P-channel transistor 3 is turned on, and P The channel transistor 2 is turned on. The charge equivalent to twice the boost reference voltage VCI stored in the capacitor 1 is discharged to the boost reference voltage VCI via the P channel transistor 2 and the P channel transistor 3. Further, it is discharged to the ground VSS via the discharge resistor 7. Therefore, charges corresponding to the respective threshold values of the P-channel transistor 2 and the P-channel transistor 3, which was a problem of the prior art, do not remain, and can be completely discharged with the time constant of the capacitor 1 and the discharge resistor 7.

  Note that the boost reference voltage VCI at the time of discharge is fixed to the ground potential. By doing in this way, it becomes possible to perform discharge by both the first discharge means composed of the P channel transistor 2 and the P channel transistor 3 and the discharge resistor 7 as the second discharge means. Here, the voltage applied to the gates of the P-channel transistor 5 and the N-channel transistor 6 is supplied with the power supply voltage VCC having a higher potential than the voltage supplied to the boost reference voltage VCI except during discharge.

(Embodiment 2)
The same effect as described above can be obtained by replacing the discharge resistor 7 with a transistor. A booster circuit in the case where the discharge resistor 7 is replaced with a transistor will be described below with reference to FIG.

  FIG. 6 is a diagram illustrating the booster circuit according to the second embodiment. As shown in FIG. 6, the booster circuit according to the second embodiment is provided with a discharge N-channel transistor 8 for discharge purpose in the prior art booster circuit.

  The configuration of the booster circuit according to the second embodiment is shown below.

  The P-channel transistor 5 has a source connected to the boost reference voltage VCI, a drain connected to the drain of the N-channel transistor 6 and one end of the capacitor 4, and a signal A in FIG. 7 is input to the gate. Yes.

  The N-channel transistor 6 has a source connected to the ground VSS, a drain connected to the drain of the P-channel transistor 5 and one end of the capacitor 4, and a gate to which the signal B in FIG. 7 is input.

  The P-channel transistor 3 has a drain connected to the boost reference voltage VCI, a source connected to the drain of the P-channel transistor 2 and the other end of the capacitor 4, and a gate to which the signal C in FIG. 7 is input. ing.

  The P-channel transistor 2 has a source connected to one end of the capacitor 1, a drain connected to the source of the P-channel transistor 3 and the other end of the capacitor 4, and a signal D in FIG. 7 is input to the gate. ing.

  One end of the capacitor 4 is connected to the connection point between the drain of the P-channel transistor 5 and the drain of the N-channel transistor 6, and the other end is connected to the connection point between the source of the P-channel transistor 3 and the drain of the P-channel transistor 2. Yes.

  The other end of the capacitor 1 is connected to the ground VSS, and one end is connected to the source of the P-channel transistor 2. As a result, a voltage (Vout) that is twice the boost reference voltage VCI is output at this location. The capacitor 1 has a role of holding a voltage (Vout) that is twice the boost reference voltage VCI.

  The N-channel transistor 8 has a source connected to the ground VSS, a drain connected to the connection point between the source of the P-channel transistor 2 and the capacitor 1, and a signal E in FIG. 7 is input to the gate. ing.

  A method for discharging the booster circuit shown in FIG. 6 will be described below.

  As in the configuration shown in FIG. 1, the signal input to the gates of the P-channel transistors 5, 3, 2, and N-channel transistor 6 is fixed, the P-channel transistor 5 is turned off, and the N-channel transistor 6 is turned on. The P channel transistor 3 is turned on, the P channel transistor 2 is turned on, and the N channel transistor 8 is turned on. Charges twice the boost reference voltage VCI stored in the capacitor 1 are discharged to the boost reference voltage VCI (fixed to the potential of the ground VSS) via the P-channel transistor 2 and the N-channel transistor 3. Further, it is also discharged to the ground VSS via the N channel transistor 8. Therefore, the charges corresponding to the respective threshold values of the P-channel transistor 2 and the P-channel transistor 3, which were the problems of the prior art, do not remain and can be completely discharged.

(Embodiment 3)
In the above description, the booster circuit that performs double boosting of the boost reference voltage VCI has been described. However, the same effect as described above can be obtained even in the case of a negative booster circuit. A negative booster circuit that boosts the voltage by -1 will be described below with reference to FIG.

  FIG. 8 is a diagram illustrating a −1 × booster circuit according to the third embodiment. As shown in FIG. 8, the booster circuit according to the third embodiment is provided with a discharge resistor 15 for the purpose of discharging in a booster circuit that is −1 times the prior art.

  The configuration of the booster circuit according to the third embodiment is shown below.

  The P-channel transistor 13 has a source connected to the boosted reference voltage VCI, a drain connected to the drain of the N-channel transistor 14 and one end of the capacitor 12, and the gate shown in FIG. Yes.

  The N-channel transistor 14 has the source connected to the ground VSS, the drain connected to the drain of the P-channel transistor 13 and one end of the capacitor 12, and the gate receives the signal B in FIG.

  The N-channel transistor 11 has a drain connected to the ground VSS, a source connected to the drain of the N-channel transistor 10 and the other end of the capacitor 12, and a gate to which the signal C in FIG. 9 is input. .

  The N-channel transistor 10 has a source connected to one end of the capacitor 9, a drain connected to the source of the N-channel transistor 11 and the other end of the capacitor 12, and a signal D in FIG. 9 is input to the gate. ing.

  One end of the capacitor 12 is connected to the drain of the P-channel transistor 13 and the drain of the N-channel transistor 14, and the other end is connected to the source of the N-channel transistor 11 and the drain of the N-channel transistor 10.

  The other end of the capacitor 9 is connected to the ground VSS, and one end is connected to the source of the N-channel transistor 10. As a result, a voltage (Vout) that is −1 times the boost reference voltage VCI is output at this location. The capacitor 1 has a role of holding a voltage (Vout) that is -1 times the boost reference voltage VCI.

  One end of the discharge resistor 15 is connected to the ground VSS, and the other end is connected to a connection point between one end of the capacitor 9 and the source of the N-channel transistor 10.

  The operation when the booster circuit having the above-described configuration shown in FIG. 8 generates a voltage (Vout) that is −1 times the boost reference voltage VCI will be described below.

  In the booster circuit shown in FIG. 8, the signal shown in FIG. 9 is inputted to the P-channel transistor 13, the N-channel transistor 14, the N-channel transistor 11 and the N-channel transistor 10 which are four transistors constituting the booster circuit. Thus, a voltage (Vout) that is −1 times the boost reference voltage VCI can be generated in the capacitor 9.

  First, the P channel transistor 13 and the N channel transistor 11 are turned on, and the N channel transistor 14 and the N channel transistor 10 are turned off. In this state, the boosted reference voltage VCI is stored in the capacitor 12.

  Next, the N channel transistor 14 and the N channel transistor 10 are turned on, and the P channel transistor 13 and the N channel transistor 11 are turned off. In this state, the capacitor 12 and the capacitor 9 are connected, and the capacitor 9 is charged with the electric charge stored in the capacitor 12. At this time, since the potential at one end of the capacitor 12 is the boost reference voltage VSS, the potential of the capacitor 9 becomes a negative value.

  By repeating the above operation, a voltage (Vout) that is −1 times the reference power supply VCI is generated in the capacitor 9.

  Next, a method for discharging the booster circuit shown in FIG. 8 will be described below.

  First, the P channel transistor 13 shown in FIG. 8 is turned off, the N channel transistor 14 is turned on, the N channel transistor 11 is turned on, and the N channel transistor 10 is turned on. As a result, the charge of −1 times the boosted reference voltage VCI stored in the capacitor 9 is discharged to the ground VSS via the N-channel transistor 10 and the N-channel transistor 11. Further, it is discharged to the ground VSS via the discharge resistor 15. Therefore, the charges corresponding to the threshold values of the N-channel transistor 10 and the N-channel transistor 11, which were the problems of the prior art, do not remain, and can be completely discharged with the time constant of the capacitor 9 and the discharge resistor 7.

(Embodiment 4)
The same effect can be obtained by replacing the discharge resistor 15 with a transistor in a negative booster circuit as well as a booster circuit that boosts the boosted reference voltage VCI twice. Hereinafter, a −1 × booster circuit which is a negative booster circuit when the discharge resistor 15 is replaced with a transistor will be described with reference to FIG.

  FIG. 10 is a diagram illustrating the booster circuit according to the fourth embodiment. As shown in FIG. 10, the booster circuit according to the fourth embodiment is provided with a discharge N-channel transistor 16 for discharge purpose in the prior art booster circuit.

  The configuration of the booster circuit according to the fourth embodiment is shown below.

  The P-channel transistor 13 has a source connected to the boosted reference voltage VCI, a drain connected to the drain of the N-channel transistor 14 and one end of the capacitor 12, and a gate to which the signal A in FIG. 11 is input. Yes.

  The N-channel transistor 14 has the source connected to the ground VSS, the drain connected to the drain of the P-channel transistor 13 and one end of the capacitor 12, and the gate receives the signal B in FIG.

  The N-channel transistor 11 has a drain connected to the ground VSS, a source connected to the drain of the N-channel transistor 10 and the other end of the capacitor 12, and a gate to which the signal C in FIG. 11 is input. .

  The N-channel transistor 10 has a source connected to one end of the capacitor 9, a drain connected to the source of the N-channel transistor 11 and the other end of the capacitor 12, and a signal D in FIG. 11 is input to the gate. ing.

  One end of the capacitor 12 is connected to the drain of the P-channel transistor 13 and the drain of the N-channel transistor 14, and the other end is connected to the source of the N-channel transistor 11 and the drain of the N-channel transistor 10.

  The other end of the capacitor 9 is connected to the ground VSS, and one end is connected to the source of the N-channel transistor 10. As a result, a voltage (Vout) that is −1 times the boost reference voltage VCI is output at this location. The capacitor 9 has a role of holding a voltage (Vout) that is -1 times the boost reference voltage VCI.

  The above is a configuration of a booster circuit that generates a voltage (Vout) that is −1 times the boost reference voltage VCI according to the prior art. The booster circuit according to the fourth embodiment has the following configuration as the booster circuit of the prior art. Different.

  The N-channel transistor 16 has a source connected to the ground VSS, a drain connected to the source of the N-channel transistor 10 and one end of the capacitor 1, and a gate to which the signal E in FIG.

  A method for discharging the booster circuit shown in FIG. 10 will be described below.

  First, the signal input to the gate to the P channel transistor 13, the N channel transistor 14, the N channel transistor 11, and the N channel transistor 10 is fixed, the P channel transistor 13 is turned off, the N channel transistor 14 is turned on, and the N channel The transistor 11 is turned on, the N channel transistor 10 is turned on, and the N channel transistor 16 is turned on. The charge corresponding to −1 times the boosted reference voltage VCI stored in the capacitor 9 is discharged to the ground VSS via the N-channel transistor 10 and the N-channel transistor 11. Further, since the ground VSS is also discharged through the N-channel transistor 16, the charges corresponding to the respective threshold values of the N-channel transistor 10 and the N-channel transistor 11 which are the problems of the prior art do not remain, and are completely Discharge is possible.

  As described above, since complete discharge within a certain period is possible, there is no influence at the next start-up, which is a problem in the prior art booster circuit.

  In the above-described embodiment, the booster circuit that boosts the boosted reference voltage VCI twice and the negative booster circuit that boosts the boosted reference voltage VCI by -1 times have been described. Even in the case of a circuit, complete discharge within a certain period as described above is possible, and similarly, there is no influence at the next start-up.

  In addition, as the switch in the description of the above embodiment, a MOS transistor, a bipolar transistor, or the like is known. However, the switch is not limited thereto, and any element having a switching function may be used.

  The booster circuit according to the present invention is useful as a booster circuit and the like because it can be discharged for a certain period of time and has a stable operation.

FIG. 3 is a circuit diagram of a double boosting circuit for boosting reference voltage VCI according to the first embodiment of the present invention. It is a circuit diagram of a prior art booster circuit. It is a wave form diagram of the signal to the gate of four transistors of the booster circuit of a prior art and the booster circuit of Embodiment 1 of this invention. FIG. 6 is a circuit diagram of an equivalent circuit of a prior art booster circuit in which switches S3 and S6 are on. FIG. 6 is an equivalent circuit diagram of a prior art booster circuit in which switches S2 and S5 are on. FIG. 10 is a double boost circuit diagram of a boost reference voltage VCI according to the second embodiment of the present invention. FIG. 7 is a waveform diagram of signals to the gates of four transistors in the booster circuit according to the second embodiment in FIG. 6. FIG. 10 is a circuit diagram for boosting a reference voltage VCI by -1 times according to a third embodiment of the present invention. It is a wave form diagram of the signal to the gate of four transistors of the booster circuit in Embodiment 3 of FIG. FIG. 10 is a circuit diagram for boosting a reference voltage VCI by −1 times according to a fourth embodiment of the present invention. It is a wave form diagram of the signal to the gate of four transistors of the booster circuit in Embodiment 4 of FIG.

Explanation of symbols

VCC power supply voltage VSS ground voltage 1 capacitance 2 P-channel transistor 3 P-channel transistor 4 capacitance 5 P-channel transistor 6 N-channel transistor 7 resistor S2 switch (equivalent circuit of P-channel transistor 2)
S3 switch (Equivalent circuit of P-channel transistor 3)
S5 switch (equivalent circuit of P-channel transistor 5)
S6 switch (equivalent circuit of N-channel transistor 6)

Claims (12)

A boosting target capacitor for accumulating charges corresponding to the supplied voltage; and a control switch element connected to the boosting target capacitor, and a voltage is supplied to the boosting target capacitor via the control switch element. Boosting voltage generating means for supplying, and first discharging means for discharging the charge accumulated in the boosting target capacitor via the control switch element,
The boosting voltage generating means is a boosting circuit that generates a desired voltage by a charge pump operation based on a given clock,
A booster circuit having second discharge means connected to the boosting target capacitor for discharging the charge accumulated in the boosting target capacitor.   2. The booster circuit according to claim 1, wherein the second discharge means includes a resistor.   2. The booster circuit according to claim 1, wherein the second discharge means includes a transistor. The boost voltage generating means includes a voltage application capacitor connected to the boost target capacitor via the control switch element, and a first switch connected to the control switch element side of the voltage application capacitor And the voltage applied by being turned on when the first switch element is on while the control switch element is off and connected to the opposite side of the voltage application capacitor to the first switch element. A second switch element that enables charging of the application capacitor; and the first switch element and the second switch element that are connected to the second switch element side of the voltage application capacitor and are off. A third switch element that enables application of the voltage stored in the voltage application capacitor via the control switch element to the boost target capacitor;
2. The booster circuit according to claim 1, wherein the first discharge means includes the control switch element and the first switch element. The first switch element is a P-channel transistor having a drain connected to a reference voltage supply line and a source connected to a connection point between one electrode of the voltage application capacitor and the control switch, The second switch element is an N-channel transistor having a source connected to the ground and a drain connected to the other electrode of the voltage application capacitor. The third switch element has a source connected to the reference voltage supply line. A P-channel transistor having a drain connected to the other electrode of the voltage application capacitor,
The second discharge means includes a resistor provided between one end of the boosting target capacitor and the ground;
In a predetermined period, the reference voltage supply line is fixed to the ground potential, and the control switch element and the first switch element are turned on, so that the first discharge means and the second discharge element are turned on. 5. The booster circuit according to claim 4, wherein the charge accumulated in the boosting target capacitor is discharged via a discharge means.   In the predetermined period, the ground potential is supplied to the gate of the first switch element, and the reference voltage is applied to the gates of the second switch element and the third switch element in a period other than the predetermined period. 6. The booster circuit according to claim 5, wherein a booster circuit operating voltage having a higher potential than a reference voltage supplied from a supply line is supplied. The first switch element is a P-channel transistor having a drain connected to a reference voltage supply line and a source connected to a connection point between one electrode of the voltage application capacitor and the control switch, The second switch element is an N-channel transistor having a source connected to the ground and a drain connected to the other electrode of the voltage application capacitor. The third switch element has a source connected to the reference voltage supply line. A P-channel transistor having a drain connected to the other electrode of the voltage application capacitor,
The second discharge means includes a discharge N-channel transistor provided between one end of the boosting target capacitor and the ground;
In a predetermined period, the reference voltage supply line is fixed to the ground potential, and the control switch element, the first switch element, and the discharge N-channel transistor are turned on, so that the first 5. The booster circuit according to claim 4, wherein the charge accumulated in the boosting target capacitor is discharged via the discharge means and the second discharge means.   In the predetermined period, the ground potential is supplied to the gate of the first switch element, and the predetermined potential is supplied to the gates of the second switch element, the third switch element, and the discharge N-channel transistor. 8. The booster circuit according to claim 7, wherein a booster circuit operating voltage having a higher potential than the reference voltage supplied from the reference voltage supply line is supplied during a period other than the above period. The first switch element is an N-channel transistor having a drain connected to the ground and a source connected to a connection point between one electrode of the voltage application capacitor and the control switch, and the second switch The element is a P-channel transistor having a source connected to a reference voltage supply line and a drain connected to the other electrode of the voltage application capacitor, and the third switch element has a source connected to the ground, An N-channel transistor having a drain connected to the other electrode of the voltage application capacitor;
The second discharge means includes a resistor provided between one end of the boosting target capacitor and the ground;
In a predetermined period, the reference voltage supply line is fixed to the ground potential, and the control switch element and the first switch element are turned on, so that the first discharge means and the second discharge element are turned on. 5. The booster circuit according to claim 4, wherein the charge accumulated in the boosting target capacitor is discharged via a discharge means.   In the predetermined period, the ground potential is supplied to the gate of the first switch element, and the reference voltage is applied to the gates of the second switch element and the third switch element in a period other than the predetermined period. 10. The booster circuit according to claim 9, wherein a booster circuit operating voltage having a higher potential than a reference voltage supplied from a supply line is supplied. The first switch element is an N-channel transistor having a drain connected to the ground and a source connected to a connection point between one electrode of the voltage application capacitor and the control switch, and the second switch The element is a P-channel transistor having a source connected to a reference voltage supply line and a drain connected to the other electrode of the voltage application capacitor, and the third switch element has a source connected to the ground, An N-channel transistor having a drain connected to the other electrode of the voltage application capacitor;
The second discharge means includes a discharge N-channel transistor provided between one end of the boosting target capacitor and the ground;
In a predetermined period, the reference voltage supply line is fixed to the ground potential, and the control switch element, the first switch element, and the discharge N-channel transistor are turned on, so that the first 5. The booster circuit according to claim 4, wherein the charge accumulated in the boosting target capacitor is discharged via the discharge means and the second discharge means.   In the predetermined period, the ground potential is supplied to the gate of the first switch element, and the predetermined potential is supplied to the gates of the second switch element, the third switch element, and the discharge N-channel transistor. 12. The booster circuit according to claim 11, wherein a booster circuit operating voltage having a higher potential than the reference voltage supplied from the reference voltage supply line is supplied during a period other than the above period.

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