JP2005223250A - Semiconductor device, and its manufacturing and inspecting methods - Google Patents

Semiconductor device, and its manufacturing and inspecting methods Download PDF

Info

Publication number
JP2005223250A
JP2005223250A JP2004031947A JP2004031947A JP2005223250A JP 2005223250 A JP2005223250 A JP 2005223250A JP 2004031947 A JP2004031947 A JP 2004031947A JP 2004031947 A JP2004031947 A JP 2004031947A JP 2005223250 A JP2005223250 A JP 2005223250A
Authority
JP
Japan
Prior art keywords
semiconductor device
probe
semiconductor
inspection
external connection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2004031947A
Other languages
Japanese (ja)
Inventor
Kazuhiro Ishikawa
和弘 石川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2004031947A priority Critical patent/JP2005223250A/en
Publication of JP2005223250A publication Critical patent/JP2005223250A/en
Withdrawn legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
    • H01L2224/05089—Disposition of the additional element
    • H01L2224/05093—Disposition of the additional element of a plurality of vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
    • H01L2224/05089—Disposition of the additional element
    • H01L2224/05093—Disposition of the additional element of a plurality of vias
    • H01L2224/05096—Uniform arrangement, i.e. array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01023—Vanadium [V]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which is made to be miniaturized and reduced in size, in such a way that alloy formation is kept fully in connectivity which is suitable in reliability, for probe marks generated at probe inspection and Au bumps. <P>SOLUTION: In the semiconductor device, probing inspection is executed to a pad electrode 1 for external connection which consists of a metal layer, such as AL electrode which is formed on a plurality of semiconductor device 5 for inspecting the characteristics inspections of a plurality of semiconductor device formed on a semiconductor wafer. A groove 3 for probe inspection is formed in the pad electrode 1 for the external connection. Namely, AL waste, generated while grinding AL electrode pad surface, is of a structure which is prevented from being generated. Thus, the groove 3, formed in a pad electrode surface for the external connection can prevent generation of the AL waste, which is the cause of electrical reliability failure (short-circuit failure) which has been a big problem. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、トランジスターなどを構成する半導体素子上に電極パッドを形成させたパッドオンエレメント（ＰＯＥ）と称する半導体素子(ＰＯＥ半導体素子)に関するものであり、特に、ＰＯＥ半導体素子上の電極パッド部にプローブ針でプロービング検査する際に生じる半導体素子へのダメージの低減や、検査工程で発生するＡＬ屑の発生等を防止できる電極パッド構造をもつ半導体装置及びそのプローブ検査方法の提案に関するものである。また、このプローブ検査を通して得た半導体素子を用いて、従来のフリップチップ実装構造の半導体装置より、更なる超小型化と高機能化及び高い信頼性を実現することができることを目的とした小型半導体装置とその製造方法に関するものである。   The present invention relates to a semiconductor element (POE semiconductor element) called a pad-on-element (POE) in which an electrode pad is formed on a semiconductor element that constitutes a transistor or the like, and particularly to an electrode pad portion on the POE semiconductor element. The present invention relates to a proposal for a semiconductor device having an electrode pad structure that can reduce damage to a semiconductor element that occurs during probing inspection with a probe needle, and prevent generation of AL debris generated in an inspection process, and a probe inspection method thereof. In addition, by using the semiconductor element obtained through the probe inspection, a small semiconductor aiming to realize further miniaturization, higher functionality and higher reliability than a conventional flip chip mounting structure semiconductor device. The present invention relates to an apparatus and a manufacturing method thereof.

以下、図面を参照して従来のプローブ針による半導体素子特性を検査確認するプローブ検査の方法について説明する（特許文献１，２）。   Hereinafter, a conventional probe inspection method for inspecting and confirming semiconductor element characteristics using a probe needle will be described with reference to the drawings (Patent Documents 1 and 2).

図５は、従来の半導体素子５のデバイス特性を検査する際のプローブ検査方法の断面構図である。図５に示すように、従来のプローブテスト工程においては、半導体ウエハ１９上にある複数の半導体素子５に設けた複数のＡＬ電極パッド部１の表層面部に検査用プローブ針１２を、ＳｉＮ膜２に接することなくＡＬパッド部１に突き刺し、ＡＬパッド部１のＡＬ材を削りながら、前記ＡＬ電極パッド１とプローブ針１２とが電気的に接触しているものである。この際、前記ＡＬ電極パッド部１の表層面上に必ずＡＬ屑１４が残存する構造である。また、プローブ荷重条件が厳しくなると、前記ＡＬ電極パッド部１の直下にあるトランジスター部１５や層間膜部１６にクラック１７が発生する危険を有した構造であった。
特開昭６２−８５４３９号公報 特開平０２−２１２７８４号公報 FIG. 5 is a cross-sectional composition of a probe inspection method when inspecting device characteristics of a conventional semiconductor element 5. As shown in FIG. 5, in the conventional probe test process, the inspection probe needles 12 are placed on the surface layer portions of the plurality of AL electrode pad portions 1 provided on the plurality of semiconductor elements 5 on the semiconductor wafer 19, and the SiN film 2. The AL electrode pad 1 and the probe needle 12 are in electrical contact with each other while piercing the AL pad portion 1 without touching and scraping the AL material of the AL pad portion 1. At this time, the AL scraps 14 always remain on the surface of the AL electrode pad portion 1. Further, when the probe load condition becomes severe, the structure has a risk of generating cracks 17 in the transistor part 15 and the interlayer film part 16 immediately below the AL electrode pad part 1.
JP-A-62-85439 Japanese Patent Laid-Open No. 02-212784

しかしながら，従来の半導体装置の検査構造では、図５に示す前記ＡＬ電極パッド部１直下へのプローブ荷重が大きく負荷された状態で半導体素子５のデバイス特性を検査している。従来の検査方法においては、プローブ荷重が高くなると、ＡＬ電極パッド部１下の層間膜部１６へのクラック１７の発生やトランジスター部１５への悪影響が発生した。現状のプロービングの仕様条件においては、工程管理マージンが少ない領域で生産管理している状況である。   However, in the conventional inspection structure of a semiconductor device, the device characteristics of the semiconductor element 5 are inspected in a state where a probe load directly below the AL electrode pad portion 1 shown in FIG. In the conventional inspection method, when the probe load is increased, the crack 17 is generated in the interlayer film portion 16 below the AL electrode pad portion 1 and the transistor portion 15 is adversely affected. Under the current probing specification conditions, production is managed in an area where the process management margin is small.

また、図５に示しているプローブの検査方法においては、プローブ針１２でＡＬ電極パッド部１の表面を削る長さ（プローブ痕１８の長さ）が長くなる。また、削ったアルミ屑１４が積み上がりＡＬ電極パッド１の表面上にアルミ屑１４の山が発生する。これらの現象により、同一のＡＬ電極パッド部１にＡｕバンプ４を形成すると、前記ＡＬ電極パッド部１表面のＡＬ面とＡｕバンプ４との合金相の形成が不十分であり、ＡＬ−Ａｕ接続の接続強度や接続特性に大きな課題があった。つまり、同一のＡＬ電極バッド部１上にプローブ針１２によるプローブ検査（プローブ痕１８が付く）とＡｕバンプ４を形成することは技術的に困難な状況にあった。前記に示すＡＬ電極バッド部１の同一パッド面上へのプローブ痕１８とＡｕバンプ４の形成は、半導体装置の小型化において必要不可欠な技術課題であり、現在はプローブ検査用のＡＬ電極パッド部１とＡｕバンプ４を形成するもうひとつのＡＬパッド部１はそれぞれ、別々のＡＬ電極パッド部１を設けた構造を有している。そのため、半導体素子５は大きくなり、必然的に半導体装置も大きくなってしまうという大きな技術的課題があった。   Further, in the probe inspection method shown in FIG. 5, the length of the surface of the AL electrode pad portion 1 with the probe needle 12 (the length of the probe mark 18) is increased. Further, the scraped aluminum scrap 14 is piled up, and a pile of aluminum scrap 14 is generated on the surface of the AL electrode pad 1. Due to these phenomena, when the Au bump 4 is formed on the same AL electrode pad portion 1, the formation of the alloy phase between the AL surface of the AL electrode pad portion 1 surface and the Au bump 4 is insufficient, and the AL-Au connection There was a big problem in connection strength and connection characteristics. That is, it was technically difficult to form the probe inspection (with the probe mark 18) by the probe needle 12 and the Au bump 4 on the same AL electrode pad portion 1. The formation of the probe marks 18 and the Au bumps 4 on the same pad surface of the AL electrode pad portion 1 described above is an indispensable technical problem in miniaturization of a semiconductor device, and is currently an AL electrode pad portion for probe inspection. 1 and another AL pad portion 1 for forming the Au bump 4 have a structure in which separate AL electrode pad portions 1 are provided. For this reason, the semiconductor element 5 is large, and there is a large technical problem that the semiconductor device is necessarily large.

さらに、ＡＬ電極パッド部１の表面をプローブ針１２で削って発生するＡＬ屑１４の屑山の一部が、Ａｕバンプ４を打つことで、一部、ＡＬ屑１４がＡＬ電極パッド部１から剥がれ落ちるものもあった。この場合、電気的導通性を有するＡＬ屑１４の塊が、隣接パッド間にまたがりショート不良を発生させるなどの信頼性の面において、大きな課題が発生していた。   Further, a part of the scrap of the AL scrap 14 generated by cutting the surface of the AL electrode pad 1 with the probe needle 12 hits the Au bump 4, so that the AL scrap 14 is partially removed from the AL electrode pad 1. Some peeled off. In this case, a large problem has occurred in terms of reliability such that the lump of AL waste 14 having electrical continuity causes a short circuit failure between adjacent pads.

したがって、この発明の目的は、前記従来の半導体装置とその検査方法に関する技術課題を解決するもので、特に、半導体素子サイズに応じたプローブ長さの調整管理を可能にしたことにより、プローブ検査時に発生するプローブ痕とＡｕバンプとの合金形成が、信頼性上問題ない接続性を十分確保することで、小型化・縮小化した半導体素子及び半導体装置を提供する。また、プローブ検査によるＡＬ電極パッド直下にあるトランジスターの特性変動や、層間膜クラックの発生を大きく低減できる半導体装置及びそのプローブ検査方法を提供することである。   Accordingly, an object of the present invention is to solve the technical problems related to the conventional semiconductor device and its inspection method, and in particular, by enabling adjustment management of the probe length according to the semiconductor element size, The alloy formation between the generated probe mark and the Au bump ensures a sufficient connectivity with no problem in reliability, thereby providing a semiconductor element and a semiconductor device that are reduced in size and reduced in size. Another object of the present invention is to provide a semiconductor device and a probe inspection method thereof that can greatly reduce the characteristic fluctuation of the transistor directly under the AL electrode pad and the occurrence of interlayer film cracks due to the probe inspection.

前述の課題を解決するために本発明の半導体装置は、以下のような構成と検査方法を有している。すなわち、本発明は、素子上にパッド電極を有したＰＯＥ構造に関するものであり、特に、半導体素子のデバイス特性検査を行うプローブテスト工程において発生するプローブ針によるプローブ荷重により、ＡＬ電極パッド直下にあるトランジスターの特性変動や層間膜クラック（ダメージ）の発生を大きく低減させることができる半導体素子装置とそのデバイス特性検査方法に関するものである。   In order to solve the above-described problems, the semiconductor device of the present invention has the following configuration and inspection method. That is, the present invention relates to a POE structure having a pad electrode on an element, and in particular, is directly below an AL electrode pad due to a probe load by a probe needle generated in a probe test process for inspecting device characteristics of a semiconductor element. The present invention relates to a semiconductor element device capable of greatly reducing the occurrence of transistor characteristic fluctuations and interlayer film cracks (damage), and a device characteristic inspection method thereof.

本発明の半導体装置は以下の構成を有している。請求項１記載の半導体装置は、半導体ウエハ上に有する複数の半導体素子の特性検査を行うために、プロービング検査が前記複数の半導体素子上に形成されたＡＬ電極等の金属層からなる外部接続用パッド電極に対して行われる半導体装置であって、前記外部接続用パッド電極にプローブ検査用の溝を形成したことを特徴とする。すなわち、検査用プローブ針と、ＡＬ電極パッド面を削りながら発生するＡＬ屑の発生をなくすことができる構造である。このように、外部接続用パッド電極面に溝を形成することにより、大きな問題であった電気的信頼性不良（ショート不良）の原因であるＡＬ屑の発生を防止することができるものである。   The semiconductor device of the present invention has the following configuration. The semiconductor device according to claim 1, wherein the probing inspection is performed for external connection comprising a metal layer such as an AL electrode formed on the plurality of semiconductor elements in order to perform characteristic inspection of the plurality of semiconductor elements on the semiconductor wafer. A semiconductor device for a pad electrode, wherein a probe inspection groove is formed in the external connection pad electrode. That is, it is a structure that can eliminate the generation of AL scraps generated while the inspection probe needle and the AL electrode pad surface are cut. Thus, by forming a groove on the pad electrode surface for external connection, it is possible to prevent the generation of AL debris that is a cause of electrical reliability failure (short circuit failure), which was a major problem.

また、請求項２記載の半導体装置は、半導体素子のＡＬ電極パッド等の金属層からなる外部接続用パッド電極上に設けたプローブ検査用の溝は、検査用のプローブ針の形状に応じて、凹型、バスタブ型、またはＶ字型等の形状を有した構造が可能であり、従来の電気的なプローブ検査の実施が可能であるだけでなく、且つプロービング時に発生するアルミ屑が発生しない構造を有しており、パッド電極部の直下にあるトランジスターの特性変動や層間膜クラック（ダメージ）の発生を大きく低減させることができるものである。   Further, in the semiconductor device according to claim 2, the probe inspection groove provided on the external connection pad electrode made of a metal layer such as the AL electrode pad of the semiconductor element is formed according to the shape of the inspection probe needle. A structure having a concave shape, a bathtub shape, a V-shape, or the like is possible, and not only can a conventional electrical probe inspection be performed, but also a structure that does not generate aluminum dust generated during probing. Therefore, it is possible to greatly reduce the characteristic variation of the transistor directly under the pad electrode portion and the generation of an interlayer film crack (damage).

さらに、請求項３記載の半導体装置では、電極パッド（外部接続用パッド電極）上に設けたプローブ検査用の溝の長さは、電極パッドの開口径に応じて凹部の設計が可能である。実際の最大寸法では、電極パッドの周囲のナイトライド保護膜（ＳｉＮ）に接触しない領域まで凹溝の広がりが可能であり、最小の場合はプローブが凹部に入り込むばらつき範囲含めた位置に、プローブ針を凹型、バスタブ型、Ｖ字型等の凹部の溝を挿入することが可能な設計ができるものである。これにより多種多様なプローブ針の選択・対応が可能であり、またプローブ検査のプロービング位置精度も向上する。このことは、後に形成するＡｕバンプとＡＬ等の電極パッド部のプローブ痕に関わる問題であるＡｕ−Ａｌの合金面積を十分確保することができるものである。   Furthermore, in the semiconductor device according to the third aspect, the length of the groove for probe inspection provided on the electrode pad (pad electrode for external connection) can be designed as a recess according to the opening diameter of the electrode pad. In the actual maximum dimension, the groove can be extended to a region not in contact with the nitride protective film (SiN) around the electrode pad, and in the minimum case, the probe needle is located at a position including a variation range where the probe enters the recess. Can be designed to be able to insert a concave groove such as a concave shape, a bathtub shape, or a V-shape. As a result, a wide variety of probe needles can be selected and handled, and the probe inspection probing position accuracy is improved. This can sufficiently secure the alloy area of Au—Al, which is a problem relating to probe bumps of electrode bumps such as Au bumps to be formed later and AL.

以上説明したプロービング検査構造を有する本発明の半導体装置を用いることにより、請求項４、請求項５記載の小型半導体装置の実現化が可能になる。   By using the semiconductor device of the present invention having the probing inspection structure described above, the small semiconductor device according to claims 4 and 5 can be realized.

請求項４記載の半導体装置の製造方法は、請求項１，２または３記載の半導体装置を用意し、前記半導体素子上の外部接続用パッド電極にバンプを形成し、バンプ高さを均一に平坦化（レベリング）させる工程と、レベリング済みバンプに半田或いは導電性ペーストを転写させ、半導体キャリア基板上の表層面部にある複数の配線電極部にフリップチップ実装する工程と、前記半田或いは導電性ペーストを硬化させ、前記半導体素子と半導体キャリア基板の間にエポキシ系樹脂を注入硬化する工程とを含む。   According to a fourth aspect of the present invention, there is provided a semiconductor device manufacturing method comprising: preparing the semiconductor device according to the first, second, or third aspect; forming bumps on the external connection pad electrodes on the semiconductor element; Leveling bumps, transferring solder or conductive paste to leveled bumps, flip-chip mounting on a plurality of wiring electrode portions on the surface layer surface of the semiconductor carrier substrate, and solder or conductive paste Curing and injecting and curing an epoxy resin between the semiconductor element and the semiconductor carrier substrate.

請求項５記載の半導体装置の製造方法は、請求項１，２または３記載の半導体装置を用意し、前記半導体素子上の外部接続用パッド電極にバンプを形成する工程と、前記半導体素子を支持する半導体キャリア基板上に、シール状の樹脂を貼り付け、バンプ形成済みの前記半導体素子を反転させ、前記半導体キャリア基板上の複数の配線電極部に位置合わせ（アライメント）を行い、前記シール状のエポキシ系樹脂を介して熱圧着させ電気的接続を得る工程とを含む。   A method of manufacturing a semiconductor device according to claim 5, wherein the semiconductor device according to claim 1, 2 or 3 is prepared, a bump is formed on a pad electrode for external connection on the semiconductor element, and the semiconductor element is supported. A sealing resin is pasted on the semiconductor carrier substrate, the semiconductor element having the bump formed thereon is inverted, alignment is performed on a plurality of wiring electrode portions on the semiconductor carrier substrate, and the sealing-like resin is A step of thermocompression bonding via an epoxy resin to obtain electrical connection.

半導体素子上に設けた複数のＡＬ等の電極パッドに凹型、バスタブ型、Ｖ字型等の凹部の溝を設けたことにより、バンプ形成の位置精度が大きく向上することができる。また、ＡｕバンプとＡＬ電極パッド間のシェア強度等の接続信頼性も更に向上することができるものである。さらに、凹部にＡｕバンプを形成する構造を有していることから、半導体装置の薄型化にも寄与することができるものである。   Providing concave grooves such as concave, bathtub, and V-shaped grooves on a plurality of electrode pads such as AL provided on a semiconductor element can greatly improve the positional accuracy of bump formation. Further, the connection reliability such as the shear strength between the Au bump and the AL electrode pad can be further improved. Furthermore, since it has a structure in which Au bumps are formed in the recesses, it can also contribute to thinning of the semiconductor device.

請求項６記載の半導体装置の製造方法は、前記半導体素子上に形成された複数の外部接続用パッド電極に設けられたプローブ検査用の溝に、プローブ針の接触性や電気特性を良好にするため金属めっきをコーティング塗布する。   7. The method of manufacturing a semiconductor device according to claim 6, wherein the probe needle contactability and electrical characteristics are improved in the probe inspection grooves provided on the plurality of external connection pad electrodes formed on the semiconductor element. Therefore, metal plating is applied.

請求項７記載のプローブ検査方法に関しては、前記に説明したように、ウエハ内の半導体素子上に形成された複数のＡＬ等の金属電極パッド面上に設けられた凹型、バスタブ型またはＶ字型等の溝（プローブ検査用の針の形状に対応）に、プローブ針を挿入し、プローブ針を横方向に滑らせながら、且つ、凹型バスタブ型・Ｖ字型等の凹部のコーナ部で完全に静止させて、アルミ屑の発生を防止し、且つトランジスターを有するＡＬ等の金属電極パッド直下にのみプローブ荷重が負荷されず荷重分散できる設計を有することが可能である。このような構造と半導体素子のプローブ検査方法により、半導体素子へのダメージの大きな低減化や半導体装置の高い接続信頼性の実現化が図れるものである。また、プローブ検査時のプローブ痕領域の縮小が可能であることから、Ａｕ−Ｓｉ合金が十分確保できる。従って、検査用のプローブ痕形成パッド電極とＡｕバンプ形成パッドを別々に設けたパッド分離構造を不要とし、同一のパッド電極上に、プローブ検査後Ａｕバンプを形成することが可能となる。これにより、半導体素子だけでなく半導体装置の小型化・縮小化の実現化が図れるものである。   In the probe inspection method according to claim 7, as described above, a concave type, bathtub type or V-shaped type provided on the surface of a plurality of metal electrode pads such as AL formed on a semiconductor element in the wafer. Insert the probe needle into the groove (corresponding to the shape of the probe for probe inspection), slide the probe needle laterally, and completely at the corner of the concave part such as a concave bathtub type or V shape It is possible to have a design that can prevent the generation of aluminum scrap and can disperse the load without being loaded with the probe load only directly under the metal electrode pad such as AL having a transistor. Such a structure and a probe inspection method for a semiconductor element can greatly reduce damage to the semiconductor element and realize high connection reliability of the semiconductor device. In addition, since the probe mark region can be reduced during probe inspection, a sufficient Au—Si alloy can be secured. Therefore, the pad separation structure in which the probe trace forming pad electrode for inspection and the Au bump forming pad are separately provided is unnecessary, and the Au bump can be formed on the same pad electrode after the probe inspection. As a result, not only semiconductor elements but also semiconductor devices can be reduced in size and reduced.

以上のように本発明の半導体装置は、半導体素子へのダメージ（ＡＬ電極パッド直下にあるトランジスターの特性変動や、層間膜クラックの発生）を大きく低減させたプローブ検査の実現が可能であるだけでなく、製品の接続信頼性を低下させる原因のひとつであったＡＬ屑の多大な低減や防止ができる。   As described above, the semiconductor device of the present invention is only capable of realizing probe inspection with greatly reduced damage to semiconductor elements (changes in characteristics of transistors directly under the AL electrode pads and generation of interlayer film cracks). Therefore, it is possible to greatly reduce or prevent the AL scrap, which is one of the causes of reducing the connection reliability of the product.

また、プローブにより、ＡＬパッド電極部を削る際に発生するプローブ痕を大きく低減・防止できることから、ＡＬ−Ａｕ合金の形成が充分確保することができた。これにより、従来の分離パッド方式から同一のＡＬ電極パッド部上でＡｕバンプを形成することができ、半導体素子の小型化が実現できるものである。また、Ａｕバンプを形成するＡＬ電極部の中央は凹部であり、この領域にＡｕバンプを形成するため、半導体装置の薄型化も図ることができるものである。   In addition, since the probe can greatly reduce and prevent probe marks generated when the AL pad electrode portion is cut, the formation of the AL-Au alloy can be sufficiently ensured. As a result, Au bumps can be formed on the same AL electrode pad portion from the conventional separation pad method, and the semiconductor element can be miniaturized. Further, the center of the AL electrode portion where the Au bump is formed is a concave portion, and since the Au bump is formed in this region, the semiconductor device can be thinned.

前述のような構成とその製造方法により、本発明の半導体装置は，半導体素子へのダメージを大きく低減させたプローブ検査の実現が可能である。またＡＬ屑の防止やバンプ形成の位置精度の向上、ＡＬ−Ａｕ合金の形成が十分確保することが可能であることから、高い接続信頼性を確保することができる。されに、半導体素子の縮小化が可能であることから、高信頼性で且つ低コスト化もできる小型薄型化した半導体装置の実現が容易にできるものである。   With the configuration and the manufacturing method as described above, the semiconductor device of the present invention can realize probe inspection with greatly reduced damage to the semiconductor element. Further, since it is possible to prevent AL dust, improve the positional accuracy of bump formation, and sufficiently form an AL-Au alloy, high connection reliability can be ensured. In addition, since the semiconductor element can be reduced, it is possible to easily realize a small and thin semiconductor device that is highly reliable and can be reduced in cost.

以下、本発明の半導体装置及びその製造方法に関する第一の実施形態について図面を参照しながら説明する。まず本実施形態の半導体装置について説明する。図1と図２は、本実施形態の半導体装置を示す断面図である。   Hereinafter, a semiconductor device and a manufacturing method thereof according to a first embodiment of the present invention will be described with reference to the drawings. First, the semiconductor device of this embodiment will be described. 1 and 2 are cross-sectional views showing the semiconductor device of this embodiment.

まず、図１に示すように、表面のＡＬ電極パッド部（外部接続用パッド電極）１上に、レーザ光等による熱エネルギーでＡＬを溶解する方法、または、ＳｉＮ膜２と同時に前記ＡＬ電極部１の一部エッチング除去するドライエッチング法などで形成した凹型部のプローブ検査用溝３（ＡＬの凹み深さはエッチング時間で調整可能）に、Ａｕなどのバンプ４を形成した半導体素子５が、表面側を下にして、有機基板を絶縁基体とした多層回路基板である半導体キャリア６上の複数の配線電極７に圧着接合されている。半導体キャリア６の上面には、半導体素子５と導通するために複数の配線電極７が形成されており、配線電極７と半導体素子５上に形成されたＡｕバンプ４とが、導電性接着剤８とエポキシ系の液状封止樹脂９を介して電気的に接合されている。なお、半導体キャリア６は、その裏面に外部端子１０を有し、表層面の配線電極部７とは、半導体キャリア６内に形成されたビア１１により、内部接続されているものである。   First, as shown in FIG. 1, on the surface AL electrode pad portion (external connection pad electrode) 1, a method of dissolving AL with thermal energy by laser light or the like, or the AL electrode portion simultaneously with the SiN film 2 A semiconductor element 5 in which bumps 4 made of Au or the like are formed in a groove 3 for probe inspection of a concave portion formed by a dry etching method or the like for removing a part of 1 (the depth of depression of AL can be adjusted by etching time) With the front side facing down, it is pressure bonded to a plurality of wiring electrodes 7 on a semiconductor carrier 6 which is a multilayer circuit board using an organic substrate as an insulating base. A plurality of wiring electrodes 7 are formed on the upper surface of the semiconductor carrier 6 so as to be electrically connected to the semiconductor element 5. The wiring electrodes 7 and the Au bumps 4 formed on the semiconductor element 5 are connected to the conductive adhesive 8. And an epoxy-based liquid sealing resin 9. The semiconductor carrier 6 has an external terminal 10 on the back surface thereof, and is internally connected to the wiring electrode portion 7 on the surface layer surface by a via 11 formed in the semiconductor carrier 6.

また図２に、もう一つの半導体装置の実施形態を示す。図２に示すように、表面のＡＬ電極パッド部１上に、レーザ光等による熱エネルギーでＡＬを溶解する方法、または、ＳｉＮ膜２と同時にＡＬ電極部１の一部エッチング除去するドライエッチング法などで形成した凹型部のプローブ検査用溝２（ＡＬの凹み深さはエッチング時間で調整可能）に、Ａｕなどのバンプ４を形成した半導体素子５が、表面側を下にして、有機基板を絶縁基体とした多層回路基板である半導体キャリア６上の複数の配線電極７に圧着接合されている。半導体キャリア６の上面には、半導体素子５と導通するために複数の配線電極７が形成されており、配線電極７と半導体素子５上に形成されたＡｕバンプ４とが、エポキシ系の封止樹脂である封止シート材９−１を介して圧着接合されている。なお、半導体キャリア６は、その裏面に外部端子１０を有し、表層面の配線電極部７とは、半導体キャリア６内に形成されたビア１１により、内部接続されているものである。   FIG. 2 shows another embodiment of the semiconductor device. As shown in FIG. 2, the AL is dissolved on the surface of the AL electrode pad portion 1 by thermal energy using laser light or the like, or the dry etching method in which the AL electrode portion 1 is partially etched away simultaneously with the SiN film 2. A semiconductor element 5 in which bumps 4 made of Au or the like are formed in a probe inspection groove 2 (AL recess depth can be adjusted by etching time) formed in a concave portion, etc. A plurality of wiring electrodes 7 on a semiconductor carrier 6, which is a multilayer circuit board as an insulating base, are pressure bonded. A plurality of wiring electrodes 7 are formed on the upper surface of the semiconductor carrier 6 so as to be electrically connected to the semiconductor element 5. The wiring electrodes 7 and the Au bumps 4 formed on the semiconductor element 5 are sealed with epoxy. It is crimped and bonded via a sealing sheet material 9-1 that is a resin. The semiconductor carrier 6 has an external terminal 10 on the back surface thereof, and is internally connected to the wiring electrode portion 7 on the surface layer surface by a via 11 formed in the semiconductor carrier 6.

次に本実施形態の半導体装置の半導体素子プロービング検査方法について、以下図面を用いて説明する。図３（ａ）、（ｂ）、図４は、本実施形態のその一例を示すものであり、半導体素子の検査方法を示す断面図である。図３（ａ）、（ｂ）、図４に示すように、半導体素子５上に形成したＡＬ電極パッド部１上に、レーザ光等による熱エネルギーでＡＬを溶解する方法、または、ＳｉＮ膜２と同時にＡＬ電極部１の一部エッチング除去するドライエッチングの方法などで形成した凹型部のプローブ検査用溝３（ＡＬの凹み深さはエッチング時間で調整可能）に、検査用のプローブ針１２を挿入し、前記プローブ針１２と凹型部のプローブ検査用溝３とが電気的に接続されている。図３（ａ）は、前記３の溝は凹型であり、図３（ｂ）は、バスタブ型の溝形状を有している。また、図４には、Ｖ型の溝形状を有した構造である。これらの溝構造は、前記プローブ針１２、Ａｕバンプ４、と凹型部を有したプローブ検査用溝３との電気特性を向上させるためＡｕなどの金属メッキ１３を施すことも可能な設計である。また、凹部はあらかじめ故意にへこませた構造を有しているため、ＡＬ屑１４の発生を防止できるものである。さらに、従来のようにＡＬ電極パッド部１のＡＬ材を削らないため、ＡＬ電極部１の直下にあるトランジスター部１５や層間膜１６部への大きな応力負荷が発生しにくい構造であるため、前記トランジスター１５部の特性変動や層間膜部１６で発生するクラック１７を防止できるものである。また、本発明のＡＬ電極パッド部１上に形成した凹型部のプローブ検査用溝３の内部に、Ａｕバンプ４を形成することで、Ａｕバンプ４の形成位置精度を大きく向上できることから、ＡＬパッド電極部１から大きく外れたＡｕバンプ４を形成した不良品を完全に無くすることができるものである。さらに、ＡＬ電極部１が凹んだ構造部であるプローブ検査用溝３に、Ａｕバンプ４を形成するため、半導体装置の高さを低くできるので薄型化した半導体装置が実現できるものである。更に、プローブ針１２によるプローブ痕１８を大きく低減できることから、ＡｕとＡＬの合金相が充分確保できることから、プローブ痕１８上にＡｕバンプ４を形成することができるため、半導体素子５の寸法サイズが縮小化できる。これにより、半導体装置の薄型化だけでなく、小型化も実現できるものである。   Next, a semiconductor element probing inspection method for the semiconductor device of this embodiment will be described below with reference to the drawings. FIGS. 3A, 3B, and 4 show an example of the present embodiment and are cross-sectional views showing a semiconductor element inspection method. As shown in FIGS. 3A, 3B, and 4, a method of dissolving AL with thermal energy by laser light or the like on the AL electrode pad portion 1 formed on the semiconductor element 5, or the SiN film 2 At the same time, the probe needle 12 for inspection is inserted into the probe inspection groove 3 (the depth of the AL recess can be adjusted by the etching time) formed by a dry etching method that partially removes the AL electrode portion 1 by etching. The probe needle 12 and the concave probe inspection groove 3 are electrically connected. In FIG. 3A, the third groove is a concave shape, and FIG. 3B has a bathtub-shaped groove shape. FIG. 4 shows a structure having a V-shaped groove shape. These groove structures are designed so that a metal plating 13 such as Au can be applied to improve the electrical characteristics of the probe needle 12, the Au bump 4, and the probe inspection groove 3 having a concave portion. Further, since the recess has a structure that is intentionally recessed in advance, the generation of AL waste 14 can be prevented. Further, since the AL material of the AL electrode pad portion 1 is not cut as in the prior art, it is difficult to generate a large stress load on the transistor portion 15 and the interlayer film 16 portion immediately below the AL electrode portion 1. It is possible to prevent the characteristic variation of the transistor 15 part and the crack 17 generated in the interlayer film part 16. In addition, since the Au bump 4 is formed inside the concave probe inspection groove 3 formed on the AL electrode pad portion 1 of the present invention, the formation position accuracy of the Au bump 4 can be greatly improved. A defective product in which the Au bump 4 greatly deviated from the electrode portion 1 can be completely eliminated. Furthermore, since the Au bump 4 is formed in the probe inspection groove 3 which is a structure part where the AL electrode part 1 is recessed, the height of the semiconductor device can be reduced, so that a thinned semiconductor device can be realized. Furthermore, since the probe mark 18 by the probe needle 12 can be greatly reduced, and an alloy phase of Au and AL can be sufficiently secured, the Au bump 4 can be formed on the probe mark 18. Can be reduced. As a result, not only the semiconductor device can be made thinner, but also the size can be reduced.

本発明にかかる半導体装置およびその製造方法と検査方法は、半導体素子へのダメージ（ＡＬ電極パッド直下にあるトランジスターの特性変動や、層間膜クラックの発生）を大きく低減させたプローブ検査の実現が可能であるだけでなく、製品の接続信頼性を低下させる原因のひとつであったＡＬ屑の多大な低減や防止ができるという効果を有し、パッドオンエレメント（ＰＯＥ）と称する半導体素子(ＰＯＥ半導体素子)として有用である。   INDUSTRIAL APPLICABILITY The semiconductor device and the manufacturing method and inspection method thereof according to the present invention can realize probe inspection that greatly reduces damage to semiconductor elements (change in characteristics of transistors directly under the AL electrode pad and generation of interlayer film cracks). In addition, the semiconductor element (POE semiconductor element) referred to as a pad-on-element (POE) has the effect of being able to greatly reduce and prevent the AL scrap that was one of the causes of reducing the connection reliability of products. ) Is useful.

本発明の第一実施形態の半導体装置を示す断面図である。It is sectional drawing which shows the semiconductor device of 1st embodiment of this invention. 本発明の第二実施形態の半導体装置を示す断面図である。It is sectional drawing which shows the semiconductor device of 2nd embodiment of this invention. （ａ）は本発明のプロービング検査方法に関するＡＬ電極パッド溝構造の第一実施形態を示す断面図、（ｂ）は本発明のプロービング検査方法に関するＡＬ電極パッド溝構造の第二実施形態を示す断面図である。(A) is sectional drawing which shows 1st embodiment of AL electrode pad groove | channel structure regarding the probing inspection method of this invention, (b) is sectional drawing which shows 2nd embodiment of AL electrode pad groove | channel structure regarding the probing inspection method of this invention. FIG. 本発明のプロービング検査方法に関するＡＬ電極パッド溝構造の第三実施形態を示す断面図である。It is sectional drawing which shows 3rd embodiment of AL electrode pad groove | channel structure regarding the probing inspection method of this invention. （ａ）は半導体ウエハと半導体素子の説明図、（ｂ）は従来のプロービング検査方法を示す断面図である。(A) is explanatory drawing of a semiconductor wafer and a semiconductor element, (b) is sectional drawing which shows the conventional probing inspection method.

符号の説明Explanation of symbols

１ ＡＬ電極パッド部
２ ＳｉＮ膜（ナイトライド保護膜）
３ 凹型部のプローブ検査用溝
４ Ａｕバンプ
５ 半導体素子
６ 半導体キャリア
７ 半導体キャリア６の配線電極部
８ 導電性樹脂
９ エポキシ系の封止樹脂（液状）
9-1 エポキシ系の封止シート材
１０ 半導体キャリア６裏面の外部端子
１１ ビア
１２ プローブ針
１３ 金属メッキ等
１４ ＡＬ屑
１５ トランジスター部
１６ 層間膜部
１７ クラック
１８ プローブ痕
１９ 半導体ウエハ 1 AL electrode pad part 2 SiN film (nitride protective film)
DESCRIPTION OF SYMBOLS 3 Probe inspection groove | channel of concave part 4 Au bump 5 Semiconductor element 6 Semiconductor carrier 7 Wiring electrode part 8 of semiconductor carrier 6 Conductive resin 9 Epoxy sealing resin (liquid)
9-1 Epoxy encapsulating sheet material 10 External terminal 11 on the back surface of the semiconductor carrier 6 Via 12 Probe needle 13 Metal plating 14 AL scrap 15 Transistor portion 16 Interlayer film portion 17 Crack 18 Probe trace 19 Semiconductor wafer

Claims (7)

半導体ウエハ上に有する複数の半導体素子の特性検査を行うために、プロービング検査が前記複数の半導体素子上に形成された金属層からなる外部接続用パッド電極に対して行われる半導体装置であって、前記外部接続用パッド電極にプローブ検査用の溝を形成したことを特徴とする半導体装置。   A semiconductor device in which a probing inspection is performed on an external connection pad electrode made of a metal layer formed on the plurality of semiconductor elements in order to perform a characteristic inspection of the plurality of semiconductor elements included on the semiconductor wafer, A semiconductor device, wherein a probe inspection groove is formed in the external connection pad electrode. 前記プローブ検査用の溝は、検査用のプローブ針の形状に応じて、凹型、バスタブ型、またはＶ字型等の形状を有した構造であり、電気的なプローブ検査の実施が可能で、且つプロービング時に屑が発生しない構造を有している請求項１記載の半導体装置。   The probe inspection groove is a structure having a concave shape, a bathtub shape, a V-shape or the like according to the shape of the probe needle for inspection, and can be used for electrical probe inspection. The semiconductor device according to claim 1, wherein the semiconductor device has a structure in which debris is not generated during probing. 前記プローブ検査用の溝の長さは、外部接続用パッド電極の開口径に応じて異なり、最大寸法は、前記パッド電極の周囲の保護膜に接触しない領域まで広がった寸法であり、最小寸法は、プローブが溝にばらつきを持って入り込む寸法である請求項１または２記載の半導体装置。   The length of the probe inspection groove varies depending on the opening diameter of the pad electrode for external connection, and the maximum dimension is a dimension that extends to a region that does not contact the protective film around the pad electrode, and the minimum dimension is 3. The semiconductor device according to claim 1, wherein the probe has a dimension that enters the groove with variation. 請求項１，２または３記載の半導体装置を用意し、前記半導体素子上の外部接続用パッド電極にバンプを形成し、バンプ高さを均一に平坦化（レベリング）させる工程と、レベリング済みバンプに半田或いは導電性ペーストを転写させ、半導体キャリア基板上の表層面部にある複数の配線電極部にフリップチップ実装する工程と、前記半田或いは導電性ペーストを硬化させ、前記半導体素子と半導体キャリア基板の間にエポキシ系樹脂を注入硬化する工程とを含む半導体装置の製造方法。   A step of preparing a semiconductor device according to claim 1, 2 or 3, forming bumps on external connection pad electrodes on the semiconductor element, and uniformly leveling the bump height; A step of transferring solder or a conductive paste and flip-chip mounting on a plurality of wiring electrode portions on a surface layer portion on a semiconductor carrier substrate; and a step of curing the solder or conductive paste between the semiconductor element and the semiconductor carrier substrate And a step of injecting and curing an epoxy resin into the semiconductor device. 請求項１，２または３記載の半導体装置を用意し、前記半導体素子上の外部接続用パッド電極にバンプを形成する工程と、前記半導体素子を支持する半導体キャリア基板上に、シール状の樹脂を貼り付け、バンプ形成済みの前記半導体素子を反転させ、前記半導体キャリア基板上の複数の配線電極部に位置合わせ（アライメント）を行い、前記シール状のエポキシ系樹脂を介して熱圧着させ電気的接続を得る工程とを含む半導体装置の製造方法。   A semiconductor device according to claim 1, 2 or 3, a step of forming a bump on an external connection pad electrode on the semiconductor element, and a sealing resin on a semiconductor carrier substrate supporting the semiconductor element The semiconductor element that has been pasted and bumped is inverted, aligned (aligned) with a plurality of wiring electrode portions on the semiconductor carrier substrate, and electrically connected by thermocompression bonding via the sealing epoxy resin. And a method for manufacturing a semiconductor device. 前記半導体素子上に形成された複数の外部接続用パッド電極に設けられたプローブ検査用の溝に、プローブ針の接触性や電気特性を良好にするため金属めっきをコーティング塗布する請求項４または５記載の半導体装置の製造方法。   6. A metal plating coating is applied to a probe inspection groove provided on a plurality of external connection pad electrodes formed on the semiconductor element in order to improve the contact property and electrical characteristics of the probe needle. The manufacturing method of the semiconductor device of description. 請求項１，２または３記載の半導体装置の外部接続用パッド電極上に設けられたプローブ検査用の溝に、プローブ針を挿入し、プローブ針を横方向に滑らせながら、且つ、前記溝のコーナ部で完全に静止させて、屑の発生を防止し、且つトランジスタを有する前記外部接続用パッド電極直下にのみプローブ荷重が負荷されず荷重分散できることを特徴とする半導体装置の検査方法。   A probe needle is inserted into a groove for probe inspection provided on an external connection pad electrode of the semiconductor device according to claim 1, 2 or 3, and the probe needle is slid laterally and the groove A method for inspecting a semiconductor device, characterized in that it can be completely stopped at a corner portion to prevent generation of dust, and a probe load can be distributed only under the external connection pad electrode having a transistor without being loaded.
JP2004031947A 2004-02-09 2004-02-09 Semiconductor device, and its manufacturing and inspecting methods Withdrawn JP2005223250A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2004031947A JP2005223250A (en) 2004-02-09 2004-02-09 Semiconductor device, and its manufacturing and inspecting methods

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004031947A JP2005223250A (en) 2004-02-09 2004-02-09 Semiconductor device, and its manufacturing and inspecting methods

Publications (1)

Publication Number Publication Date
JP2005223250A true JP2005223250A (en) 2005-08-18

Family

ID=34998621

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004031947A Withdrawn JP2005223250A (en) 2004-02-09 2004-02-09 Semiconductor device, and its manufacturing and inspecting methods

Country Status (1)

Country Link
JP (1) JP2005223250A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101964308A (en) * 2009-07-23 2011-02-02 瑞萨电子株式会社 Make method, semiconductor device and the semiconductor manufacturing facility of semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101964308A (en) * 2009-07-23 2011-02-02 瑞萨电子株式会社 Make method, semiconductor device and the semiconductor manufacturing facility of semiconductor device
CN101964308B (en) * 2009-07-23 2013-05-29 瑞萨电子株式会社 Method of manufacturing semiconductor device, semiconductor device thus manufactured, and semiconductor manufacturing apparatus

Similar Documents

Publication Publication Date Title
KR100520660B1 (en) Semiconductor wafer, semiconductor device, and method for manufacturing the same
KR101944795B1 (en) tape film package and manufacturing method of the same
JP5268752B2 (en) Semiconductor package and manufacturing method thereof
JP2010206007A (en) Semiconductor device and method of manufacturing the same
TW200618200A (en) Semiconductor device and method for making the same
JP3690407B2 (en) Manufacturing method of semiconductor device
JP2007036060A (en) Semiconductor device and manufacturing method thereof
JP2011142185A (en) Semiconductor device
US20140191397A1 (en) Package substrate and semiconductor package including the same
JP2006294976A (en) Semiconductor device and its manufacturing method
KR20080037681A (en) Semiconductor chip, method of manufacturing semiconductor chip, and semiconductor device
US20080203511A1 (en) Sensor-type semiconductor package and method for fabricating the same
JP2009076497A (en) Method of manufacturing semiconductor device
JP2005026582A (en) Semiconductor device and method for manufacturing the semiconductor device
US7332430B2 (en) Method for improving the mechanical properties of BOC module arrangements
KR100805503B1 (en) Semiconductor device, method for manufacturing the same, circuit board and electronic apparatus
US20110227212A1 (en) Semiconductor device package and method of fabricating the same
US20100269333A1 (en) Method for Mounting Flip Chip and Substrate Used Therein
JP2005223250A (en) Semiconductor device, and its manufacturing and inspecting methods
JP2005123463A (en) Semiconductor device, its manufacturing method, semiconductor device module, circuit board, and electronic equipment
JP4737995B2 (en) Semiconductor device
US9373526B2 (en) Chip package and method for forming the same
TWI529825B (en) Method for manufacturing semiconductor structure
US20080212301A1 (en) Electronic part mounting board and method of mounting the same
JP2018074022A (en) Semiconductor device

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20060511

RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20060605

A761 Written withdrawal of application

Free format text: JAPANESE INTERMEDIATE CODE: A761

Effective date: 20070731