JP2005223128A - Quality evaluation method of soi wafer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an quality evaluation method of SOI wafer capable of, with an MOS structure formed by a simple technology, evaluating the quality of a BOX oxide film of the SOI wafer in a nondestructive manner, being different from a TZDB method and TDDB method, and also capable of identifying its defective points. <P>SOLUTION: The SOI wafer is composed of a BOX oxide film and SOI layer formed sequentially on at least a support substrate. The SOI layer is partially etched to form at least one silicon island of MESA structure. An MOS structure formed of the support substrate, BOX oxide film, and silicon island is applied with a voltage to form a depletion layer. The depletion layer is irradiated with laser beam or electron ray while the applied voltage is changed, and OBIC or EBIC generated by the irradiation is observed. The quality characteristics of the BOX oxide film is evaluated on the basis of the applied voltage when observation of the OBIC or EBIC is started. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an SOI wafer quality evaluation method, and more particularly to a method for evaluating the quality of a BOX oxide film of an SOI wafer.

  In recent years, an SOI wafer having an SOI (Silicon On Insulator) structure in which an electrically insulating silicon oxide film and a silicon active layer are sequentially formed on a support substrate such as a silicon wafer has been developed. In particular, it is attracting attention as a high-performance LSI wafer for electronic devices because of its excellent properties, high pressure resistance, and environmental resistance. This is because an SOI wafer has an embedded oxide film (hereinafter sometimes referred to as a BOX oxide film) that is an insulator between a support substrate and a silicon active layer (hereinafter referred to as an SOI layer), and thus is formed in the SOI layer. This is because the electronic device has a great advantage that the withstand voltage is high and the soft error rate of α rays is low.

  In addition, in a thin film SOI wafer having an SOI layer thickness of 1 μm or less, a MOS (Metal Oxide Semiconductor) type semiconductor device formed on the SOI layer has a source / drain PN junction area when operated in a fully depleted type. Since the capacitance can be reduced, the parasitic capacitance is reduced, and the speed of driving the electronic device can be increased. Furthermore, since the capacitance of the BOX oxide film serving as the insulating layer is in series with the depletion layer capacitance formed immediately below the gate oxide film, the depletion layer capacitance is substantially reduced, and low power consumption can be realized.

  In addition, since the BOX oxide film on the SOI wafer greatly contributes to the enhancement of the performance of electronic devices formed on the SOI layer, attention is paid to the quality of the BOX oxide film, such as the uniformity of the BOX oxide film thickness and the presence or absence of pinholes. It is growing. In particular, BOX oxide insulating characteristic evaluation (hereinafter also referred to as BOX oxide film / Vbd evaluation) has been increasingly demanded as one of the quality indicators of the BOX oxide film. An example of a conventional BOX oxide film / Vbd evaluation method for forming a MOS structure will be described below.

FIG. 5 is a schematic diagram for explaining a process for forming a MOS structure at the time of BOX oxide film / Vbd evaluation in a conventional SOI wafer.
First, an SOI wafer W ′ having a BOX oxide film 2 ′ and an SOI layer 1 ′ formed on a support substrate 3 ′ is prepared. The SOI layer 1 'is removed by etching, and the BOX oxide film 2' is exposed on the surface. Next, after a polysilicon layer is grown on the BOX oxide film 2 ′ by a CVD (Chemical Vapor Deposition) method or the like, the polysilicon electrode 22 is formed at a desired position on the BOX oxide film 2 ′ by using a photolithography technique. The excess portion of the polysilicon layer is removed by etching or the like. Further, a dopant such as phosphorus is doped into the polysilicon electrode 22 by using a thermal diffusion method or an ion implantation method to form a polysilicon electrode 22 having a low resistivity. In this way, a MOS capacitor having a MOS structure is formed, and a voltage is applied thereto.

  The voltage application is performed by a TZDB (Time Zero Dielectric Breakdown) method or a TDDB (Time Dependent Dielectric Breakdown) method. In the TZDB method, the current value flowing in the MOS capacitor is monitored while changing the electric field strength in a stepwise manner to about 0 to 15 MV / cm, and when the insulating film of the MOS capacitor, in this case, the BOX oxide film is destroyed, Measure the electric field strength when breakdown occurs. Based on the ratio of the number of MOS capacitors that were good to the total number of MOS capacitors to which a voltage was applied, with an insulation film having a dielectric breakdown field strength of a predetermined value or more, for example, 8 MV / cm or more being considered good and others not being good To evaluate the quality of the insulation film.

  On the other hand, the TDDB (Time Dependent Dielectric Breakdown) method is a method in which a constant electrical stress is continuously applied to an insulating film, and the life of the insulating film is evaluated from the time until the dielectric breakdown occurs. For example, in the TDDB method in which a constant current is applied, a constant current is continuously applied to an insulating film, electric field strength is detected at a predetermined time interval to obtain a change over time, and a time until dielectric breakdown is obtained. It is a method to evaluate. When the BOX oxide film thickness is relatively thick at 100 nm, this evaluation is not required so much, but it may be necessary if the BOX oxide film becomes thinner in the future.

  However, with respect to the BOX oxide film / Vbd evaluation of an SOI wafer, the conventional method requires the formation of a MOS capacitor structure on the SOI wafer. Expensive equipment is required. Also, as SOI wafers become larger in diameter, it becomes very difficult to prepare and maintain the apparatus. In addition, since the BOX oxide film / Vbd evaluation by the TZDB method or the TDDB method is a destructive inspection, a defective MOS capacitor can be specified, but more positional information cannot be obtained. In addition, since the defective portion does not remain in its original form due to heat generation during dielectric breakdown, the cause analysis of the defect is impossible because it is a destructive inspection.

  By the way, a method is disclosed in which a MOS capacitor is formed on the main surface of a normal silicon wafer having no SOI structure, and defects in the gate oxide film are evaluated nondestructively (for example, see Patent Documents 1 and 2). . This is done in the following way. First, a MOS capacitor is formed on the main surface of a normal silicon wafer by a known method. Next, a voltage is applied from the electrode of the MOS capacitor to form a depletion layer immediately below the electrode. Subsequently, while changing the applied voltage, the depletion layer is irradiated with a laser beam or an electron beam to generate or inject carriers, thereby generating OBIC (Optical Beam Induced Current) or EBIC (Electron Beam Induced) generated in the MOS capacitor. Current) is measured.

  By evaluating the oxide film characteristics of the MOS capacitor based on the applied voltage value when the OBIC or EBIC reaches a predetermined value, not only the gate oxide film but also the substrate surface layer directly under the gate oxide film is evaluated. Therefore, it becomes possible to easily evaluate the oxide film characteristic failure that cannot be detected by the conventional TZDB method or TDDB method.

JP 2000-88782 A JP 2001-44249 A

  The present invention forms a MOS structure on an SOI wafer by a simple method, evaluates the quality of the BOX oxide film of the SOI wafer without destroying it as in the TZDB method or the TDDB method, and identifies the defective portion. An object of the present invention is to provide an SOI wafer quality evaluation method that can be used.

  In order to achieve the above object, the present invention provides a quality evaluation method for an SOI wafer comprising at least a BOX oxide film and an SOI layer sequentially formed on a support substrate, wherein the SOI layer is partially etched to form a MESA. Forming at least one silicon island having a structure, forming a depletion layer by applying a voltage to a MOS structure formed by the support substrate, the BOX oxide film, and the silicon island, and changing the applied voltage; Irradiating a laser beam or electron beam into the depletion layer, observing OBIC or EBIC generated by the irradiation, and evaluating the quality characteristics of the BOX oxide film by an applied voltage when OBIC or EBIC starts to be observed. A characteristic SOI wafer quality evaluation method is provided.

  As described above, if at least one MESA (mountain) silicon island is formed by partially etching the SOI layer, a MOS structure can be easily formed without using an expensive apparatus such as a conventional photolithography apparatus. . Then, a voltage is applied in the direction of forming a depletion layer in the MOS structure to form a depletion layer directly under the MOS structure, and a laser beam or an electron beam is irradiated into the depletion layer while changing the applied voltage, thereby generating an OBIC. Alternatively, if the quality characteristics of the BOX oxide film are evaluated based on the applied voltage when EBIC starts to be observed, the quality evaluation can be performed without destroying the BOX oxide film as in the TZDB method or the TDDB method.

In this case, it is preferable to identify a point where the OBIC or EBIC is observed stronger than the surroundings immediately below the MOS structure to which the voltage is applied (claim 2).
As described above, if a place where the OBIC or EBIC is observed more strongly than the surroundings directly under the MOS structure to which the voltage is applied is identified as a defect place, the defect place can be easily identified, so that the defect place can be directly observed. . This can greatly contribute to quality improvement of the SOI wafer by analyzing the cause of the defect.

Preferably, after a polysilicon layer is grown immediately above the SOI layer, the resistivity is lowered by doping the polysilicon layer with a dopant, and then the silicon island is formed.
In this way, after a polysilicon layer is grown directly on the SOI layer by a CVD method or the like, the resistivity is lowered by doping a dopant such as phosphorus into the polysilicon layer, and then a silicon island is formed. The silicon layer can be used as an electrode portion having a low resistivity, and the voltage applied to the MOS structure can be reduced even when the resistivity of the SOI layer is originally high.

In addition, when a polysilicon layer is grown directly on the SOI layer, it is preferable to simultaneously reduce the resistivity by doping the polysilicon layer with a dopant, and then form the silicon island.
As described above, when the polysilicon layer is grown, the resistivity is lowered by simultaneously doping the dopant, and then the silicon island is formed, so that the polysilicon layer can be used as an electrode portion having a low resistivity. .

Furthermore, it is preferable that the resistivity is lowered by doping the SOI layer with a dopant, and then the silicon island is formed.
In this way, by directly doping the SOI layer with a dopant to lower the resistivity, and then forming a silicon island, the silicon island can be used as a low resistivity electrode part. Originally, the resistivity of the SOI layer Even when the voltage is high, the voltage applied to the MOS structure can be reduced.
In this case, a CVD apparatus or the like for growing the polysilicon layer is unnecessary.

In this case, at the time of forming the silicon island, a shielding material made of at least an elastic material is placed on and closely adhered to the SOI layer, and then the SOI wafer is immersed in an etching solution so that the shielding material adheres. Preferably, the silicon island is formed by etching the SOI layer other than the inside of the portion and then removing the shielding material.
As described above, when the silicon island is formed, the shielding material made of at least an elastic material is placed on and closely adhered to the SOI layer, and then the SOI wafer is immersed in an etching solution, and the portion where the shielding material is in close contact is formed. If the silicon island is formed by etching the SOI layer other than the inside and then removing the shielding material, an inexpensive and simple jig can be obtained without using an expensive apparatus such as a conventional photolithography apparatus. A MOS structure can be easily formed by using it.

According to the present invention, if the SOI layer is partially etched to form at least one MESA structure silicon island, a MOS structure can be easily formed without using an expensive apparatus such as a conventional photolithography apparatus. When a voltage is applied to the MOS structure to form a depletion layer immediately below the MOS structure, a laser beam or an electron beam is irradiated into the depletion layer while changing the applied voltage, and OBIC or EBIC generated thereby starts to be observed If the quality characteristic of the BOX oxide film is evaluated by the applied voltage, the quality evaluation can be performed without destroying the BOX oxide film as in the TZDB method or the TDDB method.
In addition, by identifying a location where the OBIC or EBIC is observed more strongly than the surroundings immediately below the MOS structure to which the voltage is applied as a defect location, the defect location can be easily identified, so that the defect location can be directly observed. This can greatly contribute to quality improvement of the SOI wafer by analyzing the cause of the defect.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, but the present invention is not limited thereto.

In the SOI wafer evaluation method of the present invention, first, the SOI layer of the SOI wafer to be evaluated is partially etched to form a silicon island having a MESA structure.
FIG. 1 is a schematic view for explaining a process for forming a silicon island having a MESA structure in the present invention. First, an SOI wafer W is prepared. The SOI wafer W includes a support substrate 3, an SOI layer 1 which is a silicon active layer, and a BOX oxide film 2 interposed between the support substrate 3 and the SOI layer 1. There is no restriction | limiting in particular in the magnitude | size of SOI wafer W, For example, it can be set as 150 mm, 200 mm, and 300 mm in diameter. Also, the conductivity type may be either p-type or n-type.

  At this time, the resistivity of the SOI layer 1 has various values according to the user's required specifications. If the resistivity of the SOI layer 1 is high, it is preferable to lower the resistivity by doping the SOI layer 1 with a dopant before forming the silicon island. In this way, by lowering the resistivity of the SOI layer 1 serving as an electrode portion after the silicon island is formed, the applied voltage at the time of evaluation can be reduced, and the BOX oxide film can be prevented from being destroyed. As a dopant to be doped at this time, an element generally used in a semiconductor manufacturing process such as phosphorus, boron, arsenic, and antimony can be used according to the conductivity type. As a doping method, for example, a thermal diffusion method or an ion implantation method can be used. At this time, the resistivity is preferably lowered to, for example, 1 Ω · cm or less.

  Alternatively, instead of doping the SOI layer 1 with a dopant, a polysilicon layer may be grown directly on the SOI layer 1 by a CVD method or the like, and the above-described dopant may be doped into the polysilicon layer to lower the resistivity. Good. By growing the polysilicon layer used as the electrode portion in this way and lowering its resistivity, the applied voltage at the time of evaluation can be reduced, and there is no possibility that the BOX oxide film is destroyed. In this case, the dopant may be simultaneously doped while growing the polysilicon layer, or the dopant may be doped by a thermal diffusion method or the like after growing the polysilicon layer.

  Then, the SOI layer 1 is partially etched to form a silicon island 4 having a MESA structure on the BOX oxide film 2. Photolithographic techniques may be used for etching the SOI layer 1, but a simpler technique can be used in the present invention.

  For example, as shown in FIG. 1, for example, a shielding material 5 made of a silicone O-ring and a sealing material 6 that also serves as a weight are prepared, the shielding material 5 is placed on the SOI layer 1, and the sealing material 6 is formed thereon. And the sealing material 6 is laid under the support substrate 3 so that the shielding material 5 and the SOI wafer W are sandwiched between the sealing materials 6. Then, the shielding material 5 is deformed by the weight of the sealing material 6 and is in close contact with the SOI layer 1 and the sealing material 6. In this state, the SOI wafer W is immersed in an etching solution such as TMAH (tetramethylammonium hydroxide) at a predetermined temperature for a predetermined time according to the thickness of the SOI layer. Then, although the SOI layer 1 is etched, the shielding material 5, the SOI layer 1, and the sealing material 6 are in close contact with each other and are sealed, so that the etching solution is placed inside the portion of the SOI layer 1 where the shielding material 5 is in close contact. Does not penetrate and is not etched. Therefore, after completely etching the SOI layer 1 in other portions, the SOI wafer W is taken out from the etching solution, washed with pure water or the like to sufficiently remove the etching solution, and then the shielding material 5 and the sealing material 6 are removed. . In this way, the silicon island 4 having the MESA structure can be easily formed.

  The shielding material 5 may be made of a material having elasticity so as to be in close contact with the SOI layer, and the sealing material 6 may have a certain weight and may be in close contact with the shielding material 5. Further, both materials may be any material that is not etched with an alkali etching solution or an acid etching solution. For example, the shielding material 5 may be a silicone O-ring or a silicone sheet. Moreover, the sealing material 6 may be a glass plate or a vinyl chloride resin. Furthermore, the sealing material 6 may not be used if the shielding material 5 has no holes and is sufficiently large in weight. Furthermore, these may be fixed using a jig for sandwiching and fixing the SOI wafer W and the shielding material 5 with the sealing material 6.

As described above, according to the method of the present invention, since a silicon island having a MESA structure can be easily formed using a simple and inexpensive jig, an expensive apparatus such as a photolithography apparatus or a plasma etching apparatus is not required. Of course, it is easy to form silicon islands of any size at arbitrary positions, and it is also possible to easily form a plurality of silicon islands simultaneously.
As described above, in the case of an SOI wafer in which a polysilicon layer is grown directly on the SOI layer before forming the silicon island, a shielding material is placed on the polysilicon layer, and the same process as described above. Thus, the excess polysilicon layer and SOI layer are removed by etching, and the silicon island is composed of at least the polysilicon layer and the SOI layer.

The SOI wafer W on which the silicon islands 4 are formed in this manner has a MOS structure formed by the support substrate, the BOX oxide layer, and the silicon islands in the portions where the silicon islands are formed.
Next, this SOI wafer W is mounted on an oxide film defect evaluation apparatus using OBIC or EBIC for evaluation. FIG. 2 is a schematic diagram showing an example of the configuration of an oxide film defect evaluation apparatus S1 by EBIC, mainly a scanning electron microscope system (hereinafter referred to as SEM: Scanning Electron Microscope) 12, an EBIC current amplifier 9, and a CRT 8 for SEM. Consists of

  Evaluation of an SOI wafer using the EBIC of the present invention is performed according to the following procedure. First, the above-described SOI wafer W to be evaluated is placed on a sample stage (not shown) of the SEM 12. At this time, the sample stage also serves as an electrode, and the back side of the SOI wafer in contact with the sample stage is connected to the GND (ground minus, input side of the EBIC current amplifier 9) side, while the MESA structure silicon island serving as the electrode unit Reference numeral 4 denotes a DC power source 10 through the probe 11 so that a positive potential (in the case of a p-type substrate. In an n-type substrate, the connection between the silicon island electrode and the sample stage electrode is reversed and the silicon island electrode has a negative potential) can be output. Connected to. The potential is set in this way in order to apply a voltage in the direction in which the depletion layer is formed in the MOS structure. And after setting a potential according to the conductivity type of the support substrate in this way, a voltage is applied to the MOS structure to form a depletion layer.

  Next, the electron beam 13 of the SEM 12 is irradiated while being scanned, and carriers are injected into the depletion layer formed immediately below the MOS structure by voltage application. At this time, the acceleration voltage of the electron beam 13 is a parameter for determining the carrier injection depth. The depth at which the carrier injection efficiency by the electron beam 13 is the best, that is, the acceleration voltage is set to about twice the width of the depletion layer widened by voltage application. When the voltage applied to the MOS structure is increased in the positive direction from 0 during irradiation of the electron beam 13, strong EBIC is observed from the entire surface of the MOS structure.

  The minute current generated at this time is amplified by the EBIC current amplifier 9 and combined with the electron beam irradiation position information to display a defect image on the SEM CRT 8. In this case, by adjusting the detection sensitivity, it can be confirmed that the image is an EBIC image from a part of the MOS structure. The quality characteristic of the BOX oxide film is evaluated based on the voltage applied to the SOI wafer W when the EBIC starts to be observed. If the quality characteristics of the BOX oxide film are evaluated in this way, the quality evaluation can be performed without destroying the BOX oxide film as in the TZDB method or the TDDB method. For example, the BOX oxide film reliability characteristic may be defined by the voltage applied to the SOI wafer W when EBIC starts to be observed.

Then, a portion where the EBIC is observed more strongly than the surroundings is identified as a defective portion. For example, when an SOI wafer is manufactured by a known bonding method, and a BOX oxide film becomes thin or a void is generated due to the presence of particles, protrusions, or foreign matters on the support substrate during the bonding. In addition, the location can be identified.
In this way, the position of the defect portion is specified, and the defect portion is directly observed with the SEM to perform detailed structural analysis of the defect, thereby obtaining more detailed information about the defect. As a result, the cause of the occurrence of defects can be known, which can greatly contribute to quality improvement of SOI wafers. This is possible because the present invention can observe defects nondestructively.

Next, oxide film defect evaluation by OBIC will be described.
FIG. 3 is a schematic diagram showing an example of the configuration of the oxide film defect evaluation apparatus S2 by OBIC, and mainly includes a scanning laser microscope system 15, an OBIC current amplifier 16, a computer 17, and a defect image display CRT 14.
Evaluation of an SOI wafer using the OBIC of the present invention is performed according to the following procedure. First, the above-described SOI wafer W to be evaluated is placed on a sample stage (not shown) of the scanning laser microscope system 15. At this time, the sample stage also serves as an electrode, and the back side of the SOI wafer in contact with the sample stage is connected to the GND (ground minus, input side of the OBIC current amplifier 16) side, and on the other hand, a MESA structure silicon island serving as the electrode unit Reference numeral 4 denotes a DC power source 10 through the probe 11 so that a positive potential (in the case of a p-type substrate. In an n-type substrate, the connection between the silicon island electrode and the sample stage electrode is reversed and the silicon island electrode has a negative potential) can be output. Connected to. The potential is set in this way in order to apply a voltage in the direction in which the depletion layer is formed in the MOS structure. And after setting a potential according to the conductivity type of the support substrate in this way, a voltage is applied to the MOS structure to form a depletion layer.

  Next, the laser beam (wavelength: 632.8 nm) from the He—Ne laser built in the scanning laser microscope system 15 is narrowed down, and the surface of the silicon island is irradiated while being scanned by the scanner 18 to apply the voltage to apply the MOS structure. Carriers are generated in a depletion layer formed immediately below. Reference numeral 19 denotes the range of the laser scan. When the voltage applied to the MOS structure is increased in the positive direction from 0 during laser light irradiation, strong OBIC is observed from the entire MOS structure.

The minute current generated at this time is amplified by the OBIC current amplifier 16 and input to the MPU (Micro Processing Unit) 20, and the laser light irradiation electron beam irradiation position information input to the MPU 20 through the scanner 18 is synthesized, and further the computer 17. Then, the data is processed to display the defect image on the defect image display CRT 14. In this case, by adjusting the detection sensitivity, it can be confirmed that the image is an OBIC image from a part of the MOS structure. Based on the voltage applied to the SOI wafer W when the OBIC starts to be observed, the quality characteristics, for example, the reliability characteristics of the BOX oxide film are evaluated.
As in the case of the EBIC described above, a place where the OBIC is observed stronger than the surroundings can be identified as a defective place.

Examples of the present invention will be described in more detail below, but the present invention is not limited thereto.
(Example 1)
First, as a sample, an SOI wafer having a diameter of 200 mm, an SOI layer / BOX oxide film thickness of 150/135 nm, an SOI layer resistivity of 0.1 Ω · cm, and a conductivity type of p-type was prepared. This SOI wafer was divided into ¼, an O-ring having a diameter of 10 mm was placed on one of the SOI layers, and an O-ring was sandwiched from above by a glass plate. In this state, it was immersed in a 40 ° C. TMAH solution. About 3 minutes after the immersion, the SOI layer was etched, and only the SOI layer surrounded by the O-ring remained on the BOX oxide film to form a silicon island having a MESA structure. And it wash | cleaned with the pure water in this state, and removed the O-ring after that.

  This wafer was mounted on the above-mentioned EBIC oxide film defect evaluation apparatus and measured. In this example, an EBIC spot 21 as schematically shown in FIG. 4 was observed with an applied voltage of about 1V. Then, spot 21 in FIG. 4 was identified as a defect position and observed with SEM in more detail. As a result, pinholes were present in the BOX oxide film. And it became clear that this defect was a defect (BOX pinhole) which the SOI layer and the support substrate were connected.

  The present invention is not limited to the above embodiment. The above-described embodiment is an exemplification, and the present invention has substantially the same configuration as the technical idea described in the claims of the present invention, and any device that exhibits the same function and effect is the present invention. It is included in the technical scope of the invention.

  For example, in the above embodiment, the resistivity of the SOI layer was originally small. However, when evaluating an SOI wafer having an SOI layer with a large resistivity, the resistivity can be lowered by doping the SOI layer with a dopant. A silicon island may be formed after a polysilicon layer is grown immediately above the SOI layer and has a low resistivity. Moreover, in the said Example, although evaluation was performed by EBIC, evaluation can also be performed by OBIC.

It is the schematic explaining the formation process of the silicon island of the MESA structure in this invention. It is a schematic diagram which shows an example of a structure of the oxide film defect evaluation apparatus by EBIC. It is a schematic diagram which shows an example of a structure of the oxide film defect evaluation apparatus by OBIC. It is the schematic which shows evaluation of the BOX oxide film by EBIC of the Example of this invention. It is the schematic explaining the formation process of the MOS structure in the case of BOX oxide film / Vbd evaluation in the conventional SOI wafer.

Explanation of symbols

W, W '... SOI wafer,
S1 ... EBIC oxide film defect evaluation apparatus,
S2 ... OBIC oxide film defect evaluation device,
1, 1 '... SOI layer, 2, 2' ... BOX oxide film, 3, 3 '... support substrate,
4 ... Silicon island 5 ... Shielding material 6 ... Sealing material 8 ... CRT for SEM,
9 ... EBIC current amplifier, 10 ... DC power supply, 11 ... Probe,
12 ... Scanning electron microscope (SEM) system, 13 ... Electron beam,
14 ... Defect image display CRT, 15 ... Scanning laser microscope system,
16 ... OBIC current amplifier 17 ... Computer 18 ... Scanner
19 ... Laser scan range, 20 ... MPU,
21 ... EBIC spot (BOX oxide pinhole),
22: Polysilicon electrode.

Claims (6)

  A quality evaluation method of an SOI wafer comprising at least a BOX oxide film and an SOI layer sequentially formed on a support substrate, wherein the SOI layer is partially etched to form at least one silicon island having a MESA structure, A voltage is applied to the MOS structure formed by the support substrate, the BOX oxide film, and the silicon island to form a depletion layer, and a laser beam or an electron beam is irradiated into the depletion layer while changing the applied voltage. And observing the OBIC or EBIC generated by the irradiation, and evaluating the quality characteristic of the BOX oxide film based on the applied voltage when the OBIC or EBIC starts to be observed.   2. The SOI wafer quality evaluation method according to claim 1, wherein a portion where OBIC or EBIC is observed more strongly than the surrounding immediately under the MOS structure to which the voltage is applied is identified as a defective portion. Quality evaluation method.   3. The method for evaluating the quality of an SOI wafer according to claim 1, wherein after the polysilicon layer is grown directly on the SOI layer, the resistivity is increased by doping the polysilicon layer with a dopant. A method for evaluating the quality of an SOI wafer, comprising lowering and then forming the silicon island.   The quality evaluation method for an SOI wafer according to claim 1 or 2, wherein when a polysilicon layer is grown directly on the SOI layer, the resistivity is increased by simultaneously doping the polysilicon layer with a dopant. A method for evaluating the quality of an SOI wafer, comprising lowering and then forming the silicon island.   3. The SOI wafer quality evaluation method according to claim 1 or 2, wherein the SOI layer is doped with a dopant to lower the resistivity and then form the silicon island. Quality evaluation method.   6. The quality evaluation method for an SOI wafer according to claim 1, wherein a shielding material made of at least an elastic material is placed on the SOI layer when the silicon island is formed. After placing and adhering, the silicon wafer is formed by immersing the SOI wafer in an etching solution, etching the SOI layer other than the inside of the part to which the shielding material is adhered, and then removing the shielding material. The quality evaluation method of SOI wafer characterized by these.

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