JP2005218220A - Digital protection controller - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To confirm the validity of data and correct failed data even if a serial transfer system is introduced into a system bus. <P>SOLUTION: Units 3, 4, 8 and 10 are connected via a serial link 7, and when data are outputted from a transmitting circuit 33 to the serial link 7, an error correction code is added to the transmitted data and outputted as the serial data. A receiving circuit 34 for receiving the serial data from the serial link 7 determines the validity of the data based on the error correction code in the received data, corrects the received data when an abnormality is detected, and receives the corrected data. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a digital protection / control apparatus, and in particular, digital protection / control suitable for processing system information of a power system and status information of a control target as digital data and controlling the control target based on the processing result. Relates to the device.

  Conventionally, as this type of digital protection / control device, for example, a digital protection relay (second generation digital relay) is known (see Non-Patent Document 1). This digital protection relay includes an analog input unit, a digital input unit, an arithmetic processing unit, and a digital output unit. The arithmetic processing unit is provided with a microcomputer for executing protection, control, and sequence arithmetic processing. An analog input unit, a digital input unit, and a digital output unit are connected to the computer system bus. The system bus employs a parallel transfer system in which a plurality of bit lines are simultaneously transferred using a plurality of signal lines.

  In the digital protection relay, first, an analog input unit takes in a voltage / current signal from the power system, samples it, executes a digital filter operation according to the digital data obtained by the sampling, and outputs the calculation result to an arithmetic processing unit. To output. The arithmetic processing unit executes protection / control arithmetic processing based on the data selected from the analog input unit, and executes sequence control arithmetic using data based on the protection / control arithmetic result and digital input data of external device information. To do. Next, the arithmetic processing unit generates an operation command from the sequence control calculation result, and outputs the operation command to an external device via the digital output unit. An operation command to the external device is output from the digital output unit corresponding to the bit information of the digital output data of the sequence control calculation result. In the process of outputting the operation command, data input / output to / from each unit is transferred in parallel under the control of the microcomputer of the arithmetic processing unit.

  When the microcomputer of the arithmetic processing unit transfers data in parallel, it detects the failure of the data by a bus error method. However, in this method, since the response time when data is input / output is monitored, it is difficult to confirm the validity of the input / output data itself. In addition, since a plurality of bit transfers are simultaneously performed using a plurality of signal lines, the number of parts increases, power consumption becomes relatively large, and radiation noise also increases.

  Specifically, when data is exchanged between each unit via a parallel transfer system bus, the response time of the data reception end is monitored at the data transmission end, and there is no response within a predetermined time There is a bus error detected as a timeout. However, when there is a failure in the data line of the system bus, for example, when the digital output data of the control sequence output result is inverted by 1 bit, the response at the receiving end is normal and does not time out. In contrast, an incorrect operation command is output.

  In other words, just detecting a bus error in the parallel transfer system bus cannot confirm the correctness of the data itself, such as when a failure occurs that temporarily changes the data itself. Will be output.

  Therefore, a system bus that employs a serial transfer method has been proposed as a system bus for connecting the respective units (Patent Document 1).

Electric Cooperative Research Volume 50 No.1 JP 60-84912 A (2nd to 4th pages, FIG. 1)

  When the serial transfer method is adopted for the system bus, the number of signal lines is less than that of the parallel transfer method, so that the failure rate is lowered. However, even if the serial transfer method is simply adopted for the system bus, if a failure occurs in which the data itself changes, the validity of the data itself cannot be confirmed or the data cannot be corrected.

  An object of the present invention is to confirm the correctness of data itself and to correct faulty data even if a serial transfer method is adopted for the system bus.

  In order to solve the above-mentioned problems, the present invention connects a system information input unit, a digital input unit, a protection / control arithmetic unit, and a digital output unit via a serial link as a system bus, and serially transfers between the units. Units that send and receive data according to the system and output serial data to the serial link of each unit convert parallel data with an error correction code into serial data and output it to the serial link. The unit that receives the serial data from the serial link converts the parallel data into parallel data, separates the converted parallel data into error correction code and received data, and signals from the separated error correction code and signal data. Judging the validity of the data itself, Processing the signal data as parallel data, when there is abnormal bits is obtained so as to correct the abnormal bits, it processes the corrected signal data as parallel data.

  According to the present invention, even if a failure occurs in the serial link as the system bus, it is possible to prevent erroneous data from being used, and as a result, an erroneous operation command can be output to the controlled object. This can contribute to the improvement of reliability.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of a digital protection / control apparatus showing an embodiment of the present invention. In FIG. 1, a digital protection / control apparatus 1 includes an input transformer 2, an analog input unit 3, a protection / control sequence calculation unit 4, a display 5, a human interface unit 6, a serial link (system bus) 7, and a digital input unit. 8, a network interface unit 9, and a digital output unit 10. The input transformer 2 is connected to a power system 20 to be protected, and the digital input unit 8 and the digital output unit 10 are external to be controlled. Connected to the device 23, the network interface unit 9 is connected to the host computer 21 via the communication network 22.

  The input transformer 2 inputs an analog signal based on voltage and current as system information from the power system 20 to be protected, converts the input analog signal to an electronic circuit level, for example, ± 10 V, and converts the converted analog signal to analog It outputs to the input unit 3. The analog input unit 3 is configured as a system information input unit that converts an analog signal input from the input transformer 2 into digital parallel data, processes the result, and outputs the processing result to a serial link 7 as a system bus. Yes.

  Specifically, as shown in FIG. 2, the analog input unit 3 takes in an analog input signal from the input transformer 2, and performs analog processing for removing the sampling aliasing error on the taken-in analog signal. The input processing circuit 30, the sampling A / D conversion circuit 31 that converts an analog signal output from the analog input circuit 30 into a digital signal 36, and the digital signal 36 is acquired as parallel data via the bus 35, and is converted into the acquired digital data A digital filter process is executed for the CPU (microcomputer) 32 that outputs the processing result to the transmission circuit 33 via the bus 35, and parallel transmission data 37 is fetched from the bus 35, and the parallel transmission data 37 is serialized. The transmission data 39 is converted into serial transmission data 39 It is constructed 39 from transmitting circuit 33 for outputting to the serial link 7.

  The digital input unit 8 includes, for example, a digital input circuit 44 for inputting a digital signal indicating the open / close state of the circuit breaker as digital data from the external device 23 as a control target, and an input of the digital input circuit 44. A CPU (microcomputer) 43 that inputs digital data via the bus 35, performs arithmetic processing on the input digital signal, and outputs the processing result to the transmission circuit 33 via the bus 35 as parallel transmission data 37. And a transmission circuit 33 that takes in parallel transmission data 37 from the bus 35, converts the transmission data 37 into serial data, and outputs the serial data as serial transmission data 39 to the serial link 7.

  The protection / control sequence calculation unit 4 takes in serial data from the serial link 7 as reception data 40, converts the received reception data 40 into parallel reception data 38 and outputs the parallel reception data 38 to the bus 35, and the bus 35. The parallel received data 38 is taken in, and the protection / control operation program and the sequence control operation program are executed based on the received data 38, for example, information including the system information and the status information of the external device 23, and the protection / control operation From the bus 35, the CPU 41 stores the results and sequence control calculation results as parallel transmission data 37 to the transmission circuit 33 via the bus 35, and stores the protection / control calculation results and sequence control calculation results in the random access memory 42. Capture parallel transmission data 37, Submit converts the data 37 into serial data, and transmission data 39 converted serial is configured to include a transmission circuit 33 for transmitting to the serial link 7.

  The digital output unit 10 receives serial data from the serial link 7 as reception data 40, and outputs the received reception data 40 as parallel digital output data 38 to the bus 35, and the digital output data 38 from the bus 35. The CPU 45 generates an operation command for operating the external device 23, outputs the generated operation command as parallel data to the bus 35, and inputs the operation command based on the parallel data from the bus 35. The digital output circuit 46 outputs the digital signal to the external device 23.

  The human interface unit 6 is configured to input a set value or set value for protection / control calculation in a conversational manner with a human (operator) and display the result on the display 5. The network interface unit 9 is configured to interface with a modem that can be connected to the communication network 22.

  In the digital protection / control apparatus 1, data is exchanged between the units via the serial link 7, and the transmission circuit 33 and the reception circuit 34 provided in each unit are composed of the same unit. ing.

  Specifically, as shown in FIG. 3, the serial transfer transmission circuit 33 includes an error correction code (ECC) generation circuit 50, a signal synthesis circuit 51, a serial conversion circuit 52, and a transmission buffer 53. The serial transfer type reception circuit 34 includes a 1-bit error correction circuit 54, a signal separation circuit 55, a parallel conversion circuit 56, and a reception buffer 57.

  The error correction code generation circuit 50 is configured as an error correction code generation unit that takes in and writes parallel transmission data 37 from the bus 35 and generates an error correction code (ECC) from the written transmission data 37. The signal synthesis circuit 51 is configured as signal synthesis means for synthesizing the written transmission data 37 and the error correction code. The serial conversion circuit 52 is configured as serial conversion means for converting parallel data output from the signal synthesis circuit 51 into serial data. The transmission buffer 53 is configured as transmission buffer means for transmitting serial data output from the serial conversion circuit 52 to the serial link 7 as serial transmission data 39.

  On the other hand, in the serial transfer type reception circuit 34, the reception buffer 57 is configured as reception buffer means for receiving serial data transmitted from the serial link 7 by another unit, for example, the digital input unit 8 as reception data 40. . The parallel conversion circuit 56 is configured as parallel conversion means for converting data output from the reception buffer 57 into parallel data and outputting the parallel data to the signal separation circuit 55. The signal separation circuit 55 is configured as a signal separation unit that separates parallel data output from the parallel conversion circuit 56 into an error correction code and signal data. The 1-bit error correction circuit 54 checks the validity of the signal data itself based on the error correction code and the signal data output from the signal separation circuit 55, and outputs the signal data as it is to the bus 35 as parallel data 38 when normal. However, when there is an abnormal bit, it is configured as correcting means for correcting the abnormal bit and outputting the corrected signal data as parallel data 38 to the bus 35. For this reason, the CPU 41 performs an operation by fetching parallel data that has been subjected to error correction and that has been checked for validity.

  Next, a specific example of error correction processing when data is input / output by the protection / control sequence arithmetic unit 4 when transferring 32-bit data to the bus 35 will be described with reference to FIG. When outputting parallel data from the CPU 41 to the bus 35, for example, when outputting parallel data related to an operation command for operating the external device 23 to the bus 35, the 32-bit parallel data 37 is converted to the error correction code via the bus 35. Output to the generation circuit 50. In the error correction code generation circuit 50, the error correction code generation unit 60 generates a 7-bit error correction code 61 based on the input 32-bit parallel data, and the 7-bit error correction code 61 and the 32-bit signal are generated. Data 62 is output as a set to the signal synthesis circuit 51. The signal synthesis circuit 51 synthesizes the 7-bit error correction code 61 and the 32-bit signal data 62 and outputs the synthesized data in accordance with a specified law. For example, the 32-bit signal data 62 and the 7-bit error correction code 61 are always output to the serial conversion circuit 52 according to the rule of passing the signal data 62 and the error correction code 61 in this order. The serial conversion circuit 52 sequentially converts input data into serial data, and writes the converted serial data in the transmission buffer 53. The serial data written in the transmission buffer 53 is transmitted to the serial link 7 as serial transmission data 39.

  On the other hand, when signal data from another unit is received as serial reception data 40 from the serial link 7 to the reception buffer 57, for example, the reception buffer 57 receives serial data related to an operation command for operating the external device 23. When an operation command is output to the external device 23, serial data output from another unit via the serial link 7 is received by the reception buffer 57 and then converted into parallel data by the parallel conversion circuit 56. The signal is converted and then taken into the signal separation circuit 55. Since the data input to the signal separation circuit 55 includes the signal data and the error correction code ECC, the signal separation circuit 55 converts the input data into the signal data 62 and the error correction code 61 according to a prescribed law. The separated data is output to the 1-bit correction circuit 54. In the 1-bit correction circuit 54, the abnormality monitoring circuit 63 verifies the validity of the bit information of the 32-bit signal data from the 32-bit signal data and the 7-bit error correction code 61. When the signal data is output as it is to the bus 35 as the parallel data 38 and an abnormality is detected in the signal data 62 itself, the abnormal part of the 32-bit signal data 62 is corrected by the 1-bit error correction circuit 64 and the abnormality is corrected. The data is output to the bus 35 as 32-bit parallel data 38. As a result, the CPU 41 executes a calculation process, for example, a process for calculating an operation command to the external device 23, using the parallel data whose data validity is confirmed.

  Further, as shown in FIG. 5, the CPU 41 performs data input processing, fault monitoring processing, protection / control arithmetic processing, sequence control processing, and data output processing (device control command) every 30 electrical angles. ing. When a calculation result for tripping the external device 23 is obtained in the protection / control calculation processing, an operation command for tripping the external device 23 is output in the data output processing.

  According to this embodiment, data is exchanged between the units via the serial link 7, and the transmission side unit adds an error correction code to the transmission data and outputs it as serial data to the serial link 7. In this unit, the validity of the data itself is determined based on the error correction code of the received data, and when an abnormality is detected, the received data is corrected and the corrected data is received. Even if the error occurs, it is possible to prevent erroneous data from being used, and as a result, it is possible to prevent an erroneous operation command from being output to the external device 23, thereby contributing to improvement in reliability. be able to.

  In this embodiment, since the serial transfer type serial link 7 is used instead of the parallel transfer type system bus, the number of signal lines and parts is reduced as compared with the case where the parallel transfer type system bus is used. This can contribute to reduction of power consumption and radiation noise.

It is a block block diagram of the digital protection and control apparatus which shows one Embodiment of this invention. It is a block diagram of an analog input unit, a protection / control sequence calculation unit, a digital input unit, and a digital output unit. It is a block block diagram of a transmission circuit and a reception circuit of a serial transfer method. It is a specific block diagram of a transmission circuit and a reception circuit when performing 32-bit data transfer. It is a time chart for demonstrating the processing method when performing time division multiplex processing in CPU.

Explanation of symbols

1 Digital Protection / Control Device 2 Input Transformer 3 Analog Input Unit 4 Protection / Control Sequence Operation Unit 5 Display Unit 6 Human Interface Unit 7 Serial Link 8 Digital Input Unit 9 Network Interface Unit 10 Digital Output Unit 23 External Device 33 Transmitting Circuit 34 Reception circuit 50 Error correction code generation circuit 51 Signal synthesis circuit 52 Serial conversion circuit 53 Transmission buffer 54 1-bit error correction circuit 55 Signal separation circuit 56 Parallel conversion circuit 57 Reception buffer

Claims (3)

System information is input as an analog signal from the power system to be protected, the input analog signal is converted into digital parallel data, processed, and the processing result is output to the serial link. Information is input and processed as digital parallel data, a digital input unit that outputs the processing result to the serial link, and a protection / control operation is executed based on the information from the serial link. A protection / control arithmetic unit that outputs to the serial link, and a digital that outputs and processes the operation result of the protection / control arithmetic unit from the serial link and outputs an operation command generated based on this processing to the control target An output unit,
Among the units, a unit that outputs serial data to the serial link converts parallel data to which an error correction code is added into serial data, outputs the serial data to the serial link, and inputs serial data from the serial link. The unit receives serial data from the serial link and converts it into parallel data, separates the converted parallel data into an error correction code and signal data, and the signal data from the separated error correction code and signal data. A digital protection / control apparatus which judges the validity of itself, processes the signal data as parallel data when normal, corrects the abnormal bit when there is an abnormal bit, and processes the corrected signal data as parallel data. System information is input as an analog signal from the power system to be protected, the input analog signal is converted into digital parallel data, processed, and the processing result is output to the serial link. Information is input and processed as digital parallel data, a digital input unit that outputs the processing result to the serial link, and a protection / control operation is executed based on the information from the serial link. A protection / control arithmetic unit that outputs to the serial link, and a digital that outputs and processes the operation result of the protection / control arithmetic unit from the serial link and outputs an operation command generated based on this processing to the control target An output unit,
The system information input unit, the digital input unit, and the protection / control arithmetic unit convert parallel data to which an error correction code is added into serial data and output the serial data to the serial link. The control arithmetic unit receives serial data from the serial link and converts the serial data into parallel data, separates the converted parallel data into error correction codes and signal data, and converts the converted error correction code and signal data from the error correction code and signal data. Digital protection and control by judging the validity of the signal data itself, processing the signal data as parallel data when normal, correcting the abnormal bits when there are abnormal bits, and processing the corrected signal data as parallel data apparatus. A system information input unit that inputs system information as an analog signal from the power system to be protected, converts the input analog signal into parallel data using a digital signal, converts the parallel data into serial data, and outputs the serial data to a serial link; A digital input unit that inputs status information from a control target as parallel data using digital signals, converts the input parallel data to serial data and outputs the serial data to the serial link, and inputs serial data from the serial link to parallel data. A protection / control operation unit that executes protection / control operation according to the converted parallel data, converts the parallel data resulting from the operation into serial data, and outputs the serial data to the serial link; and serial data from the serial link The Force and converts the serial data inputted to the parallel data to generate an operation command, the generated operation command and a digital output unit that outputs to the control object,
The system information input unit, the digital input unit, and the protection / control arithmetic unit each have transmission means for converting the parallel data into the serial data and transmitting it to the serial link.
The digital output unit and the protection / control arithmetic unit each have a receiving means for receiving serial data from the serial link and converting it into parallel data,
Each of the transmission means includes error correction code generation means for generating an error correction code from the parallel data, signal combining means for combining the parallel data and the error correction code, and parallel data obtained by combining the signal combining means. Serial conversion means for converting into serial data, and transmission buffer means for transmitting the serial data converted by the serial conversion means to the serial link,
Each receiving means includes a receiving buffer means for receiving serial data from the serial link, a parallel converting means for converting serial data received by the receiving buffer means into parallel data, and parallel data converted by the parallel converting means. The signal separation means for separating the error correction code and the signal data, the correctness of the signal data itself is determined from the error correction code and the signal data separated by the signal separation means, and the signal data is left as it is in a normal state. A digital protection / control apparatus comprising correction means for outputting as parallel data, correcting an abnormal bit when there is an abnormal bit, and outputting the corrected signal data as parallel data.

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