JP2005217704A - Semiconductor device of detecting physical quantity distribution, method of driving and control of semiconductor device, and driving control apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent problems of reduction in saturation charge quantity due to fluctuation of a well potential, a fixed pattern noise, and saturation shading, in a CMOS sensor in which a unit pixel is formed of a light-receiving element and three transistors. <P>SOLUTION: A transition time (fall time) in turning off a voltage of a drain line 57 common among all the pixels is made long for any of transition time of turning off reset wiring and transfer wiring. Therefore, a multi-value pulse such as three or four value in which the level shifts gradually by a combination of control pulses having different levels is used as a control pulse for driving wiring. By this multiple level, voltage response in driving the vertical drain line 57 is preferably made slower than any of transition time at the time of turning off/on in voltage response in driving the reset wiring and transfer wiring, when seen from a big point of view. The voltage response is preferably set at a value within a range of 5-10,000 times, and more preferably within a range of 50-600 times. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a physical quantity distribution detecting semiconductor device in which a plurality of unit components are arranged, and a drive control method thereof. More specifically, for example, a plurality of unit components that are sensitive to electromagnetic waves input from the outside such as light and radiation are arranged, and the physical quantity distribution converted into an electric signal by the unit components is addressed. The present invention relates to a semiconductor device for detecting a physical quantity distribution, such as a solid-state imaging device, which can be arbitrarily selected by control and read as an electric signal, and a drive control method and drive control device thereof.

  In particular, a semiconductor of a type that does not have a dedicated selection transistor for selecting a unit component to be read but has a substantial unit component composed of a conversion element sensitive to light and radiation and three transistors. The present invention relates to a drive control technique in an apparatus.

  2. Description of the Related Art Physical quantity distribution detection semiconductor devices in which a plurality of unit components (for example, pixels) that are sensitive to electromagnetic waves input from the outside such as light and radiation are arranged in a line or matrix form are used in various fields. ing. For example, in the field of video equipment, a CCD (Charge Coupled Device) type, a MOS (Metal Oxide Semiconductor) type, or a CMOS (Complementary Metal-oxide Semiconductor) type solid state imaging device that detects light in a physical quantity is used. These read out, as an electrical signal, a physical quantity distribution converted into an electrical signal by a unit component (a pixel in a solid-state imaging device).

  Further, in some solid-state imaging devices, an amplifying solid-state imaging device (APS; Active Pixel Sensor) that has a driving transistor for amplification in a pixel signal generation unit that generates a pixel signal corresponding to the signal charge generated in the charge generation unit. There is an amplification type solid-state imaging device including a pixel having a configuration (also called a gain cell). For example, many CMOS solid-state imaging devices have such a configuration. In such an amplification type solid-state imaging device, in order to read out pixel signals to the outside, address control is performed on a pixel unit in which a plurality of unit pixels are arranged, and signals from individual unit pixels are arbitrarily selected. I am trying to read it out. That is, the amplification type solid-state imaging device is an example of an address control type solid-state imaging device.

  For example, an amplification type solid-state imaging device which is a kind of XY address type solid-state imaging device in which unit pixels are arranged in a matrix form an active element (MOS transistor) such as a MOS structure in order to give the pixel itself an amplification function. ) To form a pixel. That is, signal charges (photoelectrons) accumulated in a photodiode which is a photoelectric conversion element are amplified by the active element and read out as image information.

  In this type of XY address type solid-state imaging device, for example, a plurality of pixel transistors are arranged in a two-dimensional matrix to form a pixel unit, and a signal charge corresponding to incident light for each line (row) or each pixel. Accumulation is started, and a current or voltage signal based on the accumulated signal charge is sequentially read out from each pixel by addressing.

  Here, in general, in the CMOS type sensor, the configuration of the unit pixel tends to be complicated because noise is reduced as compared with the CCD. For example, as a general-purpose CMOS sensor, a floating diffusion (FD) that is a diffusion layer having a parasitic capacitance is used as a charge storage unit, and four transistors (TRansistor) are used in a unit pixel. A four-transistor pixel configuration (hereinafter referred to as a 4TR configuration) is well known. Further, a three-transistor pixel configuration (hereinafter referred to as a 3TR configuration) that has three transistors in the unit pixel portion and can reduce the pixel size has been proposed (for example, see Patent Document 1).

Japanese Patent No. 2708455

<Conventional Unit Pixel Configuration; 4TR Configuration>
FIG. 16A is a diagram illustrating a configuration example of a unit pixel 3 having a conventional 4TR configuration. The unit pixel 3 having a 4TR configuration includes a charge generation unit 32 having both a photoelectric conversion function for converting light into a charge and a charge storage function for storing the charge, and a charge reading unit (transfer gate unit / read gate unit). ) For amplifying a source follower configuration which is an example of a detection element for detecting a potential change of a read selection transistor 34 which is an example), a reset transistor 36 which is an example of a reset gate unit, a vertical selection transistor 40, and a floating diffusion 38. A transistor 42 is included.

  The read selection transistor 34 is driven by the transfer drive buffer 150 via a transfer wiring (read selection line) 55. The reset transistor 36 is driven by the reset driving buffer 152 via the reset wiring 56. The vertical selection transistor 40 is driven by the selection drive buffer 154 via the vertical selection line 52.

  The unit pixel 3 includes a pixel signal generation unit 5 having an FDA (Floating Diffusion Amp) configuration including a floating diffusion 38 which is an example of a charge injection unit having a function of a charge storage unit. The floating diffusion 38 is a diffusion layer having parasitic capacitance.

  The reset transistor 36 in the pixel signal generation unit 5 has a source connected to the floating diffusion 38 and a drain connected to the power supply VDD, and a reset pulse RST is input from the reset drive buffer 152 to the gate (reset gate RG).

  The vertical selection transistor 40 has a drain connected to the power supply VDD, a source connected to the drain of the amplification transistor 42, and a gate (in particular, a vertical selection gate SELV) connected to a vertical selection line 52. A vertical selection signal is applied to the vertical selection line 52. The amplification transistor 42 has a gate connected to the floating diffusion 38, a drain connected to the source of the vertical selection transistor 40, and a source connected to the vertical signal line 53 via the pixel line 51.

  In such a configuration, since the floating diffusion 38 is connected to the gate of the amplifying transistor 42, the amplifying transistor 42 sends a signal corresponding to the potential of the floating diffusion 38 (hereinafter referred to as FD potential) via the pixel line 51. To the vertical signal line 53. The reset transistor 36 resets the floating diffusion 38. The read selection transistor (transfer transistor) 34 transfers the signal charge generated by the charge generator 32 to the floating diffusion 38. A large number of pixels are connected to the vertical signal line 53. To select a pixel, the vertical selection transistor 40 is turned on only for the selected pixel. Then, only the selected pixel is connected to the vertical signal line 53, and the signal of the selected pixel is output to the vertical signal line 53.

  As described above, the unit pixel 3 having the 4TR configuration generally includes the vertical selection transistor 40 for the purpose of selecting a pixel, and the unit pixel 3 in most current CMOS sensors has a selection transistor. ing.

<Conventional Unit Pixel Configuration; 3TR Configuration>
On the other hand, FIG. 16B is a diagram illustrating a configuration example of the unit pixel 3 having a conventional 3TR configuration. The unit pixel 3 having the 3TR configuration corresponds to the charge generation unit 32 (for example, a photodiode) that generates a signal charge corresponding to the received light by performing photoelectric conversion, and the signal charge generated by the charge generation unit 32. Each has an amplifying transistor 42 connected to the drain line (DRN) for amplifying the signal voltage, and a reset transistor 36 for resetting the charge generation unit 32. In addition, a read selection transistor (transfer gate portion) 34 that is scanned from a vertical shift register (not shown) via a transfer wiring (TRF) 55 is provided between the charge generation portion 32 and the gate of the amplification transistor 42. Yes.

  The gate of the amplifying transistor 42 and the source of the reset transistor 36 are connected to the charge generation unit 32 via the read selection transistor 34, and the drain of the reset transistor 36 and the drain of the amplifying transistor 42 are connected to the drain line. The source of the amplifying transistor 42 is connected to the vertical signal line 53. The read selection transistor 34 is driven by the transfer drive buffer 150 via the transfer wiring 55. The reset transistor 36 is driven by the reset driving buffer 152 via the reset wiring 56. Both the transfer drive buffer 150 and the reset drive buffer 152 operate with a reference voltage of 0 V and a binary power supply voltage. In particular, the low level voltage supplied to the gate of the conventional read selection transistor 34 in this pixel is 0V.

  In the unit pixel 3 having the 3TR configuration, the floating diffusion 38 is connected to the gate of the amplifying transistor 42 as in the 4TR configuration, so that the amplifying transistor 42 outputs a signal corresponding to the potential of the floating diffusion 38 to the vertical signal. Output to line 53.

  In the reset transistor 36, a reset wiring (RST) 56 extends in the row direction, and a drain line (DRN) 57 is common to most pixels. The drain line 57 is driven by a drain drive buffer (hereinafter referred to as a DRN drive buffer) 140. The reset transistor 36 is driven by the reset drive buffer 152 and controls the potential of the floating diffusion 38. Here, in the technique described in Patent Document 1, the drain line 57 is separated in the row direction. However, since the drain line 57 has to pass a signal current of pixels for one row, it is actually in the column direction. Wiring is common to all rows so that current can be passed through.

  The signal charge generated by the charge generation unit 32 (photoelectric conversion element) is transferred to the floating diffusion 38 by the read selection transistor 34.

  Here, unlike the 4TR configuration, the unit pixel 3 having the 3TR configuration is not provided with the vertical selection transistor 40 connected in series with the amplification transistor 42. A large number of pixels are connected to the vertical signal line 53, but the pixels are selected by controlling the FD potential instead of the selection transistor. Usually, the FD potential is set to low. When selecting a pixel, the signal of the selected pixel is output to the vertical signal line 53 by setting the FD potential of the selected pixel to high. Thereafter, the FD potential of the selected pixel is returned to low. This operation is performed simultaneously for one row of pixels.

  In order to control the FD potential in this way, 1) when the selected row FD potential is made high, the drain line 57 is made high, and the FD potential is made high through the reset transistor 36 of the selected row. When returning the row FD potential to low, the drain line 57 is set low and the FD potential is set low through the reset transistor 36 of the selected row.

  However, when the inventor of the present application prototyped a solid-state imaging device (device) having the unit pixel 3 having the 3TR configuration, the following problems were recognized.

  1) When a pixel is driven to read out a signal, a substrate in the pixel (referred to as a pixel well) is shaken by coupling. In the process in which the pixel well potential fluctuates, there is a phenomenon in which the fluctuation of the pixel well potential increases or the relaxation time of the pixel well to a steady state increases.

  2) As the fluctuation of the pixel increases and the relaxation time increases, the signal charge (electrons) stored in the charge generation unit 32 including a photosensitive element such as a photodiode is transferred to a node such as a floating diffusion. Leakage is observed.

  3) When the signal charge leaks to the floating diffusion, a phenomenon such as a decrease in saturation charge amount, fixed noise, or a difference in characteristics between the peripheral pixel and the central pixel causes a shading phenomenon. The maximum amount of charge (the number of saturated electrons) that can be stored in the conversion element is small in the center. These problems are particularly noticeable when the wiring that is the entire wiring is changed from the high level in the on state to the low level in the off state.

  With regard to this problem, the inventor of the present application analyzed the phenomenon and clarified the following.

  A) Since the drain line 57 is a wiring that extends over almost the entire area of the pixel portion, the potential of the well of the pixel portion (hereinafter, the description will continue to be representatively described as a P-type well) fluctuates when the drain line 57 is driven. A contact for applying a potential to the P-well is placed around the pixel portion. However, depending on whether the contact is near or far from the contact, the P-well potential varies differently and changes the characteristics of the pixel. In particular, when the drain line 57 is set to low, the P well is shaken negatively, so that the signal charge leaks from the charge generation unit 32 to the floating diffusion 38 and the P well. The central portion far from the P-well contact has a large fluctuation in the P-well potential, and the number of saturated electrons decreases at the central portion. This is particularly called saturation shading.

  B) As one method for preventing the fluctuation of the P well potential, a bias wiring for fixing the well potential is prepared, and a contact for connecting the bias wiring and the well is provided for each pixel or every several pixels or several tens of pixels. It is conceivable to provide a substrate contact or a well contact. However, in the unit pixel 3 having the 3TR configuration in which the selection transistor is omitted, the selection transistor is omitted for the purpose of reducing the pixel size, and having a well capacitor in the pixel goes against reducing the pixel size. It is difficult to hit a wellcon in a pixel.

  C) If the well contact cannot be formed, the resistance between the pixel well and the substrate increases, and the above problems 1) to 3) cannot be solved.

  The above problems and analysis results are all new matters that do not exist in a CMOS sensor of a type in which pixels are selected by the vertical selection transistor 40.

  The present invention has been made in view of the above circumstances, and a physical quantity distribution detecting semiconductor device having a unit pixel having a configuration in which a selection transistor used for pixel selection in a 4TR configuration is omitted (typically, Providing drive technology that can improve problems caused by fluctuations in substrate potential in pixels, such as reduced saturation charge, fixed pattern noise, or saturation shading, when using solid-state imaging devices) The purpose is to do.

  The present invention analyzes a problem in a unit pixel having a three-transistor configuration described in the prior art and, in detail, will be described in an embodiment described later, finds a solution to the problem (operation principle and its effect). That's what was done.

  That is, when the voltage of the drain wiring, which is substantially common to all the pixels, is changed from the on state to the off state (for example, a fall time when the NMOS sensor is swung to a low level), or when the off state is turned on. If the time (for example, rise time when swinging high for an NMOS sensor) is lengthened, fluctuations in well potential can be reduced. This reduces the amount of saturation charge by aligning the characteristics of the peripheral and central pixels, reducing the saturation shading amount and fixed pattern noise, and there is an optimum value depending on the device drive conditions. It was made by discovering such points.

  That is, the drive control method according to the present invention is a solid-state imaging device including a unit component (for example, unit pixel) having a configuration including a charge generation unit that generates a signal charge corresponding to an incident electromagnetic wave and three transistors. Drive control method for driving a semiconductor device for physical quantity distribution detection, etc., in which the transition time at the time of OFF or ON in the voltage response when driving the drain wiring is when driving the reset wiring and the transfer wiring The drain wiring drive voltage is set to be slower than any of the off-time and on-time transition times in the voltage response, preferably in the range of 5 to 10,000 times and more preferably 50 to 600 times. It was decided to drive dull.

  A drive control device according to the present invention is a device for driving a semiconductor device for physical quantity distribution detection using the drive control method according to the present invention, wherein the drain wiring is a combination of a plurality of control pulses having different levels. Thus, a drive control unit that is driven by a multi-value pulse whose level is gradually changed is provided.

  The drive control unit, for example, has a level stepwise by a combination of a plurality of control pulses having different levels based on a pulse signal generation unit that generates a plurality of control pulses and a plurality of control pulses generated by the pulse signal generation unit. It is preferable to have a multi-level pulse generation unit that generates a multi-level pulse that transitions.

  A semiconductor device for physical quantity distribution detection according to the present invention is a semiconductor device configured to be able to carry out the drive control method according to the present invention, and the transition time at the time of OFF or ON in the voltage waveform of the drain wiring, The reset wiring driven by the reset driving buffer and the transfer wiring driven by the transfer driving buffer are made slower than the transition time at each OFF time, preferably 5 times or more and 10,000 times or less, more preferably Is configured to be able to be driven by dulling the drive voltage of the drain wiring so as to be in the range of 50 to 600 times.

  The transition time of the drive pulse itself applied to the reset drive buffer and the transfer drive buffer has a sufficiently short fall and rise, and can be said to be a “pulse” in binary (on and off) drive as a general concept. do it.

  Various mechanisms are conceivable as specific mechanisms for satisfying the above-described conditions for the transition time when the drain wiring is off or on. For example, the W / L ratio of the transistor connected to the drain wiring is 1 than the W / L ratio of the transistor connected to the transfer wiring and the W / L ratio of the transistor connected to the reset wiring. It is conceivable to set within a range of several times to several thousand times.

  Also, a method of providing a resistance element for limiting the drive current between the off-side reference wiring of the drain drive buffer and the reference power supply that defines the off-side voltage with respect to the drain wiring, or a current source that defines the drive current It is also possible to provide a method.

  However, these methods are all analog methods, and it is not always easy to manage and handle the transition time. In addition, changing the W / L ratio of a transistor requires a design change of the device itself, and thus cannot be applied to an existing device.

  Therefore, in the present invention, the level of the control pulse itself for driving the drain wiring is changed stepwise by a combination of a plurality of control pulses having different levels instead of the conventional binary driving, that is, simple on / off driving. Use multivalued pulses.

  In order to cause the level to change stepwise, it is impossible with binary values, and driving is performed using multi-valued pulses with levels of at least three values, preferably four values or more. And by this multi-value level, preferably, when the voltage response when driving the drain wiring is viewed as a whole, it is preferably 5 times or more and 10,000 times or less, more preferably 50 to 600 times. To be in range.

  For example, a device that has been driven with a binary value of 0 V (off) / 3 V (on) in the past is driven with 0 V, 1 V, and 3 V, for example, with three values. In this way, at the time of transition from on to off, driving can be performed so that the voltage gradually changes from 3V → 1V → 0V.

  The same applies to the transition from OFF to ON. For devices that have been driven with binary values of 0 V (off) / 3 V (on), for example, three values are 0 V, 1 V, and 3 V. By driving at the time of transition from OFF to ON, it is possible to drive so that the voltage gradually changes from 0V → 1V → 3V.

  If the output timing between a plurality of control pulses can be adjusted, the transition time can be freely set by adjusting the switching timing from 3V → 1V → 0V or 0V → 1V → 3V. It is also easy to make the switching timing asymmetric at the time of transition to off and transition to on, and the voltage change can be set relatively freely.

  As a result, when viewed globally, the transition time at the off time or the on time is made slower than the transition time at each off time or the on time in the voltage response when driving the reset wiring and the transfer wiring. For example, the drain wiring drive voltage can be dulled so as to be in the range of 5 times or more and 10,000 times or less, more preferably 50 to 600 times.

  By using multi-level pulse drive with four or more levels, or by making the pulse voltage setting value different (asymmetric) at the time of transition to off and on, the transition process can be further improved. It is possible to finely adjust the waveform response (voltage change).

  Note that the multi-value pulse driving as described above does not necessarily need to be performed at both the off time and the on time, and may function at least one of them, preferably at the time of transition from on to off. For example, in the case of ternary driving, the voltage is driven so that the voltage gradually changes from 3V → 1V → 0V at the transition to OFF, while the driving from 0V → 3V is performed at the transition to ON as in the binary driving. May be. This is because problems such as a decrease in saturation charge, fixed pattern noise, or saturation shading caused by the substrate in the pixel swaying due to coupling change from an on-state high level to an off-state low level. This corresponds to what is noticeable in

  According to the present invention, the drain wiring is driven by a multi-value pulse of ternary, quaternary, or higher levels. As a result, when viewed from a standpoint, the transition time when the drain voltage is turned off or on can be made slower than any of the transition times when the reset wiring or transfer wiring is turned off. For example, the length can be increased to 5 times or more and 10,000 times or less.

  For this reason, even when a device including a unit pixel having a configuration in which a selection transistor used for pixel selection in the 4TR configuration is omitted, the substrate potential in the pixel is fluctuated. It has become possible to reduce phenomena such as a decrease in saturation charge, fixed pattern noise, and saturation shading.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the following, a case where a CMOS image sensor, which is an example of an XY address type solid-state imaging device, is used as a device will be described as an example. The CMOS image sensor will be described on the assumption that all pixels are made of NMOS.

  However, this is merely an example, and the target device is not limited to a MOS imaging device. All the semiconductor device for physical quantity distribution detection in which a plurality of unit components that are sensitive to electromagnetic waves input from outside such as light and radiation are arranged in a line or matrix form, and all implementations described later. Forms are applicable as well.

<Configuration of solid-state imaging device>
FIG. 1 is a schematic configuration diagram of a CMOS solid-state imaging device according to an embodiment of the present invention. The solid-state imaging device 1 is applied as an electronic still camera that can capture a color image. For example, in a still image capturing mode, a mode for sequentially reading all pixels is set. .

  The solid-state imaging device 1 includes an imaging unit in which pixels including light receiving elements that output a signal corresponding to the amount of incident light are arranged in rows and columns (that is, in a two-dimensional matrix), and a signal output from each pixel is a voltage. It is a signal and is a column type in which a CDS (Correlated Double Sampling) processing function section is provided for each column. That is, as illustrated in FIG. 1A, the solid-state imaging device 1 includes a pixel unit (imaging unit) 10 in which a plurality of unit pixels 3 are arranged in rows and columns, and a drive provided outside the pixel unit 10. A control unit 7 and a CDS processing unit (column circuit) 26 are provided. As the drive control unit 7, for example, a horizontal scanning circuit 12 and a vertical scanning circuit 14 are provided.

  In FIG. 1A, some of the rows and columns are omitted for the sake of simplicity, but in reality, tens to thousands of pixels are arranged in each row and each column. Further, as another component of the drive control unit 7, a timing generator 20 that supplies a pulse signal with a predetermined timing to the horizontal scanning circuit 12, the vertical scanning circuit 14, and the CDS processing unit 26 is provided. Each element of these drive control units 7 is formed integrally with a pixel unit 10 in a semiconductor region such as single crystal silicon using a technique similar to a semiconductor integrated circuit manufacturing technique, and is a solid-state imaging which is an example of a semiconductor system It is configured as an element (imaging device). Each unit pixel 3 of the pixel unit 10 is connected to ground (GND) as a master reference voltage that defines the reference voltage of the entire device.

  The timing generator 20 is an embodiment of a drive control unit according to the present invention that includes a pulse signal generation unit that generates a plurality of control pulses for driving the vertical drain line 57. By providing only the pulse signal generation unit, the drive control device according to the present invention may be configured. A so-called semiconductor integrated circuit (IC) for a timing generator is used.

  The timing generator 20 may be provided as another semiconductor integrated circuit independently of other functional elements such as the pixel unit 10 and the horizontal scanning circuit 12. In this case, an imaging apparatus is constructed by the imaging device including the pixel unit 10 and the horizontal scanning circuit 12 and the timing generator 20. This imaging device may be provided as an imaging module in which peripheral signal processing circuits, power supply circuits, and the like are also incorporated.

  The unit pixel 3 is connected to a vertical scanning circuit 14 via a vertical control line 15 and a CDS processing unit 26 via a vertical signal line 19 for selecting a vertical column. Here, the vertical control line 15 indicates all the wiring that enters the pixel from the vertical scanning circuit 14. For example, in the pixel of FIG. 16B, when the transfer wiring 55 and the reset wiring 56 and the drain line enters from the vertical scanning circuit 14, the drain line is also included.

  The horizontal scanning circuit 12 and the vertical scanning circuit 14 are configured to include, for example, a decoder, and start a shift operation (scanning) in response to a driving pulse supplied from the timing generator 20. Therefore, the vertical control line 15 includes various pulse signals (for example, a reset pulse RST, a transfer pulse TRG, a DRN control pulse DRN, etc.) for driving the unit pixel 3.

  In addition to the timing generator 20, the horizontal scanning circuit 12 and the vertical scanning circuit 14 may be included to constitute the drive control device according to the present invention. In this case, for example, in the vertical scanning circuit 14, the level is stepwise by combining a plurality of control pulses having different levels based on the plurality of control pulses generated by the timing generator 20 for driving the vertical drain line 57. It is preferable to provide a multi-level pulse generation unit that generates a multi-level pulse that transitions.

  The CDS processing unit 26 as a column circuit is provided for each column, receives a signal of pixels for one row, and processes the signal. For example, on the basis of two sample pulses such as the sample pulse SHP and the sample pulse SHD given from the timing generator 20, the signal level immediately after the pixel reset is applied to the voltage mode pixel signal input via the vertical signal line 19 ( (Noise level) and signal level are processed. As a result, noise signal components called fixed pattern noise (FPN) and reset noise are removed. Note that an AGC (Auto Gain Control) circuit, an ADC (Analog Digital Converter) circuit, or the like may be provided in the same semiconductor region as the CDS processing unit 26 as necessary after the CDS processing unit 26.

  The horizontal scanning circuit 12 defines a horizontal readout column (selects an individual column circuit in the CDS processing unit 26), and a CDS processing unit 26 according to a readout address defined by the horizontal decoder 12a. And a horizontal drive circuit 12b for guiding each signal to the horizontal signal line 18. The vertical scanning circuit 14 defines a vertical readout row (selects a row of the pixel unit 10), and controls the unit pixel 3 on the readout address (row direction) defined by the vertical decoder 14a. And a vertical drive circuit 14b that drives the line by supplying pulses.

  Note that the vertical decoder 14a selects a row for electronic shutter, in addition to a row from which a signal is read. The timing generator 20 outputs a horizontal address signal to the horizontal decoder 12a and a vertical address signal to the vertical decoder 14a, and each decoder 12a, 14a receives it and selects a corresponding row or column.

  The voltage signal processed by the CDS processing unit 26 is transmitted to the horizontal signal line 18 via a horizontal selection switch (not shown) driven by a horizontal selection signal from the horizontal scanning circuit 12, and further input to the output buffer 28. After that, it is supplied to the external circuit 100 as the imaging signal S0. That is, in the column-type solid-state imaging device 1, the output signal (voltage signal) from the unit pixel 3 is output in the order of the vertical signal line 19 → CDS processing unit 26 → horizontal signal line 18 → output buffer 28. The drive is such that the pixel output signals for one row are sent in parallel to the CDS processing unit 26 via the vertical signal line 19, and the signals after the CDS processing are serially output via the horizontal signal line 18. The vertical control line 15 controls selection of each row.

  As long as the drive for each vertical column or horizontal column is possible, the pulse signal is arranged in the row direction or the column direction with respect to the unit pixel 3, that is, the physicality of the drive clock line for applying the pulse signal. The general wiring method is free.

  As the external circuit 100 of the solid-state imaging device 1, a circuit configuration corresponding to each photographing mode is adopted. For example, as shown in FIG. 1B, an A / D (Analog to Digital) conversion unit 110 that converts an analog imaging signal S0 output from the output buffer 28 into digital imaging data D0, and A / D conversion A digital signal processor (DSP) 130 that performs digital signal processing based on the imaging data D0 digitized by the unit 110.

  The digital signal processing unit 130 performs, for example, color separation processing to generate image data RGB representing each image of R (red), G (green), and B (blue), and outputs other signals to the image data RGB. Processing is performed to generate image data D2 for monitor output. In addition, the digital signal processing unit 130 includes a functional unit that performs signal compression processing for storing imaging data in a recording medium.

  The external circuit 100 also includes a D / A (Digital to Analog) converter 136 that converts the image data D2 digitally processed by the digital signal processor 130 into an analog image signal S1. The image signal S1 output from the D / A converter 136 is sent to a display device such as a liquid crystal monitor (not shown). The operator can perform various operations while viewing the display image of the display device.

  Although details of the unit pixel 3 are not shown, the unit pixel 3 has the same configuration as that of the three-transistor configuration shown in FIG. The drain line 57 is common to most of the pixels of the pixel portion 10 and extends in the column direction and is common at the end of the pixel portion 10 or is a lattice-like shape having holes on the charge generation portion 32. Wiring. There may be some pixels such as dummy pixels that have separate drain lines 57. Further, although not shown in the figure, a wiring and a contact for supplying a potential of the P well are provided around the pixel portion 10.

  Since the drain line 57 is connected to most or all of the pixels, when the drain line 57 is swung low, the potential of the P well of the pixel unit 10 fluctuates, and the fluctuation width and time are different between the periphery and the center. The charge leaking from the charge generation unit 32 increases in the center, and the saturation signal charge in the center decreases. In other words, as described in the section of the prior art, this causes a problem that the characteristics of the peripheral pixel and the central pixel are different.

  2 to 10 are diagrams for explaining the problem that the pixel well is shaken by the coupling and the countermeasure approach. First, FIG. 2 is a diagram for specifically explaining the problem of the pixel well being shaken by the coupling and the saturation shading caused by this. As a device, a CMOS sensor conforming to the VGA standard of about 300,000 pixels (640 × 480 pixels) was used. The unit pixel 3 has the three-transistor configuration shown in the second example of the prior art, and the pixel pitch is 4.1 μm. VGA is an abbreviation for “Video Graphics Array” and defines a graphics mode and display resolution.

  The power supply voltage supplied to the prototype device is 3.0 V, and the clock frequency is 6 MHz (frame rate 13.3 fps). The prototype device can change the low level of the transfer gate drive voltage (hereinafter also referred to as the transfer gate low level), and the low level potential (here, 0 V) of the drain line 57 is applied from the outside of the device. It has a supply terminal (DRN drive buffer ground side wiring terminal) DRNL. The other driving for the unit pixel 3 is performed at 0 V (grounding; GND) and the power supply voltage (3.0 V).

  As a measurement method of saturation shading, a signal obtained by the output buffer 28 is observed with a waveform monitor such as an oscilloscope while irradiating a light amount sufficiently saturated by the charge generation unit, and a peripheral monitor The difference from the central part was measured as the shading amount. As shown in FIG. 2, in the prototype device used for verification, a large difference is seen between the peripheral portion and the central portion. And it turns out that the signal output in a center part is smaller than the signal output in a peripheral part.

  FIG. 3 is a diagram showing a measurement circuit for examining the voltage change of the drain line 57. The control resistor 146 is inserted between the ground side wiring terminal DRNL and GND of the DRN drive buffer 140 of the prototype device, and the voltage of the control resistor 146 is measured. The voltage source 149 is set to 0V. The DRN drive buffer 140 is provided in the vertical drive circuit 14b of the vertical scanning circuit 14.

  When a DRN control pulse (pulse-shaped DRN control signal) is input to the DRN drive buffer 140 (not shown) of the prototype device, the voltage waveform measured by the control resistor 146 reflects the current waveform flowing through the DRN drive buffer 140. The voltage waveform in the drain line 57 is also represented.

  FIG. 4 is a diagram illustrating the relationship between the resistance value and the saturation shading when the control resistor 146 is inserted between the ground side wiring terminals DRNL and GND and the DRN control pulse is blunted. In the figure, the low level voltage of the transfer gate is indicated by Vtl. The resistance value used for the measurement is 1,10,47,150,330,680,1000 (unit is Ω) according to the E12 series.

  As shown in FIG. 4A, in the case of Vtl = −0.6 V, the change in the saturation shading amount is small in the range of 1Ω to 10Ω, and there is a sign of change in the saturation shading amount from about 10Ω. A big change is seen. That is, if the resistance value of the control resistor 146 is smaller than about 10Ω, it does not affect the current device. If it is about 10Ω or more, the effect of reducing the saturation shading can be obtained, and if it is 50Ω or more, a significant effect can be obtained.

  Further, as shown in FIG. 4B, when Vtl = −1V, a large change is seen in the saturation shading amount even in the range of 1Ω to 10Ω, the smallest in the range of 50Ω to 200Ω, and the higher ( The saturation shading amount tends to increase slightly (for example, up to about 200Ω to 1000Ω). That is, when the resistance value of the control resistor 146 is about 10Ω or more, a significant effect of reducing the saturation shading is seen, and about 50 to 200Ω is considered best.

  FIG. 5 is a diagram showing the results shown in FIG. 4 in relation to the fall time of the voltage waveform (transition time at the OFF time) in the control resistor 146 and saturation shading. The drive pulse shape in the CMOS sensor is generally set to fall time and rise time (on-time transition time) of several ns (for example, 1 to 3 ns) for any of the transfer wiring 55, reset wiring 56, and drain line 57. Below. Therefore, if the fall time and the rise time of the voltage waveform appearing at the control resistor 146 are about several ns or less, it can be considered that the device is generally driven under normal conditions.

  As shown in FIG. 5A, when Vtl = −0.6 V, the saturation shading amount changes until the fall time 10 ns corresponding to the range of 1Ω to 10Ω (normally about 3 to 10 times or more). There is a sign of a change in the saturation shading amount from about 10 ns corresponding to about 10Ω, and a large change is seen at 40 ns or more corresponding to about 50Ω.

  That is, focusing on the fall time, if it is smaller than about 10 ns, it does not affect the current device. Further, if it is about 10 ns or more, the effect of reducing the saturation shading can be obtained, and if 40 ns or more, a significant effect can be obtained. This effect continues until a fall time of 10,000 ns (normally about 3000 to 10,000 times or less).

  In addition, as shown in FIG. 5B, when Vtl = −1V, a large change is seen in the saturation shading amount even at 10 ns to 40 ns, and the fall time is 40 ns (usually about 13 to 20 times) or more. In particular, the saturation shading amount is the smallest in a range of 170 to 600 to 1000 ns (about 56 to 1000 times the normal value) corresponding to a resistance value of about 50 to 200 Ω, and more than that (for example, about 1000 ns to 5000 ns) ; About 330 to 5000 times normal), the saturation shading amount tends to slightly increase.

  That is, it is possible to improve the saturation shading by dulling the DRN voltage, and a significant effect of reducing the saturation shading when the fall time is about 40 ns or more is seen, and about 170 to 600 ns (for example, the normal 56 to (About 600 times) is considered the best.

  Thus, although the range in which the effect appears depends on the low level voltage Vtl, the transition time at the off time (in this example, the fall time) is approximately 3 to 10 (on average, 5 times the normal time). Saturation shading can be improved by dulling the DRN voltage in the range of about) to 10,000 (10,000) times, more preferably in the range of about 50 to 600 times.

  6 to 10 are diagrams showing the results of reproducing the fluctuation of the P-well potential by simulation. Each is shown for each value of the control resistor 146. The simulation result is shown here because it was difficult to actually measure the fluctuation of the P well potential. The waveform lines W1 to W4 in each figure are at the respective device positions shown in each figure. Further, as shown in FIG. 6, the waveform line of SEL_0 indicates that of the DRN control pulse, and the waveform line of VSS_D is at the terminal measured in the experiment.

  As shown in the figure, when the value of the control resistor 146 is increased, the fall time of the DRN voltage in the drain line 57 is increased, the fluctuation of the P well potential is reduced, and the difference between the central portion and the peripheral portion is also reduced. I understand. In other words, increasing the value of the control resistor 146 or increasing the fall time of the DRN voltage leads to the uniform characteristics of the peripheral pixel and the central pixel, which improves saturation shading. It can be seen that the effect is high.

  In the configuration of the present embodiment, based on the above analysis result, a configuration for improving saturation shading and the like by dulling the DRN voltage is adopted as a method for improving the problem caused by well shaking. Specifically, a mechanism for controlling the fall time when the drain line 57 is swung low and improving the saturation shading phenomenon is provided. This mechanism will be briefly described. First, when the drain line 57 is swung to a low level, a driving method is adopted in which the fall time is lengthened and the voltage gradually falls.

  As a result, the fluctuation width of the potential of the P well can be reduced, or the P well potential difference between the periphery and the center of the pixel portion 10 can be reduced. In the configuration of the present embodiment, the fall time is significantly (intentionally) longer than that in the normal driving method.

  It can be seen that when the value of the control resistor 146 is increased, the fall time of the DRN voltage in the drain line 57 is lengthened, the fluctuation of the P well potential is reduced, and the difference between the central portion and the peripheral portion is also reduced. In other words, increasing the value of the control resistor 146 or increasing the fall time of the DRN voltage leads to the uniform characteristics of the peripheral pixel and the central pixel, which improves saturation shading. It can be seen that the effect is high.

  In the configuration of the present embodiment, a configuration in which the DRN voltage is blunted is adopted as a technique for improving a problem caused by the substrate potential in the pixel swinging based on the above analysis result. Specifically, a mechanism is provided for controlling the falling time when the drain line 57 is swung low and the rising time when the drain line 57 is swung high by using a multi-level pulse driving technique. The switching timing between the levels is based on the same idea as changing the voltage response according to the resistance value of the control resistor 146, and when viewed from the standpoint, gives the same change as the response change due to the resistance value of the control resistor 146. You may adjust so that you may obtain.

  This mechanism will be briefly described. First, when the drain line 57 is swung to a low level, the pulse voltage for driving the drain is decreased stepwise, so that the driving in the vertical drain line 57 is viewed globally. A driving method is adopted in which the voltage fall time is lengthened and the voltage falls slowly.

  As a result, the fluctuation width of the potential of the P well can be reduced, or the P well potential difference between the periphery and the center of the pixel portion 10 can be reduced. In the configuration of the present embodiment, the fall time is significantly (intentionally) longer than that in the normal driving method.

  As a definition method when “making the fall time significantly longer than in the normal drive method”, a method of specifying the ratio (multiple) of the drive pulse fall time in the normal drive method, A method defined by the ratio of the fall time in correspondence with the number of pixels (more specifically, the driving cycle), or the potential difference between the peripheral portion and the central portion of the P well is equal to or less than a predetermined level (a level at which image quality deterioration is not noticeable) Various definition methods are conceivable, such as a method of defining as a period of time.

  Further, when the ratio is specified by the ratio (multiple) of the drive pulse fall time in the normal drive method, it is not limited to the comparison with the fall time of the DRN voltage in its own normal drive, but in comparison with other drive pulses. You may prescribe. For example, the size of the buffer for driving each wiring may be determined so that the falling time of the DRN voltage is longer than the falling time of the transfer wiring and the reset wiring by a predetermined multiple or more.

  The operation of returning the selected pixel to the non-selected state is performed by setting the DRN control pulse to the low level within the blanking period. When the ratio is specified by the ratio of the fall time in correspondence with the driving cycle, the method of defining the maximum value becomes a problem. For example, the maximum value is defined by the low level period of the DRN control pulse, and is actually within this range. It is recommended to specify the fall time of. In the CMOS sensor of this experiment, the low level period of the DRN control pulse (that is, the off period with respect to the drain line 57) is set to about 600 ns.

  Note that setting the fall time to be equal to or longer than the off period with respect to the drain line 57 is not excluded, and in this experiment, the fall time of 600 ns or more is obtained from the extrapolation curve of the measurement data. In this case, it is required to reach a low voltage enough to return the selected pixel to the non-selected state.

  In any case, in order to solve the problem that the characteristic is different between the peripheral pixel and the central pixel and that the cause is caused by the P-well potential difference, this embodiment This approach is characterized in that the fall time is set to a level at which image quality deterioration (saturation shading phenomenon) due to the P-well potential difference is not noticeable.

  For example, based on the results shown in FIGS. 2 to 10, a falling time that is 10 times or more longer than each falling time of the transfer pulse TRG and the reset pulse RST which are other pulses of the pixel unit 10 is given. For example, the pulse shape in the other part of the CMOS sensor has a fall time of about several ns or less, and this is set so that the DRN voltage at the drain line 57 is 40 ns (nanoseconds) or more. This 40 ns is a period of about half of the pixel clock period when an image is output at 30 frames / second from a VGA (about 300,000 pixels) CMOS sensor. Here, the case of a VGA-compliant CMOS sensor is shown, but it is considered that even a display sensor with other display resolutions may have a period longer than about half of the pixel clock cycle.

  If the display resolution, that is, the total number of pixels is different, the absolute amount of the fall time is naturally different accordingly. Here, the fall time may be a general definition, that is, a transition time from 90 to 10 where the high level is 100 and the low level is 0.

  The same can be said at the transition of the rising edge. When the drain line 57 is swung high, the pulse voltage for driving the vertical drain line 57 is increased stepwise so that it can be seen globally. Then, a driving method is adopted in which the rising time of the driving voltage in the vertical drain line 57 is lengthened and gradually rises. As a result, the fluctuation width of the potential of the P well can be reduced. In the configuration of the present embodiment, this rise time is significantly (intentionally) longer than that in the normal driving method.

  The definition method for “making the rise time significantly longer than in the normal driving method” may be considered in accordance with the definition method for “fall time”. For example, a method defined by a ratio (multiple) of the drive pulse to the rise time in a normal driving method, a method defined by a ratio of the rise time in correspondence with the number of pixels (more specifically, the drive cycle), or a P-well Various definition methods are conceivable, such as a method of defining the time when the potential difference between the peripheral part and the central part is equal to or less than a predetermined level (a level at which image quality deterioration is not noticeable).

  Hereinafter, a specific example of a method for improving the problem caused by the substrate potential in the pixel fluctuating will be described.

  FIG. 11 is a diagram for explaining the basics of a method for controlling the fall time and rise time of the drive voltage applied to the drain line 57 by multi-value pulse driving. Here, ternary driving is illustrated.

  First, FIG. 11A shows a circuit diagram of a basic configuration for driving the unit pixel 3. As shown in the figure, the unit pixel 3 having a 3TR configuration includes a charge generation unit 32 including an embedded photodiode as a photosensitive element that generates a signal charge corresponding to light received by performing photoelectric conversion, and charge generation. An amplifying transistor 42 connected to the drain line (DRN) for amplifying a signal voltage corresponding to the signal charge generated by the unit 32, and a reset transistor 36 for resetting the charge generating unit 32, respectively. Have.

  Further, a read selection transistor (transfer gate portion) 34 that is scanned via the transfer wiring (TRG) 55 is provided between the charge generation portion 32 and the gate of the amplification transistor 42. The read selection transistor 34 functions as a switch for transferring the signal charge generated by the charge generation unit 32 to the floating diffusion 38 as a node.

  The transfer wiring (TRG) 55 is driven by the vertical drive circuit 14b of the vertical scanning circuit 14 shown in FIG. 1, but in this embodiment, the floating switch SW153 is provided at the subsequent stage of the transfer drive buffer 150 of the vertical drive circuit 14b. The transfer driving buffer 150 and the transfer wiring 55 are connected via the floating switch SW153. The floating switch SW153 is turned on when a high level is supplied to its control terminal.

  Note that the floating switch SW153 is not an essential component in that multilevel pulse driving is performed on the vertical drain line 57, which is a characteristic part of the present embodiment, and the transfer wiring 55 and the transfer drive buffer 150 are not essential elements. And may be directly connected to each other.

  The floating switch SW153 functions as a switch for floating the transfer wiring 55 by separating the gate of the read selection transistor 34 from the output of the transfer drive buffer 150. The reason why the floating switch SW153 is provided is as follows.

  When the vertical drain line 57 is changed from the high level to the low level, the P well is pulled in the negative direction. Thereby, the potential under the photodiode of the charge generation unit 32 is also pushed up in the negative direction in the potential diagram. Here, the difference in the way of increasing the potential under the readout selection transistor 34 as the photodiode and the transfer gate TRG is larger in the photodiode, and as a result, the signal charge of the photodiode overflows to the floating diffusion 38. The leakage of the signal charge causes a decrease in the saturation charge amount, fixed pattern noise, or shading.

  Therefore, if the transfer gate TRG (read selection transistor 34) is floated, the load is reduced and the potential of the transfer gate TRG is also boosted in the same manner as the photodiode, so that the signal charge is transferred from the photodiode to the floating diffusion 38. It will not leak.

  That is, it is possible to reduce the leakage of signal charges from the charge generation unit 32, which is generated when the pixel well potential fluctuates when the unit pixel 3 having the 3TR configuration is driven. As a result, it is possible to suppress the reduction of the saturation charge amount, the fixed pattern noise, or the occurrence of shading, and even in the CMOS image sensor including the unit pixel 3 having a 3TR configuration with a small pixel size, the saturation is achieved with low noise. A sensor with a large charge amount can be created.

  The gate of the amplifying transistor 42 and the source of the reset transistor 36 are connected to the charge generation unit 32 via the read selection transistor 34, and the drain of the reset transistor 36 and the drain of the amplifying transistor 42 are connected to the drain line 57, respectively. . The source of the amplifying transistor 42 is connected to the vertical signal line 53.

  The read selection transistor 34 is driven by the transfer drive buffer 150 via the transfer wiring 55. The reset transistor 36 is driven by the reset driving buffer 152 via the reset wiring 56. Both the transfer drive buffer 150 and the reset drive buffer 152 operate with a reference voltage of 0 V and a binary power supply voltage. In particular, the low level voltage supplied to the gate of the conventional read selection transistor 34 in this pixel is 0V.

  On the other hand, the vertical drain line 57 functioning as a selection signal line SEL for determining a selected row is basically a wiring common to all pixels. However, the driving may be divided into several parts in order to reduce the load on the DRN driving buffer 140.

  The DRN drive buffer 140 for driving the vertical drain line 57 is driven by a multilevel drive pulse of three or more levels as a configuration unique to the present embodiment.

  FIG. 11B shows a DRN control pulse DRN for driving the DRN drive buffer 140, that is, a signal for driving the vertical drain line 57, a transfer pulse TRG for driving the read selection transistor 34 as the transfer gate TRG, and a reset transistor 36. It is the timing chart which showed the example timing of reset pulse RST which drives.

  First, in order to reset the charge in the floating diffusion 38, the transfer pulse TRG (low level) is supplied to the transfer drive buffer 150 to lower the transfer wiring 55 to the low level, and at the same time, the reset pulse RST is input. (T10 to t22), the floating diffusion 38 is reset by making the reset transistor 36 active.

  Next, during a period in which the reset transistor 36 is active (t10 to t20), the DRN control pulse DRN is gradually lowered to a low level with three values in the DRN drive buffer 140 that drives the vertical drain line 57 functioning as the selection signal line SEL. After that, it is gradually raised to a high level with three values (t10 to t18).

  After the ternary pulse is supplied stepwise to the vertical drain line 57 in this way to suppress the fluctuation of the P well potential, the reset transistor 36 is made inactive (t20), and the transfer pulse TRG (high level). Is supplied to the transfer drive buffer 150 to activate the read selection transistor 34 (t24 to t26).

  When the read selection transistor 34 is activated, the transfer drive buffer 150 and the transfer wiring 55 are connected and the transfer pulse TRG needs to be transmitted to the gate of the read selection transistor 34. Before supplying the transfer pulse TRG (high level) to 150, the floating switch SW153 is turned on (t22).

  In other words, the floating switch SW153 is turned off before that. By doing this, normally, when the vertical drain line 57 functioning as the selection signal line SEL moves from OFF to ON (that is, up and down), although the fluctuation of the P well potential is greatly seen, the floating switch SW153 is turned on. By turning off and floating the gate of the read selection transistor 34 as a transfer gate, fluctuation of the P well potential is reduced. In combination with reducing the fluctuation of the P well potential by driving the vertical drain line 57 stepwise with the ternary pulse, the effect of reducing the fluctuation of the P well potential is dramatically improved.

  By turning on the floating switch SW153 (t22) and supplying the transfer pulse TRG (high level) to the transfer drive buffer 150 (t24 to t26), the pixel information (signal charge) obtained by the charge generating unit 32 is floated. The charge information is sent to the diffusion 38 and the charge information is read out to the vertical signal line 53 by the amplifying transistor 42.

  After reading the signal charge, the floating switch SW153 is turned off to make the transfer wiring 55 floating (t28).

  Here, as a ternary level for driving the vertical drain line 57, for example, for a device which has been conventionally driven with a binary value of 0 V (off) / 3 V (on), for example, low level = Drive at 0V, middle level = 1V, high level = 3V. By doing so, it is possible to drive so that the voltage gradually changes from 3V → 1V → 0V at the transition from on to off. The same applies to the transition from OFF to ON, and the driving can be performed so that the voltage gradually changes from 0V → 1V → 3V. When viewed globally, the vertical drain line 57 can be driven so as to change gradually.

  Here, the switching timing from 3V → 1V → 0V or 0V → 1V → 3V is substantially equal to “1T”. As a result, when viewed globally, the transition time at the off time or the on time is made slower than the transition time at each off time or the on time in the voltage response when driving the reset wiring and the transfer wiring. For example, the drain wiring drive voltage can be dulled so as to be in the range of 5 times or more and 10,000 times or less, more preferably 50 to 600 times.

  For example, the pulse shape of the DRN voltage output from the DRN drive buffer 140 and driving the drain line 57 can have a fall time of, for example, 40 ns or more. By performing such driving, it is possible to reduce the fluctuation of the P well potential.

  By gently starting up not only at the time of transition from on to off but also at the time of transition from off to on, fluctuation of the P-well potential can be prevented even at the time of transition from off to on. For example, the rising side does not affect the number of saturated electrons. However, it is similar to the falling in that the P-well is shaken and the difference between the periphery and the center is different.

  In addition, when there is a low-voltage N-type diffusion layer in the pixel, it becomes forward biased with the P well, and electrons are injected into the P well, and there is a risk that it enters the charge generation unit 32. is there. Therefore, if time permits, it is preferable to drive so that the rise also becomes gentle. However, since the signal current of the pixel flows when the vertical drain line 57 is high, it is necessary to prevent the voltage from decreasing so as to cause a problem.

  FIG. 12 is a timing chart showing another timing example of the DRN control pulse DRN for driving the DRN drive buffer 140, that is, the signal for driving the vertical drain line 57.

  In the example shown in FIG. 11 (B), the switching timing from 3V → 1V → 0V and 0V → 1V → 3V was made almost uniform. However, in the example shown in FIG. It is adjusted to be asymmetric between falling and rising). For example, when expressed as a ratio, the transition from 3V to 1V is set to “1T” at the transition to OFF, and the transition from 1V to 0V is set to “2T”, while the transition from 1V to 0V at the transition to “ 1T ".

  By doing so, the transition to OFF is relatively slow, and the transition to ON is relatively quick. This has the significance of approximating the drive waveform that appears as a transient response when driven using resistance. Since the switching timing can be easily adjusted by the control of the timing generator 20, the transition process, that is, the voltage change applied to the vertical drain line 57 can be set relatively freely.

  In the example shown in FIG. 12B, an example in which quaternary driving is used instead of ternary driving is shown. Here, a case of driving with four values of 0V, 1V, 2V, and 3V is shown. At the time of transition from on to off, driving is performed so that the voltage changes in order from 3V → 2V → 1V → 0V, At the time of transition from OFF to ON, driving is performed so that the voltage changes in order from 0V → 1V → 2V → 3V, and the switching timing is adjusted uniformly.

  In addition, the example shown in FIG. 12C also shows an example in which quaternary driving of 0V, 1V, 2V, and 3V is used instead of ternary driving, but 3V → 2V at the time of transition from on to off. While driving so that the voltage changes in order from 1V to 0V, at the time of transition from OFF to ON, switching from 0V to 2V to 3V, the transition between OFF and ON The switching timing is adjusted unevenly.

  By doing so, it is possible to drive so that the voltage rises relatively quickly at the time of transition to ON. As a result, the fluctuation of the P-well potential can be prevented at the time of transition from OFF to ON, and it is possible to make it difficult to adversely affect the reading of the pixel signal current by starting up relatively quickly.

  By using 4 values instead of 3 values, the change in voltage can be mitigated by the increase in the usable voltage level, and the setting value of the pulse voltage at the time of transition to OFF and at the time of transition to ON is different. By making (asymmetric), the waveform response in the transition process can be finely adjusted. Compared to the example shown in FIG. 12A, it is possible to approximate a drive waveform that appears as a transient response when driving using a resistor.

  Needless to say, the degree of freedom is further increased if pulse driving is performed with five or more values. However, if the output response of the DRN drive buffer 140 does not follow, the voltage level of the vertical drain line 57 is not changed step by step, but the voltage is substantially changed continuously. Therefore, since it is useless to increase the number of levels extremely, it is sufficient to set the number of stages in consideration of this point.

  FIG. 13 is a diagram illustrating an example in which a transition time control method for controlling the fall time and the rise time of the drive voltage applied to the drain line 57 using a multilevel pulse is applied to a device.

  Here, FIG. 13A is a conceptual diagram paying attention to a circuit that drives the drain line 57, and FIG. 13B is a detailed example of the vicinity of a DRN drive buffer (hereinafter also simply referred to as a buffer) 140 that drives the drain line 57. The figure shown and FIG.13 (C) are figures which show an example of a drive timing.

  As shown in FIG. 13A, the drain line 57 extends in the column direction corresponding to each column of the pixel portion 10, and an output IF (including a DRN drive buffer (hereinafter also simply referred to as a buffer) 140 at the lower end ( Interface) part 143 is connected to the output terminal. The output IF unit 143 is in each column, and a ternary level control pulse (DRN control pulse) for driving the drain line 57 is applied from the outside of the pixel unit 10. In response to this, each output IF unit 143 performs the same drive for the drain line 57 in each column. That is, the drain line 57 in each column is substantially common to all pixels.

  As shown in FIG. 13B, there is provided a level shift unit 142 that receives three types of drain control pulses DRN1, DRN2, and DRN3 and generates multi-level pulses of three levels of 0V, 1V, and 3V. An output IF unit 143 that drives the drain line 57 is disposed between the drain line 57 and the level shift unit 142. The output IF unit 143 is configured to use both the DRN drive buffer 140 and the switch corresponding to the three levels. The drain control pulses DRN1, DRN2, and DRN3 are supplied from the timing generator 20 shown in FIG.

  In other words, the timing generator 20 functions as a pulse signal generation unit that generates a plurality of DRN control pulses DRN1, DRN2, and DRN3, and supplies a combination of a plurality of DRN control pulses to the vertical scanning circuit 14, thereby having different levels. A multi-value pulse that gradually changes from a high level to a low level and from a low level to a high level is generated by a combination of a plurality of DRN control pulses, and the vertical drain line 57 is driven by the generated multi-value pulse. It functions as a drive control device.

  The level shift unit 142 transitions from a high level to a low level and from a low level to a high level in a stepwise manner by combining a plurality of DRN control pulses having different levels based on the plurality of DRN control pulses from the timing generator 20. It functions as a multilevel pulse generator that generates multilevel pulses.

  In this way, by applying the transition time control method of the vertical drain line 57 using the multi-level DRN control pulse to the device, the DRN control pulse applied to the vertical drain line 57 via the DRN drive buffer 140 is changed. The fall time and the rise time can be set to 40 ns or more, for example. Thereby, by reducing the fluctuation of the P well potential, it is possible to solve the problem of reduction of the saturation charge amount that the number of saturated electrons is small in the central portion of the pixel portion 10, and to reduce the P well potential difference to a practical level. Image quality deterioration such as saturation shading and fixed pattern noise can be suppressed and improved.

  FIG. 14 is a diagram showing another example (hereinafter referred to as a modified example) in which the transition time control method of the vertical drain line 57 using the multi-level DRN control pulse is applied to the device. As shown in FIG. 14, this modification is characterized in that the drain line 57 is driven from the lateral direction of the pixel portion 10. A vertical drain line 57 is connected to the output terminal of the DRN drive buffer 140 at the left and right ends of the pixel unit 10.

  The drain line 57 is a grid-like wiring with a hole on the photodiode (charge generation unit 32). The DRN drive buffer 140 is provided in each row, and the DRN drive buffer 140 performs the same drive with respect to the drain line 57 of each row by a multi-level DRN control pulse of three or more values from the outside of the pixel unit 10. .

  By doing so, as shown in FIG. 13, the pulse shape for driving the drain line 57 can have a fall time of 40 ns or more, and the same effect as that of the configuration in which the DRN drive buffer 140 is provided in each column. Can be enjoyed.

  Note that the transition time control method of the vertical drain line 57 using the multi-level DRN control pulse is not limited to the configuration shown in FIGS. 13 and 14, but the drain line 57 on the entire surface of the pixel portion is connected to one DRN. The present invention can also be applied to a configuration driven by the drive buffer 140. Such a configuration is not practically adopted in a normal design, but can be adopted in the first example. In this case, if the conventional mechanism for setting the fall time to several ns or less is adopted, the W / L ratio of the buffer final stage NMOS used for the DRN drive buffer 140 is set in consideration of the load of the DRN drive buffer 140. There is a need to. On the other hand, in this embodiment, the transition time of the vertical drain line 57 may be moderated, and the degree of freedom in setting the W / L ratio is also increased.

  FIG. 15 is a diagram illustrating the details of the output IF unit 143. FIG. 15A shows an example thereof, and FIG. 15B shows a specific example of the switch circuit in this example. The level shift unit (SFT) 142 is provided in the vertical drive circuit 14b.

  Three types of DRN control pulses DRN1, DRN2, and DRN3 are input from the timing generator 20 to the level shift unit 142 as drive control pulses. The timing generator 20 includes a timing adjustment unit 21 that adjusts the output timing between these three types of DRN control pulses DRN1, DRN2, and DRN3.

  The timing adjustment unit 21 sets the output timing of the DRN control pulses DRN1, DRN2, and DRN3 based on a command from a central control unit that controls the overall operation of the solid-state imaging device 1 (not shown). Note that the central control unit gives this timing adjustment instruction to the timing adjustment unit 21 by receiving a user instruction via an operation panel or the like provided in the camera device. For example, it is possible to adjust the saturation shading amount to be small while confirming the output image, and the usability is very good.

  The output IF unit 143 shown in FIG. 15A includes three DRN drive buffers 140 (inputting individual DRN control pulses DRN1, DRN2, and DRN3 corresponding to the three values level-shifted by the level shift unit 142, respectively. And a switch circuit having switches SW1, SW2, and SW3. That is, the switch SW is driven through the buffer 140 after the level shift. Corresponding voltages 0V, 1V, and 3V are input to one of the switches SW1, SW2, and SW3, and the other is connected in common and input to the vertical drain line 57.

  The three switches SW1, SW2, and SW3 are connected to the individual DRN control pulses DRN1, DRN2, and DRN3 corresponding to the three values from the timing generator 20, and the outputs of the switches SW1, SW2, and SW3 are connected in common. The level shift unit 142 may be configured so that the outputs of the switches SW1, SW2, and SW3 are input to one DRN drive buffer 140. However, the DRN drive buffer 140 itself also has individual DRN control pulses. It is preferable to operate according to DRN1, DRN2, and DRN3, which are separated into three.

  Each of the switches SW1, SW2 and SW3 may be a simple one using a MOS transistor as shown in FIG. 15B, for example, and the circuit configuration becomes very simple. However, since the MOS transistor drives the vertical drain line 57, a large transistor having sufficient driving capability is used.

  Note that an n-MOS that is turned on in response to an active H pulse is used as the switch SW1, and a p-MOS that is turned on in response to an active L pulse is used as the switches SW2 and SW3. In either case, the terminals are wired as shown in the figure so as not to cause a problem in the power supply voltage range 0-3V.

  Each switch SW1, SW2, SW3 also functions as a driver, but its driving capability can be changed according to the switch element size (transistor size).

  As described above, if the transition time of the vertical drain line 57 is controlled using a multi-level DRN control pulse as in this embodiment, the drive voltage fall time and rise time are positively controlled. (Intentionally) can be lengthened. As a result, even in the case of a three-transistor type pixel structure without a selection transistor, it is possible to prevent a decrease in the number of saturated electrons in the central portion of the pixel portion, which may be caused by a well potential fluctuation. As a result, image quality degradation such as fixed pattern noise and saturation shading caused by the P-well potential difference can be made inconspicuous in practice, and the image quality is improved.

  For example, the device side uses a device having a unit pixel of the same 3TR configuration as the conventional one, and the input of the drive signal input to the DRN drive buffer 140 is dulled so as to satisfy the above-described conditions. It can also be considered. However, in this case, it is necessary to provide a waveform shaping circuit that dulls the drive pulse supplied from the timing generator 20 so as to satisfy the above-mentioned conditions, and it is difficult to freely adjust the degree of dullness.

  On the other hand, as in this embodiment, by using a multi-level DRN control pulse, the voltage waveform of the vertical drain line 57 satisfies the above-mentioned condition when viewed from the opposite side. A device having a unit pixel having a three-transistor configuration similar to the conventional one can be used on the device side, and the transition time can be freely adjusted by the control of the timing generator 20, which is convenient.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. Various changes or improvements can be added to the above-described embodiment without departing from the gist of the invention, and embodiments to which such changes or improvements are added are also included in the technical scope of the present invention.

  Further, the above embodiments do not limit the invention according to the claims (claims), and all combinations of features described in the embodiments are not necessarily essential to the solution means of the invention. Absent. The embodiments described above include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. Even if some constituent requirements are deleted from all the constituent requirements shown in the embodiment, as long as an effect is obtained, a configuration from which these some constituent requirements are deleted can be extracted as an invention.

  For example, in the above-described embodiment, a sensor composed of unit pixels composed of NMOS has been described as an example. However, the present invention is not limited to this. By conversely, it is possible to enjoy the same operations and effects as described in the above embodiment.

  In the above-described embodiment, the pixel of one photodiode and three transistors has been described as an example. However, the present invention is not limited to this, and a reset transistor is used for two photodiodes and two readout selection transistors. The same applies to a device including a unit pixel having a configuration in which a selection transistor used for pixel selection in a 4TR configuration is omitted, such as sharing an amplification transistor one by one.

  In the above, we focused on saturation shading, which was the most experimentally affected. However, if the well potential fluctuates differently in the center and the periphery of the pixel portion, characteristics other than the saturation signal amount also have shading. That is obvious. Dulling the fall time or the rise time for driving the drain line reduces the fluctuation of the potential of the well and brings it closer to the uniform, so that the shading phenomenon other than the saturation signal amount is also improved.

1 is a schematic configuration diagram of a CMOS solid-state imaging device according to an embodiment of the present invention. It is a figure explaining a saturation shading phenomenon. It is a figure which shows the measurement circuit for investigating the voltage change of a drain line. It is a figure which shows the relationship between resistance value and saturation shading when a DRN control pulse is blunted. FIG. 5 is a diagram showing the result shown in FIG. 4 in relation to the fall time of the voltage waveform in the control resistor and the saturation shading. It is a figure which shows the result of having reproduced the fluctuation | variation of P well electric potential by simulation (control resistance 146 = 0 ohms). It is a figure which shows the result of having reproduced the fluctuation | variation of P well electric potential by simulation (control resistance 146 = 10 (ohm)). It is a figure which shows the result of having reproduced the fluctuation | variation of P well electric potential by simulation (control resistance 146 = 150 (ohm)). It is a figure which shows the result of reproducing the fluctuation | variation of P well electric potential by simulation (control resistance 146 = 330 (ohm)). It is a figure which shows the result of having reproduced the fluctuation of P well potential by simulation (control resistance 146 = 680 ohms). It is the figure which showed the circuit diagram and timing example of the unit pixel explaining the basics of multi-value pulse drive. It is the figure which showed the other timing example of multi-valued pulse drive. It is the figure which showed the example which applied multi-value pulse drive to the device. It is the figure which showed the other example which applied multi-value pulse drive to the device. It is a figure explaining the structural example of an output IF part. It is a figure which shows the structural example of the unit pixel in the conventional CMOS sensor.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Solid-state imaging device, 3 ... Unit pixel, 5 ... Pixel signal generation part, 7 ... Drive control part, 10 ... Pixel part, 100 ... External circuit, 110 ... A / D conversion part, 12 ... Horizontal scanning circuit, 12a ... Horizontal decoder, 12b ... Horizontal drive circuit, 14 ... Vertical scanning circuit, 14a ... Vertical decoder, 14b ... Vertical drive circuit, 15 ... Vertical control line, 20 ... Timing generator, 21 ... Timing adjustment unit, 26 ... CDS processing unit, 28 ... Output buffer, 32 ... Charge generator, 34 ... Read selection transistor, 36 ... Reset transistor, 38 ... Floating diffusion, 40 ... Vertical selection transistor, 42 ... Amplification transistor, 51 ... Pixel line, 52 ... Vertical selection line 53 ... Vertical signal line, 55 ... Transfer wiring, 56 ... Reset wiring, 57 ... Vertical drain line, 130 ... Digital signal processor 136 ... D / A conversion unit, 140 ... DRN drive buffer, 142 ... level shift unit, 143 ... output IF section 150 ... transfer driving buffer 152 ... reset driving buffer 154 ... selection driving buffer

Claims (7)

A charge generation unit that generates a charge corresponding to the incident electromagnetic wave;
A charge storage section for storing the charge generated by the charge generation section;
A transfer gate unit disposed between the charge generation unit and the charge storage unit to transfer the charge generated by the charge generation unit to the charge storage unit;
A unit signal generation unit for generating a unit signal corresponding to the charge accumulated in the charge accumulation unit;
A reset unit for resetting the charge in the charge storage unit;
A drain line connected to the reset unit and the unit signal generation unit in a unit component,
The selection operation for outputting the unit signal generated by the unit signal generation unit to the outside is a drive control method for driving a semiconductor device for physical quantity distribution detection performed by controlling the potential of the charge storage unit. And
The drive control method, wherein the drain wiring is driven by a multi-value pulse whose level is changed stepwise by a combination of a plurality of control pulses having different levels. The drain wiring is connected substantially in common with other unit components,
The drive control method according to claim 1, wherein the drain wiring is driven by the multilevel pulse in the process of turning off the drain wiring. A charge generation unit that generates a charge corresponding to the incident electromagnetic wave;
A charge storage section for storing the charge generated by the charge generation section;
A transfer gate unit disposed between the charge generation unit and the charge storage unit to transfer the charge generated by the charge generation unit to the charge storage unit;
A unit signal generation unit for generating a unit signal corresponding to the charge accumulated in the charge accumulation unit;
A reset unit for resetting the charge in the charge storage unit;
A drain line connected to the reset unit and the unit signal generation unit in a unit component,
The selection operation for outputting the unit signal generated by the unit signal generation unit to the outside is a drive control device that drives a semiconductor device for physical quantity distribution detection performed by controlling the potential of the charge storage unit. And
A drive control device comprising: a drive control unit that drives the drain wiring with a multi-value pulse whose level is changed stepwise by a combination of a plurality of control pulses having different levels. The drive control unit
A pulse signal generator for generating the plurality of control pulses;
A multi-level pulse generation unit that generates a multi-level pulse whose level transitions stepwise based on a combination of a plurality of control pulses having different levels based on the plurality of control pulses generated by the pulse signal generation unit. The drive control device according to claim 3, wherein The drive control device according to claim 3, wherein the pulse signal generation unit is configured to be able to adjust an output timing between the plurality of control pulses. A charge generation unit that generates a charge corresponding to the incident electromagnetic wave;
A charge storage section for storing the charge generated by the charge generation section;
A transfer gate unit disposed between the charge generation unit and the charge storage unit to transfer the charge generated by the charge generation unit to the charge storage unit;
A unit signal generation unit for generating a unit signal corresponding to the charge accumulated in the charge accumulation unit;
A reset unit for resetting the charge in the charge storage unit;
A drain wiring connected to the reset unit and the unit signal generation unit and a drain driving buffer for driving the drain wiring are included in a unit component,
A selection operation for outputting the unit signal generated by the unit signal generation unit to the outside is a semiconductor device for physical quantity distribution detection performed by controlling the potential of the charge storage unit,
A semiconductor device comprising: a drive control unit that drives the drain drive buffer with a multi-value pulse whose level is changed stepwise by a combination of a plurality of control pulses having different levels. The drain wiring is connected substantially in common with other unit components,
The semiconductor device according to claim 6, wherein the drive control unit drives the drain drive buffer with the multilevel pulse in the process of turning off the drain wiring.

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