JP2005214753A - Semiconductor device and its test method - Google Patents

Semiconductor device and its test method Download PDF

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JP2005214753A
JP2005214753A JP2004020734A JP2004020734A JP2005214753A JP 2005214753 A JP2005214753 A JP 2005214753A JP 2004020734 A JP2004020734 A JP 2004020734A JP 2004020734 A JP2004020734 A JP 2004020734A JP 2005214753 A JP2005214753 A JP 2005214753A
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pad
test
semiconductor chip
semiconductor device
regions
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Kazuhiro Tashiro
一宏 田代
Shigeyuki Maruyama
茂幸 丸山
Koji Ogiwara
康次 荻原
Giichi Arisaka
義一 有坂
Takumi Kumatahara
巧 熊田原
Daisaku Hirano
大作 平野
Hiroshi Nakaita
浩 中板
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Fujitsu Ltd
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Fujitsu Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Abstract

<P>PROBLEM TO BE SOLVED: To prevent generation of a contact flaw on a pad or a crack on a layer under the pad caused by pushing a probe in several times onto the pad for the test at the inspection test time, concerning a miniaturized semiconductor device. <P>SOLUTION: A plurality of pads are provided to one external connection terminal on the semiconductor chip surface, and some of them are used as the pads for the test. Hereby, since contact positions of a probe needle in the test can be dispersed, a damage applied to a pad region can be prevented, and the semiconductor chip and this semiconductor device having high reliability can be provided. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は半導体装置及び試験方法に関し、特により微細化が図られた半導体チップ表面に設けられる試験用パッドの構造及び半導体チップの試験方法に関する。   The present invention relates to a semiconductor device and a test method, and more particularly to a structure of a test pad provided on the surface of a semiconductor chip that has been further miniaturized and a test method for a semiconductor chip.

近年、無線で情報が交信でき、かつ記録できる情報量も大きなＩＣタグが、物品や商品の情報管理、物流管理等に広く利用されるようになってきている。ＩＣタグは、ＲＦＩＤ（Ｒａｄｉｏ Ｆｒｅｑｕｅｎｃｙ Ｉｄｅｎｔｉｆｉｃａｔｉ ｏｎ）システムの媒体として、電波を用いて非接触で情報の交信ができるタグである（例えば、特許文献１参照）。   In recent years, IC tags that can exchange information wirelessly and have a large amount of information that can be recorded have been widely used for information management of goods and products, logistics management, and the like. An IC tag is a tag that can exchange information in a non-contact manner using radio waves as a medium of an RFID (Radio Frequency Identification on) system (see, for example, Patent Document 1).

ＩＣタグは、紙やプラスチック等の基材に設けたアンテナパターンと半導体チップからなり、アンテナパターンを通じて無線でリーダライタと交信することができる。  An IC tag includes an antenna pattern and a semiconductor chip provided on a base material such as paper or plastic, and can communicate with a reader / writer wirelessly through the antenna pattern.

半導体チップの表面には、アンテナ接続ためのボンディングパッドが形成されている。ボンディングパッドは、半導体チップの配線層の最上層に形成される導体層であり、通常は半導体チップの素子・回路形成領域とは別に周辺部に設けたボンディングパッド形成領域に形成される。
特開２００３−２２９４５６号公報（第３頁、図７） Bonding pads for antenna connection are formed on the surface of the semiconductor chip. The bonding pad is a conductor layer formed in the uppermost layer of the wiring layer of the semiconductor chip, and is usually formed in a bonding pad forming region provided in the peripheral portion separately from the element / circuit forming region of the semiconductor chip.
JP 2003-229456 A (page 3, FIG. 7)

ＩＣタグに用いられる等、より微細化が求められる半導体チップにあっても、高い信頼性が求められており、製品出荷前に十分な試験を行なう必要がある。   Even in a semiconductor chip that is required to be miniaturized, such as used in an IC tag, high reliability is required, and it is necessary to perform a sufficient test before shipping the product.

通常、半導体チップの試験は、半導体チップ表面に設けられた試験用パッドにプローブを接触させ、試験装置により半導体チップ内の回路の特性評価や信頼性評価を行なう。   Usually, in testing a semiconductor chip, a probe is brought into contact with a test pad provided on the surface of the semiconductor chip, and a characteristic evaluation and a reliability evaluation of a circuit in the semiconductor chip are performed by a test apparatus.

試験用パッドは、一般的に、前記ボンディングパッドと兼用されて、或いは当該ボンディングパッドに近接して、素子・回路形成領域の直上の領域を外してその周辺部に配設される。   In general, the test pad is also used as the bonding pad or in the vicinity of the bonding pad, and the area just above the element / circuit formation area is removed and disposed in the peripheral portion.

しかしながら、ＩＣタグに用いられる半導体チップなど、より小形化が必要とされる半導体装置では、試験用パッドを設けるスペースが限られてきており、導体層上の半導体チップの素子及び或いは回路形成領域（活性領域）上に配設しなければならない。   However, in a semiconductor device that requires further miniaturization, such as a semiconductor chip used for an IC tag, a space for providing a test pad has been limited, and a semiconductor chip element and / or circuit formation region on a conductor layer ( Active region).

一方、半導体チップの製造工程に於いては、試験用パッドには複数回にわたりプローブが押圧され、接触されるため、パッド上にコンタクト傷が発生することにより、外観不良やボンディング不良、電流容量が不足する等の問題が起こったり、パッド下の層にクラックが発生したりする可能性があり、当該半導体チップの製造歩留りの低下、信頼性の低下を招く一因となる。   On the other hand, in the manufacturing process of a semiconductor chip, the probe is pressed and contacted with the test pad a plurality of times, and contact scratches are generated on the pad, resulting in poor appearance, bonding failure, and current capacity. Problems such as shortage may occur, or cracks may occur in the layer under the pad, which causes a decrease in manufacturing yield and reliability of the semiconductor chip.

このような問題に対応するために、コンタクト荷重を低下させたり、コンタクト面を縮小させることが考えられるが、反対にコンタクト不良が起こり易くなってしまう問題がある。また、半導体チップにおいては、パッド下に設けられる保護層を厚くする等が考えられるが、半導体チップの薄型化及びコストダウンのためその厚さあるいは層数を増やすことができない。   In order to deal with such a problem, it is conceivable to reduce the contact load or reduce the contact surface, but there is a problem that contact failure tends to occur. In addition, in a semiconductor chip, it is conceivable to increase the thickness of a protective layer provided under the pad. However, the thickness or the number of layers cannot be increased because the semiconductor chip is reduced in thickness and cost.

上記の課題を解決するために、本発明では、半導体基板に形成された半導体素子及び或いは回路の形成領域上に、当該半導体素子或いは回路の外部接続部位に対応してパッドが配設された半導体装置において、前記パッドは、その表面が複数の領域に分割され、且つ隣接するパッド領域間が電気的に接続されてなることを特徴とする。   In order to solve the above-described problems, in the present invention, a semiconductor device in which pads are disposed on a semiconductor element and / or circuit formation region formed on a semiconductor substrate so as to correspond to an external connection portion of the semiconductor element or circuit. In the device, the surface of the pad is divided into a plurality of regions, and adjacent pad regions are electrically connected.

また、半導体基板に形成された半導体素子及び或いは回路の形成領域上に、当該半導体素子或いは回路の外部接続部位に対応してパッドが配設された半導体装置の当該パッドにプローブを接して試験を行う試験方法に於いて、前記パッドは、その表面が複数の領域に分割され、且つ隣接するパッド領域間が電気的に接続されてなり、前記パッドの表面領域の選択された一つのみに前記プローブを接触せしめることを特徴とする半導体装置の試験方法が特徴とされる。   In addition, a test is conducted by contacting a probe to the pad of the semiconductor device in which a pad is disposed on the semiconductor element or circuit formation region formed on the semiconductor substrate corresponding to the external connection portion of the semiconductor element or circuit. In the test method to be performed, the surface of the pad is divided into a plurality of regions, and adjacent pad regions are electrically connected, and the pad has only one selected surface region. A semiconductor device test method is characterized in that a probe is brought into contact.

本発明によれば、半導体チップ表面に、当該半導体チップの外部接続端子のそれぞれに於いて、パッドを複数の領域に分割され、隣接するパッド領域間を電気的に接続した構成とし、複数回行なわれる試験の際、１度試験に用いたパッドは避けて他のパッドを用いて次の試験を実施することにより、プローブの接触回数の低減及び／或いは接触位置の分散を図る。   According to the present invention, the pad is divided into a plurality of regions in each of the external connection terminals of the semiconductor chip on the surface of the semiconductor chip, and the adjacent pad regions are electrically connected to each other. In the test, the pad used for the test is avoided and the next test is performed using another pad to reduce the number of contact times of the probe and / or distribute the contact positions.

これにより、一つのパッドの同じ位置にプローブが複数回押圧、接触されることを避け、個々のパッド領域のダメージを防ぎ、信頼性の高い半導体チップ、半導体装置を提供することができる。   As a result, the probe can be prevented from being pressed and contacted to the same position of one pad a plurality of times, damage to individual pad regions can be prevented, and a highly reliable semiconductor chip and semiconductor device can be provided.

また、本発明のもう１つ発明によれば、半導体チップの外部接続端子のそれぞれ一つ毎に設けられるパッドの表面が複数の領域に分割され、１度試験に用いた領域は避けて他の領域を用いて次の試験を実施することにより、試験においてプローブの接触位置を分散する。   According to another aspect of the present invention, the surface of the pad provided for each of the external connection terminals of the semiconductor chip is divided into a plurality of regions, and the region used for the test once is avoided. By performing the following test using the region, the contact position of the probe is dispersed in the test.

このような手段によっても、一つのパッドの同じ位置に複数回プローブを押し付けることを避け、個々のパッド領域のダメージを防ぎ、信頼性の高い半導体チップ、半導体装置を提供することができる。   Also by such means, it is possible to avoid pressing the probe a plurality of times at the same position of one pad, prevent damage to individual pad regions, and provide a highly reliable semiconductor chip and semiconductor device.

次に、本発明を実施するための最良の形態について図面と共に説明する。   Next, the best mode for carrying out the present invention will be described with reference to the drawings.

図１は、本発明の第１の実施例である半導体チップの構成を示す平面図である。   FIG. 1 is a plan view showing a configuration of a semiconductor chip according to a first embodiment of the present invention.

同図に於いて、半導体チップ１０の回路形成面１０ａの上には、当該半導体チップの外部接続部位（電極）のそれぞれに対応してパッド２０が配設されている。   In the figure, pads 20 are arranged on the circuit forming surface 10a of the semiconductor chip 10 so as to correspond to the respective external connection portions (electrodes) of the semiconductor chip.

即ち、半導体基板に形成された半導体素子及び或いは回路の形成領域上に、当該半導体素子或いは回路の外部接続部位に対応してパッド２０が配設されている。   That is, the pads 20 are disposed on the semiconductor element and / or circuit formation region formed on the semiconductor substrate so as to correspond to the external connection portions of the semiconductor element or circuit.

当該パッド２０は、横方向に並べて配設された３つのパッド部即ち、第１のパッド部２１、第２のパッド部２２及び第３のパッド部２３より構成され、各々のパッド部２１乃至２３は、パッド２０と同一材料或いは異種材料からなる導電性材料をもって構成される連結部２４，２５により連結されている。   The pad 20 includes three pad portions arranged side by side, that is, a first pad portion 21, a second pad portion 22, and a third pad portion 23, and each of the pad portions 21 to 23 is provided. Are connected by connecting portions 24 and 25 made of a conductive material made of the same material or different material as the pad 20.

ここで、パッド部２１乃至２３のうち何れか一つ（必要に応じて複数個）は、後の外部接続端子配設工程に於いて、金ワイヤ等が接続されるか或いは突起電極が配設されて外部接続用パッドとされる。   Here, any one (a plurality if necessary) of the pad portions 21 to 23 is connected to a gold wire or a protruding electrode in a subsequent external connection terminal arrangement step. And used as an external connection pad.

図２は、第１実施例におけるパッド配設構成を有する半導体チップ１０の試験方法を示す。   FIG. 2 shows a test method of the semiconductor chip 10 having the pad arrangement configuration in the first embodiment.

かかる半導体装置の試験において、第１回目の試験では、半導体チップ１０の外縁に近い第１のパッド部２１ａ，２１ｂ，２１ｃに対して、順次或いは同時にプローブ針４０ａ、４０ｂ、４０ｃを押圧し、接触させて所望の試験を行なう。   In the test of the semiconductor device, in the first test, the probe needles 40a, 40b, and 40c are pressed against the first pad portions 21a, 21b, and 21c close to the outer edge of the semiconductor chip 10 sequentially or simultaneously to make contact. And perform the desired test.

２回目の試験においては、前記第１のパッド部２１ａ，２１ｂ，２１ｃの内側に配設された第２のパッド部２２ａ，２２ｂ，２２ｃに対して、順次あるいは同時にプローブ針４０ａ，４０ｂ、４０ｃを押圧し、接触させて所望の試験を行なう。   In the second test, the probe needles 40a, 40b, and 40c are sequentially or simultaneously applied to the second pad portions 22a, 22b, and 22c disposed inside the first pad portions 21a, 21b, and 21c. Press and contact to perform the desired test.

更に、次の試験においては、最も内側の第３のパッド部２３ａ，２３ｂ，２３ｃに対して順次あるいは同時にプローブ針４０ａ，４０ｂ、４０ｃを押圧し、接触させて所望の試験を行なう。   Furthermore, in the next test, the probe needles 40a, 40b, and 40c are pressed sequentially and simultaneously against the innermost third pad portions 23a, 23b, and 23c, and a desired test is performed.

このように、本発明の第１の実施例によれば、複数回の試験が必要とされる半導体チップにおいて、一つのパッド部に対してはプローブ針を１回接触させるだけであるため、当該パッド部に於けるキズの発生を低減することができると共に、当該パッド部のダメージを防ぐことができる。   As described above, according to the first embodiment of the present invention, in the semiconductor chip that requires a plurality of tests, the probe needle is only brought into contact with one pad portion once. The occurrence of scratches in the pad portion can be reduced, and damage to the pad portion can be prevented.

試験完了後、試験用としてのみ用いられたパッド部は、必要に応じて樹脂等によりコーティングされ保護される。   After the test is completed, the pad portion used only for testing is coated and protected with a resin or the like as necessary.

図３は、本発明の第２の実施例である半導体チップの構成を示す平面図である。   FIG. 3 is a plan view showing the configuration of a semiconductor chip according to the second embodiment of the present invention.

同図に於いて、半導体チップ１１の回路形成面１１ａ上には、当該半導体チップの外部接続部位（電極）のそれぞれに対応してパッド３０が配設されている。   In the figure, pads 30 are disposed on the circuit forming surface 11a of the semiconductor chip 11 so as to correspond to the respective external connection portions (electrodes) of the semiconductor chip.

当該パッド３０は、試験工程、或いは外部接続端子の配設工程に於いては、その表面が３つのパッド領域即ち、第１のパッド領域３１、第２のパッド領域３２及び第３のパッド領域３３の３つ領域に分割されて扱われる。   The pad 30 has three pad regions, that is, a first pad region 31, a second pad region 32, and a third pad region 33 in the test process or the external connection terminal disposing process. Are divided into three areas.

ここで、パッド領域３１乃至３３のうち何れか一つは、後の外部接続端子の配設工程に於いて、金ワイヤ等が接続されるか或いは突起電極が配設されて外部接続用パッド部とされる。   Here, any one of the pad regions 31 to 33 has an external connection pad portion in which a gold wire or the like is connected or a protruding electrode is disposed in a subsequent external connection terminal disposition process. It is said.

図４は第２実施例におけるパッド構成を有する半導体チップ１１の試験方法を示す。   FIG. 4 shows a test method of the semiconductor chip 11 having the pad configuration in the second embodiment.

かかる半導体装置の試験において、第１回目の試験では、半導体チップ１１の外縁に近い第１のパッド領域３１ａ，３１ｂ，３１ｃに順次あるいは同時にプローブ針４０ａ，４０ｂ、４０ｃを押圧し、接触させて所望の試験を行なう。   In such a test of the semiconductor device, in the first test, the probe needles 40a, 40b, and 40c are sequentially pressed or brought into contact with the first pad regions 31a, 31b, and 31c near the outer edge of the semiconductor chip 11 to make a desired test. Perform the test.

２回目の試験においては、前記第１のパッド領域３１ａ，３１ｂ，３１ｃの隣（内側）に位置する第２のパッド領域３２ａ，３２ｂ，３２ｃに、順次あるいは同時にプローブ針４０ａ，４０ｂ、４０ｃを押圧し、接触させて所望の試験を行なう。   In the second test, the probe needles 40a, 40b, and 40c are sequentially or simultaneously pressed against the second pad regions 32a, 32b, and 32c located next to (inner side) the first pad regions 31a, 31b, and 31c. And contact to perform the desired test.

次の試験においては、最も内側の第３のパッド領域３３ａ，３３ｂ，３３ｃに順次あるいは同時にプローブ針４０ａ，４０ｂ、４０ｃを押圧し、接触させて所望の試験を行なう。   In the next test, the probe needles 40a, 40b, and 40c are pressed and contacted sequentially or simultaneously with the innermost third pad regions 33a, 33b, and 33c to perform a desired test.

このように、本発明の第２の実施例によれば、複数回の試験が必要とされる半導体チップにおいて、一つのパッド領域に対してはプローブ針を１回接触させるだけであるため、当該パッド領域に於けるキズの発生を低減することができると共に、当該パッド領域のダメージを防ぐことができる。   Thus, according to the second embodiment of the present invention, in a semiconductor chip that requires a plurality of tests, the probe needle is only brought into contact with one pad region once. The occurrence of scratches in the pad area can be reduced, and damage to the pad area can be prevented.

試験完了後、試験用としてのみ用いられたパッド領域は、必要に応じて樹脂等によりコーティングされ保護される。   After the test is completed, the pad area used only for testing is coated and protected with a resin or the like as necessary.

図５は本発明の第３の実施例である半導体チップの構成を示す平面図である。   FIG. 5 is a plan view showing a configuration of a semiconductor chip according to a third embodiment of the present invention.

同図に於いて、半導体チップ１２の回路形成面１２ａの上には、当該半導体チップの外部接続部位（電極）のそれぞれに対応してパッド５０が配設されている。   In the figure, pads 50 are disposed on the circuit forming surface 12a of the semiconductor chip 12 so as to correspond to the external connection portions (electrodes) of the semiconductor chip.

図６に示すように、パッド５０は、その表面が４つのパッド領域即ち、第１のパッド領域５１、第２のパッド領域５２、第３のパッド領域５３及び第４のパッド領域５４に、絶縁層からなるカバー膜６０によって分割されている。   As shown in FIG. 6, the surface of the pad 50 is insulated from four pad regions, that is, a first pad region 51, a second pad region 52, a third pad region 53, and a fourth pad region 54. It is divided by a cover film 60 made of layers.

ここで、パッド領域５１乃至５４のうち何れか一つは、後の外部接続端子の配設工程に於いて、金ワイヤ等が接続されるか或いは突起電極が配設されて外部接続用パッド部とされる。   Here, any one of the pad areas 51 to 54 is connected to a gold wire or a projecting electrode in a later step of providing an external connection terminal, and an external connection pad portion is provided. It is said.

図７は第３実施例における半導体チップ１２の試験方法を示す図である。   FIG. 7 is a diagram showing a test method for the semiconductor chip 12 in the third embodiment.

かかる半導体装置の試験において、第１回目の試験では、図７（Ａ）に示す様に、前記半導体素子の複数パッド領域に対応して、複数のプローブ針４０が一体に配設されたプローブカード（図示せず）を用い、複数のプローブ針４０を同時にそれぞれのパッド領域に於ける第１のパッド領域５１に押圧し、接触させて所望の試験を行なう。   In the test of the semiconductor device, in the first test, as shown in FIG. 7A, a probe card in which a plurality of probe needles 40 are integrally arranged corresponding to a plurality of pad regions of the semiconductor element. (Not shown), a plurality of probe needles 40 are simultaneously pressed against and brought into contact with the first pad area 51 in each pad area to perform a desired test.

２回目の試験においては、図７（Ｂ）に示す様に、プローブカードを例えば時計回りに移動させた後、複数のプローブ針４０をそれぞれ対応する第２のパッド領域５２に同時に押圧し、接触させて所望の試験を行なう。   In the second test, as shown in FIG. 7B, after the probe card is moved, for example, clockwise, the probe needles 40 are simultaneously pressed against the corresponding second pad regions 52 to make contact. And perform the desired test.

これ以降、３回目の試験、４回目の試験も、プローブカード或いは被試験半導体チップを移動させてパッド領域を変更しつつ実施する。   Thereafter, the third test and the fourth test are also performed while changing the pad area by moving the probe card or the semiconductor chip to be tested.

このように、本発明の第３の実施例によれば、複数回の試験が必要とされる半導体チップにおいて、試験の度に、例えば時計周りに順次プローブ針が接触するパッド領域を変えてゆくことにより、一つのパッド領域に対してはプローブ針を１回接触させるだけであるため、当該パッド領域に於けるキズの発生を低減することができると共に、当該パッド領域のダメージを防ぐことができる。   As described above, according to the third embodiment of the present invention, in a semiconductor chip that requires a plurality of tests, the pad area with which the probe needle contacts sequentially, for example, clockwise is changed at each test. As a result, since the probe needle is only brought into contact with one pad area once, generation of scratches in the pad area can be reduced and damage to the pad area can be prevented. .

試験完了後、試験用としてのみ用いられたパッド領域は、必要に応じて樹脂等によりコーティングされ保護される。   After the test is completed, the pad area used only for testing is coated and protected with a resin or the like as necessary.

尚、本発明にあっては、半導体チップの外部接続部位（電極）の一つに対応して配設された複数個のパッド領域或いはパッド部のうち、半導体チップの外部接続部位（端子）に最も遠い位置にあるパッドを最初の試験の際に用い、以後半導体チップの外部接続部位（端子）に近づく方向にバットを選択しても良い。   In the present invention, among the plurality of pad regions or pad portions arranged corresponding to one of the external connection portions (electrodes) of the semiconductor chip, the external connection portion (terminal) of the semiconductor chip is used. The pad at the farthest position may be used for the first test, and the bat may be selected in the direction approaching the external connection portion (terminal) of the semiconductor chip thereafter.

このようなパッドの選択により、直前の試験の際にパッドに付されたキズなどにより当該パッド部と半導体チップの外部接続部位（端子）との間の抵抗が増加する影響を回避することができる。   By selecting such a pad, it is possible to avoid the influence of an increase in resistance between the pad portion and the external connection portion (terminal) of the semiconductor chip due to a scratch attached to the pad during the previous test. .

また、複数個のパッド領域或いはパッド部のうち、何れか少なくとも一つが、外部接続用パッド部を構成するとして説明したが、当業者であれば、かかる構成に止まることなく、複数のパッド領域を含む試験用パッドとは別個に、外部接続用の専用パッドを配設することは必要に応じて行うことができる。   Further, at least one of the plurality of pad regions or pad portions has been described as constituting an external connection pad portion. However, those skilled in the art will not be limited to such a configuration, and a plurality of pad regions may be defined. Separately from the included test pads, a dedicated pad for external connection can be provided as necessary.

図１は本発明の第１実施例である半導体チップの平面図である。FIG. 1 is a plan view of a semiconductor chip according to a first embodiment of the present invention. 図２は本発明の第１実施例における半導体チップの試験方法を示す図である。FIG. 2 is a diagram showing a method for testing a semiconductor chip in the first embodiment of the present invention. 図３は本発明の第２実施例である半導体チップの平面図である。FIG. 3 is a plan view of a semiconductor chip according to the second embodiment of the present invention. 図４は本発明の第２実施例における半導体チップの試験方法を示す図である。FIG. 4 is a diagram showing a method for testing a semiconductor chip in the second embodiment of the present invention. 図５は本発明の第３実施例である半導体チップの平面図である。FIG. 5 is a plan view of a semiconductor chip according to a third embodiment of the present invention. 図６は本発明の第３実施例における半導体チップのパッドの平面及び断面図を示す図である。FIG. 6 is a diagram showing a plan view and a sectional view of a pad of a semiconductor chip in a third embodiment of the present invention. 図７は本発明の第３実施例における半導体チップの試験方法を示す図である。FIG. 7 is a diagram showing a semiconductor chip testing method in the third embodiment of the present invention.

符号の説明Explanation of symbols

１０、１１、１２…半導体チップ
１０ａ、１１ａ、１２ａ…回路形成面
２０、３０，５０…パッド
２１…第１のパッド部
２２…第２のパッド部
２３…第３のパッド部
３１、５１…第１のパッド領域
３２、５２…第２のパッド領域
３３、５３…第３のパッド領域
４０、４０ａ、４０ｂ、４０ｃ…プローブ針
５４…第４のパッド領域
６０…カバー膜

DESCRIPTION OF SYMBOLS 10, 11, 12 ... Semiconductor chip 10a, 11a, 12a ... Circuit formation surface 20, 30, 50 ... Pad 21 ... 1st pad part 22 ... 2nd pad part 23 ... 3rd pad part 31, 51 ... 1st 1 pad region 32, 52 ... second pad region 33, 53 ... third pad region 40, 40a, 40b, 40c ... probe needle 54 ... fourth pad region 60 ... cover membrane

Claims (5)

パッドの同じ位置にコンタクトダメージが集中しないことを特徴とする半導体装置。   A semiconductor device characterized in that contact damage does not concentrate on the same position of a pad. 半導体基板に形成された半導体素子及び或いは回路の形成領域上に、当該半導体素子或いは回路の外部接続部位に対応してパッドが配設された半導体装置において、
前記パッドは、その表面が複数の領域に分割され、且つ隣接するパッド領域間が電気的に接続されてなることを特徴とする半導体装置。 In a semiconductor device in which pads are disposed on a semiconductor element and / or circuit formation region formed on a semiconductor substrate so as to correspond to an external connection portion of the semiconductor element or circuit.
The pad has a surface divided into a plurality of regions and electrically connected between adjacent pad regions. 請求項２記載の半導体装置において、
前記複数個のパッド領域の配置は、同一のプローブカードでコンタクトできるような配置としたことを特徴とする半導体装置。 The semiconductor device according to claim 2,
The semiconductor device according to claim 1, wherein the plurality of pad regions are arranged such that they can be contacted by the same probe card. 半導体基板に形成された半導体素子及び或いは回路の形成領域上に、当該半導体素子或いは回路の外部接続部位に対応してパッドが配設された半導体装置の当該パッドにプローブを接して試験を行う試験方法に於いて、
前記パッドは、その表面が複数の領域に分割され、且つ隣接するパッド領域間が電気的に接続されてなり、
前記パッドの表面領域の選択された一つにのみに前記プローブを接触せしめることを特徴とする半導体装置の試験方法。 A test in which a probe is brought into contact with a pad of a semiconductor device in which a pad corresponding to an external connection portion of the semiconductor element or circuit is formed on a semiconductor element and / or circuit formation region formed on the semiconductor substrate. In the method,
The pad has a surface divided into a plurality of regions and electrically connected between adjacent pad regions,
A test method for a semiconductor device, wherein the probe is brought into contact with only one selected surface area of the pad. 請求項４記載の半導体装置の試験方法において、
同一のプローブカードで、複数のパッドに位置をずらしてコンタクトすることを特徴とする半導体装置の試験方法。

The semiconductor device testing method according to claim 4,
A test method for a semiconductor device, wherein the same probe card is used to contact a plurality of pads while shifting their positions.

JP2004020734A 2004-01-29 2004-01-29 Semiconductor device and its test method Withdrawn JP2005214753A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015228472A (en) * 2014-06-03 2015-12-17 株式会社ソシオネクスト Semiconductor device and manufacturing method of the same
US9824939B2 (en) 2015-04-01 2017-11-21 Sumitomo Electric Device Innovations, Inc. Semiconductor assembly and method to form the same
CN111370343A (en) * 2020-02-17 2020-07-03 长江存储科技有限责任公司 Failure analysis method and structure

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015228472A (en) * 2014-06-03 2015-12-17 株式会社ソシオネクスト Semiconductor device and manufacturing method of the same
US9824939B2 (en) 2015-04-01 2017-11-21 Sumitomo Electric Device Innovations, Inc. Semiconductor assembly and method to form the same
CN111370343A (en) * 2020-02-17 2020-07-03 长江存储科技有限责任公司 Failure analysis method and structure

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