JP2005203388A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device for preventing the deviation of the alignment of an inner lead, and the occurrence of short circuit failure between adjacent bump electrodes by eutectic melt overflown from the bump electrode in the junction process between the inner lead and the salient electrode. <P>SOLUTION: The surface of a semiconductor chip 5 in which the bump electrode 6 is formed, and that of a film base 2 in which the inner lead 4a is formed in a recess provided at a position corresponding to the bump electrode 6 and a projection is formed between mutually adjacent inner leads 4a, are arranged opposingly. The bump electrode 6 and the inner lead 4a are joined, the width of the bump electrode 6 is made smaller than that of the inner lead 4a at a part joined to the bump electrode 6, and the depth of the recess provided at the film base 2 is made larger than the thickness of the inner lead 4a and is made smaller than the addition of the height of the bump electrode 6a and the thickness of the inner lead 4a. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device using a tape carrier having no device hole and a method for manufacturing the same.

Semiconductor products such as LSIs continue to require high-density mounting in order to achieve low price, light weight, thinning, and miniaturization.
In general, as a semiconductor device that realizes high-density mounting of semiconductor elements, there is a tape carrier package (hereinafter referred to as TCP). Among them, there is no device hole or bending slit, and an inner connected to a metal electrode on a semiconductor chip. A structure in which the lead is in close contact with the tape base material is called a chip-on-film (hereinafter referred to as COF) structure. Since the COF has no device hole and the inner lead is in close contact with the film substrate, there is no flying lead that tends to bend, and the conductor lead can be made thin. Thereby, the etching property of the conductor lead is improved as compared with the conventional TCP having a device hole, and a finer conductor pattern can be formed. Currently, COF tapes with a pitch of 45 μm are mass-produced, and further refinement is realistically expected.

  A general semiconductor device having a COF structure will be described with reference to FIG. FIG. 7A is a plan view seen from the conductor lead side of a conventional semiconductor device having a COF structure, and sees through the film base material and the sealing resin. 7B is a cross-sectional view taken along the line CC ′ of FIG. 7A, and FIG. 7C is a cross-sectional view taken along the line DD ′ of FIG. 7A.

  The film 1 ′ has insulating and flexible properties, and is composed of a film base 2 ′ formed of a resin such as polyimide and a conductor lead 4 ′ formed of a metal foil such as copper. A region of the conductor lead 4 ′ that is not covered with the solder resist 3 from the tip of the portion connected to the metal bump electrode 6 formed on the semiconductor chip 5 to the solder resist 3 is called an inner lead 4 a ′. Of the conductor leads 4 ′ extended on the film base 2 ′ outside 4 a ′, the region connected to the external circuit is called an outer lead 4 b ′. The conductor lead 4 'is usually plated. The area around the inner lead 4a ′ is covered with a sealing resin 7 for protecting the surface of the semiconductor chip 5 and ensuring the strength of the semiconductor device itself.

  Next, a general assembly process of a conventional COF in which the inner lead 4a ′ of the film 1 ′ and the metal protruding electrode 6 formed on the semiconductor chip 5 are bonded by intermetallic bonding such as eutectic is illustrated in FIG. 8 will be used for explanation.

  In the film 1 ′, inner leads 4 a ′ are formed on the film substrate 2 ′ in accordance with the position of the metal protruding electrode 6 (see FIG. 8A). The surface of the inner lead 4a 'is plated with tin or gold. The film substrate 2 ′ is 38 μm, 25 μm, etc., which is considerably thinner than 75 μm, which is the thickness of a conventional general TCP. A method for producing the film 1 'will be described with reference to FIG.

  As shown in FIGS. 11A to 11B, a metal foil 15 such as copper is formed on the surface of a film base 2 ′ made of a resin such as polyimide by a sputtering method or the like. Then, as shown in FIG. 11C, a photoresist 16 is applied, a photomask having a desired conductor lead 4 ′ pattern is applied and exposed, and then, as shown in FIG. 16 is developed with a developing solution to expose the metal foil 15 other than the desired conductor lead 4 '.

  Next, as shown in FIGS. 11E to 11F, the exposed metal foil 15 is chemically dissolved and removed, and the photoresist 16 is chemically dissolved and removed to thereby form a desired pattern of the conductor lead 4 '. Can be obtained. Thereafter, a plating material is applied to the surface of the conductor lead 4 ′, and the solder resist 3 is applied to complete.

  The semiconductor chip 5 is placed on the bonding stage 11, and the metal protruding electrodes 6 are arranged along the outer periphery of the semiconductor chip 5 or on the entire surface of the semiconductor chip 5 (see FIG. 8A). ). The film 1 ′ is provided with a gap between the inner lead 4 a ′ of the film 1 ′ and the metal protruding electrode 6 on the semiconductor chip 5 by using the forming plate 8 having the opening 12 through which the bonding tool 10 enters and exits and the clamper 9. Is fixed. Then, after aligning the metal protruding electrode 6 on the semiconductor chip 5 and the inner lead 4a 'of the film 1' at a predetermined position, the bonding tool 10 descends while deforming the film 1 ', and the inner lead 4a' and the metal protruding electrode are deformed. 6 are joined by a thermocompression bonding method (see FIG. 8B). The thermocompression bonding method refers to the inner lead 4a while applying a temperature (about 300 ° C. to 500 ° C.) and a load necessary for eutectic fusion or solid phase diffusion of the plating material applied to the inner lead and the metal projection material. 'And the metal projection electrode 6 are joined together. Then, after pressing and heating for a predetermined time, the bonding tool 10 is lifted and detached.

  Note that the metal protrusion electrode 6 on the semiconductor chip 5 and the inner lead 4a ′ of the film 1 ′ are aligned at a predetermined position, as shown in FIG. 9A, the center of the inner lead 4a ′ and the metal protrusion electrode 6 This means that the stage 11 on which the semiconductor chip 5 is mounted is moved so that the centers of the two coincide.

  FIG. 9 shows the positional relationship between the inner lead 4 a ′ and the metal protrusion electrode 6 immediately before and after bonding. FIG. 9A is a cross-sectional view when the inner lead 4a ′ immediately before joining is set to a predetermined position, FIG. 9B is a cross-sectional view at the time of joining, and FIG. 9C is a view after joining. FIG. 7 is a plan view of the joint between the inner lead 4a ′ and the metal protruding electrode 6 as seen from the film base 2 ′ side, and the film base 2 ′ is seen through.

  As shown in FIG. 9 (a), after the inner lead 4a 'is aligned at a predetermined position, the inner lead 4a' is joined by a thermocompression bonding method. In this case, as shown in FIGS. 9B and 9C, the eutectic melt 14 is generated on the side surface of the inner lead 4 a ′ on the metal protruding electrode 6.

  After the thermocompression bonding, the sealing resin 7 is coated with a film to protect the joint portion between the inner lead 4a 'and the metal protruding electrode 6 and the surface portion where the circuit of the semiconductor chip 5 exists and to ensure the mechanical strength of the entire semiconductor device. It inject | pours into the clearance gap between 1 'and the semiconductor chip 5 using the resin supply nozzle 13 (refer FIG.8 (c)). After sealing, stamping and inspection are performed to complete the COF product. The step of joining the inner lead 4a ′ and the metal bump electrode 6 is called an ILB (inner lead bonding) step, and the step of sealing the inner lead 4a ′ and the surface of the semiconductor chip 5 with the sealing resin 7 is called a sealing step.

  In the ILB process, a plurality of films 1 'are continuously connected, and the inner leads 4a are applied while applying temperature and load from the alignment between the metal protruding electrodes 6 on the semiconductor chip 5 and the inner leads 4a' of the film 1 '. When a series of operations up to joining the metal protrusion electrode 6 and the metal projection electrode 6 is finished, the film 1 ′ to which the semiconductor chip 5 is joined is fed out from the opening 12, and the next film 1 ′ is supplied to the opening 12. Then, the semiconductor chip 5 is supplied to the stage 11 and a series of operations starts.

  A method for aligning the metal protrusion electrode 6 and the inner lead 4a 'of the film 1' in this continuous production will be described. Before the start of continuous production, the following preparation steps (1) to (4) are necessary.

  (1) The position of the film alignment mark 17 on the film 1 ′ and the chip alignment mark 18 on the semiconductor chip 5 are detected using separate cameras (image receiving device: not shown).

(2) The positions of the detected film alignment mark 17 and chip alignment mark 18 are recorded in the storage device. This position is called a reference position.
(3) Then, the stage 11 on which the semiconductor chip 5 is mounted is moved so that the center of the inner lead 4a 'and the center of the metal protruding electrode 6 coincide.

(4) The shift amount between the position of the stage when the centers coincide with the reference position of the chip alignment mark 18 detected in (1) is recorded in the storage device. During continuous production after the above preparation steps are completed, if the position of the film alignment mark 17 and the chip alignment mark 18 is detected, the amount of deviation from the reference position recorded in (2) and (3) If the stage is moved by an amount equal to the shift amount, the center of the inner lead 4a 'and the center of the metal projection electrode 6 coincide.
Japanese Patent No. 3456576

  However, in the above-described continuous production using the conventional film 1 ′, the center of the inner lead 4a ′ and the center of the metal projection electrode 6 coincide with each other at the start of production. A deviation occurs between the center of the inner lead 4 a ′ and the center of the metal protrusion electrode 6. The causes of this shift are as follows: (1) The position of the two cameras that detect the film alignment mark 17 and the chip alignment mark 18 are shifted from the initial position due to the thermal environment change and mechanical vibration of the apparatus due to continuous production. This is because (2) a mechanical error when the bonding stage 11 moves a distance from the detection position of the chip alignment mark 18 to the opening 12.

Thus, the malfunction when the center of inner lead 4a 'and the center of metal projection electrode 6 arise will be described with reference to FIG.
FIG. 10 shows the positional relationship between the inner lead 4a ′ and the metal projection electrode 6 immediately before and after joining when the center of the inner lead 4a ′ and the center of the metal projection electrode 6 are displaced by a distance X. Show. FIG. 10A is a cross-sectional view when the inner lead 4a just before joining is aligned at a distance X from the predetermined position, and FIG. 10B is the moment when the inner lead 4a contacts the metal protruding electrode 6. FIG. It is. FIG. 10C is a cross-sectional view when a predetermined amount of pressure is applied, and FIG. 10D shows the bonded portion between the inner lead 4a ′ and the metal protrusion electrode 6 after film bonding. It is the top view seen from the base-material 2 'side, and is seeing through film base-material 2'.

  As shown in FIG. 10 (a), when the center of the inner lead 4a 'and the center of the metal projection electrode 6 are displaced by a distance X, the bonding tool 10 is lowered while deforming the film 1'. The moment when the inner lead 4a ′ contacts the metal bump electrode 6, the state is as shown in FIG. 10B. At this time, the eutectic reaction starts between the plating material on the surface of the inner lead 4a ′ and the metal bump electrode 6. Each is in a molten state. Thereafter, pressure is applied by a bonding tool up to a predetermined pressurizing amount. When the width of the inner lead 4a 'with respect to the metal projection electrode 6 is less than 1/2, the inner lead 4a' is shown in FIG. It is easy to shift in the arrow direction shown in This is because the surface of only one side of the metal projection electrode 6 is melted and soft, so that the pressurization becomes uneven and the inner lead 4a 'slips. Therefore, after bonding, as shown in FIG. 10C, the inner lead 4a 'straddles between the adjacent metal protrusion electrodes 6, and a defect due to a short circuit between the metal protrusion electrodes 6 (hereinafter referred to as a short defect) occurs. .

  In addition, short-circuit defects due to the eutectic melt 14 may occur as shown in FIGS. This is caused by the plating material on the surface of the inner lead 4 a ′ not uniformly spreading on the metal bump electrode 6 due to contamination on the surface of the metal bump electrode 6, and is biased to melt to one side and overflow from the metal bump electrode 6. .

  Accordingly, an object of the present invention is to provide misalignment of the inner lead and the metal protruding electrode in the bonding (ILB) process between the inner lead and the metal protruding electrode in a semiconductor device having a chip-on-film (COF) structure. An object of the present invention is to provide a semiconductor device and a method for manufacturing the same that can prevent the occurrence of a short circuit between adjacent metal protrusion electrodes due to the eutectic melt overflowing from the substrate.

  In order to solve the above problems, a semiconductor device according to claim 1 of the present invention is provided at a position corresponding to the surface of a semiconductor chip on which a protruding electrode (metal protruding electrode) is formed, and the protruding electrode. Conductor leads (inner leads) are formed in the recesses, and the surface of the film substrate formed with the protrusions between the adjacent conductor leads is disposed opposite to each other, and the protruding electrodes and the conductor leads Are joined.

  According to a second aspect of the present invention, there is provided the semiconductor device according to the first aspect, wherein the width of the protruding electrode is made smaller than the width of the conductor lead in the portion joined to the protruding electrode. The depth of the recess provided in the base material is made larger than the thickness of the conductor lead and smaller than the sum of the height of the protruding electrode and the thickness of the conductor lead.

  A method for manufacturing a semiconductor device according to claim 3 is the method for manufacturing a semiconductor device according to claim 1 or 2, wherein a step of applying a photoresist to the surface of a film substrate formed of resin; A step of exposing after applying a photomask having a conductor lead pattern on the surface of the coated photoresist, and removing the photoresist in the exposed portion to expose an exposed portion of the same pattern as the conductor lead on the surface of the film substrate. The step of forming, the step of forming uneven portions of a predetermined shape by etching the surface of the film base in the exposed portion, the step of laminating a metal material on the surface of the film base, and the remaining photoresist chemically A method of forming a pattern of conductor leads on the surface of the film substrate.

  Furthermore, the manufacturing method of the semiconductor device which concerns on Claim 4 WHEREIN: The manufacturing method of Claim 3 WHEREIN: The process which makes the film base material and the surface of a semiconductor chip oppose, and joins a protruding electrode and a conductor lead. It is equipped.

  According to the semiconductor device of the first aspect, the conductor leads are formed in the surface of the semiconductor chip on which the projecting electrodes are formed and the recesses provided at the positions corresponding to the projecting electrodes, and adjacent to each other. The surface of the film base material in which convex portions are formed between the conductor leads to be disposed is opposed to each other, and the projecting electromotive electrode and the conductor lead are joined together, thereby The projection prevents the eutectic melt from flowing out to the adjacent projecting electrodes, preventing the occurrence of short-circuit defects, and the projection of the film substrate between the conductor leads is located between the projecting electrodes. The self-alignment effect due to entering the gap between the protrusions and the conductor leads is facilitated, and the short circuit due to the misalignment of the conductor leads is prevented. Can.

  Further, according to the semiconductor device of the second aspect, in addition to the same effect as the first aspect, a gap can be formed between the film base and the surface of the semiconductor chip. Can be inserted between the film base and the surface of the semiconductor chip, and the resin sealing can be reliably performed.

  According to the method for manufacturing a semiconductor device according to claim 3, the same effect as in claim 1 or 2 can be obtained, and the conductor lead can be formed using the photoresist used for forming the concave portion of the film base as it is. Since it is formed, it is not necessary to pattern the conductor lead again, so that the number of steps for producing the film substrate can be reduced. Moreover, a conductor lead can be formed in the exact position of the recessed part of a film base material.

  Furthermore, according to the method for manufacturing a semiconductor device according to claim 4, the film base between the conductor leads is formed by forming the conductor lead in the concave portion of the film base and joining the protruding electrode and the conductor lead. Can prevent the eutectic melt from flowing out to the adjacent projecting electrode and prevent the occurrence of short circuit defects. Thus, since a self-alignment effect is produced, it is possible to prevent occurrence of a short circuit failure due to misalignment of the conductor leads.

[Embodiment]
Hereinafter, a semiconductor device and a manufacturing method thereof according to embodiments of the present invention will be described with reference to the drawings.

  FIG. 1A is a view of the semiconductor device according to the present embodiment as viewed from the direction of the film base material, and sees through the film base material and the sealing resin. 1B is an AA ′ cross-sectional view of the semiconductor device of FIG. 1A, and FIG. 1C is an enlarged view of the BB ′ cross-section of the semiconductor device of FIG. FIG. 2 shows a method for manufacturing a film used in the semiconductor device according to the embodiment. FIG. 3 shows the positional relationship between the inner lead and the metal projection electrode of the semiconductor device according to the embodiment. FIG. 3A shows a state immediately before pressing with the bonding tool, and FIG. ) Is a state in which the pressure is applied by the bonding tool, and FIG. 3C is a view of the state after the inner lead and the metal projection electrode are joined as seen from the direction of the film base. The inner lead is seen through (the inner lead outer shape is shown). FIG. 4 shows a method for manufacturing the semiconductor device of the embodiment.

  As shown in FIG. 1, in the semiconductor device according to the present embodiment, a film 1 has insulating and flexible properties, a film base 2 formed of a resin such as polyimide, and a metal foil such as copper. And the conductor lead 4 formed by A region of the conductor lead 4 that is not covered with the solder resist 3 from the tip of the portion connected to the metal protruding electrode (projecting electrode) 6 formed on the semiconductor chip 5 to the solder resist 3 is defined as an inner lead 4a, Of the conductor leads 4 extended on the film base 2 outside the leads 4a, a region connected to an external circuit is called an outer lead 4b. The conductor lead 4 is usually plated. The inner lead 4a and the metal protruding electrode 6 are joined by intermetallic joining such as eutectic. The area around the inner lead 4a is covered with a sealing resin 7 for protecting the surface of the semiconductor chip 5 and ensuring the strength of the semiconductor device itself.

  Each part dimension is demonstrated using FIG.1 (c). The height HB of the metal projection electrode 6 is 15 μm or more, the depth HP of the recess 2a of the film base 2 is larger than the thickness HL of the inner lead, and the height HB of the metal projection electrode 6 and the thickness HL of the inner lead are Less than the combined value. Further, the width WB of the metal protruding electrode 6 is smaller than the width WL of the inner lead.

  Here, examples of actual dimensions applied when the distance between the centers of adjacent metal protrusion electrodes 6 is 45 μm will be given. If the height HB of the metal projection electrode 6 is 15 μm, the width WB is 20 μm, the thickness HL of the inner lead 4a is 8 μm, and the width WL is 30 μm, the depth HP of the recess 2a of the film substrate 2 is greater than 8 μm and It may be smaller than 23 μm (15 μm + 8 μm). Here, it is 18 μm. In this case, the height HT of the convex portion 2b of the film base 2 between the inner leads 4a and 4a is 10 μm.

  The reason for this dimension is that the gap between the film base 2 and the surface of the semiconductor chip 5 is sufficiently secured as 5 μm, so that the sealing resin is between the film base 2 and the surface of the semiconductor chip 5 at the time of sealing. This is because the resin sealing can be surely performed, and the height HT of the projection 2b of the film base 2 between the inner leads 4a is 10 μm or more. The height is high enough to stop, and a short circuit due to the eutectic melt 14 between the adjacent metal projection electrodes 6 can also be prevented.

Next, the manufacturing method of the film used for the semiconductor device of this Embodiment is demonstrated based on FIG. FIG. 2 is a main cross-sectional view for each process showing a film manufacturing method.
As shown in FIGS. 2A to 2B, a photoresist 16 is applied to the surface of the film base 2 formed of a resin such as polyimide. Then, a photomask having a desired conductor lead 4 pattern is applied and exposed. Next, as shown in FIG. 2C, the exposed photoresist 16 is developed with a developer to form a polyimide exposed portion having the same pattern as the desired conductor lead 4. Next, as shown in FIG. 2 (d), the film base material 2 having uneven portions is formed by performing half etching of the film base material 2 to a predetermined depth together with the photoresist 16 by plasma etching. Next, as shown in FIG. 2E, a metal material such as copper is laminated on the entire surface by sputtering or the like. Then, as shown in FIG. 2F, the metal material laminated on the photoresist 16 is removed by chemically dissolving and removing the photoresist 16, so that a desired conductor lead 4 is obtained.

  Thereafter, a plating material is applied to the surface of the conductor lead 4, and the solder resist 3 is applied to complete. Although plasma etching is used to obtain good flatness of the surface of the conductor lead 4, there is no problem even if wet etching is used. Further, when performing the plasma etching, the photoresist 16 is also etched at the same time as the film base 2, so that the coating thickness of the photoresist 16 needs to be thicker than the thickness to be etched.

Next, a method for manufacturing a semiconductor device will be described with reference to FIG.
As shown in FIG. 4A, the semiconductor chip 5 is placed on the bonding stage 11, and the film 1 is formed on the film 1 by using a forming plate 8 and a clamper 9 each having an opening 12 through which the bonding tool 10 enters and exits. The inner lead 4a and the metal protruding electrode 6 on the semiconductor chip 5 are fixed with a gap. Then, as shown in FIG. 4 (b), the metal projection electrode 6 on the semiconductor chip 5 and the inner lead 4a of the film 1 are respectively set to predetermined positions, and then the bonding tool 10 is lowered while the film 1 is deformed. The inner lead 4a and the metal protruding electrode 6 are joined by a thermocompression bonding method. The thermocompression bonding method refers to the inner lead 4a while applying a temperature (about 300 ° C. to 500 ° C.) and a load necessary for eutectic fusion or solid phase diffusion of the plating material applied to the inner lead 4a and the metal projection material. In this method, the metal bump electrodes 6 are joined. Then, after pressing and heating for a predetermined time, the bonding tool 10 is lifted and detached.

Here, the moment of joining the metal protrusion electrode 6 and the inner lead 4a will be described in more detail.
As shown in FIGS. 3A and 3B, when the centers of the metal protrusion electrodes 6 on the semiconductor chip 5 and the inner leads 4a of the film 1 are aligned, the bonding tool 10 When the film 1 descends while deforming the film 1, the convex portion of the film base 2 between the inner leads 4 a enters the gap between the metal protruding electrodes 6 without any resistance, and the inner surface of the metal protruding electrode 6 and the film 1. The respective centers of the lead 4a coincide and are joined. In the case of bonding by eutectic fusion, as shown in FIGS. 3B and 3C, the eutectic melt 14 is held in the recesses of the film base 2 around the metal bump electrodes 6, It does not flow out to the adjacent metal projection electrode 6.

  On the other hand, as shown in FIG. 5A, when the metal protrusion electrodes 6 on the semiconductor chip 5 and the inner leads 4a of the film 1 are aligned, the respective centers are displaced by a distance X. FIG. As shown in FIG. 5, when the bonding tool 10 descends while deforming the film 1, the convex portion of the film base 2 between the inner leads 4 a comes into contact with the metal projection electrode 6 and further descends. ), Since the film base 2 formed of a resin such as polyimide is more flexible than the metal projection electrode 6, the convex portion of the film base 2 is deformed as the tool descends, and the convex portion In order to release the stress generated by the deformation of the metal, it tries to slip into the gap between the metal bump electrodes 6 (in the direction of the arrow). Therefore, the entire film 1 is displaced in the direction of the arrow and bonded as shown in FIGS. 5D and 5E (this is called a self-alignment effect). That is, conventionally, when the same distance X is shifted as shown in FIG. 10, a short circuit between adjacent neighbors has occurred, but this can be avoided.

  Further, as shown in FIGS. 6A to 6C, the plating material on the surface of the inner lead 4a is not uniformly spread on the metal protruding electrode 6 due to contamination on the surface of the metal protruding electrode 6, and is biased to one side and melts. Even in this case, the eutectic melt 14 is prevented from overflowing to the adjacent metal protruding electrodes 6 by the convex portions of the film base 2, and the occurrence of short-circuit defects can be prevented.

  The semiconductor device according to the present invention can block the flow of the eutectic melt in the COF, can produce a self-alignment effect, facilitate the alignment between the protruding electrode and the conductor lead, and is adjacent to the semiconductor device. Short circuit failure between the protruding electrodes can be prevented, and therefore, it is useful as a semiconductor device used for a flat panel display or the like.

BRIEF DESCRIPTION OF THE DRAWINGS It is a figure which shows the structure of the semiconductor device in embodiment of this invention, (a) is the top view seen through from the direction of a film base material, (b) is AA 'sectional drawing in (a), (c) is It is BB 'sectional drawing in (a). It is sectional drawing explaining the manufacturing method of the film used for the semiconductor device. 2A and 2B are views showing a joining process between an inner lead and a metal protruding electrode in the semiconductor device, wherein FIG. 2A and FIG. 2B are cross-sectional views, and FIG. It is sectional drawing explaining the manufacturing method of the same semiconductor device. 4A and 4B are diagrams showing a bonding process when the center between the inner lead and the metal protruding electrode in the semiconductor device is shifted by a distance X, wherein FIGS. 4A to 4D are cross-sectional views and FIG. In the same semiconductor device, it is a figure which shows the joining state of the inner lead when a eutectic melt becomes non-uniform | heterogenous, and a metal protrusion electrode, (a) And (b) is sectional drawing, (c) is a top view. . 2A and 2B are diagrams illustrating a configuration of a conventional semiconductor device, in which FIG. 1A is a plan view viewed from a conductor lead side, FIG. 2B is a cross-sectional view taken along line CC ′ in FIG. It is D 'sectional drawing. It is sectional drawing which shows the assembly process of the conventional semiconductor device (COF). It is a figure which shows the joining process of the inner lead of the conventional semiconductor device, and a metal protrusion electrode, (a) And (b) is sectional drawing, (c) is a top view. It is a figure which shows the joining process when the center of the inner lead of the conventional semiconductor device and the metal protrusion electrode has shifted | deviated by the distance X, (a)-(c) is sectional drawing, (d) is a top view. It is sectional drawing explaining the manufacturing method of the film used for the conventional semiconductor device. It is a figure which shows the joining state of the inner lead and metal protrusion electrode when the eutectic melt of the conventional semiconductor device becomes non-uniform, (a) and (b) are sectional views, and (c) are plan views. .

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Film 1 'Film 2 Film base material 2' Film base material 3 Solder resist 4 Conductor lead 4 'Conductor lead 4a Inner lead 4a' Inner lead 4b Outer lead 4b 'Outer lead 5 Semiconductor chip 6 Metal protrusion electrode 7 Sealing resin 8 Forming plate 9 Clamper 10 Bonding tool 11 Bonding stage 12 Clamper opening 13 Resin supply nozzle 14 Eutectic melt 15 Metal foil 16 Photo resist 17 Film alignment mark 18 Chip alignment mark

Claims (4)

A film in which conductor leads are formed in the surface of the semiconductor chip on which the projecting electrodes are formed and recesses provided at positions corresponding to the projecting electrodes, and projections are formed between the conductor leads adjacent to each other. It is placed facing the surface of the substrate,
A semiconductor device, wherein the protruding electrode and the conductor lead are joined.   The width of the projecting electrode is made smaller than the width of the conductor lead in the portion joined to the projecting electrode, and the depth of the recess provided in the film base is made larger than the thickness of the conductor lead and 2. The semiconductor device according to claim 1, wherein the height of the electrode is smaller than the sum of the thickness of the conductor lead and the thickness of the conductor lead. A method of manufacturing a semiconductor device according to claim 1 or 2,
A step of applying a photoresist to the surface of a film substrate formed of a resin, a step of applying a photomask having a conductor lead pattern on the surface of the applied photoresist, and an exposure step; Forming an exposed portion of the same pattern as the conductor lead on the surface of the film base, forming a concavo-convex portion of a predetermined shape by etching the surface of the film base in the exposed portion, and a metal material And laminating the film on the surface of the film substrate, and chemically dissolving and removing the remaining photoresist,
A method of manufacturing a semiconductor device, comprising forming a pattern of conductor leads on a surface of a film substrate.   4. The method of manufacturing a semiconductor device according to claim 3, further comprising a step of bonding the protruding electrodes and the conductor leads so that the surfaces of the film base and the semiconductor chip face each other.

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