JP2005198024A - Macro-cell, integrated circuit apparatus, and electronic instrument - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a macro-cell capable of freely allocating a first and a second pad for a differential signal to a first and a second differential signal, and to provide an integrated circuit apparatus and an electronic instrument. <P>SOLUTION: The macro-cell MC 1 includes: a single end receiver 34 connected to the pad P 1 for one of a DP (D+) or a DM (D-) being a signal for constituting a differential signal, and outputting a signal SEQ 1; and a single end receiver 36 connected to the pad P2 for the other one and outputting a signal SEQ 2. A selector 100 included in the MC 1 outputs the SEQ 1 as an SLQ 1 and the SEQ 2 as an SLQ 2 in a first mode and outputs the SEQ 2 as the SLQ 1 and the SEQ 1 as the SLQ 2 in a second mode. A differential receiver 32 outputs a signal DFQ and its reversal signal XDFQ by connecting a first and a second differential input to the pad 1 and the pad 2. A selector 104 outputs the DFQ as an SLQ 3 in the first mode and the XDFQ as the SLQ 3 in the second mode. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a macro cell, an integrated circuit device, and an electronic device.

  In recent years, USB (Universal Serial Bus) has attracted attention as an interface standard for connecting electronic devices. In this USB, data transfer is performed using signals DP (D +) and DM (D−) constituting a differential signal. Therefore, an integrated circuit device having a USB data transfer function has DP and DM pads (first and second pads), and these DP and DM pads are externally connected via external terminals. Connected to a USB receptacle.

However, in conventional integrated circuit devices, the arrangement of these DP and DM pads has been fixed. Therefore, when changing the pad layout for DP and DM according to the specifications of the circuit board (circuit board) on which the integrated circuit device (semiconductor IC) is mounted, the mask pattern and layout of the macrocell of the integrated circuit device are changed. There was a problem that had to be done.
JP 2000-148716 A

  SUMMARY OF THE INVENTION An object of the present invention is to provide a macro cell capable of freely assigning first and second pads for differential signals to first and second signals of a differential signal, an integrated circuit device including the macro cell, and an electronic apparatus. Is to provide.

  The present invention is a macro cell including at least a physical layer circuit of a given interface standard that performs data transfer using a differential signal, and is one of first and second signals constituting the differential signal. A first single-ended receiver that outputs a first output signal, and an input that is connected to a second pad for the other side different from the one, A second single-ended receiver that outputs a first output signal of the first and second output signals from the first and second single-ended receivers in the first mode. 1 as a selector output signal and a second output signal as a second selector output signal. In the second mode, the second output signal of the first and second output signals is the first output signal. 1 selector output Relating the first output signal and outputs a signal to the macrocell and a selector for outputting as said second selector output signal.

  The macro cell according to the present invention includes first and second single-ended receivers as circuits in a physical layer (for example, the lowest layer) that performs data transfer using a differential signal. One of the first and second signals constituting the differential signal is input to the first single-ended receiver via the first pad. The other of the first and second signals is input to the second single-ended receiver via the second pad. In the first mode, the selector outputs the first output signal from the first single-ended receiver as the first selector output signal, and the second output signal from the second single-ended receiver as the second output signal. As a selector output signal. On the other hand, in the second mode, the second output signal from the second single-ended receiver is output as the first selector output signal, and the first output signal from the first single-ended receiver is output as the second selector. Output as an output signal. By doing in this way, it becomes possible to freely assign the first and second pads for differential signals to the first and second signals of the differential signal, and the convenience can be improved.

  In the present invention, the first and second output terminals for outputting the first and second selector output signals from the selector to a second macro cell including a circuit in a layer higher than the physical layer are provided. In the first mode, the selector outputs the first output signal as the first selector output signal to the second macro cell via the first output terminal and the second mode. An output signal is output as the second selector output signal to the second macro cell via the second output terminal, and in the second mode, the second output signal is output to the first selector output signal. Output to the second macro cell via the first output terminal and output the first output signal as the second selector output signal to the second macro cell via the second output terminal. You It may be so.

  In this way, for example, a signal corresponding to the first signal can always be output from the first output terminal, and a signal corresponding to the second signal can always be output from the second output terminal. The influence of the change in the pad arrangement can be prevented from reaching the second macro cell.

  In the present invention, the first and second output terminals may be arranged in a reception interface area provided along one of the four sides of the macro cell.

  In this way, the timing design of signals exchanged between the macro cell and the second macro cell can be facilitated.

  In the present invention, a macro cell includes a first transmission driver that drives a signal line connected to the first pad, and a second transmission driver that drives a signal line connected to the second pad, When the direction from the first side to the third side opposite to the first side is the first direction, the first and second transmission drivers are configured so that the first and second pads of the first and second pads The first and second single-ended receivers are arranged on the direction side and arranged symmetrically about the first line along the first direction as an axis of symmetry. It may be arranged on the first direction side.

  In this way, it is possible to provide a macro cell that can maintain the signal characteristics of a differential signal and the like even if it is arranged in various places, and to reduce the area of the macro cell.

  According to the present invention, there is provided a wiring region for wiring a signal line connecting the first and second single-ended receivers and the first and second pads along the first direction. , And may be provided in an area between the second transmission drivers.

  In this way, the first and second single-ended receivers are connected to the first and second pads by effectively utilizing the empty space between the first and second transmission drivers arranged symmetrically with respect to the line. It is possible to wire a signal line to be performed.

  Further, the present invention is a macro cell including at least a physical layer circuit of a given interface standard that performs data transfer using a differential signal, and is one of first and second signals constituting the differential signal. The first differential input is connected to the first pad for one side, the second differential input is connected to the second pad for the other side different from the one, and the first output signal; A differential receiver that outputs a second output signal that is an inverted signal of the first output signal; and a first mode out of the first and second output signals from the differential receiver in the first mode. An output signal is output as a selector output signal, and the second mode includes a selector that outputs a second output signal of the first and second output signals from the differential receiver as the selector output signal. Related to macrocells.

  The macro cell of the present invention includes a differential receiver as a circuit in a physical layer (for example, the lowest layer) that performs data transfer using a differential signal. One of the first and second signals constituting the differential signal is input to the first differential input of the differential receiver through the first pad. The other of the first and second signals is input to the second differential input of the differential receiver via the second pad. In the first mode, the selector outputs and outputs the first output signal from the differential receiver as a selector output signal. On the other hand, in the second mode, the second output signal from the differential receiver is output as a selector output signal. By doing in this way, it becomes possible to freely assign the first and second pads for differential signals to the first and second signals of the differential signal, and the convenience can be improved.

  The present invention further includes an output terminal for outputting a selector output signal from the selector to a second macro cell including a circuit in a layer higher than the physical layer, and the selector is in the first mode, The first output signal is output as the selector output signal to the second macro cell via the output terminal. In the second mode, the second output signal is output as the selector output signal to the output terminal. And output to the second macro cell.

  In this way, even when the pad arrangement is changed, an appropriate differential amplified signal of the first and second signals can be output from the output terminal.

  In the present invention, the output terminal may be arranged in a reception interface area provided along one of the four sides of the macro cell.

  In this way, the design of the timing of signals exchanged between the macro cell and the second macro cell can be facilitated.

  In the present invention, a macro cell includes a first transmission driver that drives a signal line connected to the first pad, and a second transmission driver that drives a signal line connected to the second pad, When the direction from the first side to the third side opposite to the first side is the first direction, the first and second transmission drivers are configured so that the first and second pads of the first and second pads The differential receiver is arranged on the direction side and arranged symmetrically about the first line along the first direction as an axis of symmetry, and the differential receiver is arranged in the first direction of the first and second transmission drivers. It may be arranged on the side.

  According to the present invention, a wiring region for wiring a signal line connecting the differential receiver and the first and second pads along the first direction is the first and second transmission drivers. You may make it provide in the area | region between.

  In the present invention, the given interface standard may be a USB (Universal Serial Bus) standard.

  In the present invention, the entire macro cell I / O area is arranged so as to overlap with a part of the I / O area of the second macro cell including the upper layer circuit than the physical layer. , When the length of the first side of the macro cell is L and the pitch width of the I / O cell arranged in the I / O region of the second macro cell is PL, L = PL × N ( N may be an integer of 2 or more.

  In this way, the macro cell can be arranged in various places, and convenience can be improved. Even when the macrocells are arranged in various places as described above, it is possible to maintain the signal characteristics and the like of the differential signal.

  The present invention also relates to an integrated circuit device that is a physical layer circuit including a plurality of macrocells, and includes any one of the above macrocells and a second macrocell including a higher layer circuit than the physical layer.

  The present invention also relates to an electronic apparatus including the integrated circuit device described above and a processing unit that controls the integrated circuit device.

  Hereinafter, preferred embodiments of the present invention will be described in detail. The present embodiment described below does not unduly limit the contents of the present invention described in the claims, and all the configurations described in the present embodiment are indispensable as means for solving the present invention. Not necessarily.

1. Configuration of Integrated Circuit Device FIG. 1 shows a configuration example of an integrated circuit device to which the macro cell of this embodiment is applied. This integrated circuit device includes a macro cell MC1 and a second macro cell MC2. Note that these macrocells MC1 and MC2 (megacells and macroblocks) are units of a medium-scale or large-scale circuit having a logic function. Further, the integrated circuit device of this embodiment may include three or more macro cells.

  In FIG. 1, a macro cell MC1 is a macro cell including at least a physical layer circuit of an interface standard (for example, USB or IEEE 1394) that performs data transfer using a differential signal (serial bus). The physical layer circuit includes, for example, a transmission circuit (first and second transmission drivers) and a reception circuit (differential receiver, first and second) that realize a USB FS (full speed) mode and an HS (high speed) mode. A single-ended receiver) and a resistor circuit (pull-up resistor circuit, pull-down resistor circuit) and the like. Note that the macro cell MC1 may include a circuit (a logic layer circuit or the like) other than the physical layer circuit.

  The macro cell MC1 is, for example, a hard macro whose wiring and circuit cell arrangement are fixed. More specifically, for example, wiring and circuit cell placement are performed by manual layout (part of wiring and placement may be automated).

  On the other hand, the macro cell MC2 is a macro cell including circuits in layers higher than the physical layer (logical layer, link layer, transaction layer, application layer, etc.). Taking USB as an example, the macro cell MC2 can include a logic layer circuit (another part of the logic layer circuit included in the MC1) such as an SIE (Serial Interface Engine) or a user logic (device-specific circuit).

  The macro cell MC2 is, for example, a soft macro whose wiring and circuit cell arrangement are automatically arranged and wired. More specifically, for example, wiring between basic cells is automatically performed by a gate array automatic placement and routing tool (part of placement and wiring may be fixed).

  In FIG. 1, a macro cell including only a physical layer circuit may be used as the macro cell MC1. The macro cell MC2 only needs to include at least a circuit of a layer higher than the physical layer.

  In FIG. 1, I / O regions are provided along the four sides of the integrated circuit device. In this I / O area, a plurality of I / O cells (input-only cells, output-only cells, and input / output cells) are arranged side by side. A plurality of pads including pads P1 and P2 (terminals) for differential signals DP (D +) and DM (D−) are arranged side by side outside the I / O region. In FIG. 1, MC1 is arranged so that the entire I / O area of macro cell MC1 overlaps a part of the I / O area of macro cell MC2. Note that the pad may be provided in the I / O region (in the I / O cell).

2. Configuration of Data Transfer Control Device FIG. 2 shows a configuration example of a data transfer control device realized by the integrated circuit device of FIG. Note that the device realized by the integrated circuit device of this embodiment is not limited to the configuration shown in FIG. For example, a data transfer control device having a configuration different from that shown in FIG. 2 may be realized. Alternatively, an application layer device, a CPU (processor in a broad sense), or the like may be added to the configuration of FIG. 2 to form a single chip as an integrated circuit device.

  The data transfer control device (integrated circuit device) of FIG. 2 includes a transceiver 200, a transfer controller 210, a buffer controller 220, a data buffer 230, and an interface circuit 240. Note that some of these circuit blocks may be omitted or the connection form between these circuit blocks may be changed.

  The transceiver 200 is a circuit for transmitting and receiving data using differential signals DP and DM (differential data signals). The transceiver 200 can include, for example, a physical layer circuit (analog front-end circuit) of USB (a given interface standard in a broad sense). The transceiver 200 may include circuits in layers other than the physical layer.

  The transfer controller 210 is a controller for controlling data transfer via the USB, and is for realizing a so-called SIE (Serial Interface Engine) function and the like. For example, the transfer controller 210 performs packet handle processing, suspend / resume control, or transaction management.

  The buffer controller 220 secures a storage area (endpoint area or the like) in the data buffer 230 and controls access to the storage area of the data buffer 230. More specifically, the buffer controller 220 controls access from the application layer device side via the interface circuit 240, access from the CPU side via the interface circuit 240, and access from the USB (transfer controller 210) side. Access arbitration, access address generation and management.

  The data buffer 230 (packet buffer) is a buffer (FIFO) for temporarily storing (buffering) data (transmission data or reception data) transferred via the USB. The data buffer 230 can be constituted by a memory such as a RAM.

  The interface circuit 240 is a circuit for realizing an interface via a DMA (Direct Memory Access) bus to which an application layer device is connected and a CPU bus to which a CPU is connected. The interface circuit 240 can include a DMA handler circuit for DMA transfer.

  The macro cell MC1 of FIG. 1 can include some or all of the transceiver 200 of FIG. The macro cell MC2 can include a part or all of the transfer controller 210, the buffer controller 220, the data buffer 230, and the interface circuit 240. The macro cell MC2 may include a circuit such as an application layer device.

3. Configuration of Transceiver FIG. 3 shows a detailed configuration example of the transceiver 200 (physical layer circuit).

  In FIG. 3, a transmission circuit 10 is a circuit for performing a data transmission process using differential signals DP and DM in, for example, the USB FS mode. The transmission circuit 10 includes a first transmission driver 12 that drives a signal line connected to a pad of a signal DP (first signal in a broad sense) that constitutes a differential signal, and a signal DM that constitutes the differential signal. A second transmission driver 14 for driving a signal line connected to a pad (second signal in a broad sense) is included. By driving the signal lines of the DP and DM pads by the transmission drivers 12 and 14, differential signals can be transmitted using the DP and DM pads (data terminals).

  The transmission circuit 10 includes a first damping resistor RDP1 and a second damping resistor RDP2 connected to DP and DM pads (first and second pads in a broad sense). One end of these damping resistors RDP1, RDP2 is connected to the outputs of the transmission drivers 12, 14, and the other end is connected to the pads of DP, DM. The transmission circuit 10 (integrated circuit device) may not include the damping resistors RDP1 and RDP2. In this case, the damping resistors RDP1 and RDP2 may be realized with external parts.

  The first and second transmission control circuits 22 and 24 are circuits for controlling the first and second transmission drivers 12 and 14. Specifically, the transmission control circuit 22 receives the transmission data signal DOUT1 and the output disable signal OUTDIS from the preceding circuit (for example, the circuit in the macro cell MC2), and outputs the control signals OP1 and ON1 to the transmission driver 12. The transmission control circuit 24 receives the signals DOUT2 and OUTDIS from the preceding circuit, and outputs control signals OP2 and ON2 to the transmission driver 14.

  The reception circuit 30 is a circuit for performing data reception processing using the differential signals DP and DM in, for example, the USB FS mode. The receiving circuit 30 includes a differential receiver 32 and first and second single-ended receivers 34 and 36.

  The differential receiver 32 (differential comparator) differentially amplifies the differential signal input through the DP and DM pads, and outputs the differential signal as a data signal DIN to a subsequent circuit (for example, a circuit in the macro cell MC2). . The differential receiver 32 can be realized by an operational amplifier circuit in which the differential signals DP and DM are input to the first and second differential inputs. The operation of the differential receiver 32 is enabled or disabled by an enable signal COMPENB.

  The single-ended receiver 34 amplifies the single-ended signal input via the DP pad, and outputs the amplified signal as a data signal SEDIN1 to a subsequent circuit (for example, a circuit in the macro cell MC2). The single-ended receiver 36 amplifies the single-ended signal input via the DM pad and outputs the amplified signal as a data signal SEDIN2 to a subsequent circuit. These single-ended receivers 34 and 36 can be realized by, for example, a buffer circuit having a hysteresis characteristic with different thresholds at the time of rising and falling of the input voltage. The operations of the single end receivers 34 and 36 are enabled or disabled by enable signals SEENB1 and SEENB2.

  The pull-up resistor circuit 40 is a circuit for pulling up the DP signal line, and is connected to the DP pad (first pad). This resistance circuit 40 includes a switch element SUP1 realized by a transistor or the like and a pull-up resistor RUP1 of, for example, 1.5 K ohms. Specifically, one end of the switch element SUP1 is connected to the DP pad, and the other end is connected to one end of the resistor RUP1. The other end of the resistor RUP1 is connected to the power supply VDD.

  The resistance circuit 42 is a dummy resistance circuit for forming, in the DM signal line, a parasitic capacitance equivalent to the parasitic capacitance formed by connecting the resistance circuit 40 to the DP signal line. Connected to signal line. The resistor circuit 42 includes a switch element SUP2 and a resistor RUP2 having the same configuration (same gate length / gate width and the same resistance) as the switch element SUP1 and resistor RUP1 of the resistor circuit 40. Specifically, one end of the switch element SUP2 is connected to the DM pad, and the other end is connected to one end of the resistor RUP2.

  In FIG. 3, the resistors RUP1 and RUP2 are provided on the power supply VDD side, but the switch elements SUP1 and SUP2 may be provided on the power supply VDD side.

  The resistance control circuits 50 and 52 are circuits for controlling the resistance circuits 40 and 42. Specifically, the resistance control circuits 50 and 52 generate signals RUPSW1 and RUPSW2 for controlling on / off of the switch elements SUP1 and SUP2, and output them to the resistance circuits 40 and 42.

  The resistance control circuit 50 outputs a signal RUPSW1 based on a pull-up enable signal RUPENB1 from a preceding circuit (for example, a circuit in the macro cell MC2), and controls on / off of the switch element SUP1. On the other hand, the resistance control circuit 52 outputs a signal RUPSW2 based on the pull-up enable signal RUPENB2 from the preceding circuit, and controls the on / off of the switch element SUP2.

  FIG. 4A shows a specific circuit configuration example of the transmission circuit 10 (for FS). The transmission driver 12 includes a P-type transistor TPTR1 and an N-type transistor TNTR1 connected in series between power supplies VDD and VSS (first and second power supplies in a broad sense). A damping resistor RDP1 is provided between the output node TN1 and the node of DP. The transmission driver 14 includes a P-type transistor TPTR2 and an N-type transistor TNTR2 connected in series between the power supplies VDD and VSS. A damping resistor RDP2 is provided between the output node TN2 and the node of DM.

  The transmission control circuit 22 receives the signals DOUT1 and OUTDIS from the preceding circuit, performs a logical operation according to the truth table shown in FIG. 4B, and outputs the signals OP1 and ON1 to the transmission driver 12. The transmission control circuit 24 receives the signals DOUT2 and OUTDIS from the preceding circuit, performs a logical operation according to the truth table shown in FIG. 4B, and outputs the signals OP2 and ON2 to the transmission driver 14. For example, assume that OUTDIS is at a low level (L level). Then, when DOUT1 is low level, DP becomes low level, and when DOUT1 is high level (H level), DP becomes high level. When DOUT2 is at a low level, DM is at a low level, and when DOUT2 is at a high level, DM is at a high level. On the other hand, when OUTDIS is high bell, both DP and DM are in a high impedance state.

  FIG. 5 shows a specific circuit configuration example of the differential receiver 32 (for FS). The differential receiver 32 includes operational amplifier circuits 120 and 122, an output circuit 124, inverter circuits 126 and 128, and a reference voltage generation circuit 130. Note that some of these may be omitted.

  Here, the operational amplifier circuit 120 includes transistors TA1 and TA2 constituting a current mirror circuit, transistors TA3 and TA4 constituting a differential pair, and a transistor TA5 constituting a current source. The operational amplifier circuit 122 includes transistors TA6 and TA7 that constitute a current mirror circuit, transistors TA8 and TA9 that constitute a differential pair, and a transistor TA10 that constitutes a current source. The output circuit 124 includes a driving transistor TA11 and a transistor TA12 that is connected in series to TA11 and forms a current source. The output circuit 124 also includes a transistor TA13 for setting the output node NA5 of the output circuit 124 to a predetermined voltage (VDD) when the enable signal ENB (COMPENB) is at a low level (non-active).

  The signals DP and DM (first and second signals) are input to the gates of the transistors TA3 and TA4 which are the first and second differential inputs of the operational amplifier circuit 120. Output signals from the output nodes NA2 and NA1 of the operational amplifier circuit 120 are input to the gates of the transistors TA8 and TA9 which are the first and second differential inputs of the arithmetic operation circuit 122. An output signal from the output node NA4 of the arithmetic operation circuit 122 is input to the gate of the transistor TA11 of the output circuit 124. The output signal from the output node NA5 of the output circuit 124 is buffered by the inverter circuit 126 configured by the transistors TA14 and TA15 and the inverter circuit 128 configured by the transistors TA16 and TA17, and is output as the signal DIN.

  The reference voltage generation circuit 130 receives the comparator enable signal COMPENB and outputs a reference voltage VREF and an enable signal ENB. The reference voltage VREF is input to the gates of the transistors TA5, TA10, and TA12 that constitute the current source. The enable signal ENB is input to the gate of the transistor TA13 of the output circuit 124.

  FIG. 6 shows a circuit configuration example of the reference voltage generation circuit 130. Reference voltage generation circuit 130 includes transistors TB1 and TB2 constituting a current mirror circuit, transistor TB3 connected in series to TB1, transistor TB4 connected in series to TB2, and transistor TB5 connected to output node NB2. .

  When the signal COMPENB becomes high level (active), the transistor TB3 is turned on, and the current flowing through the transistors TB1 and TB3 flows to the transistors TB2 and TB4 by the current mirror, thereby generating the reference voltage VREF at the output node NB2. On the other hand, when the signal COMPENB becomes low level (non-active), the transistor TB3 is turned off and the transistor TB5 is turned on. As a result, the reference voltage VREF is set to VSS (for example, 0 V) and the current flowing in the reference voltage generation circuit 130 is cut off. Further, when the reference voltage VREF becomes VSS, the transistors TA5, TA10, and TA12 in FIG. 5 are turned off, and the current flowing in the operational amplifier circuits 120 and 122 and the output circuit 124 is cut off. Further, when the signal ENB becomes low level and the transistor TA13 in FIG. 5 is turned on, the voltage of the output node NA5 becomes VDD, and generation of a through current due to the unstable voltage of NA5 is prevented. As described above, when the differential receiver 32 is disabled, the current flowing in the differential receiver 32 can be cut off (limited), and the power consumption can be reduced.

  FIG. 7 shows a circuit configuration example of the single end receiver 34 (36). The single-ended receiver 34 (36) includes a buffer circuit 140 having a threshold voltage hysteresis characteristic and inverter circuits 142 and 144.

  The buffer circuit 140 includes transistors TC1, TC2, TC3, and TC4 connected in series, a transistor TC5 connected in parallel to TC1, a transistor TC6 connected in parallel to TC2, and a transistor TC7 connected in parallel to TC4. The buffer circuit 140 includes a feedback inverter circuit 141 including transistors TC8, TC9, TC10, and TC11. Note that VSS is connected to the gate of the transistor TC1, and VDD is connected to the gate of the TC4.

  The signal DP (DM) is input to the gates of the transistors TC2 and TC3 of the buffer circuit 140. The output signal from the output node NC2 of the buffer circuit 140 is buffered by the inverter circuit 142 composed of the transistors TC12 and TC13 and the inverter circuit 144 composed of the transistors TC14 and TC15, and output as a signal SEDIN1 (SEDIIN2). Is done.

  When the signal DP (DM) is at a low level, the voltage at the output node NC2 is at a low level, the transistor TC5 is turned on, and the on-resistance on the P-type transistor side is reduced. As a result, the threshold voltage when the signal DP (DM) changes from the low level to the high level is increased. On the other hand, when the signal DP (DM) is at a high level, the voltage at the output node NC2 is at a high level, the transistor TC7 is turned on, and the on-resistance on the N-type transistor side is reduced. Thereby, the threshold voltage when the signal DP (DM) changes from the high level to the low level is lowered. Thus, the hysteresis characteristic of the threshold voltage of the buffer circuit 140 is realized.

  When the enable signal SEENB1 becomes low level (non-active), the transistor TC6 is turned on and the voltage of the node NC1 is set to VDD. Further, the transistor TC11 is turned on, and the voltage of the node NC2 is set to VSS. Further, the transistor TC8 is turned off, and the current flowing in the feedback inverter circuit 141 is cut off. As described above, when the single end receiver 34 (36) is disabled, the current flowing in the single end receiver 34 (36) can be cut off (restricted), and the power consumption can be reduced.

4). Circuit Configuration of Macro Cell MC1 When the integrated circuit device of FIG. 1 is mounted on a circuit board, there are the following problems. For example, in FIG. 8A, the integrated circuit device 500 and the USB receptacle 510 are mounted on the same surface on one surface side (for example, the front surface side) of the circuit board 520. The DP and DM terminals of the integrated circuit device 500 and the DP and DM terminals of the receptacle 510 are connected to each other by wirings WL1 and WL2 as indicated by E1 in FIG. The USB receptacle 510 includes an A receptacle, a B receptacle, a Mini-A receptacle, a Mini-B receptacle, a Mini-AB receptacle, and the like.

  On the other hand, in FIG. 8B, the integrated circuit device 500 is mounted on one surface side (for example, the front surface side) of the circuit board 520, and the USB receptor 510 is mounted on the other surface side (for example, the back surface side) of the circuit board 520. It is mounted on the reverse side. Then, the DP and DM terminals of the integrated circuit device 500 and the DP and DM terminals of the receptacle 510 are connected by wirings WL1 and WL2 as indicated by E2 in FIG. 8B.

  In this case, as apparent from comparing E3 in FIG. 8A and E4 in FIG. 8B, the arrangement of the DP and DM terminals of the integrated circuit device 500 is different. Therefore, in order to correspond to various mounting forms as shown in FIGS. 8A and 8B, the arrangement of DP and DM terminals and the arrangement of pads connected to these terminals via bonding wires are changed. There is a need.

  However, in conventional integrated circuit devices, the DP and DM pad arrays have been fixed. Therefore, in order to cope with various mounting modes such as the same surface mounting and the reverse surface mounting as shown in FIGS. 8A and 8B, it is necessary to cross the wirings WL1 and WL2, and this is because DP , DM signal characteristics are degraded.

  Also, an integrated circuit device (macrocell) in which DP and DM pads are arranged in the arrangement of E3 in FIG. 8A, and an integrated circuit device in which DP and DM pads are arranged in the arrangement of E4 in FIG. If a different model is prepared, the cost of the product will be increased and the development period will be prolonged. Further, by changing the arrangement of the DP and DM pads, the symmetry of the DP and DM signal characteristics may be lost, and the signal characteristics may be deteriorated.

  Therefore, in the present embodiment, a technique is employed in which the arrangement of DP and DM can be arbitrarily changed by simply inputting a select signal without changing the layout of the macro cell MC1. FIG. 9 shows a circuit configuration example of the macro cell MC1 using this technique. In FIG. 9, various enable signals (OUTDIS, COMPENB, etc.) described in FIG. 3 are omitted.

  In FIG. 9, the first pad P1 is a pad for one of signals DP and DM (first and second signals in a broad sense) constituting a differential signal, and the second pad P2 is This is a pad for the other side different from the one side. For example, in the first mode, the pad P1 is a DP pad, and the pad P2 is a DM pad. On the other hand, in the second mode, the pad P1 is a DM pad and the pad P2 is a DP pad. These first and second modes can be switched by a select signal SEL. When the signal SEL is at a first level (for example, high level), the first mode is set, and the signal SEL is at a second level ( For example, in the case of low level), the second mode is set.

  The input of the first single-ended receiver 34 is connected to the pad P1 (signal line SL1 connected to P1), and the first output signal SEQ1 is output. The second single-ended receiver 36 has its input connected to the pad P2 (signal line SL2 connected to P2), and outputs a second output signal SEQ2. As these single-ended receivers 34 and 36, for example, a circuit having a configuration as shown in FIG. 7 can be adopted, but the present invention is not limited to this.

  When the select signal SEL becomes the first level and is set to the first mode, the selector 100 outputs SEQ1 as the first selector output signal SLQ1 from the output signals SEQ1 and SEQ2 from the single-ended receivers 34 and 36. To do. The output signal SEQ2 is output as the second selector output signal SLQ2. On the other hand, when the select signal SEL becomes the second level and the second mode is set, SEQ2 of the output signals SEQ1 and SEQ2 is output as the selector output signal SLQ1. The output signal SEQ1 is output as the selector output signal SLQ2.

  In this manner, in the first mode, the signal (for example, DP) from the pad P1 is amplified by the single end receiver 34 and output as the selector output signal SLQ1, and the signal (for example, DM) from the pad P2 is single. The signal is amplified by the end receiver 36 and output as the selector output signal SLQ2. On the other hand, when the pad arrangement is changed to the second mode, the signal (for example, DP) from the pad P2 is amplified by the single-ended receiver 36 and output as the selector output signal SLQ1, and the signal (for example, DM) from the pad P1. Is amplified by the single-ended receiver 34 and output as the selector output signal SLQ2.

  9, the differential receiver 32 has its first differential input connected to the pad P1, its second differential input connected to the pad P2, and the first output signal DFQ and the DFQ of the DFQ. A second output signal XDFQ which is an inverted signal is output. As the differential receiver 32, for example, a circuit having a configuration as shown in FIG. 5 can be adopted, but the present invention is not limited to this. As the output signal XDFQ, for example, the output signal of the inverter circuit 126 in FIG. 5 can be used.

  When the selector 102 is set to the first mode, the selector 102 outputs the DFQ of the output signals DFQ and XDFQ from the differential receiver 32 as the selector output signal SLQ3. On the other hand, when the second mode is set, XDFQ of the output signals DFQ and XDFQ from the differential receiver 32 is output as the selector output signal SLQ3.

  As described above, in the first mode, proper differential amplification in which the signal from the pad P1 (for example, DP) has a positive polarity and the signal from the pad P2 (for example, DM) has a negative polarity is performed by the differential receiver 32. The differentially amplified signal is output as the selector output signal SLQ3. On the other hand, when the pad arrangement is changed to the second mode, proper differential amplification in which the signal from the pad P2 (for example, DP) has a positive polarity and the signal from the pad P1 (for example, DM) has a negative polarity is differential. A signal that is differentially amplified by the receiver 32 is output as the selector output signal SLQ3.

  The setting information of the select signal SEL can be stored in a memory (register) such as an EEPROM (rewritable nonvolatile memory) or a mask ROM incorporated in the integrated circuit device (macrocell MC1). For example, when the pad P1 is set as the DP pad and the pad P2 is set as the DM pad, the information for setting the first signal by setting the select signal SEL to the first level is stored in the memory. Just remember. For example, when the pad P1 is set as a DM pad and the pad P2 is set as a DP pad, information for setting the select signal SEL to the second level, for example, to set the second mode is stored in the memory. You can memorize it.

  9 includes output terminals TM1, TM2, and TM3 for outputting the selector output signals SLQ1 and SLQ2 from the selector 100 and the selector output signal SLQ3 from the selector 102 to the macrocell MC2 in FIG. Can do. Here, as described above, the macro cell MC2 is a macro cell including a circuit in a layer higher than the physical layer (a logical layer, a link layer, a transaction layer, an application layer, or the like).

  In the first mode, selector 100 outputs output signal SEQ1 as selector output signal SLQ1 to macro cell MC2 via output terminal TM1. Further, the output signal SEQ2 is outputted as the selector output signal SLQ2 to the macro cell MC2 via the output terminal TM2. On the other hand, in the second mode, the output signal SEQ2 is output as the selector output signal SLQ1 to the macro cell MC2 via the output terminal TM1. The output signal SEQ1 is output to the macro cell MC2 via the output terminal TM2 as the selector output signal SLQ2.

  In the first mode, the selector 102 outputs the output signal DFQ as the selector output signal SLQ3 to the macro cell MC2 via the output terminal TM3. On the other hand, in the second mode, the output signal XDFQ is output as the selector output signal SLQ3 to the macro cell MC2 via the output terminal TM3.

  These output terminals TM1, TM2, and TM3 can be fixedly arranged in a reception interface region provided along one side (for example, the third side) of the four sides of the macro cell MC1. The output terminals TM1, TM2, and TM3 are signal lines for outputting the signals SLQ1, SLQ2, and SLQ3 in an actual layout, and are defined as output terminals in the net list of the macro cell MC1, for example. The reception interface area will be described later.

  The selector output signal SLQ1 output via the output terminal TM1 corresponds to the signal SEDIN1 in FIG. 3, and the selector output signal SLQ2 output via the output terminal TM2 corresponds to the signal SEDIN2. A selector output signal SLQ3 output via the output terminal TM3 corresponds to the signal DIN. Note that a buffer circuit that performs buffering of these signals, a circuit that performs voltage level shift, and the like can be included in the selectors 100 and 102.

  In FIG. 9, when the selector 104 is set to the first mode, the selector 104 outputs SLI4 of the first and second input signals SLI4 and SLI5 (data signal) as the first selector output signal SLQ4. The input signal SLI5 is output as the second selector output signal SLQ5. On the other hand, when the second mode is set, SLI5 of the input signals SLI4 and SLI5 is output as the selector output signal SLQ4. The input signal SLI4 is output as the selector output signal SLQ5.

  The transmission driver 12 receives transmission control signals OP1 and ON1 corresponding to the selector output signal SLQ4, and drives the signal line SL1 connected to the pad P1. The transmission driver 14 receives transmission control signals OP2 and ON2 corresponding to the selector output signal SLQ5, and drives the signal line SL2 connected to the pad P2.

  In this manner, in the first mode, the signal line SL1 connected to the pad P1 (for example, DP) is driven by the transmission driver 12 with a voltage corresponding to the input signal SLI4, and is applied to the pad P2 (for example, DM). The signal line SL2 to be connected is driven by the transmission driver 14 with a voltage corresponding to the input signal SLI5. On the other hand, when the pad arrangement is changed to enter the second mode, the signal line SL2 connected to the pad P2 (for example DP) is driven by the transmission driver 14 with a voltage corresponding to the input signal SLI4, and the pad P1 (for example DM ) Is driven by the transmission driver 12 at a voltage corresponding to the input signal SLI5.

  In FIG. 9, when the selector 106 is set to the first mode, the selector 106 outputs SLI6 among the first and second input signals SLI6 and SLI7 as the first selector output signal SLQ6. The input signal SLI7 is output as the second selector output signal SLQ7. On the other hand, when the second mode is set, SLI7 of the input signals SLI6 and SLI7 is output as the selector output signal SLQ6. The input signal SLI6 is output as the selector output signal SLQ7.

  The first resistance circuit 40 receives a resistance control signal RUPSW1 corresponding to the selector output signal SLQ6. The first resistor circuit 40 functions as a pull-up or dummy resistor circuit connected to the pad P1. The second resistance circuit 42 receives a resistance control signal RUPSW2 corresponding to the selector output signal SLQ7. The second resistor circuit 42 functions as a pull-up or dummy resistor circuit connected to the pad P2.

  In this way, in the first mode, the resistor circuit 40 connected to the pad P1 (for example, DP) functions as, for example, a pull-up resistor circuit, the signal line SL1 is pulled up, and the pad P2 ( For example, the resistor circuit 42 connected to DM) functions as a dummy resistor circuit, for example. On the other hand, when the pad arrangement is changed to the second mode, the resistor circuit 42 connected to the pad P2 (for example, DP) functions as, for example, a pull-up resistor circuit and is connected to the pad P1 (for example, DM). The resistor circuit 40 functions as a dummy resistor circuit, for example. As a result, proper pull-up control can be realized even if the pad arrangement is changed.

  In order to support USB OTG (On-The-Go), a first pull-down resistor circuit connected to the signal line SL1 and a second pull-down resistor circuit connected to the signal line SL2 are used. And a selector for these resistance circuits may be provided. The pull-down first and second resistor circuits and the selector may be operated in the same manner as the resistor circuits 40 and 42 and the selector 106 in FIG.

  9 can include input terminals TM4, TM5, TM6, and TM7 for inputting input signals SLI4, SLI5, SLI6, and SLI7 from the macrocell MC2 of FIG.

  In the first mode, the selector 104 outputs the input signal SLI4 input via the input terminal TM4 as the selector output signal SLQ4. Also, the input signal SLI5 input via the input terminal TM5 is output as the selector output signal SLQ5. On the other hand, in the second mode, the input signal SLI5 input via the input terminal TM5 is output as the selector output signal SLQ4. Also, the input signal SLI4 input through the input terminal TM4 is output as the selector output signal SLQ5.

  In the first mode, the selector 106 outputs the input signal SLI6 input through the input terminal TM6 as the selector output signal SLQ6. Further, the input signal SLI7 input via the input terminal TM7 is output as the selector output signal SLQ7. On the other hand, in the second mode, the input signal SLI7 input via the input terminal TM7 is output as the selector output signal SLQ6. Further, the input signal SLI6 input through the input terminal TM6 is output as the selector output signal SLQ7.

  These input terminals TM4 to TM7 can be fixedly arranged in a transmission interface area provided along one side (for example, the third side) of the four sides of the macro cell MC1. Input terminals TM4 to TM7 are signal lines for inputting signals SLQ4 to SQ7 in the actual layout, and are defined as input terminals in the net list of macro cell MC1, for example. The transmission interface area will be described later.

  The signal SLI4 input via the input terminal TM4 corresponds to the signal DOUT1 in FIG. 3, and the signal SLI5 input via the input terminal TM5 corresponds to the signal DOUT2. The signal SLI6 input via the input terminal TM6 corresponds to the signal RUPENB1, and the signal SLI7 input via the input terminal TM7 corresponds to the signal RUPENB2.

  FIG. 10A shows a circuit configuration example of the selectors 100, 104, and 106 in FIG. 9, and FIG. 10B shows a circuit configuration example of the selector 102. Note that the configurations of these selectors are not limited to the configurations shown in FIGS.

  For example, in FIG. 10A, when the signal S (select signal SEL) is at a high level (first level), the transfer gates TG1 and TG4 composed of P-type transistors and N-type transistors are turned on (conductive state). TG2 and TG3 are turned off (non-conducting state). As a result, the input signals I1 and I2 are output as the output signals Q1 and Q2, respectively. On the other hand, when the signal S becomes low level (second level), the transfer gates TG2 and TG3 are turned on and TG1 and TG4 are turned off. As a result, the input signals I1 and I2 are output as output signals Q2 and Q1, respectively.

  In FIG. 10B, when the signal S becomes high level, the input signal I1 is selected and output as the output signal Q. When the signal S becomes low level, the input signal I2 is selected and output as the output signal Q. Will come to be.

  According to the macro cell MC1 of FIG. 9 described above, the DP and DM pad arrangement can be arbitrarily changed by changing the setting of the select signal SEL without changing the layout of the macro cell MC1.

  For example, if the select signal is set to the first level to set the first mode, the pad P1 can be used as a DP pad and the pad P2 can be used as a DM pad. On the other hand, if the select signal is set to the second level to set the second mode, the pad P2 can be used as a DP pad, and the pad P1 can be used as a DM pad. Thereby, it is possible to flexibly cope with various mounting forms as shown in FIGS.

  Even if the pad arrangement is changed in this way, according to the present embodiment, the terminals TM1, TM4, and TM6 can be used as dedicated DP terminals, and the terminals TM2, TM5, and TM7 can be used as dedicated DM terminals. There is an advantage that it can be used. Further, there is an advantage that an appropriate differential amplified signal corresponding to the polarities of the signals DP and DM can be output from the terminal TM3.

  That is, according to the present embodiment, in the first mode, the signal SLQ1 corresponding to the signal DP input to the pad P1 is output from the terminal TM1, and the signal SLQ2 corresponding to the signal DM input to the pad P2 is Output from terminal TM2. Even when the pad arrangement is changed in the second mode, the signal SLQ1 corresponding to the signal DP input to the pad P2 is output from the terminal TM1 and corresponds to the signal DM input to the pad P1. The signal SLQ2 to be output is output from the terminal TM2. That is, regardless of whether the mode is set to the first mode or the second mode, a signal corresponding to the signal DP is always output from the terminal TM1, and a signal corresponding to the signal DM is output from the terminal TM2. become.

  Further, according to the present embodiment, in the first mode, the signal SLQ3 differentially amplified with the signal DP input to the pad P1 having the positive polarity and the signal DM input to the pad P2 having the negative polarity is the terminal TM3. Is output from. Even when the pad arrangement is changed in the second mode, the signal DP input to the pad P2 has a positive polarity, and the signal DM input to the pad P1 has a negative polarity to be differentially amplified. SLQ3 is output from the terminal TM3. That is, regardless of the first mode or the second mode, an appropriate differential amplified signal corresponding to the polarities of the signals DP and DM is always output from the terminal TM3.

  According to the present embodiment, in the first mode, the signal line SL1 of the DP pad P1 is driven based on the DP input signal SLI4 input from the terminal TM4, and DM input from the terminal TM5. The signal line SL2 of the DM pad P2 is driven based on the input signal SLI5. Even when the pad arrangement is changed in the second mode, the signal line SL2 of the DP pad P2 is driven based on the DP input signal SLI4 input from the terminal TM4, and the terminal TM5 The signal line SL1 of the DM pad P1 is driven based on the input signal SLI5 for DM input from. That is, regardless of whether the mode is set to the first mode or the second mode, a DP signal can always be input to the terminal TM4 and a DM signal can be input to the terminal TM5.

  Further, according to the present embodiment, in the first mode, the signal line SL1 of the DP pad P1 is pulled up based on the DP input signal SLI6 input from the terminal TM6 and input from the terminal TM7. Based on the DM input signal SLI7, the signal line SL2 of the DM pad P2 is not pulled up. Even when the pad arrangement is changed in the second mode, the signal line SL2 of the DP pad P2 is pulled up based on the DP input signal SLI6 input from the terminal TM6, and the terminal Based on the DM input signal SLI7 input from TM7, the signal line SL1 of the DM pad P1 is not pulled up. That is, regardless of whether the mode is set to the first mode or the second mode, a DP signal can always be input to the terminal TM6 and a DM signal can be input to the terminal TM7.

  As described above, according to the present embodiment, the DP and DM pad arrays can be arbitrarily changed, while the terminals TM1 to TM7 can be fixed as DP and DM terminals, respectively. Accordingly, the interface portion (terminal-wiring connection portion) with the macro cell MC2 including the upper layer circuit can be fixed, and even when the DP and DM pad arrangement is changed, the macro cell MC2 can be prevented from being affected.

  In the present embodiment, the DP and DM pad arrangement can be changed simply by changing the setting of the select signal SEL. The differential receiver 32, the single-ended receivers 34 and 36, the transmission drivers 12 and 14, the resistance circuit 40, There is no need to change the layout of the physical layer circuit such as 42. Therefore, there is an advantage that good signal characteristics of the signals DP and DM can be maintained.

5). Layout of Macro Cell MC1 FIG. 11 shows a layout example of the macro cell MC1 of the present embodiment. The layout of the macro cell MC1 is not limited to the example shown in FIG. 11, and various modifications can be made.

  The macro cell MC1 in FIG. 11 includes an I / O region in which a plurality (N) of I / O cells are arranged. The plurality of I / O cells are arranged side by side along the longitudinal direction of the I / O region. A plurality of pads including DP and DM pads P1 and P2 are arranged outside the I / O region. The I / O region (I / O cell) may include a pad.

  It is assumed that the direction from the first side SD1 of the macro cell MC1 toward the third side SD3 facing the SD1 is a first direction DR1. Then, the transmission drivers 12 and 14 included in the transmission circuit 10 are disposed on the first direction DR1 side of the pads P1 and P2 (I / O region). Specifically, the transmission drivers 12 and 14 are arranged so as to be adjacent to the I / O area.

  A line along the first direction DR1 is defined as a first line SYL. Then, the transmission drivers 12 and 14 are arranged in line symmetry (including the case of being substantially line symmetrical) with the line SYL as the axis of symmetry. When the transmission circuit 10 (integrated circuit device) includes the damping resistors RDP1 and RDP2, the damping resistors RDP1 and RDP2 are also arranged in line symmetry with the line SYL as the symmetry axis. The pads P1 and P2 can also be arranged line-symmetrically with the line SYL as the axis of symmetry.

  In the present embodiment, the reception circuit 30 is disposed on the first direction DR1 side of the transmission circuit 10 (transmission drivers 12 and 14). More specifically, the receiving circuit 30 is arranged so as to be adjacent to the transmitting circuit 10 on the first direction DR1 side. The receiving circuit 30 includes a differential receiver 32 and single-ended receivers 34 and 36.

  In this embodiment, the transmission control circuits 22 and 24 for controlling the transmission drivers 12 and 14 are also arranged on the first direction DR1 side of the transmission circuit 10. More specifically, the transmission control circuits 22 and 24 are arranged so as to be adjacent to the transmission circuit 10 on the first direction DR1 side. The receiving circuit 30 is disposed in an area between the transmission control circuits 22 and 24.

  In the area between the transmission control circuit 22 and the reception circuit 30 and in the area between the transmission control circuit 24 and the reception circuit 30, another circuit block (for example, a level shifter for converting the signal level) is arranged. Also good. It is also possible to arrange other circuit blocks in a region between the transmission circuit 10, the reception circuit 30, and the transmission control circuits 22 and 24.

  In the present embodiment, a wiring region 60 for wiring a signal line connecting the receiving circuit 30 and the pads P1 and P2 is provided in a region between the transmission driver 12 and the transmission driver 14. Note that the wiring region 60 may be provided in another location (for example, the left side of the transmission driver 12 or the right side of the transmission driver 14).

  Further, it is assumed that the direction from the second side SD2 of the macro cell MC1 toward the fourth side SD4 opposite to SD2 is the second direction DR2. Then, in this embodiment, the resistor circuit 40 and the resistor circuit 42 are arranged on the second direction DR2 side of the transmission circuit 10 (transmission drivers 12 and 14). The resistance control circuits 50 and 52 are arranged on the first direction DR1 side of the resistance circuits 40 and 42.

  In FIG. 11, the left side of the macro cell MC1 is the second side SD2, and the right side is the fourth side SD4. However, the left side is the fourth side SD4 and the right side is the second side SD2. Good. In this case, the resistance circuits 40 and 42 are arranged on the left side of the transmission circuit 10. Further, other circuit blocks may be arranged in a region between the transmission circuit 10 and the resistance circuits 40 and 42 or a region between the resistance circuits 40 and 42 and the resistance control circuits 50 and 52. It is also possible to arrange the resistance circuit 40 (and the resistance control circuit 50) and the resistance circuit 42 (and the resistance control circuit 52) in line symmetry with the first line SYL as the axis of symmetry.

  Conventionally, the physical layer circuit for the FS mode has been arranged by an automatic placement and routing technique such as a gate array (sea of gate). Therefore, circuit cells constituting the transmission circuit 10 and the reception circuit 30 are scattered in various places of the integrated circuit device, and the arrangement positions thereof are changed for each type of integrated circuit device. As a result, the signal characteristics of the differential signals DP and DM also change depending on the model of the integrated circuit device, and the signal characteristics of the DP and DM must be re-evaluated every time a new integrated circuit device is commercialized. There was a problem.

  On the other hand, in this embodiment, as shown in FIG. 11, physical layer circuits such as the transmission circuit 10 and the reception circuit 30 are formed into macro cells as hard macros whose wiring and circuit cell arrangement are fixed. Accordingly, it is possible to prevent the arrangement positions of the circuit cells constituting the transmission circuit 10 and the reception circuit 30 from being scattered in the integrated circuit device, and to keep the signal characteristics of the differential signals DP and DM constant among the models. It becomes easy. As a result, when a new integrated circuit device is commercialized as an ASIC, it is not necessary to re-evaluate the signal characteristics of DP and DM, and the development cost and the development period can be shortened.

  Further, in the method of realizing the damping resistors RDP1 and RDP2 and the pull-up resistor RUP1 in the resistor circuit 40 with external parts of the integrated circuit device, various types of resistors may be used depending on the user. It becomes difficult to guarantee the signal characteristics of DP, DM. In contrast, in the present embodiment, the damping resistors RDP1, RDP2 and the pull-up resistor RUP1 are built in the macro cell MC1 as on-chip resistors. Therefore, it becomes easier to guarantee the signal characteristics of DP and DM as compared with a method of realizing these resistors with external parts of the integrated circuit device.

  The damping resistors RDP1 and RDP2 can be realized by, for example, a diffusion resistor configured by a diffusion region into which an impurity having a predetermined polarity is introduced. In this way, the parasitic diode formed between the diffusion region constituting the diffusion resistor and the substrate can be used as an electrostatic protection circuit for the DP and DM signal lines, and the reliability of the integrated circuit device can be improved. . That is, by incorporating the damping resistors RDP1 and RDP2 composed of diffusion resistors in the integrated circuit device, there is an advantage that both the guarantee of the DP and DM signal characteristics and the improvement of the reliability of the integrated circuit device can be achieved.

  In the present embodiment, the transmission drivers 12 and 14 are arranged symmetrically with the line SYL as the axis of symmetry. Therefore, the signal lines from the pads P1 and P2 can also be wired symmetrically with the line SYL as the axis of symmetry, and the wiring lengths of these signal lines can be made equal. As a result, the parasitic capacitance and parasitic resistance of the DP signal line and the parasitic capacitance and parasitic resistance of the DM signal line can be made equal (including substantially the same case), and the DP and DM signal characteristics are improved. it can.

  For example, FIG. 12A shows DP and DM signal characteristics (eye patterns) when the transmission circuit 10 and the reception circuit 30 are arranged by an automatic arrangement and wiring method such as a gate array. In FIG. 12A, the symmetry of the DP and DM signal waveforms cannot be maintained as indicated by C1 and C2, and the cross point of these signals is an ideal value (for example, half of 3.3V which is a full swing voltage). 1.65V). As a result, for example, as indicated by C3 and C4, the margin between the DP and DM signal waveforms and the prohibited region (hexagonal region) is reduced, and good signal characteristics cannot be obtained.

  On the other hand, FIG. 12B shows the signal characteristics of DP and DM when the transmission circuit 10 and the reception circuit 30 are arranged by the method of this embodiment. In FIG. 12B, the symmetry of the DP and DM signal waveforms is maintained as indicated by C5 and C6, and the cross point of these signals can be brought close to the ideal value. As a result, as indicated by C7 and C8, for example, the margin between the DP and DM signal waveforms and the prohibited region is increased, and good signal characteristics can be obtained.

  In the present embodiment, the transmission circuit 10 is disposed on the first direction DR1 side of the pads P1 and P2, and the reception circuit 30 is disposed on the first direction DR1 side of the transmission circuit 10, whereby the macro cell MC1. The layout area can be significantly reduced.

  That is, since the transmission drivers 12 and 14 of the transmission circuit 10 need to drive the USB DP and DM lines, a constant current driving capability (for example, 18 mA) is required. Therefore, if the line widths of the signal lines SLT1 and SLT2 that connect the pads P1 and P2 and the transmission circuit 10 are thin, the signal lines may be cut by electron migration. For this reason, it is desirable to make the signal lines SLT1 and SLT2 as wide as possible.

  On the other hand, on the receiving circuit 30 side, the DP and DM signals are input to the gates of the CMOS transistors constituting the receiving circuit 30. Therefore, the signal lines SLR1 and SLR2 in the wiring region 60 connecting the pads P1 and P2 and the receiving circuit 30 can be narrower than the signal lines SLT1 and SLT2 on the transmission circuit 10 side. That is, for example, the minimum line width on the design rule can be achieved.

  Therefore, for example, if the layout of the transmission circuit 10 is arranged on the first direction DR1 side of the reception circuit 30 contrary to FIG. 11, wiring for connecting the signal lines SLT1 and SLT2 having thick line widths to the transmission circuit 10 Space is needed. For this reason, the width of the macro cell MC1 (length of SD1) is increased by the thick signal lines SLT1 and SLT2, and the circuit area of the integrated circuit device is increased, resulting in an increase in cost of the product.

  In contrast, in the present embodiment, as shown in FIG. 11, the receiving circuit 30 is arranged on the side of the transmitting circuit 10 in the first direction DR1. Therefore, the signal lines SLT1 and SLT2 having thick line widths need only be wired up to the transmission circuit 10 arranged near the pads P1 and P2. As a result, it is possible to prevent a situation in which the width of the macro cell MC1 is increased due to the wiring areas of the signal lines SLT1 and SLT2 having the large line width. Then, the line widths of the signal lines SLR1 and SLR2 wired in the wiring region 60 provided between the transmission drivers 12 and 14 can be reduced. Accordingly, since the width of the wiring region 60 is narrowed, even if these wiring regions 60 are provided between the transmission drivers 12 and 14, the width of the macro cell MC1 does not become so large. As a result, the circuit area of the integrated circuit device can be reduced, and the cost of the product can be reduced.

  In addition, since the transmission drivers 12 and 14 are required to have a large current supply capability, the size (W / L) of the transistors (TPTR1, TNTR1, TPTR2, and TNTR2 in FIG. It needs to be bigger. Therefore, as shown in FIG. 11, the layout area of the transmission circuit 10 including the transmission drivers 12 and 14 is larger than the layout area of the reception circuit 30. Therefore, according to the technique of arranging the receiving circuit 30 on the first direction DR1 side of the transmitting circuit 10 as shown in FIG. 11, an empty space can be formed on both sides of the receiving circuit 30. If the transmission control circuits 22 and 24 are arranged in the empty space on both sides of the receiving circuit 30, the empty space can be used effectively and the layout efficiency can be improved.

  In FIG. 11, the resistance circuits 40 and 42 (and the resistance control circuits 50 and 52) are not arranged symmetrically about the line SLY as an axis of symmetry. In this respect, for the purpose of equalizing the parasitic resistance and parasitic capacitance of the DP and DM signal lines, it is desirable to arrange the resistance circuits 40 and 42 in line symmetry with respect to SLY. However, when arranged symmetrically in this way, the distance between the resistance circuits 40 and 42 is increased. For this reason, due to variations in the manufacturing process, the resistance and parasitic capacitance of the resistance circuit 40 and the resistance and parasitic capacitance of the resistance circuit 42 are not equalized, and the signal characteristics of DP and DM may be deteriorated.

  On the other hand, in FIG. 11, the resistance circuits 40 and 42 are not arranged in line symmetry but are provided on the second direction DR2 side of the transmission circuit 10. Accordingly, the resistance circuits 40 and 42 are arranged close to each other, and the resistance and parasitic capacitance of the resistance circuit 40 and the resistance and parasitic capacitance of the resistance circuit 42 can be made substantially equal even if the manufacturing process varies. Further, as shown by A1 in FIG. 11, if dummy wirings that are not necessary are provided, the wiring lengths of DP and DM can be made equal without arranging the resistance circuits 40 and 42 symmetrically. As a result, it is possible to prevent the signal characteristics of DP and DM from deteriorating.

6). Arrangement of Macro Cell MC1 If the macro cell MC1 having the layout of FIG. 11 is used, as shown in FIG. 1 and FIG. is there.

  That is, when the user who uses the integrated circuit device requests the macro cell MC1 to be arranged on the right side of the integrated circuit device as shown in FIG. 13 instead of arranging it on the lower side of the integrated circuit device as shown in FIG. There is. In order to meet such a demand, it is desirable that the macro cell MC1 can be arranged on any four sides of the integrated circuit device. Further, if the pads P1 and P2 are arranged at the corners, DP and DM bonding wires cannot be wired, or the lengths of the DP and DM bonding wires are different, and the load balance between DP and DM is lost. There is a case. Therefore, it is desirable that the macro cell MC1 can be disposed at any location on each of the four sides of the integrated circuit device.

  In this regard, in the present embodiment, the macro cell MC2 is a macro cell in which the wiring and circuit cell arrangement are automatically arranged and wired, and an I / I is provided on the inner periphery of the four sides of the macro cell MC2, as shown in FIG. An I / O region in which O cells are arranged side by side is provided. Then, the macro cell MC1 is arranged so that the entire I / O area of the macro cell MC1 overlaps a part of the I / O area of the macro cell MC2. That is, the macro cell MC1 is arranged so that the upper and lower lines extending in the longitudinal direction of the I / O region of the macro cell MC1 coincide with the upper and lower lines extending in the longitudinal direction of the I / O region of the macro cell MC2.

  When the length of the first side SD1 of the macro cell MC1 is L and the pitch width of the I / O cell arranged in the I / O region of the macro cell MC2 is PL, L = PL × N (N is 2 The above integer) relationship is established.

  In this way, the macro cell MC1 can be arranged at any location on any four sides of the integrated circuit device (macro cell MC2). And since MC1 is a macro cell whose wiring and circuit cell arrangement is fixed, the signal characteristics of DP and DM can be kept constant even if MC1 is arranged at any place, and the signal characteristics can be reevaluated. There is an advantage that it becomes unnecessary.

7). Interface Area In FIG. 11, interface areas IFRX, IFTX1, IFTX2, and IFRC for exchanging signals between the macrocells MC1 and MC2 are provided in the macrocell MC1. These interface areas IFRX, IFTX1, IFTX2, and IFRC include a buffer that buffers a signal from the macro cell MC1 and outputs the buffer to the macro cell MC2, a buffer that buffers a signal from the macro cell MC2 and inputs the buffer to the macro cell MC1, and the like. It is an area.

  For example, the reception interface area IFRX is an area for interfacing signals between the reception circuit 30 and the macro cell MC2. In the reception interface area IFRX, for example, the selectors 100 and 102 of FIG. 9 and the terminals TM1, TM2, and TM3 can be arranged.

  The transmission interface areas IFTX1 and IFTX2 are areas for interfacing signals between the transmission control circuits 22 and 24 and the macro cell MC2. In the transmission interface areas IFTX1 and IFTX2, for example, the selector 104 of FIG. 9 and terminals TM4 and TM5 can be arranged.

  The resistance control interface area IFRC is an area for interfacing signals between the resistance control circuits 50 and 52 and the macro cell MC2. In the resistance control interface area IFRC, for example, the selector 106 of FIG. 9 and terminals TM6 and TM7 can be arranged.

  In the present embodiment, such interface areas IFRX, IFTX1, IFTX2, and IFRC are provided along, for example, the third side of the macrocell MC1 (any one of the four sides of MC1 in a broad sense). More specifically, it is fixedly arranged along the third side. In this way, it becomes easy to keep the delay and delivery timing of signals exchanged between the macrocells MC1 and MC2 within an allowable range, and a stable circuit even when the circuit configuration or scale of the macrocell MC2 changes. Operation can be guaranteed.

  That is, if the locations of the interface areas IFRX, IFTX1, IFTX2, and IFRC are fixed, it is possible to easily estimate the parasitic capacitance of the signal line between the macro cells MC1 and MC2. Therefore, it is possible to perform the automatic placement and routing of the macro cell MC2, which is a soft macro, by setting the parasitic capacitance of these signal lines to be within an allowable range, and the design of the signal timing can be facilitated. In addition, routing conditions for automatic placement and routing of the macro cell MC2 can be easily set, and the wiring efficiency of the automatic placement and routing of the macro cell MC2 can be improved.

8). HS Mode USB defines an FS (Full Speed) mode with a transfer rate of 12 Mbps. In USB 2.0, in addition to this FS mode, an HS (High Speed) mode with a transfer rate of 480 Mbps is defined.

  FIG. 14 shows a configuration example of the physical layer circuit when realizing the HS mode. FIG. 14 is different from FIG. 3 in that an HS transmission circuit 70 and transmission control circuits 82 and 84 thereof, an HS reception circuit 90, and a detection circuit 98 are further provided.

  The HS transmission circuit 70 is connected to DP and DM pads, and includes a current source 76 (constant current source) and first and second transmission drivers 72 and 74 (current drivers). The current source 76 supplies current to the transmission drivers 72 and 74 when the enable signal HSENB becomes active.

  The first and second transmission control circuits 82 and 84 for HS are circuits for controlling the first and second transmission drivers 72 and 74. Specifically, the transmission control circuit 82 receives the transmission data signal HSDOUT1 and the output disable signal HSOUTDIS from the preceding circuit, and outputs the control signal GC1 to the transmission driver 72. The transmission control circuit 84 receives the signals HSDOUT2 and HSOUTDIS from the previous stage circuit, and outputs a control signal GC2 to the transmission driver 74.

  The reception circuit 90 is a circuit for performing reception processing in the USB HS mode, and includes a differential receiver 92. The differential receiver 92 (differential comparator) differentially amplifies the differential signal input through the DP and DM pads, and outputs the differential signal as a data signal HSDIN to a subsequent circuit. The differential receiver 92 can be realized by an operational amplifier circuit in which the differential signals DP and DM are input to the first and second differential inputs. The operation of the differential receiver 92 is enabled or disabled by an enable signal HSCOMPENB.

  The detection circuit 98 (squelch circuit) is a circuit for distinguishing whether a signal (DP, DM) on the USB is valid data or noise. More specifically, the detection circuit 98 holds the peak value of the USB signal and detects the amplitude of the signal by detecting the envelope of the signal. For example, if the amplitude is 100 mV or less, the signal is determined to be noise, and if the amplitude is 150 mV or more, it is determined to be valid data. If it is determined that the data is valid, the output signal HSSQ is activated. The operation of the detection circuit 98 is enabled or disabled by an enable signal HSSQENB.

  FIG. 15 shows a configuration example of the transmission circuit 70. In FIG. 15, IS corresponds to the current source 76, the transistor TE1 corresponds to the transmission driver 72, and the transistor TE2 corresponds to the transmission driver 74.

  When the control signal GC1 becomes high level (active), a current (constant current) flows from the current source IS to the DP via the transistor TE1, and the USB bus state becomes the J state. On the other hand, when the control signal GC2 becomes high level, a current flows from the current source IS to the DM via the transistor TE2, and the USB bus state becomes the K state. Then, the USB bus state is set to the J or K state according to the transmission data, thereby enabling transmission in the HS mode. On the other hand, in a period other than the transmission (HS transmission) period, the control signal GC3 becomes active, and a current flows from the current source IS to VSS (AVSS) via the transistor TE3. Thereby, a stable current can be flowed immediately at the start of transmission, and the response of the transmission circuit 70 can be improved.

  The macro cell MC1 corresponding to the HS mode can include the circuit shown in FIG. 16 in addition to the circuit shown in FIG.

  In FIG. 16, the differential receiver 70 has a first differential input connected to the pad P1, a second differential input connected to the pad P2, and a first output signal HSDFQ and an inverted signal of HSDFQ. A second output signal HSXDFQ is output.

  In the first mode, selector 110 outputs output signal HSDFQ from differential receiver 70 as selector output signal SLQ8. On the other hand, in the second mode, the output signal HSXDFQ from the differential receiver 70 is output as the selector output signal SLQ8. The output signal SLQ8 is output to the macro cell MC2 via the output terminal TM8.

  In FIG. 16, in the first mode, the selector 112 outputs SLI9 as the selector output signal SLQ9 and outputs SLI10 as the selector output signal SLQ10 among the input signals SLI9 and SLI10. On the other hand, in the second mode, SLI10 is output as the selector output signal SLQ9, and SLI9 is output as the selector output signal SLQ10.

  The transmission driver 72 receives the transmission control signal GC1 corresponding to the selector output signal SLQ9, and drives the signal line SL1 connected to the pad P1. The transmission driver 74 receives the transmission control signal GC2 corresponding to the selector output signal SLQ10, and drives the signal line SL2 connected to the pad P2.

  In FIG. 16, a selector corresponding to the detection circuit 98 is not provided, but such a selector may be provided depending on the circuit configuration of the detection circuit 98.

9. Electronic Device FIG. 17 shows a configuration example of an electronic device including a data transfer control device realized by the integrated circuit device (macro cell) of this embodiment. The electronic device 300 includes the data transfer control device 310 (integrated circuit device) described in the present embodiment, an application layer device 320 including an ASIC, a CPU 330, a ROM 340, a RAM 350, a display unit 360, and an operation unit 370. A part of these functional blocks may be omitted.

  Here, the application layer device 320 is, for example, a device that realizes an application engine of a mobile phone, a device that controls a drive of an information storage medium (hard disk, optical disk), a device that controls a printer, an MPEG encoder, an MPEG decoder, or the like Including the device. The processing unit 330 (CPU) controls the data transfer control device 310 and the entire electronic device. The ROM 340 stores control programs and various data. The RAM 350 functions as a work area and a data storage area for the processing unit 330 and the data transfer control device 310. The display unit 360 displays various information to the user. The operation unit 370 is for the user to operate the electronic device.

  In FIG. 17, the DMA bus and the CPU bus are separated, but they may be shared. Further, a processing unit that controls the data transfer control device 310 and a processing unit that controls the electronic apparatus may be provided separately. As electronic devices to which the present embodiment can be applied, mobile phones, optical disk drives (CD-ROM, DVD), magneto-optical disk drives (MO), hard disk drives, TVs, TV tuners, VTRs, video cameras, audio devices, projectors. There are various types such as personal computers, electronic notebooks, and word processors.

  In addition, this invention is not limited to this embodiment, A various deformation | transformation implementation is possible within the range of the summary of this invention.

  For example, terms in the specification and drawings have broad or synonymous terms (a given interface standard, first signal, second signal, first pad, second pad, first power source, second power source Etc.) (USB, DP, DM, DP pad, DM pad, VDD, VSS, etc.) can be replaced with broad or synonymous terms in the description and other descriptions in the drawings. .

  Further, the data transfer control device realized by the present invention is not limited to the configuration described with reference to FIG. 2 and the like, and various modifications can be made. The circuit configuration and layout of the macro cell of the present invention are not limited to those described with reference to FIGS. 9, 11, 16, and the like, and various modifications can be made.

2 shows a configuration example of an integrated circuit device. 1 is a configuration example of a data transfer control device realized by an integrated circuit device. The structural example of a physical layer circuit. 4A and 4B show configuration examples of the transmission circuit. The example of a structure of a differential receiver. 2 is a configuration example of a reference voltage generation circuit. Configuration example of single-ended receiver. 8A and 8B are explanatory diagrams of various mounting forms. The structural example of macrocell MC1. 10A and 10B are configuration examples of the selector. The layout example of macrocell MC1. 12A and 12B are explanatory diagrams of signal characteristics of DP and DM. Explanatory drawing of the arrangement | positioning method of macrocell MC1. 2 is a configuration example of a physical layer circuit for HS. 2 shows a configuration example of a transmission circuit for HS. The structural example of macrocell MC1 for HS. Configuration example of an electronic device.

Explanation of symbols

MC1, MC2 macrocell, RDP1, RDP2 damping resistor,
SD1 to SD4, first to fourth sides, TM1 to TM13, output terminals or input terminals,
10 transmission circuit, 12, 14 transmission driver, 22, 24 transmission control circuit,
30 receiver circuit, 32 differential receiver, 34, 36 single-ended receiver,
40, 42 resistance circuit, 50, 52 resistance control circuit,
100, 102, 104, 106, 110, 112 selector,
200 transceiver, 210 transfer controller, 220 buffer controller,
230 data buffer, 240 interface circuit,

Claims (14)

A macrocell comprising at least a physical layer circuit of a given interface standard for transferring data using differential signals,
A first single-ended receiver whose input is connected to the first pad for one of the first and second signals constituting the differential signal and outputs the first output signal;
A second single-ended receiver whose input is connected to a second pad for the other different from the one and outputs a second output signal;
In the first mode, a first output signal of the first and second output signals from the first and second single-ended receivers is output as a first selector output signal and a second output signal is output. Is output as the second selector output signal, and in the second mode, the second output signal of the first and second output signals is output as the first selector output signal and the first output signal is output. A selector that outputs the second selector output signal as a second selector output signal;
A macrocell characterized by containing. In claim 1,
Including first and second output terminals for outputting the first and second selector output signals from the selector to a second macrocell including a circuit in a layer higher than the physical layer;
The selector
In the first mode, the first output signal is output as the first selector output signal to the second macro cell via the first output terminal, and the second output signal is output to the second macro cell. As a selector output signal to the second macro cell via the second output terminal, and in the second mode, the second output signal is used as the first selector output signal as the first output. And outputting the first output signal as the second selector output signal to the second macro cell via the second output terminal as well as outputting to the second macro cell via the terminal. Macro cell. In claim 2,
The first and second output terminals are
A macro cell arranged in a reception interface area provided along one of four sides of a macro cell. In any one of Claims 1 thru | or 3,
A first transmission driver for driving a signal line connected to the first pad;
A second transmission driver for driving a signal line connected to the second pad,
When the direction from the first side of the macro cell to the third side facing the macro cell is the first direction,
The first and second transmission drivers are
Arranged on the first direction side of the first and second pads and arranged symmetrically about the first line along the first direction as an axis of symmetry;
The first and second single-ended receivers are:
A macro cell arranged on the first direction side of the first and second transmission drivers. In claim 4,
A wiring region for wiring a signal line connecting the first and second single-ended receivers and the first and second pads along the first direction is the first and second transmissions. A macro cell provided in an area between drivers. A macrocell comprising at least a physical layer circuit of a given interface standard for transferring data using differential signals,
The first differential input is connected to the first pad for one of the first and second signals constituting the differential signal, and the second differential pad is connected to the second pad for the other of the first and second signals. A differential receiver to which a second differential input is connected and which outputs a first output signal and a second output signal that is an inverted signal of the first output signal;
In the first mode, the first output signal of the first and second output signals from the differential receiver is output as a selector output signal. In the second mode, the first output signal from the differential receiver is output from the first receiver. A selector that outputs a second output signal of the first and second output signals as the selector output signal;
A macrocell characterized by containing. In claim 6,
Including an output terminal for outputting a selector output signal from the selector to a second macro cell including a circuit in a layer higher than the physical layer;
The selector
In the first mode, the first output signal is output as the selector output signal to the second macro cell via the output terminal, and in the second mode, the second output signal is output to the selector. A macro cell that outputs an output signal to the second macro cell via the output terminal. In claim 7,
The output terminal is
A macro cell arranged in a reception interface area provided along one of four sides of a macro cell. In any of claims 6 to 8,
A first transmission driver for driving a signal line connected to the first pad;
A second transmission driver for driving a signal line connected to the second pad,
When the direction from the first side of the macro cell to the third side facing the macro cell is the first direction,
The first and second transmission drivers are
Arranged on the first direction side of the first and second pads and arranged symmetrically about the first line along the first direction as an axis of symmetry;
The differential receiver is
A macro cell arranged on the first direction side of the first and second transmission drivers. In claim 9,
A wiring region for wiring a signal line connecting the differential receiver and the first and second pads along the first direction is in a region between the first and second transmission drivers. A macrocell characterized by being provided. In any one of Claims 1 thru | or 10.
The macro cell according to claim 1, wherein the given interface standard is a USB (Universal Serial Bus) standard. In any one of Claims 1 thru | or 11,
In the case where the entire I / O area of the macro cell overlaps with a part of the I / O area of the second macro cell including the upper layer circuit than the physical layer,
When the length of the first side of the macro cell is L and the pitch width of the I / O cell arranged in the I / O region of the second macro cell is PL, L = PL × N (N is A macro cell characterized by being an integer of 2 or more. A physical layer circuit including a plurality of macrocells,
A macrocell according to any one of claims 1 to 12,
A second macrocell including a circuit in an upper layer than the physical layer;
An integrated circuit device comprising: An integrated circuit device according to claim 13;
A processing unit for controlling the integrated circuit device;
An electronic device comprising:

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