JP2005197843A - Multilayer substrate and power amplifier module - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a multilayer substrate capable of obtaining a high impedance value with a small occupied area, and to provide a power amplifier module. <P>SOLUTION: Strip lines are each formed into a spiral shape, and have the same shape or a shape laterally inverted. The directions of strip lines whose shape are the same or laterally inverted are changed and a core substrate and fifth-seventh RCCs are successively stacked, and the strip lines are connected to each other through a via hole. A choke coil formed in this way can obtain a high impedance value with a small occupied area, compared with a helical, meander line or conventional spiral choke coil. Since a dielectric substrate in which a plurality of such choke coils are formed in an inner layer and a power amplifier module comprising the dielectric substrates can ensure sufficient isolation among the choke coils, the miniaturization thereof can be realized. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a multilayer substrate and a power amplifier module.

As a method of forming an inductor pattern in a multilayer component, a meander line-shaped inductor electrode is formed on the same plane, and ground electrode patterns are provided on upper and lower layers so as to sandwich the inductor electrode (for example, refer to Patent Document 1). There is known a technique (see, for example, Patent Document 2) in which a large inductor value is obtained by increasing the number of turns of an inductance element by increasing the number of turns of an inductance element by forming a plurality of inductor electrodes in a multilayer shape. Yes.
JP 2002-280218 A (FIG. 1). Japanese Patent Laying-Open No. 2003-133882 (FIG. 22).

  A choke coil for applying a bias voltage to an amplifying element such as a transistor and preventing a high-frequency signal from flowing into the bias circuit is formed in an inner layer of a multilayer substrate constituting a power amplifier module, an antenna switch module, or the like. Ideally, such a choke coil is composed of λ / 4 strip lines connected in parallel so that the impedance to the RF (Radio Frequency) line is sufficiently high at the target frequency.

  However, in reality, since there is a restriction such as the volume of the module, the choke coil is generally constituted by a meander-line strip line formed on one plane. In this case, since currents in opposite directions flow between adjacent lines, the coupling of magnetic flux is weakened. This has caused a decrease in inductance value. In order to prevent the inductance value from decreasing, it can be resolved by increasing the line length. However, if the line length is increased, the voltage drop due to the conductor resistance increases accordingly. The power consumption of the switch module etc. will increase.

  In addition, a choke coil constituted by helical strip lines formed in multiple layers can obtain a higher impedance value with a smaller occupied area than a choke coil constituted by meander line strip lines. Since the dead space becomes large, it is difficult to reduce the size of the power amplifier module and the antenna switch module.

  The present invention has been made to solve the above-described problems, and an object thereof is to provide a multilayer substrate and a power amplifier module that can obtain a high impedance value with a small occupied area. It is another object of the present invention to provide a multilayer substrate and a power amplifier module that can realize power saving and downsizing of the multiband module to be configured.

  In order to achieve the above object, a multilayer substrate according to a first aspect of the present invention is formed by laminating a plurality of dielectrics each having a spiral strip line formed on a surface thereof, and connecting the strip lines via via holes. Thus, an inductance element is formed in the inner layer.

  In the multilayer substrate, the strip line may be formed in a spiral shape by sequentially increasing or decreasing the diameter every half turn.

  Further, in the multilayer substrate, the strip lines formed on the plurality of dielectrics have the same or left-right inverted shape, and the inductance element is the same or left-right inverted of the plurality of dielectrics. The strip lines may be stacked by sequentially changing the direction of the strip lines, and the strip lines are connected to each other via via holes.

  In order to achieve the above object, a power amplifier module according to a second aspect of the present invention is a power amplifier module used in a transmission unit of a communication terminal device, and includes a transistor functioning as an amplifying element on the surface, The multi-layer substrate according to claim 1, wherein the inductance element is connected to an output terminal of a transistor so that the inductance element functions as a choke coil.

  According to the present invention, it is possible to provide a multilayer substrate capable of obtaining a high impedance value with a small occupied area. Further, according to the present invention, it is possible to provide a multilayer substrate capable of realizing power saving and downsizing of the multiband module to be configured.

  Hereinafter, a communication terminal apparatus according to an embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 is a block diagram showing a configuration of a communication terminal apparatus according to an embodiment of the present invention. The communication terminal device is, for example, a mobile phone, and includes an RF (Radio Frequency) unit 10 and a signal processing circuit 20 as shown in FIG. 1, and the RF unit 10 includes an antenna 11, a duplexer. 12, a transmission unit 13, a local oscillator 14, and a reception unit 15.

The transmission unit 13 includes a mixer 131 and a power amplifier module 132, and filters 133 and 134 are connected to a front stage and a rear stage of the power amplifier 132, respectively. The mixer 131 mixes the signal supplied from the signal processing circuit 20 and the signal supplied from the local oscillator 14 and supplies the signal obtained by mixing to the power amplifier module 132. The power amplifier module 132 amplifies the signal supplied from the mixer 131 and transmits the amplified signal to the antenna 11 via the duplexer 12 .

  The receiving unit 15 includes an amplifier 151 and a mixer 152, and filters 153 and 154 are connected to a front stage and a rear stage of the amplifier 151, respectively. The amplifier 151 amplifies the signal input from the antenna 11 via the duplexer 12, and the filter 154 extracts a signal having a predetermined frequency component from which the noise component is removed from the amplified signal. The mixer 152 mixes the reception signal output from the filter 154 and the signal supplied from the local oscillator 14 and supplies the signal processing circuit 20 with an intermediate frequency signal obtained by mixing.

  FIG. 2 is a circuit diagram showing a specific configuration of power amplifier module 100 shown in FIG. As shown in FIG. 2, the power amplifier module 100 includes an input matching circuit unit 101, a semiconductor circuit unit 102, an interstage matching circuit unit 103, a bias circuit unit 104, and an output matching circuit unit 105. ing.

  The input matching circuit unit 101 includes a reactance element R1, inductance elements L1 and L2, and a capacitance element C1, and the inductance element L1 and the capacitance element C1 are connected in an L shape. The input matching circuit unit 101 has a function of matching the impedance (50 [Ω]) at the Pin terminal with the input impedance of the semiconductor circuit unit 102, and the semiconductor circuit without loss due to impedance mismatching of the signal input from the Pin terminal To the input of the unit 102.

  The semiconductor circuit unit 102 includes two-stage transistors Tr1 and Tr2, and amplifies and outputs a signal input from the input matching circuit unit 101. The base terminals of the transistors Tr1 and Tr2 are connected to the output terminal of the input matching circuit unit 101, and the emitter terminal is grounded.

  The interstage matching circuit unit 103 includes capacitance elements C2, C3, and C4, and inductance elements L3 and L4. The capacitance element C2, the inductance element L3, the inductance element L4, and the capacitance element C4 are respectively It is connected in an L shape. The interstage matching circuit unit 103 matches the output impedance of the transistor Tr1 with the input impedance of the transistor Tr2, and transmits the signal output from the transistor Tr1 to the input of the transistor Tr2 without loss due to impedance mismatching.

  The bias circuit unit 104 includes reactance elements R2 and R3, inductance elements L8 and L9, ground capacitance elements C9 and C10, and bias circuits 104a and 104b. The reactance elements R2 and R3 form power supply lines to the base terminals of the transistors Tr1 and Tr2, respectively, and the bias circuits 104a and 104b apply bias voltages to the transistors Tr1 and Tr2, respectively. Due to this bias voltage, the transistors Tr1 and Tr2 of the semiconductor circuit unit 102 operate as amplification elements. The inductance elements L8 and L9 are connected to the output terminals of the transistors Tr1 and Tr2, in this embodiment, the collector terminal C, and the signals amplified by the transistors Tr1 and Tr2 are leaked to the power supply terminals such as Vcc1 and Vcc2. It functions as a choke coil that prevents this from occurring.

  The Vref terminal is a terminal provided for output control, and the output of the power amplifier module 100 is controlled by the voltage level applied to the Vref terminal.

  The output matching circuit unit 105 includes inductance elements L5, L6 and L7, and capacitance elements C5, C6, C7 and C8. The inductance element L6 and the capacitance element C6, the inductance element L7 and the capacitance element C8, Are connected in an L shape. The output matching circuit unit 105 matches the output impedance of the semiconductor circuit unit 102 with the impedance (50 [Ω]) seen at the Pout terminal, and the signal output from the semiconductor circuit unit 102 is output to the Pout terminal without loss due to impedance mismatching. Transmit to.

  FIG. 3 is a front view of the power amplifier module shown in FIG. As shown in FIG. 3, the power amplifier module 132 is roughly composed of a dielectric substrate 1 and an MMIC (Microwave Monolithic IC) 2, and a thermal via 3, a long hole through hole is formed in the surface thereof. 4 are provided.

  The dielectric substrate 1 includes a core substrate 5 and first to eighth resin-attached copper foils (RCC: Resin Coated Copper) 21 to 28. The dielectric substrate 1 has first to fourth resin-coated copper foils (RCC) 21 to 24 on the surface of the core substrate 5, and fifth to eighth RCCs 25 to 28 on the back surface in order. It is formed by laminating, pressing and heating.

  The core substrate 5 and the first to eighth RCCs 21 to 28 are composed of a resin layer made of a polyvinyl benzyl ether compound or the like, or a hybrid layer containing a polyvinyl benzyl ether compound and a ceramic dielectric powder such as titanium barium, The core substrate 5 includes glass cloth in its inner layer.

  The first to eighth RCCs 21 to 28 are mounted with chip components excluding the transistors Tr1 and Tr2 included in the MMIC 2 among the circuit components included in the circuit diagram shown in FIG. So that the circuit configuration is correct. The arrangement of the circuit components is not particularly limited, but an example that can be adopted will be described with reference to FIG.

  FIG. 4 shows a plan view of the first to eighth RCCs 21 to 28 viewed from the front surface side and a plan view of the eighth RCC 28 viewed from the rear surface side.

  As shown in FIG. 4, on the surface (upper surface) 31 of the first RCC 21, a part of the circuit elements constituting the bias circuit unit 104, the input matching circuit unit 101, and the interstage matching circuit unit 102 in FIG. And the circuit element which comprises the output matching circuit part 105 is mounted. Specifically, as shown in FIG. 5, reactance elements R1 to R3, inductance elements L1 to L7, capacitance elements C1 to C10, and the like are mounted. Among these chip parts, the capacitance elements C1 to C10 are constituted by chip parts, and can be attached to a conductor pattern formed in advance on the surface 31 of the first RCC 21 by a technique such as soldering. The inductance elements L1 to L7 can be configured by strip lines formed on the surface (upper surface) 31 of the first RCC 21.

  Conductor patterns are respectively formed on the core substrate 5 and the front surfaces (upper surfaces) 31 to 39 of the second to eighth RCCs 22 to 28 and the rear surface 40 of the eighth RCC 28 shown in FIG. The conductor pattern formed on the surface 34 of the RCC 24, the surface 36 of the fifth RCC 25, and the back surface 40 of the eighth RCC 28 is a ground conductor pattern connected to the ground terminal GND.

  Further, on the surfaces 35 to 38 of the core substrate 5 and the fifth to seventh RCCs 25 to 27, the spiral strip lines L8a to L8a constituting part of the inductance elements L8 and L9 in the bias circuit unit 104 shown in FIG. L8d and L9a to L9d are formed, and a strip line L8e constituting a part of the inductance element L8 is formed on the surface 39 of the eighth RCC 28. The inductance elements L8 and L9 are obtained by connecting these strip lines L8a to L8e and L9a to L9d through via holes (not shown).

  As described above, the input matching circuit unit 101, the interstage matching circuit unit 102, and the output matching circuit unit 105 are formed on the surface 31 of the first RCC 21, and the inductance elements L8 and L9 functioning as choke coils are formed on the core substrate 5. Of the fourth RCC 24 and is physically separated by a ground conductor pattern formed on the surface 34 of the fourth RCC 24. For this reason, the power amplifier module 132 can sufficiently isolate the input matching circuit unit 101, the interstage matching circuit unit 102 and the output matching circuit unit 105, and the inductance elements L8 and L9. The high-frequency signal input from the Pin terminal can be transmitted to the Pout terminal with low loss.

  The dielectric substrate 1 is provided with a signal input terminal Pin, a signal output terminal Pout, a ground terminal GND, power supply terminals Vdd1, Vdd2, and the like in the form of side electrodes or back electrodes.

  The MMIC 2 mounts the circuit components of the semiconductor circuit unit 102 composed of the transistors Tr1 and Tr2 among the circuit components included in the circuit diagram shown in FIG. 2, and the electrode thereof is a dielectric by wire bonding or the like. It is connected to a conductor pattern formed on the substrate 1. The MMIC 2 is mounted in a sealed state with a sealing resin in order to ensure its reliability.

  A plurality of thermal vias 3 are provided at appropriate intervals so as to continuously penetrate between the core substrate 5 and the first to eighth RCCs 21 to 28 in the mounting area of the MMIC 2. The thermal via 3 is filled with a filler made of a conductive paste such as an Ag paste. The filler filled in the thermal via 3 may be a non-conductive material as long as it has excellent thermal conductivity.

  The long hole through hole 4 is provided in the vicinity of the side surface of the dielectric substrate 1 so as to continuously penetrate between the core substrate 5 and the first to eighth RCCs 21 to 28. The thermal via 3 and the through hole 4 can improve the heat dissipation of the power amplifier module 132.

  Next, the helical choke coil having the same outer shape and the choke coil of the present invention are formed in the inner layer of the dielectric substrate 1 of the power amplifier module 132 having the above-described configuration, and the frequency characteristics of each are formed. And I measured impedance characteristics.

  FIG. 6 is a plan view of each layer of the dielectric substrate in which the helical choke coil is formed in the inner layer, and FIG. 7 is a plan view in each layer of the dielectric substrate in which the choke coil of the present invention is formed in the inner layer. FIG.

  As shown in FIGS. 6 and 7, the dielectric substrate 1 is configured by laminating a square core substrate 5 having a side length of 4.0 [mm] and first to eighth RCCs 21 to 28. On the surface of each layer, a strip line having the outermost diameter of a square having a side length of 1.0 [mm] is formed. The length of the helical choke coil shown in FIG. 6 is 13.0 [mm], and the width is 0.15 [mm].

  The strip lines shown in FIG. 7 are formed in a spiral shape, and have the same or left-right inverted shape. By changing the direction of the strip lines that are the same or horizontally reversed, the core substrate 5 and the fifth to seventh RCCs 25 to 27 are sequentially stacked, and the strip lines are connected to each other through via holes. A choke coil is obtained.

FIG. 8 is a graph showing the frequency characteristics of the choke coil when the impedance is 50 [Ω].

As shown in FIG. 8, the choke coil of the present invention can obtain a larger inductance value than the helical choke coil at the same frequency. In particular, in a power amplifier module used for a mobile phone or the like, as shown in FIG. 8, an inductance value about 1.5 times that of a helical choke coil is obtained in a frequency band of 1 to 2 [GHz]. Can be obtained.

FIG. 9 is an impedance chart of the helical choke coil, and FIG. 10 is an impedance chart of the choke coil of the present invention. It is desirable that the choke coil is sufficiently open (open state) when viewed from the Vcc1 terminal and the Vcc2 terminal side so that a high frequency signal does not flow into the Vcc1 terminal and the Vcc2 terminal at the fundamental frequency f0.

As shown in FIG. 9 and FIG. 10, the choke coil of the present invention is sufficiently open at the fundamental frequency f0 as compared with the helical choke coil, so that the inflow of high-frequency signals to the Vcc1 terminal and the Vcc2 terminal is further improved. It can be effectively prevented. This indicates that the choke coil of the present invention is more suitable than the helical choke coil as the choke coil of the power amplifier module in which the load variation of the output impedance is severe depending on the operation state.

  Subsequently, a conventional spiral choke coil, meander line choke coil, and choke coil of the present invention are formed on the inner layer of the dielectric substrate 1 of the power amplifier module 132 having the above-described configuration. I tried to measure the frequency characteristics.

FIG. 11 is a plan view of each layer of a dielectric substrate in which a meanderline choke coil is formed in the inner layer, and FIG. 12 is a diagram of each layer of the dielectric substrate in which a conventional spiral choke coil is formed in the inner layer. FIG. FIG. 13 is a plan view of each layer of the dielectric substrate having the choke coil of the present invention formed in the inner layer.

The length and width of the choke coil shown in FIGS. 11, 12 and 13 are formed to be equal to the helical choke coil shown in FIG. 6, and are 13.0 [mm] and 0.15 [mm], respectively. It is.

FIG. 14 is a graph showing the frequency characteristics of the choke coil when the impedance is 50 [Ω].

As shown in FIG. 14, the choke coil of the present invention can obtain a larger inductance value than the helical choke coil, the meander line choke coil, and the conventional spiral choke coil at the same frequency.

  For this reason, if the choke coil of the present invention obtains the same inductance value as that of the helical choke coil, the meander line choke coil, and the conventional spiral choke coil, the length thereof is compared with these. Can be shortened. By using such a choke coil, the power amplifier module 132 can reduce the voltage drop due to the conductor resistance and save power.

On the other hand, as shown in FIG. 6, FIG. 11, FIG. 12 and FIG. 13, the choke coil of the present invention includes a helical choke coil, a meander line choke coil and a conventional spiral choke coil. Is the same, the occupied area in each layer can be reduced compared to these.

  For this reason, even if a plurality of choke coils of the present invention are formed in the same layer on the dielectric substrate 1, it becomes easy to form a ground conductor pattern between the choke coils, and the isolation between the choke coils is sufficient. Can be secured.

  By using the choke coil capable of obtaining a large inductance value and sufficient isolation as described above, it is possible to reduce the size of the power amplifier module 132 that needs to form a plurality of choke coils.

  In addition, this invention is not limited to the said embodiment, A various deformation | transformation and application are possible. Hereinafter, modifications of the above-described embodiment applicable to the present invention will be described.

In the above embodiment, the number of turns of the choke coil in each layer is approximately one, but the present invention is not limited to this, and the number of turns is arbitrary, for example, as shown in FIG. Alternatively , approximately two turns may be used. In the above embodiment, the shape of the strip line constituting the choke coil is a substantially square shape. However, the present invention is not limited to this, and as shown in FIG. The shape may be a substantially circular shape. In this case, as shown in FIG. 15B , the strip line is formed in a spiral shape by sequentially increasing or decreasing the diameter every 1/2 turn.

  In the above embodiment, the choke coil of the present invention is formed in the inner layer of the dielectric substrate 1 constituting the power amplifier module 132. However, the present invention is not limited to this, and the choke coil of the present invention is The present invention can also be applied to the dielectric substrate 1 constituting another multiband module such as an antenna switch module.

It is a block diagram which shows the structure of the communication terminal device in this Embodiment. It is a circuit diagram which shows the structure of the power amplifier module shown in FIG. FIG. 3 is a front view of the power amplifier module shown in FIG. 2. It is a top view which shows the structure of the back surface in the surface in each layer of the dielectric substrate shown in FIG. 3, and a lowermost layer. It is a top view which shows the detail of the surface of 1st RCC. It is a top view which shows the structure of each layer of the dielectric substrate in which the helical choke coil was formed. It is a top view which shows the structure of each layer of the dielectric substrate in which the choke coil of this invention was formed. It is a graph which shows the frequency characteristic of each choke coil. It is an impedance chart which shows the impedance characteristic of a helical. It is an impedance chart which shows the impedance characteristic of this invention. It is a top view which shows the structure of each layer of the dielectric substrate in which the meander line-shaped choke coil was formed. It is a top view which shows the structure of each layer of the dielectric substrate in which the spiral choke coil was formed. It is a top view which shows the structure of each layer of the dielectric substrate in which the choke coil of this invention was formed. It is a graph which shows the frequency characteristic of each choke coil. It is a diagram showing a modified embodiment of the choke coil shown in FIGS. 7 and 13.

Explanation of symbols

1 Dielectric substrate 2 MMIC
3 Thermal Via 4 Long Hole Through Hole 5 Core Substrate 21 First RCC
22 Second RCC
23 Third RCC
24 Fourth RCC
25 5th RCC
26 6th RCC
27 Seventh RCC
28 8th RCC
100 power amplifier module 101 input matching circuit unit 102 semiconductor circuit unit 103 interstage matching circuit unit 104 bias circuit unit 105 output matching circuit unit L8 inductance element L9 inductance element Tr1 transistor Tr2 transistor

Claims (4)

By laminating a plurality of dielectrics having spiral striplines formed on the surface, and connecting the striplines with each other through via holes, an inductance element was formed on the inner layer.
A multilayer substrate characterized by that. The strip line is formed in a spiral shape by sequentially increasing or decreasing its diameter every 1/2 turn.
The multilayer substrate according to claim 1. The strip lines formed in the plurality of dielectrics have the same or left-right inverted shape, respectively.
The inductance element is formed by sequentially stacking the plurality of dielectrics by changing the direction of the strip lines that are the same or horizontally reversed, and connecting the strip lines via via holes.
The multilayer substrate according to claim 1 or 2, characterized in that A power amplifier module used in a transmission unit of a communication terminal device,
A multilayer substrate according to claim 1, 2 or 3, wherein a transistor that functions as an amplifying element is mounted on the surface, and the inductance element is connected to an output terminal of the transistor so that the inductance element functions as a choke coil. Prepare
A power amplifier module characterized by that.

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