JP2005191072A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which can improve adhesive properties of an electrode pad while preventing a wiring part and the root of a pad electrode layer from being disconnected. <P>SOLUTION: The semiconductor device includes a semiconductor layer 10, an interlayer insulating layer 26 provided above the semiconductor layer 10, a contact hole 74a provided in the interlayer insulating layer 26, a first barrier metal layer 40a provided on the inner surface of the contact hole 74 and above the interlayer insulating layer, a contact layer 74 embedded in the contact hole 74a, a protective layer 42 provided at least above the contact layer 74, a conductive layer 40b provided above the protective layer 42, and a protective insulating layer 50 provided above the conductive layer 40b and having a pad opening. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device having a bonding pad structure and a manufacturing method thereof.

In a conventional semiconductor device, there is a method in which a barrier metal is interposed between the wiring layer and the insulating layer in order to improve the reliability (stress migration resistance, electromigration resistance, etc.) of the wiring layer. However, if a barrier metal is also interposed between the electrode pad connected to the wiring and the insulating film, the pad electrode layer may be peeled off at the time of bonding due to poor adhesion between the barrier metal layer and the insulating film. .
Japanese Patent Laid-Open No. 2002-2222811

  An object of the present invention is to provide a semiconductor device capable of improving the adhesion of the pad electrode layer while preventing disconnection at the base portion between the wiring portion and the pad electrode layer, and a method for manufacturing the same.

The semiconductor device of the present invention includes a semiconductor layer,
An interlayer insulating layer provided above the semiconductor layer;
A contact hole provided in the interlayer insulating layer;
A first barrier metal layer provided above the inner surface of the contact hole and the interlayer insulating layer;
A contact layer embedded in the contact hole;
A protective layer provided at least above the contact layer;
A conductive layer provided above the protective layer;
And a protective insulating layer provided above the conductive layer and provided with a pad opening.

  According to the semiconductor device of the present invention, the protective layer is provided on the conductive layer buried in the contact hole. Therefore, it is possible to prevent the surface of the conductive layer buried in the contact hole from being exposed. As a result, a stable contact hole layer with low resistance and little variation can be formed, and a highly reliable semiconductor device can be provided. In the semiconductor device of the present invention, the protective layer and the first barrier metal layer in the region where the pad opening is formed are removed, and the conductive layer is in direct contact with the interlayer insulating layer. Therefore, the adhesion between the conductive layer and the interlayer insulating layer can be improved, and a semiconductor device with improved adhesion between the wiring portion and the pad electrode layer can be provided.

  In the present invention, the fact that another specific layer (hereinafter referred to as “B layer”) is provided above a specific layer (hereinafter referred to as “A layer”) means that B directly The case where the layer is provided and the case where the B layer is provided via another layer on the A layer are included.

  The semiconductor device of the present invention can further take the following aspects.

  In the semiconductor device of the present invention, the pad opening may be formed in a region other than vertically above the contact hole.

  In the semiconductor device of the present invention, the protective layer and the first barrier metal layer below the pad opening can be removed.

  In the semiconductor device of the present invention, the material of the protective layer may be the same as that of the conductive layer.

  In the semiconductor device of the present invention, the material of the protective layer may be the same as that of the barrier layer.

  In the semiconductor device of the present invention, a second barrier metal layer can be provided between the protective insulating layer and the conductive layer.

A method for manufacturing a semiconductor device of the present invention includes:
(A) forming an interlayer insulating layer above the semiconductor layer;
(B) forming a contact hole in the interlayer insulating layer;
(C) forming a first barrier metal layer above the inner surface of the contact hole and the interlayer insulating layer;
(D) forming a contact layer in the contact hole;
(E) forming a protective layer at least above the contact layer;
(F) removing the protective layer and the first barrier metal layer in a region where a pad opening is to be formed;
(G) forming a conductive layer above the protective layer;
(H) forming a protective insulating layer having the pad opening above the conductive layer.

  According to the method for manufacturing a semiconductor device of the present invention, after the conductive layer is embedded in the contact hole, the protective layer is formed so as to cover the upper surface of the conductive layer. In the pad opening, a step of removing the barrier layer in the pad opening is performed in order to prevent film peeling. In this step, the mask layer is formed and the barrier layer is removed, and then the mask layer is removed. When the mask layer is removed, since the upper surface of the conductive layer is covered with the protective layer, the surface of the conductive layer can be prevented from coming into contact with the etching solution. Therefore, the surface of the conductive layer can be prevented from being corroded, and a good contact layer can be formed. As a result, a highly reliable semiconductor device in which variation in resistance is reduced can be manufactured. Further, in the step (f), since the protective layer and the first barrier metal layer in the region where the pad opening is formed are removed, the conductive layer and the interlayer insulating layer can be in direct contact with each other, and adhesion is improved Can be improved. As a result, film peeling between the wiring layer portion and the pad electrode layer can be prevented, and a highly reliable semiconductor device can be manufactured.

  In the method for manufacturing a semiconductor device of the present invention, forming another specific layer (hereinafter referred to as “B layer”) above a specific layer (hereinafter referred to as “A layer”) The case where the B layer is directly formed and the case where the B layer is formed via another layer on the A layer are included.

In the method for manufacturing a semiconductor device of the present invention,
After (g)
Forming a second barrier metal layer above the conductive layer;
Removing the second barrier metal layer in a region where the pad opening is to be formed.

  Hereinafter, a preferred embodiment of the present invention will be described with reference to FIGS.

1. Semiconductor Device FIG. 1A is a plan view schematically showing a planar shape of a wiring layer in a semiconductor device. FIG. 1B is a cross-sectional view schematically showing a cross section taken along line AA in FIG.

  First, a planar structure of the semiconductor device 1000 will be described with reference to FIG. As shown in FIG. 1, the semiconductor device 1000 includes a pad unit 100 and a lead-out wiring unit 200 that is connected to the pad unit 100 and integrated therewith. The lead-out wiring part 200 is composed of a conductive layer that is narrower than the pad part 100. In the pad unit 100, a pad opening 60 is provided in a predetermined region.

  Next, a cross-sectional structure of the semiconductor device is described with reference to FIG. A first interlayer insulating layer 20 is formed above the semiconductor substrate 10. A first wiring layer 30 is formed on the first interlayer insulating layer 20, and a second interlayer insulating layer 22 is formed above the first wiring layer 30. As shown in FIG. 1B, above the second interlayer insulating layer 22, the second and third wiring layers 32 and 34, the pad wiring layer 40, the third and fourth interlayer insulating layers 24, 26 are alternately stacked. In the semiconductor device according to the present embodiment, as shown in FIG. 1B, the case where the first wiring layers 30, 32, and 34 and the pad wiring layer 40 have the same planar shape will be described as an example. In this way, when wiring layers having the same planar shape are stacked below the pad wiring layer 40, one library can be obtained without being affected by fluctuations in the number of wiring layers below the pad wiring layer 40. The wiring layer absorbs shock during bonding, so that the bonding strength can be increased and the reliability of the semiconductor device can be improved.

  A protective insulating layer 50 is formed on the uppermost pad wiring layer 40. The protective insulating layer 50 has a pad opening 60 so that the pad wiring layer 40 is exposed in a predetermined region in the pad portion 100. In the pad opening 60, for example, wire bonding is performed to electrically connect the outside to the pad wiring layer 40.

  The pad wiring layer 40 has a structure in which a barrier metal layer 40a, a pad electrode layer 40b, and a barrier metal layer 40c are stacked. In the pad wiring layer 40, a protective layer 42 is provided on the barrier metal layer 40a below. The first wiring layer 30 has a structure in which a barrier metal layer 30a, an electrode layer 30b, and a barrier metal layer 30c are stacked. The second and third wiring layers 32 and 34 can have the same structure as the first wiring layer 30. Further, the barrier metal layers 40a and 40c constituting the pad wiring layer 40 have the same opening as the pad opening 60 in plan view. That is, the barrier metal layers 40 a and 40 c are not provided on the bottom surface of the pad opening 60, and the pad electrode layer 40 b is in direct contact with the fourth interlayer insulating layer 26 in the pad opening 60. Become.

  The first to third wiring layers 30, 32, 34 and the pad wiring layer 40 are electrically connected by a plurality of contact layers 70, 72, 74. For example, the first wiring layer 30 and the second wiring layer 32 are electrically connected by the contact layer 70. Similarly, the second wiring layer 32 and the third wiring layer 34 are electrically connected by a contact layer 72, and the third wiring layer 34 and the pad wiring layer 40 are connected by a contact layer 74. Electrically connected. As shown in FIGS. 1A and 1B, the contact layers 70, 72, and 74 can be arranged in a staggered pattern so as not to overlap in plan view.

  Hereinafter, advantages of the semiconductor device of this embodiment will be described.

  According to the semiconductor device of the present embodiment, the protective layer 42 is provided on the contact layer 74 buried in the contact hole 74a. Therefore, it is possible to prevent the surface of the contact layer 74 buried in the contact hole 74a from being exposed. As a result, a stable contact hole layer with low resistance and little variation can be formed, and a highly reliable semiconductor device can be provided.

  In the semiconductor device according to the present embodiment, the barrier metal layers 40a and 40c constituting the pad wiring layer 40 have the same opening as the pad opening 60 in plan view. That is, the barrier metal layers 40a and 40c are not provided on the top and bottom surfaces of the pad wiring layer 40 in the pad opening 60, and the pad electrode layer 40b and the fourth interlayer insulating layer 26 are in direct contact with each other. . Therefore, the adhesion strength between the pad wiring layer 40 and the fourth interlayer insulating layer 26 can be improved, and film peeling can be prevented and a highly reliable semiconductor device can be provided.

2. Semiconductor Device Manufacturing Method Hereinafter, a semiconductor device manufacturing method according to the present embodiment will be described with reference to FIGS. 2-5, (A) is a top view which shows the shape of a wiring layer, (B) shows sectional drawing along the AA of (A).

  First, a semiconductor element (for example, a MIS transistor or a memory transistor) is formed on a semiconductor substrate 10 that is a semiconductor layer. Next, as shown in FIG. 2, a first interlayer insulating layer 20 made of, for example, silicon oxide is formed by a known method. The first interlayer insulating layer 20 is planarized by a chemical mechanical polishing method (CMP method) as necessary.

  Next, the first wiring layer 30 is formed on the first interlayer insulating layer 20. For forming the first wiring layer 30, first, a barrier metal layer 30a including a nitride film of a refractory metal such as TiN is formed by a known method. As the barrier metal layer 30a, a refractory metal film such as Ti or a laminated film of these films can be used. In this case, for example, Ti / TiN, a laminated film of Ti / TiN / Ti, or the like can be used. Next, the conductive layer 30b is formed by a known method. Examples of the conductive layer 30b include an aluminum layer and an alloy layer of aluminum and copper. Further, a barrier metal layer 30c is formed on the conductive layer 30b. The barrier metal layer 30c can be formed in the same manner as the barrier metal layer 30a described above.

  Next, the first wiring layer 30 can be formed as shown in FIG. 2 by patterning the laminated body of the barrier metal layer 30a, the conductive layer 30b, and the barrier metal layer 30c into a predetermined pattern. At this time, the first wiring layer 30 may be patterned so as to have the same planar shape as a pad electrode layer formed in a later step. In this case, a wiring layer having the same planar shape is stacked below the pad wiring layer 40, and the user is not affected by fluctuations in the number of stacked wirings below the pad wiring layer 40. There is an advantage that the design can be performed using two libraries.

  Next, a second interlayer insulating layer 22 made of silicon oxide is formed above the first wiring layer 30 by a known method. The second interlayer insulating layer 22 is planarized by a CMP method as necessary. Next, a contact hole 70 a reaching the first wiring layer 30 is formed in the second interlayer insulating layer 22. The contact hole 70a is formed in a region outside a pad opening formed in a later process. In the semiconductor device of the present embodiment, it is formed in the lead wiring part 200 region. Next, a barrier metal layer 70b is formed on the inner surface of the contact hole 70a by a known method. In the present embodiment, the barrier metal layer 70b is formed in the same process as the formation of the barrier metal layer 32a of the second wiring layer 32. The first contact layer 70 is formed so as to fill the contact hole 70a. The first contact layer 70 is formed, for example, by forming a tungsten layer on the entire surface and etching back the tungsten layer.

  Next, the second wiring layer 32 is formed on the first contact layer 70 and the second interlayer insulating layer 22. The second wiring layer 32 is formed using the same formation method and material as the first wiring layer 30. Then, by repeating the formation of the wiring layer and the interlayer insulating layer, the first to fourth interlayer insulating layers 20, 22, 24, 26 and the first to third wiring layers 30, as shown in FIG. 32 and 34 are laminated alternately and sequentially.

  Next, in the fourth interlayer insulating layer 26, a contact layer 74 for electrically connecting the pad wiring layer 40 and the third wiring layer 30 is formed on the fourth interlayer insulating layer 26 and the uppermost pad wiring. Layer 40 is formed. First, in the region of the lead-out wiring part 200, the contact hole 74a is formed by a known general technique. Thereafter, a barrier metal layer 40a is formed above the fourth interlayer insulating layer 26, and a barrier metal layer 74b is formed on the inner surface of the contact hole 74a. The method for forming the barrier metal layers 40 a and 74 b can be performed in the same manner as the formation of the barrier metal layer of the first wiring layer 30. Thereafter, a conductive layer (not shown) is formed by a known technique so as to fill the contact hole 74a, and the contact layer 74 is formed. Next, the protective layer 42 is formed on the surfaces of the barrier metal layer 40 a and the contact layer 74. As the protective layer 42, the same material as the barrier metal layer 40a or the same material as the pad electrode layer 40b formed in the process described later can be used. Further, the protective layer 42 is not particularly limited as long as it has a film thickness that can prevent the surface of the barrier metal layer 40a from being exposed in the patterning of the barrier metal layer 40a. Next, a mask layer M 1 having a predetermined pattern is formed on the protective layer 42. At this time, the mask layer M1 may have a shape similar to that of a mask layer for forming a pad opening 60 described later.

  Using this mask layer M1 as a mask, the barrier metal layer 40a and the protective layer 42 are removed by a known method. As a result, as shown in FIG. 3, the fourth interlayer insulating layer 26 is exposed in a region where the pad opening is formed in a later step. Thereafter, the mask layer M1 is removed.

  Next, as shown in FIG. 4, a pad electrode layer 40 b and a barrier metal layer 40 c are sequentially stacked on the protective layer 42 and the exposed fourth interlayer insulating layer 26. The pad electrode layer 40b and the barrier metal layer 40c can be formed in the same manner as the conductive layer 30b and the barrier metal layer 30a. Next, as shown in FIG. 4, a mask layer M2 for forming a pad electrode layer is formed on the uppermost barrier metal layer. Using this mask layer M2 as a mask, as shown in FIG. 5, the pad wiring layer 40 is formed by patterning the barrier metal layer 40a, the pad electrode layer 40b, and the barrier metal layer 40c.

  Next, a protective insulating layer 50 (see FIG. 1) is formed above the pad wiring layer 40 by a known method. Next, a mask layer M3 for forming a pad opening is formed on the protective insulating layer 50 by a known technique. Using this mask layer M3 as a mask, the protective insulating layer 50 and the barrier metal layer 40c are etched. In the etching of the barrier metal layer 40c, it is preferable to remove the surface of the pad electrode layer 40b by performing over-etching after removing the barrier metal layer 40c. An altered layer may be formed between the pad electrode layer 40b and the barrier metal layer 40c depending on the material of the barrier metal layer 40c. Such a deteriorated layer contributes to a decrease in the adhesion strength between the pad wiring layer 40 and the bonding electrode. In the present embodiment, this altered layer can be removed by over-etching the surface of the pad electrode layer 40b in this way, and the reliability of the wiring layer can be improved. As described above, when the protective insulating layer 50 and the barrier metal layer 40c are patterned using the same mask layer, the semiconductor device can be manufactured without increasing the number of steps.

  As a result, a pad opening 60 is formed in the pad portion 100, and the semiconductor device shown in FIG. 1 can be manufactured.

  According to the manufacturing method of the semiconductor device of the present embodiment, after forming the contact layer 74 in the contact hole 74a, the protective layer 42 is formed so as to cover the upper surface of the contact layer 74. In the pad opening 60, a process of removing the barrier metal layer 40a formed in the pad opening 60 region is performed in order to prevent film peeling. In this step, the mask layer M1 is formed and the patterning of the barrier metal layer 40a is completed, and then the mask layer M1 is removed. When the mask layer M1 is removed, the upper surface of the contact layer 74 is covered with the protective layer, so that the surface of the contact layer 74 can be prevented from coming into contact with the etching solution. Therefore, the surface of the contact layer can be prevented from being corroded or oxidized, and a good contact layer can be formed. As a result, a highly reliable semiconductor device in which variation in resistance is reduced can be manufactured.

  Further, according to the method for manufacturing the semiconductor device of the present embodiment, the barrier metal layers 40a and 40c constituting the pad wiring layer 40 can be removed in the region of the pad opening 60. Therefore, the pad electrode layer 40b of the pad wiring layer 40 and the fourth interlayer insulating layer 26 are in direct contact with each other. As a result, the adhesion strength between the pad electrode layer 40b and the fourth interlayer insulating layer 26 can be improved, and a highly reliable semiconductor device in which film peeling during bonding is prevented can be manufactured.

  The present invention is not limited to the above-described embodiment, and can be modified within the scope of the gist of the present invention. For example, in the present embodiment, the case where the planar shapes of the first to third wiring layers 30, 32, and 34 and the pad wiring layer 40 are the same is illustrated, but it is not necessary to be limited to this form. Moreover, the opening shape of the barrier metal layers 40 a and c constituting the pad wiring layer 40 may be the same as or different from the opening shape of the pad opening 60. In the semiconductor device according to the present embodiment, the pad wiring layer 40 has been described as an example in which the conductive layer 40b is sandwiched between the barrier metal layers 40a and c. Only the metal layer 40a may be provided.

The figure which shows typically the semiconductor device concerning this Embodiment. The figure which shows typically the manufacturing process of the semiconductor device concerning this Embodiment. The figure which shows typically the manufacturing process of the semiconductor device concerning this Embodiment. The figure which shows typically the manufacturing process of the semiconductor device concerning this Embodiment. The figure which shows typically the manufacturing process of the semiconductor device concerning this Embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Semiconductor layer 20, 22, 24, 26 1st-4th interlayer insulation layer, 30, 32, 34 1st-3rd wiring layer, 30a, 30c, 32a, 32c, 34a, 34c Barrier metal layer, 42 Protection layer 50 Protective insulating layer, 60 pad opening, 70, 72, 74 contact layer, 100 pad, 200 lead-out wiring

Claims (8)

A semiconductor layer;
An interlayer insulating layer provided above the semiconductor layer;
A contact hole provided in the interlayer insulating layer;
A first barrier metal layer provided above the inner surface of the contact hole and the interlayer insulating layer;
A contact layer embedded in the contact hole;
A protective layer provided at least above the contact layer;
A conductive layer provided above the protective layer;
And a protective insulating layer provided above the conductive layer and provided with a pad opening. In claim 1,
The pad opening is a semiconductor device formed in a region other than vertically above the contact hole. In claim 2,
The semiconductor device, wherein the protective layer and the first barrier metal layer below the pad opening are removed. In any one of Claims 1-3,
The semiconductor device is a semiconductor device in which the material of the protective layer is the same as that of the conductive layer. In any one of Claims 1-3,
A semiconductor device, wherein the material of the protective layer is the same as that of the barrier metal layer. In any one of Claims 1-5,
A semiconductor device, wherein a second barrier metal layer is provided between the protective insulating layer and the conductive layer. (A) forming an interlayer insulating layer above the semiconductor layer;
(B) forming a contact hole in the interlayer insulating layer;
(C) forming a first barrier metal layer above the inner surface of the contact hole and the interlayer insulating layer;
(D) forming a contact layer in the contact hole;
(E) forming a protective layer at least above the contact layer;
(F) removing the protective layer and the first barrier metal layer formed below the region where the pad opening is formed;
(G) forming a conductive layer above the protective layer;
(H) forming a protective insulating layer having the pad opening above the conductive layer; and a method of manufacturing a semiconductor device. In claim 7,
After (g)
Forming a second barrier metal layer above the conductive layer;
Removing the second barrier metal layer in a region where the pad opening is to be formed.

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