JP2005183745A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method Download PDF

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JP2005183745A
JP2005183745A JP2003423911A JP2003423911A JP2005183745A JP 2005183745 A JP2005183745 A JP 2005183745A JP 2003423911 A JP2003423911 A JP 2003423911A JP 2003423911 A JP2003423911 A JP 2003423911A JP 2005183745 A JP2005183745 A JP 2005183745A
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semiconductor element
film substrate
film
electrode
conductor wiring
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JP3792227B2 (en
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Koichi Nagao
浩一 長尾
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83192Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body

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  • Wire Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To efficiently manufacture a chip-on film type semiconductor device with high connection reliability. <P>SOLUTION: A film substrate 7 is used as a tape carrier substrate. The substrate comprises a film base material 1, conductive wiring 2 formed on the surface of the film base material 1, a plurality of projected electrodes 3 formed on the conductive wiring 2 correspondingly to a plurality of electrode pads 9 of a semiconductor element 8 to be loaded, and coats 5 formed with the same thickness as that of the electrode pads 9 of the semiconductor elements 8 so as to cover the surfaces of these projected electrodes 3 and the conductive wiring 2. The semiconductor element 8 is joined with the film substrate 7 by solid phase dispersion on a contact between the plating coats 5 of the projected electrodes 3 formed on the film substrate 7 and the electrode pads 9 of the semiconductor element 8. Consequently, formation of projected electrodes on the semiconductor element 8 is made unnecessary, the diffusion of tin into the conductive wiring 2 on the tape carrier substrate 7 can be prevented, and the high reliability of connection with the semiconductor element 8 can be realized. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明はフィルム基板を用いたチップオンフィルム(Chip On Film)型の半導体装置およびその製造方法に関するものであり、特にフィルム基板と半導体素子との接続方法及び接続構造に関するものである。   The present invention relates to a chip-on-film semiconductor device using a film substrate and a method for manufacturing the same, and more particularly to a connection method and a connection structure between a film substrate and a semiconductor element.

従来のチップオンフィルム(Chip On Film)型の半導体装置(以下、COFとも称す)について説明する。
図5(a)はCOFの一部を示す断面図、図5(b)は同COFの図5(a)におけるC−C′断面の一部を示す断面図である。このCOFは、フラットパネルディスプレイの駆動用ドライバーとして主に使用されるもので、柔軟な絶縁性フィルム基板であるテープキャリア基板55に半導体素子56が搭載され、封止樹脂63により保護されている。
A conventional chip on film type semiconductor device (hereinafter also referred to as COF) will be described.
FIG. 5A is a cross-sectional view showing a part of the COF, and FIG. 5B is a cross-sectional view showing a part of the CC ′ cross section in FIG. 5A of the COF. The COF is mainly used as a driver for driving a flat panel display. A semiconductor element 56 is mounted on a tape carrier substrate 55 which is a flexible insulating film substrate and is protected by a sealing resin 63.

テープキャリア基板55は、ポリイミドなどよりなる絶縁性フィルム基材51、銅などよりなる導体配線52、導体配線52を被覆する金属めっき被膜53、及び絶縁樹脂であるソルダーレジスト54により構成されている。   The tape carrier substrate 55 includes an insulating film base 51 made of polyimide or the like, a conductor wiring 52 made of copper, a metal plating film 53 that covers the conductor wiring 52, and a solder resist 54 that is an insulating resin.

半導体素子56は、電極パッド57上にバリア層59を介して突起電極61が形成されていて、この突起電極61を介してテープキャリア基板55上の導体配線52と接続されている。突起電極61の周囲の電極パッド57表面は保護層58で覆われている。   In the semiconductor element 56, the protruding electrode 61 is formed on the electrode pad 57 via the barrier layer 59, and is connected to the conductor wiring 52 on the tape carrier substrate 55 via the protruding electrode 61. The surface of the electrode pad 57 around the protruding electrode 61 is covered with a protective layer 58.

このCOFを製造する際にはまず、図6(a)に示すように、テープキャリア基板55(絶縁性フィルム基材51、導体配線52、金属めっき被膜53、ソルダーレジスト54)の素子搭載領域の所定部分に封止樹脂63を塗布する。   When manufacturing this COF, first, as shown in FIG. 6A, the element mounting region of the tape carrier substrate 55 (insulating film base 51, conductor wiring 52, metal plating film 53, solder resist 54) is formed. A sealing resin 63 is applied to a predetermined portion.

次に、図6(b)に示すように、半導体素子56をフェースダウンでテープキャリア基板55に対向させ、突起電極61と導体配線52とを位置合わせしたうえで、テープキャリア基板7上に載置する。   Next, as shown in FIG. 6B, the semiconductor element 56 is faced down to face the tape carrier substrate 55, the protruding electrodes 61 and the conductor wiring 52 are aligned, and then mounted on the tape carrier substrate 7. Put.

次に、導体配線52と突起電極61とを接続させる。ここで、突起電極61は、例えば金を用いて高さ10〜20μm程度に形成されている。導体配線52上の金属めっき被膜53は、例えば錫や金を用いて膜厚0.3〜0.7μm程度に形成されている。このため、金属めっき被膜53が例えば錫の場合には、300〜400℃程度まで熱を加えることにより、錫と金の固相拡散によって接続を生じさせる。金属めっき被膜53が例えば金の場合には、熱の他に、図6(C)に示すように超音波振動65を加えることがある。   Next, the conductor wiring 52 and the protruding electrode 61 are connected. Here, the protruding electrode 61 is formed to a height of about 10 to 20 μm using, for example, gold. The metal plating film 53 on the conductor wiring 52 is formed with a film thickness of about 0.3 to 0.7 μm using, for example, tin or gold. For this reason, when the metal plating film 53 is, for example, tin, the connection is caused by solid phase diffusion of tin and gold by applying heat to about 300 to 400 ° C. When the metal plating film 53 is gold, for example, in addition to heat, an ultrasonic vibration 65 may be applied as shown in FIG.

次に、封止樹脂63を硬化させることにより、図6(d)に示すような、半導体素子56とテープキャリア基板55とが固定されたCOFを得る(たとえば特許文献1参照)。
特開平10−335373号公報
Next, the sealing resin 63 is cured to obtain a COF in which the semiconductor element 56 and the tape carrier substrate 55 are fixed as shown in FIG. 6D (see, for example, Patent Document 1).
JP 10-335373 A

上述したように、チップオンフィルム型の半導体装置を構成するには、突起電極61を持った半導体素子56が必要であり、半導体素子56上に予め突起電極61を形成する工程を要する分、製造工程が複雑になり、製造コストの増加にもつながっていた。   As described above, in order to configure a chip-on-film type semiconductor device, the semiconductor element 56 having the protruding electrode 61 is required, and the process of forming the protruding electrode 61 in advance on the semiconductor element 56 is required. The process has become complicated, leading to an increase in manufacturing costs.

また、導体配線52上の金属めっき被膜53が錫である場合には、経時変化によって錫が導体配線52の中へ拡散してしまい、突起電極61との接続強度が低下し、接続信頼性の低下を招くことがあり、テープキャリア基板55の管理コストの増加にもつながっていた。   In addition, when the metal plating film 53 on the conductor wiring 52 is tin, tin diffuses into the conductor wiring 52 due to a change with time, the connection strength with the protruding electrode 61 is reduced, and connection reliability is improved. This may lead to a decrease, leading to an increase in the management cost of the tape carrier substrate 55.

本発明は上記問題を解決するもので、チップオンフィルム型の半導体装置を効率よく、かつ接続信頼性高く製造することを目的とする。   SUMMARY OF THE INVENTION The present invention solves the above problems, and an object of the present invention is to manufacture a chip-on-film type semiconductor device efficiently and with high connection reliability.

上記課題を解決するために、本発明のフィルム基板は、フィルム基材と、前記フィルム基材の表面に形成された導体配線と、搭載対象の半導体素子の複数の電極パッドに対応して前記導体配線上に形成された複数の突起電極と、前記複数の突起電極と導体配線の表面を被覆して前記半導体素子の電極パッドと同等の厚みに形成されためっき被膜とを有した構成としたことを特徴とする。   In order to solve the above-described problems, the film substrate of the present invention includes a film base material, conductor wiring formed on the surface of the film base material, and a plurality of electrode pads corresponding to a plurality of electrode pads of a semiconductor element to be mounted. A structure having a plurality of protruding electrodes formed on the wiring, and a plating film that covers the plurality of protruding electrodes and the surface of the conductor wiring and has a thickness equivalent to the electrode pad of the semiconductor element. It is characterized by.

また本発明のフィルム基板の製造方法は、導体配線が表面に形成されたフィルム基材上をフォトレジストで覆い、このフォトレジストに、搭載対象の半導体素子の複数の電極パッドに対応する導体配線部分を露出させる開口をフォトリソグラフィー法により形成する工程と、前記開口から露出した前記導体配線上に電解めっき法により突起電極を形成する工程と、前記フォトレジストを除去する工程と、前記複数の突起電極と導体配線の表面を被覆するめっき被膜を前記半導体素子の電極パッドと同等の厚みにて形成する工程とを行なうことを特徴とする。   In the film substrate manufacturing method of the present invention, the film substrate on which the conductor wiring is formed is covered with a photoresist, and the conductor wiring portion corresponding to the plurality of electrode pads of the semiconductor element to be mounted is covered with the photoresist. A step of forming an opening for exposing the photoresist by a photolithography method, a step of forming a protruding electrode by an electrolytic plating method on the conductor wiring exposed from the opening, a step of removing the photoresist, and the plurality of protruding electrodes And a step of forming a plating film covering the surface of the conductor wiring with a thickness equivalent to the electrode pad of the semiconductor element.

また本発明の半導体装置は、上記したフィルム基板と、複数の電極パッドを有し、前記電極パッドと前記フィルム基板の突起電極との接触部における固相拡散で接合されて前記フィルム基板上に搭載された半導体素子とを有した構成としたことを特徴とする。   The semiconductor device of the present invention includes the above-described film substrate and a plurality of electrode pads, and is mounted on the film substrate by being bonded by solid phase diffusion at a contact portion between the electrode pad and the protruding electrode of the film substrate. It is characterized by having a configuration including a semiconductor element.

具体的には、半導体素子の電極パッドはアルミニウムで形成され、フィルム基板のめっき被膜は金で形成されたことを特徴とする。
また、半導体素子の電極パッドとフィルム基板のめっき被膜がそれぞれ厚み0.6μm〜1.5μmにて形成されたことを特徴とする。
Specifically, the electrode pad of the semiconductor element is formed of aluminum, and the plating film of the film substrate is formed of gold.
Further, the electrode pad of the semiconductor element and the plating film of the film substrate are each formed with a thickness of 0.6 μm to 1.5 μm.

また本発明の半導体装置の製造方法は、フィルム基板の突起電極と半導体素子の電極パッドとを位置合わせする工程と、位置合わせした突起電極と電極パッドとを突起電極表面のめっき被膜を介して接触させ、その接触部に熱と超音波振動の少なくとも一方を印可して固相拡散で接合を形成させることにより、前記フィルム基板上に半導体素子を搭載する工程と、前記半導体素子の搭載前あるいは搭載後に前記フィルム基板上の半導体素子搭載領域に封止樹脂を供給する工程と、前記フィルム基材上の封止樹脂を硬化させる工程とを行なうことを特徴とする。   The method for manufacturing a semiconductor device of the present invention includes a step of aligning the protruding electrode of the film substrate and the electrode pad of the semiconductor element, and contacting the aligned protruding electrode and the electrode pad through a plating film on the surface of the protruding electrode. A step of mounting a semiconductor element on the film substrate by applying at least one of heat and ultrasonic vibration to the contact portion to form a bond by solid phase diffusion, and before or after mounting the semiconductor element A step of supplying a sealing resin to the semiconductor element mounting region on the film substrate and a step of curing the sealing resin on the film substrate are performed.

本発明によれば、上記したようなフィルム基板を用いるため、フィルム基板の導体配線に半導体素子を接続させる際に、従来のように錫の拡散を利用することなく、接続部分に電極パッド(アルミニウム)とめっき被膜(金)で構成される強度の高い金属間化合物を多量に生成することができ、それにより接続部の強度を増大して、高い信頼性を確保することができる。また、半導体素子に予め突起電極を形成する必要がないため、その加工工程を排除でき、さらに突起電極形成専用の設備が不要になる分、半導体素子に関して低コスト化を実現できる。一方、フィルム基板には突起電極を形成することになるが、半導体素子への突起電極形成と異なって、フィルム基板の加工工程をそのまま利用して突起電極を形成できるため、新たな設備投資は不要であり、その分、低コスト化を実現できる。さらに、経年変化による錫の拡散を抑制する必要がない分、フィルム基板の管理コストを低下できる。   According to the present invention, since the film substrate as described above is used, when the semiconductor element is connected to the conductor wiring of the film substrate, the electrode pad (aluminum) is used in the connection portion without using the diffusion of tin as in the prior art. ) And a plating film (gold) and a high strength intermetallic compound can be produced, thereby increasing the strength of the connecting portion and ensuring high reliability. In addition, since it is not necessary to previously form the protruding electrode on the semiconductor element, the processing steps can be eliminated, and further, the cost for the semiconductor element can be reduced because the dedicated equipment for forming the protruding electrode is unnecessary. On the other hand, bump electrodes are formed on the film substrate. Unlike bump electrode formation on semiconductor elements, bump electrodes can be formed using the film substrate processing process as it is, so no new capital investment is required. Therefore, the cost can be reduced accordingly. Furthermore, the management cost of the film substrate can be reduced because it is not necessary to suppress the diffusion of tin due to aging.

以下、本発明の実施の形態を、図面を参照しながら説明する。
(実施の形態1)
図1(a)は本発明の実施の形態1における半導体装置の一部を示す断面図、図1(b)は同半導体装置の図1(a)におけるa−a′断面の一部を示す断面図、図2は同半導体装置の製造方法を説明する工程断面図、図3は同半導体装置を構成するテープキャリア基板の製造方法を説明する工程断面図である。この実施の形態1の半導体装置は、先に図5および図6を用いて説明した従来のCOFタイプの半導体装置とほぼ同様の構成を有しており、フラットパネルディスプレイの駆動用ドライバーとして主に使用される。
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(Embodiment 1)
1A is a cross-sectional view showing a part of the semiconductor device according to the first embodiment of the present invention, and FIG. 1B is a cross-sectional view taken along the line aa ′ of FIG. 1A of the semiconductor device. FIG. 2 is a process cross-sectional view illustrating a method for manufacturing the semiconductor device, and FIG. 3 is a process cross-sectional view illustrating a method for manufacturing a tape carrier substrate constituting the semiconductor device. The semiconductor device of the first embodiment has substantially the same configuration as the conventional COF type semiconductor device described above with reference to FIGS. 5 and 6, and is mainly used as a driver for driving a flat panel display. used.

図1(a)(b)に示す半導体装置は、柔軟な絶縁性テープキャリア基板7上に半導体素子8が搭載され、封止樹脂16により保護されている。
半導体素子8は、アルミニウムよりなる複数の電極パッド9が形成されており、電極パッド9の周縁部表面は保護層10で覆われている。
In the semiconductor device shown in FIGS. 1A and 1B, a semiconductor element 8 is mounted on a flexible insulating tape carrier substrate 7 and protected by a sealing resin 16.
The semiconductor element 8 is formed with a plurality of electrode pads 9 made of aluminum, and the peripheral surface of the electrode pad 9 is covered with a protective layer 10.

テープキャリア基板7は、ポリイミドなどよりなる絶縁性フィルム基材1上に銅などよりなる複数の導体配線2が形成され、各導体配線2上に前記半導体素子8の複数の電極パッド9をそれぞれ接続する突起電極3が形成され、各突起電極3および導体配線2の表面を被覆する第1および第2の金属めっき被膜4,5が積層形成されている。そして、突起電極3の最表面の第2の金属めっき被膜5と前記半導体素子8の電極パッド9との接触部での固相拡散による接合で、半導体素子8に対して電気的に接続されている。   In the tape carrier substrate 7, a plurality of conductor wirings 2 made of copper or the like are formed on an insulating film substrate 1 made of polyimide or the like, and a plurality of electrode pads 9 of the semiconductor element 8 are connected to each conductor wiring 2. The protruding electrodes 3 are formed, and the first and second metal plating films 4 and 5 covering the surfaces of the protruding electrodes 3 and the conductor wiring 2 are laminated. Then, it is electrically connected to the semiconductor element 8 by bonding by solid phase diffusion at the contact portion between the second metal plating film 5 on the outermost surface of the protruding electrode 3 and the electrode pad 9 of the semiconductor element 8. Yes.

なお、突起電極3は、導体配線2の上面と側面方向に等方的にめっきを成長させることで形成されていて、第1および第2の金属めっき被膜4,5を含んだ突起電極3の断面形状は半円状(蒲鉾型)となっている。第2の金属めっき被膜5は半導体素子8の電極パッド9と同等の厚みに形成されている。   The protruding electrode 3 is formed by growing isotropically in the direction of the upper surface and the side surface of the conductor wiring 2, and the protruding electrode 3 including the first and second metal plating films 4 and 5 is formed. The cross-sectional shape is a semicircular shape (a bowl shape). The second metal plating film 5 is formed to have the same thickness as the electrode pad 9 of the semiconductor element 8.

上記半導体装置の製造方法を以下に説明する。
まず、図2を参照しながらテープキャリア基板7の製造方法を説明する。
図2(a)に示すように、フィルム基材1の表面に複数の導体配線2を並べて形成する。ここでは矩形のフィルム基材1の周縁領域に複数の導体配線2を、それぞれフィルム基材1の各辺と直交する方向に延びるように、かつ、フィルム基材1の各辺に沿う方向に互いに間隙を形成するように、並列に配列している。フィルム基材1は例えばポリイミドフィルムを用いる。導体配線2は例えば銅を用いて、その配列ピッチにもよるが、厚さ10〜20μm程度に形成する。さらに、矩形のフィルム基材1の周縁領域には、導体配線2を保護するソルダーレジスト6を形成しておく。ソルダーレジスト6の形成方法としては印刷法などを用いる。
A method for manufacturing the semiconductor device will be described below.
First, a manufacturing method of the tape carrier substrate 7 will be described with reference to FIG.
As shown in FIG. 2A, a plurality of conductor wirings 2 are formed side by side on the surface of the film substrate 1. Here, a plurality of conductor wirings 2 are extended in a direction perpendicular to each side of the film base 1 in the peripheral region of the rectangular film base 1 and in a direction along each side of the film base 1. They are arranged in parallel so as to form a gap. For example, a polyimide film is used as the film substrate 1. The conductor wiring 2 is made of, for example, copper and has a thickness of about 10 to 20 μm, depending on the arrangement pitch. Further, a solder resist 6 for protecting the conductor wiring 2 is formed in the peripheral area of the rectangular film substrate 1. As a method for forming the solder resist 6, a printing method or the like is used.

次に、図2(b)に示すように、複数の導体配線2をも覆うようにフィルム基材1の全表面にフォトレジスト20を形成する。そして、図2(c)に示すように、フィルム基材1に対して、導体配線2の配列方向に沿う方向(フィルム基材1の各辺に沿う方向)に連続した露光パターン21aが形成された露光マスク21を対向配置し、この露光マスク側から露光する。ここでは露光パターン21aは、導体配線2の内端部にオーバーラップする適当なサイズおよび位置に開口するように、四角枠状に形成している。   Next, as shown in FIG. 2B, a photoresist 20 is formed on the entire surface of the film substrate 1 so as to cover the plurality of conductor wirings 2. And as shown in FIG.2 (c), the exposure pattern 21a which followed the direction (direction along each side of the film base material 1) along the sequence direction of the conductor wiring 2 with respect to the film base material 1 is formed. The exposed exposure mask 21 is placed oppositely and exposed from the exposure mask side. Here, the exposure pattern 21a is formed in a square frame shape so as to open at an appropriate size and position overlapping the inner end portion of the conductor wiring 2.

その後に、露光されたフォトレジスト20を現像して、図2(d)に示すように、開口部20aを形成する。形成される四角枠状の開口部20aは、上記した露光パターン21aを持った露光マスク21によるため、たとえ露光マスク21が位置ずれしていても必ず各導体配線2と交わる。この開口部20aから露出した導体配線2上の露出部が突起電極形成領域である。   Thereafter, the exposed photoresist 20 is developed to form an opening 20a as shown in FIG. The formed rectangular frame-shaped opening 20a is formed by the exposure mask 21 having the above-described exposure pattern 21a. Therefore, even if the exposure mask 21 is displaced, the opening 20a always intersects each conductor wiring 2. The exposed portion on the conductor wiring 2 exposed from the opening 20a is a protruding electrode formation region.

この状態で、図2(e)に示すように、導体配線2上の露出部に電解めっき法によって突起電極3を形成する。このとき突起電極3は、上記したように露光パターン21aに対応するものであることから、設計した寸法通りに形成できる。なおこのとき突起電極3は、導体配線2と同じ材料を用いて、例えば導体配線2が銅であれば突起電極3も銅を用いて形成する。突起電極3の厚さは5〜15μm程度とする。   In this state, as shown in FIG. 2E, the protruding electrode 3 is formed on the exposed portion on the conductor wiring 2 by electrolytic plating. At this time, since the protruding electrode 3 corresponds to the exposure pattern 21a as described above, it can be formed according to the designed dimensions. At this time, the protruding electrode 3 is formed using the same material as that of the conductor wiring 2, for example, if the conductor wiring 2 is copper, the protruding electrode 3 is also formed using copper. The thickness of the protruding electrode 3 is about 5 to 15 μm.

次に、図2(f)に示すようにフォトレジスト20を剥離する。その後に、導体配線2と突起電極3の表面に、例えばニッケルよりなる第1のめっき被膜4と金よりなる第2のめっき被膜5とを順次に形成することにより、図1に示したテープキャリア基板7を得る。   Next, the photoresist 20 is removed as shown in FIG. Thereafter, a first plating film 4 made of nickel and a second plating film 5 made of gold, for example, are sequentially formed on the surfaces of the conductor wiring 2 and the protruding electrode 3, whereby the tape carrier shown in FIG. A substrate 7 is obtained.

なお、第1のめっき被膜4は、導体配線2と第2のめっき被膜5とが経時変化により固体拡散するのを防止する目的でバリア層として設けるもので、膜厚0.3〜0.7μm程度に形成する。第2のめっき被膜5は、半導体素子8の電極パッド9とほぼ同じ厚さに形成する。電極パッド9の厚さは、半導体素子8の製造プロセスに拠って概ね0.6〜1.5μm程度なので、めっき被膜5の厚さも0.6〜1.5μmの範囲とする。   The first plating film 4 is provided as a barrier layer for the purpose of preventing the conductor wiring 2 and the second plating film 5 from solid-diffusing due to changes over time, and has a film thickness of 0.3 to 0.7 μm. Form to the extent. The second plating film 5 is formed to have substantially the same thickness as the electrode pad 9 of the semiconductor element 8. Since the thickness of the electrode pad 9 is approximately 0.6 to 1.5 μm depending on the manufacturing process of the semiconductor element 8, the thickness of the plating film 5 is also in the range of 0.6 to 1.5 μm.

めっき被膜5の厚さが0.6μmより小さい場合、接続部に形成される金属間化合物がアルミニウム(電極パッド9)が多い組成となり、強度が低く、もろい特性となってしまい、接続部の強度が低下して接続信頼性が確保できなくなる。逆に、めっき被膜5の厚さが1.5μmより大きい場合には、接続部に形成される金属間化合物の特性に悪影響はないが、めっき被膜5の形成コストが高くなり、テープキャリア基板8のコストアップにつながる。   When the thickness of the plating film 5 is smaller than 0.6 μm, the intermetallic compound formed in the connection portion has a composition with a large amount of aluminum (electrode pad 9), the strength is low, and the brittle property is obtained, and the strength of the connection portion As a result, connection reliability cannot be ensured. On the contrary, when the thickness of the plating film 5 is larger than 1.5 μm, there is no adverse effect on the characteristics of the intermetallic compound formed at the connection portion, but the formation cost of the plating film 5 becomes high, and the tape carrier substrate 8 Lead to higher costs.

次に、図3を参照しながらテープキャリア基板7と半導体素子8との接続を説明する。
図3(a)に示すように、テープキャリア基板7上に封止樹脂16を塗布する。この封止樹脂16はフィルム基材1上、導体配線2に囲まれた中央部に供給するが、導体配線2や突起電極3を覆うところまで広がってもよい。
Next, the connection between the tape carrier substrate 7 and the semiconductor element 8 will be described with reference to FIG.
As shown in FIG. 3A, a sealing resin 16 is applied on the tape carrier substrate 7. The sealing resin 16 is supplied to the central portion surrounded by the conductor wiring 2 on the film base 1, but may extend to a place covering the conductor wiring 2 and the protruding electrode 3.

次に、図3(b)に示すように、半導体素子8をフェースダウンでテープキャリア基板7に対向させて、電極パッド9と突起電極3とを位置合わせし、両者が接近する方向に加圧することにより、テープキャリア基板7と半導体素子8との間に介在する封止樹脂16を押し出しながら、電極パッド9と突起電極3とを接触させる。このとき封止樹脂16を60〜200℃程度に加熱すると、封止樹脂16を押し出す効果が高まる。   Next, as shown in FIG. 3B, the semiconductor element 8 is faced down to face the tape carrier substrate 7, the electrode pad 9 and the protruding electrode 3 are aligned, and the pressure is applied in the direction in which both approach each other. Thus, the electrode pad 9 and the protruding electrode 3 are brought into contact with each other while the sealing resin 16 interposed between the tape carrier substrate 7 and the semiconductor element 8 is pushed out. At this time, when the sealing resin 16 is heated to about 60 to 200 ° C., the effect of extruding the sealing resin 16 is enhanced.

次に、図3(c)に示すように、半導体素子8に超音波振動18を加えて、その電極パッド9と突起電極3上の第2のめっき被膜5とを接続させる。このときの接続条件としては、超音波振動18のパワーは1電極当たり0.1〜0.8W程度、温度は80〜200℃程度、加圧力は1電極あたり20〜100g程度とする。これにより、アルミニウム製の電極パッド9と金よりなるめっき被膜5との接触部分で、互いのアルミニウムと金とが固相拡散して金属間化合物が形成され、接続部が形成される。   Next, as shown in FIG. 3C, ultrasonic vibration 18 is applied to the semiconductor element 8 to connect the electrode pad 9 and the second plating film 5 on the protruding electrode 3. As connection conditions at this time, the power of the ultrasonic vibration 18 is about 0.1 to 0.8 W per electrode, the temperature is about 80 to 200 ° C., and the applied pressure is about 20 to 100 g per electrode. Thereby, at the contact portion between the electrode pad 9 made of aluminum and the plating film 5 made of gold, the mutual aluminum and gold are solid-phase diffused to form an intermetallic compound, and a connection portion is formed.

その際に、接続部において、アルミニウム膜たる電極パッド9の全厚みを金属間化合物に変化させることが必要である。アルミニウムの層が残留すると、経時変化によって脆い金属間化合物が生成して接続部の強度低下をまねき、接続信頼性を低下させる結果となる。このため、電極パッド9の全厚みを金属間化合物とする目的で、上記したように第2のめっき被膜5と同等の膜厚が必要となるのである。   In that case, it is necessary to change the total thickness of the electrode pad 9 which is an aluminum film into an intermetallic compound in a connection part. If the aluminum layer remains, a brittle intermetallic compound is generated with the passage of time, resulting in a decrease in the strength of the connection portion, resulting in a decrease in connection reliability. For this reason, for the purpose of making the entire thickness of the electrode pad 9 an intermetallic compound, a film thickness equivalent to the second plating film 5 is required as described above.

電極パッド9としては、上記したようにアルミニウムのみで形成する他、アルミニウムを主成分とした材料で構成されることも多く、銅、シリコン等が微量混ぜられる場合もある。電極パッド9をアルミニウムで形成する場合、テープキャリア基板7のめっき被膜5を金にすることで、非常に強度の高い金属間化合物を形成することができ、接続信頼性を確保できる。これ以外の組み合わせでは、金属間化合物を形成できなかったり、強度の弱い金属間化合物が形成されてしまう。   The electrode pad 9 is not only formed of aluminum as described above, but is often made of a material mainly composed of aluminum, and a small amount of copper, silicon, or the like may be mixed. When the electrode pad 9 is formed of aluminum, an extremely strong intermetallic compound can be formed by using the plating film 5 of the tape carrier substrate 7 as gold, and connection reliability can be ensured. In other combinations, an intermetallic compound cannot be formed, or an intermetallic compound having a low strength is formed.

最後に、図3(d)に示すように、封止樹脂16をオーブン等で加熱して硬化させることにより、半導体素子8とテープキャリア基板7とを固定する。ただし、封止樹脂16は、上述したようにテープキャリア基板7上に予め塗布するのでなく、導体配線2と突起電極3とを接続した後にテープキャリア基板7と半導体素子8との間隙に注入してもよい。   Finally, as shown in FIG. 3D, the semiconductor resin 8 and the tape carrier substrate 7 are fixed by heating and curing the sealing resin 16 in an oven or the like. However, the sealing resin 16 is not applied to the tape carrier substrate 7 in advance as described above, but is injected into the gap between the tape carrier substrate 7 and the semiconductor element 8 after connecting the conductor wiring 2 and the protruding electrode 3. May be.

以上のようにして半導体装置を製造することにより、半導体素子8への突起電極形成が不要なため半導体素子8の低コスト化を実現するとともに、テープキャリア基板7の導体配線2への錫の拡散がないため、テープキャリア基板7の管理コストを低下できるだけでなく、半導体素子8との接続の高信頼性化を実現することができる。このような半導体装置は、上記したフラットパネルディスプレイの駆動用ドライバーなど、情報通信機器、事務用電子機器等に好適に使用できる。
(実施の形態2)
図4(a)は本発明の実施の形態2における半導体装置の一部を示す断面図、図4(b)は同半導体装置の図4(a)におけるb−b′断面の一部を示す断面図である。
By manufacturing the semiconductor device as described above, it is not necessary to form a protruding electrode on the semiconductor element 8, so that the cost of the semiconductor element 8 is reduced and the diffusion of tin into the conductor wiring 2 of the tape carrier substrate 7 is achieved. Therefore, not only can the management cost of the tape carrier substrate 7 be reduced, but also high reliability of connection with the semiconductor element 8 can be realized. Such a semiconductor device can be suitably used for information communication equipment, office electronic equipment, and the like such as the driver for driving the flat panel display described above.
(Embodiment 2)
4A is a cross-sectional view showing a part of the semiconductor device according to the second embodiment of the present invention, and FIG. 4B is a partial cross-sectional view taken along the line bb ′ in FIG. 4A of the semiconductor device. It is sectional drawing.

この実施の形態2の半導体装置が上記した実施の形態1の半導体装置と相違するのは、テープキャリア基板7の突起電極3上に金のめっき被膜11のみが形成されている点である。めっき被膜11の厚みは半導体素子8の電極パッド9の厚さと同等であり、このため実施の形態1と同様の効果が得られる。   The semiconductor device according to the second embodiment is different from the semiconductor device according to the first embodiment in that only the gold plating film 11 is formed on the protruding electrode 3 of the tape carrier substrate 7. The thickness of the plating film 11 is equivalent to the thickness of the electrode pad 9 of the semiconductor element 8, and therefore the same effect as in the first embodiment can be obtained.

この半導体装置の製造方法は、実施の形態1の半導体装置とほぼ同様であるが、めっき被膜11が単層であることにより、実施の形態1に比べてめっき工程を1工程削減でき、さらなる低コスト化を図ることができる。   The manufacturing method of this semiconductor device is almost the same as that of the semiconductor device of the first embodiment. However, since the plating film 11 is a single layer, the plating process can be reduced by one process compared to the first embodiment, and further reduced. Cost can be reduced.

本発明に係る半導体装置は、半導体素子との接続が高信頼性化したものとなるため、情報通信機器、事務用電子機器等に有用である。   Since the semiconductor device according to the present invention is highly reliable in connection with a semiconductor element, it is useful for information communication equipment, office electronic equipment, and the like.

本発明の実施の形態1における半導体装置の構成を示す断面図Sectional drawing which shows the structure of the semiconductor device in Embodiment 1 of this invention 図1の半導体装置の製造方法を説明する工程断面図Process sectional drawing explaining the manufacturing method of the semiconductor device of FIG. 図1の半導体装置を構成するテープキャリア基板の製造方法を説明する工程断面図Process sectional drawing explaining the manufacturing method of the tape carrier substrate which comprises the semiconductor device of FIG. 本発明の実施の形態2における半導体装置の構成を示す断面図Sectional drawing which shows the structure of the semiconductor device in Embodiment 2 of this invention. 従来の半導体装置の構成を示す断面図Sectional drawing which shows the structure of the conventional semiconductor device 図5の半導体装置の製造方法を説明する工程断面図Process sectional drawing explaining the manufacturing method of the semiconductor device of FIG.

符号の説明Explanation of symbols

1 フィルム基材
2 導体配線
3 突起電極
4 めっき被膜
5 めっき被膜
7 テープキャリア基板(フィルム基板)
8 半導体素子
9 電極パッド
16 封止樹脂
18 超音波振動
20 フォトレジスト
20a 開口
21 露光マスク
21a 露光パターン
DESCRIPTION OF SYMBOLS 1 Film base material 2 Conductor wiring 3 Protruding electrode 4 Plating film 5 Plating film 7 Tape carrier substrate (film substrate)
8 Semiconductor elements 9 Electrode pads
16 Sealing resin
18 Ultrasonic vibration
20 photoresist
20a opening
21 Exposure mask
21a Exposure pattern

Claims (6)

フィルム基材と、前記フィルム基材の表面に形成された導体配線と、搭載対象の半導体素子の複数の電極パッドに対応して前記導体配線上に形成された複数の突起電極と、前記複数の突起電極と導体配線の表面を被覆して前記半導体素子の電極パッドと同等の厚みに形成されためっき被膜とを有したフィルム基板。   A film substrate; a conductor wiring formed on a surface of the film substrate; a plurality of protruding electrodes formed on the conductor wiring corresponding to a plurality of electrode pads of a semiconductor element to be mounted; A film substrate having a protruding electrode and a plating film that covers the surface of the conductor wiring and is formed to a thickness equivalent to the electrode pad of the semiconductor element. 請求項1記載のフィルム基板の製造方法であって、
導体配線が表面に形成されたフィルム基材上をフォトレジストで覆い、このフォトレジストに、搭載対象の半導体素子の複数の電極パッドに対応する導体配線部分を露出させる開口をフォトリソグラフィー法により形成する工程と、前記開口から露出した前記導体配線上に電解めっき法により突起電極を形成する工程と、前記フォトレジストを除去する工程と、前記複数の突起電極と導体配線の表面を被覆するめっき被膜を前記半導体素子の電極パッドと同等の厚みにて形成する工程とを行なうフィルム基板の製造方法。
A method for producing a film substrate according to claim 1,
Cover the film substrate on which the conductor wiring is formed with a photoresist, and form an opening in the photoresist to expose the conductor wiring portions corresponding to the plurality of electrode pads of the semiconductor element to be mounted. A step of forming a protruding electrode on the conductor wiring exposed from the opening by electrolytic plating, a step of removing the photoresist, and a plating film covering the surface of the plurality of protruding electrodes and the conductor wiring A method of manufacturing a film substrate, comprising performing a step of forming a thickness equivalent to the electrode pad of the semiconductor element.
請求項1記載のフィルム基板と、複数の電極パッドを有し、前記電極パッドと前記フィルム基板の突起電極との接触部における固相拡散で接合されて前記フィルム基板上に搭載された半導体素子とを有した半導体装置。   The film substrate according to claim 1, a plurality of electrode pads, and a semiconductor element mounted on the film substrate bonded by solid phase diffusion at a contact portion between the electrode pad and the protruding electrode of the film substrate, A semiconductor device having 半導体素子の電極パッドはアルミニウムで形成され、フィルム基板のめっき被膜は金で形成された請求項3に記載の半導体装置。   4. The semiconductor device according to claim 3, wherein the electrode pad of the semiconductor element is formed of aluminum, and the plating film of the film substrate is formed of gold. 半導体素子の電極パッドとフィルム基板のめっき被膜がそれぞれ厚み0.6μm〜1.5μmにて形成された請求項3または請求項4のいずれかに記載の半導体装置。   5. The semiconductor device according to claim 3, wherein the electrode pad of the semiconductor element and the plating film of the film substrate are formed with a thickness of 0.6 μm to 1.5 μm, respectively. 請求項3〜請求項5のいずれかに記載された半導体装置の製造方法であって、
フィルム基板の突起電極と半導体素子の電極パッドとを位置合わせする工程と、位置合わせした突起電極と電極パッドとを突起電極表面のめっき被膜を介して接触させ、その接触部に熱と超音波振動の少なくとも一方を印可して固相拡散で接合を形成させることにより、前記フィルム基板上に半導体素子を搭載する工程と、前記半導体素子の搭載前あるいは搭載後に前記フィルム基板上の半導体素子搭載領域に封止樹脂を供給する工程と、前記フィルム基材上の封止樹脂を硬化させる工程とを行なう半導体装置の製造方法。
A method of manufacturing a semiconductor device according to any one of claims 3 to 5,
The process of aligning the protruding electrode of the film substrate and the electrode pad of the semiconductor element, bringing the aligned protruding electrode and electrode pad into contact with each other through a plating film on the surface of the protruding electrode, and heat and ultrasonic vibration at the contact portion A step of mounting a semiconductor element on the film substrate by applying at least one of them to form a bond by solid phase diffusion, and a semiconductor element mounting region on the film substrate before or after mounting the semiconductor element A method for manufacturing a semiconductor device, comprising: supplying a sealing resin; and curing the sealing resin on the film substrate.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100891334B1 (en) 2007-05-25 2009-03-31 삼성전자주식회사 Circuit board, semiconductor package having the board, and methods of fabricating the circuit board and the semiconductor package

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100891334B1 (en) 2007-05-25 2009-03-31 삼성전자주식회사 Circuit board, semiconductor package having the board, and methods of fabricating the circuit board and the semiconductor package

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