JP2005183595A - Method and apparatus for polishing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that defective connection is established since a contact hole after etching at a place where a film is thick in thickness cannot reach metal wiring due to the characteristic of the distribution of the film thickness in a substrate surface at the silicon of an interlayer insulation film in a conventional manufacturing method of a conventional semiconductor. <P>SOLUTION: This method for polishing the semiconductor comprises a process of etching a part which belongs to a film formed on a semiconductor substrate and is thicker in thickness than the other part, prior to the other part. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device polishing method and a polishing apparatus using the polishing method.

  5 and 6 are cross-sectional views showing a conventional method for polishing a semiconductor device. Hereinafter, a conventional method for polishing a semiconductor device will be described with reference to FIGS.

  Step S20: The surface of the silicon substrate 100 is mirror-polished. The entire surface in the diameter direction of the silicon substrate 100 is shown as a cross section. The EL region is the left side region on the outer periphery of the silicon substrate, the MEL region is the middle region between the center and the left side of the silicon substrate, the CE region is the central region of the silicon substrate, and the MER region is The middle region between the silicon substrate center and the right outer periphery, and the ER region indicate the right outer region of the silicon substrate.

  Step S21: A gate insulating film is formed on the surface of the silicon substrate 100 (not shown), and gate electrodes 101a, 101b, 101c, 101d, 101e, 101f, 101g, 101h, 101i, and 101j are formed thereon.

  Step S22: An interlayer insulating film 102 such as silicon oxide is grown on the silicon substrate 100 on which the gate electrodes 101a to 101j are formed and the gate electrodes 101a to 101j by a CVD (Chemical Vapor Deposition) method or a plasma CVD method.

  Step S23: The same composition as the interlayer insulating film 102 used for CMP (Chemical Mechanical Polishing) to obtain a flat surface to be described later on the interlayer insulating film 102 by a deposition method such as a CVD method and a plasma method. That is, a sacrificial film 103 made of silicon oxide is deposited.

  Step S24: The surface of the sacrificial film 103 is substantially planarized by performing the above CMP on the sacrificial film 103.

  Step S25: photolithography is performed, and the gate electrode is etched by a predetermined depth d based on the thickness of the interlayer insulating film 102, the thickness of the sacrificial film 103, and the thickness polished by CMP. Contact holes 104a, 104b, 104c, 104d, 104e, and 104f used to connect 101a to 101j and metal wiring (not shown) to be formed in a later step on the surface of the planarized sacrificial film 103. , 104g, 104h, 104i, and 104j.

  However, in the above-described conventional method for polishing a semiconductor device, even if the surface of the sacrificial film 103 is subjected to CMP, as shown in step S24 of FIG. The film thickness is different. Thereby, as shown in step S25 of FIG. 6, in the region where the film thickness is large, that is, 103b, the contact holes 104a and 104b after the etching of the depth d described above are formed into the metal wiring 101a, There is a problem that a connection failure occurs in which the terminal 101b cannot be reached. Alternatively, there is a problem that the portion of the depth L, that is, the contact holes 104c and 104d excessively etch the surfaces of the metal wirings 101c and 101d, or the reverse phenomenon described above occurs to cause contact failure.

  According to another aspect of the present invention, there is provided a method for polishing a semiconductor device, comprising: one part of a film formed on the semiconductor substrate having a thickness larger than the other part. A step of polishing preferentially over the other portion.

  According to the semiconductor device polishing method of the present invention, the one portion having a thickness larger than that of the other portion of the film formed on the semiconductor substrate is preferentially polished over the other portion. Therefore, the flatness of the surface of the film can be improved as compared with the conventional method for polishing a semiconductor device in which the preferential polishing is not performed. Thereby, it is possible to avoid the above-described connection failure between the contact hole formed in the film and the metal wiring on the semiconductor substrate.

  A polishing apparatus for a semiconductor device according to the present invention includes a holding mechanism capable of moving while holding a semiconductor substrate having a film formed on a surface thereof in a state in which the surface is faced down, and an etching solution that flows out to remove the etching solution. A polishing mechanism that polishes the film by contacting the film, and the polishing mechanism is one part of the film and the other part of the film with the assistance of movement by the holding mechanism. The larger one part is polished preferentially over the other part.

  In the above-described polishing apparatus for a semiconductor device according to the present invention, the polishing mechanism causes the etching solution to flow out to the extent that it can be aggregated by surface tension, and causes the etching solution aggregated by the surface tension to contact the film.

  The above-described polishing apparatus for a semiconductor device according to the present invention further includes a cylindrical polishing mechanism having a cylindrical shape that polishes a portion of the film located near the periphery of the semiconductor substrate.

  A semiconductor device polishing apparatus according to the present invention will be described with reference to the drawings.

  FIG. 1 is a side view illustrating a configuration of a polishing apparatus for a semiconductor device according to an embodiment. More specifically, the polishing apparatus 1 for a semiconductor device according to the embodiment is configured so that the sacrificial film 2 used for flattening the silicon substrate 10 as a whole is polished flatly. The holding part 3 and the discharge part 4 are provided to preferentially flatten the part where the degree of the above is remarkable.

  The holding unit 3 serving as a holding mechanism is arranged between the contact surface 3a and the contact surface 10a of the silicon substrate 10 so that the position of the prominent raised portion on the silicon substrate 10 and the position of the discharge unit 4 coincide with each other. By contact, for example, with physical gripping or vacuum chucking and with the silicon substrate 10 held upside down, the contact is made in the direction perpendicular to the contact surface 10a of the silicon substrate 10 and the contact is made. Move back and forth and right and left in a direction parallel to the surface 10a. In addition, the holding unit 3 rotates the silicon substrate 10 about a direction perpendicular to the contact surface 10a as a rotation axis in order to dry the silicon substrate 10 as described later.

  The discharge unit 4 serving as a polishing mechanism discharges an etching solution 6 such as hydrofluoric acid from the discharge port 4a, and more accurately flows out. Specifically, the discharge unit 4 intensively applies the etching solution 5 at a flow rate such that the etching solution 5 can maintain an upwardly convex arc shape by the surface tension of the solution 5 or a specific place. The etching solution 5 having a flow rate and a flow velocity that causes a discharge state having such directivity is discharged.

  2 and 3 are cross-sectional views illustrating the operation of the polishing apparatus for a semiconductor device according to the embodiment. Hereinafter, the operation of the polishing apparatus of the semiconductor device of the embodiment will be described with reference to FIGS. In order to facilitate explanation and understanding, the silicon substrate 10 illustrated in FIGS. 2 and 3 and the silicon substrate 10 illustrated in FIG. 1 are in an upright and inverted relationship.

  Step S10: The surface 10b of the silicon substrate 10 is mirror-polished.

  Step S11: After forming a gate insulating film (not shown) on the surface 10b of the silicon substrate 10 by a conventionally known method, polysilicon is deposited on the entire surface 10b of the silicon substrate 10 by a CVD (Chemical Vapor Deposition) method. A film (not shown) is formed, and the polysilicon film is further subjected to photolithography and etching to form a plurality of substantially rectangular gate electrodes 11 as shown.

  Step S12: ILD to function as an interlayer insulating film between the gate electrode 11 and a metal wiring (not shown) to be formed on the silicon substrate 10 and the gate electrode 11 above the gate electrode 11 by the CVD method. (Inter-Level (Layer) Dielectric) film 12 is deposited.

  Step S13: A sacrificial film 13 having the same composition as the ILD film 12 is grown on the ILD film 12 by a CVD method. When looking at the entire silicon substrate, there is a film thickness difference K as shown in the figure. This is a characteristic of the CVD method, and the film thickness distribution changes concentrically. As an example, it is assumed that the in-plane tendency of the film thickness is as shown. Further, when viewed microscopically, unevenness due to each pattern occurs, but it is a size that can be sufficiently ignored compared with the film thickness difference K in the previous period.

  Step S14: The holding unit 3 holding the silicon substrate 10 moves or moves back and forth as described above so that the position of the outer peripheral portion 13b, 13c of the silicon substrate having the largest film thickness matches the position of the discharge unit 4. Move to move. After the movement by the holding unit 3, the discharge unit 4 adjusts the etching solution 5 to a condition capable of maintaining the surface tension or realizing the above-described directed protruding state.

  After adjusting the outflow state of the etching solution 5 by the discharge unit 4, the holding unit 3 makes the convex regions 13 b and 13 c of the sacrificial film 13 abut on the etching solution 5 of the discharge unit 4 by performing the above-described vertical movement. The contact is maintained for a predetermined time based on calculation and empirical rules. Thus, the raised portions 13b and 13c are polished in preference to the thin regions 13a, 13d and 13e, so that the convex portions 13c and 13d are approximately the same height as the other portions 13a, 13d and 13e. Say it.

  After the polishing of the region portion 13b, the discharge unit 4 switches the etching solution 5 to pure water, washing away the etching solution 5 remaining on the silicon substrate 10, and the holding unit is applied to the contact surface 10a of the silicon substrate 10. The silicon substrate 10 is dried by rotating the silicon substrate 10 around the vertical direction.

  Step S15: The surface of the sacrificial film 13 is entirely polished by performing CMP, thereby planarizing the entire surface of the sacrificial film 13.

  Step S16: Contact holes 14 for establishing connection with the gate electrode 11 are formed in the ILD film 12 and the sacrificial film 13 by performing photolithography and etching.

  As described above, in the polishing apparatus 1 of the semiconductor device of the embodiment, the discharge unit 4 preferentially etches the portions 13b and 13c having a relatively large thickness as the entire silicon substrate in the surface of the sacrificial film 13. As a result, the flatness of the surface of the sacrificial film 13 can be improved as compared with the polishing by the conventional polishing apparatus, thereby reducing the connection failure between the gate electrode 11 and the contact hole 14. .

FIG. 4 shows a configuration of a polishing apparatus for a semiconductor device according to a modification. As shown in step S13 of FIG. 2, regions where the thicknesses of the insulating film 12 and the sacrificial film 13 formed on the silicon substrate 10 are relatively thick are 13b, 13d, and 13c, as shown in FIG. In addition, for example, the degree of convexity of the insulating film 12 manufactured by the high-density plasma CVD method, the raised portion located at the approximate center on the surface of the sacrificial film 13, and the ring-like raised portion located at the substantially peripheral edge. When it is remarkable, the polishing apparatus 1 replaces the discharge unit 4 described above with a cylindrical first discharge unit 8 and a first discharge unit 7 as shown in FIG. It is desirable to use the second discharge unit 9 provided in the center. By polishing the sacrificial film 13 using the first discharge portion 7 and the second discharge portion 8, the above-described raised portion located at the center and the raised portion located at the periphery of the silicon substrate are preferentially and simultaneously provided. Can be flattened.
Here, we have described the adjustment of the in-plane distribution of the film thickness in the silicon substrate of the insulating film formed by the CVD method. In addition, the polishing characteristics of CMP and the polishing rate distribution in the silicon substrate surface are also included. It is obvious that the same effect can be obtained by performing the processing based on the nozzle position and etching time of the semiconductor device of the present invention.

The figure which shows the structure of the grinding | polishing apparatus of the semiconductor device of an Example. The figure which shows operation | movement of the polisher of the semiconductor device of an Example (the 1). The figure which shows operation | movement of the grinding | polishing apparatus of the semiconductor device of an Example (the 2). The figure which shows the structure of the other grinding | polishing apparatus of the semiconductor device of an Example. The figure which shows the grinding | polishing method of the conventional semiconductor device (the 1). FIG. 2 is a diagram illustrating a conventional method for polishing a semiconductor device (part 2);

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Polishing apparatus 2 Sacrificial film 3 Holding part 4 Discharge part 5 Etching liquid 10 Silicon substrate.

Claims (4)

  Polishing a portion of the film formed on the semiconductor substrate, the portion having a thickness greater than that of the other portion, with priority over the other portion. Polishing method of the apparatus. A holding mechanism capable of moving while holding a semiconductor substrate having a film formed on the surface with the surface facing down;
A polishing mechanism for polishing the film by flowing out the etching liquid and bringing the etching liquid into contact with the film;
The polishing mechanism is configured to preferentially polish one portion of the film that is thicker than the other portion, with the assistance of movement by the holding mechanism, over the other portion. An apparatus for polishing a semiconductor device.   3. The polishing of a semiconductor device according to claim 2, wherein the polishing mechanism causes the etching solution to flow out to an extent that can be aggregated by surface tension, and causes the etching solution aggregated by the surface tension to contact the film. apparatus. 3. The polishing apparatus for a semiconductor device according to claim 2, further comprising a cylindrical polishing mechanism having a cylindrical shape for polishing a portion of the film located in the vicinity of the periphery of the semiconductor substrate.

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