JP2005182433A - Packaging design device and method for semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a design system capable of proposing a design pattern employing a low power consumption flip-flop while preventing the deterioration of a target machine cycle (delay). <P>SOLUTION: In designing of a semiconductor integrated circuit having a plurality of types of flip-flops that are the same in logical function and different in power consumption and delay characteristics, there are provided a two-stage path delay calculation means for performing delay calculation for both of a path from a flip-flop of interest to a flip-flop at the preceding stage and a path to a flip-flop at the following stage; a means for calculating the preceding-stage path delay and the following-stage path delay, and the amount of change in power consumption resulting from switching of the flip-flops by using the results of the two-stage path delay calculation; and a means for switching the flip-flops by determining a reference value of the delay or power consumption. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a mounting design apparatus and method for supporting circuit mounting design by switching flip-flops of a semiconductor integrated circuit for the purpose of power consumption and delay control when designing a semiconductor integrated circuit.

  Conventionally, low power consumption in LSI design of a semiconductor integrated circuit has been performed at the time of layout design (placement and routing). For example, there is a technique of reducing the power consumption by reducing the cell driving capability at the time of placement and routing, and the techniques described in Patent Document 1 and Patent Document 2 are known. When the delay of the path from the flip-flop to the next flip-flop causes a delay violation, the target delay value is divided from the delay value of the path from the flip-flop to the next flip-flop. In order of increasing delay violation rate (over value with respect to the target), the internal resistance is changed so as to increase the operation speed of the logic element (cell) constituting the path from the flip-flop to the next flip-flop, In this case, the power consumption is controlled so that the power consumption does not exceed the limit value.

  Non-Patent Document 1 describes a leakage power optimization by cell replacement.

JP 2002-312415 A

JP 2001-332625 A “New In-Place Optimization Multi-Vt / Logic Resynthesis” reported by Yuji Hisaki at Cadence R & D Seminar on May 15, 2003

  In the prior art, the path delay calculation result for one stage from the flip-flop to the next flip-flop is used. Therefore, it is possible to switch the cells constituting the path in consideration of the path delay for one stage (the latter stage).

  However, when the flip-flop that is the start point or the end point of the path is switched, the delay values of both the preceding path and the subsequent path of the flip-flop change with the switching. In the prior art, only one stage (later stage) of path delay is considered, and it is difficult to efficiently switch to the optimum flip-flop and design an LSI.

  In addition, as a means for reducing power consumption, lowering power consumption by reducing the driving power of cells other than flip-flops is the consumption per cell as compared to flip-flops that are always operated by a clock signal. Since the amount of power reduction is small, it is necessary to reduce the driving force of many cells.

  Furthermore, even when the cell driving force is changed during placement and routing, a design method with a small number of design steps is desirable.

  An object of the present invention is to solve the above-mentioned problems of the prior art and provide a design method capable of providing a layout / mounting pattern switched to a low power consumption flip-flop while considering a target machine cycle (or delay). It is in.

  Another object of the present invention is to provide an efficient semiconductor integrated circuit design method that is highly accurate and reduces the occurrence of design reversal even when the cell driving force is changed during placement and routing.

  According to the present invention, the object is a method for mounting and designing a semiconductor integrated circuit having a plurality of types of flip-flops using a computer, which has the same logical function but different power consumption and delay characteristics. A step of fetching data related to a flip-flop group including a plurality of types of flip-flops, and a path delay calculation of both the preceding path from the target flip-flop of the semiconductor integrated circuit to the preceding flip-flop and the subsequent path to the succeeding flip-flop A two-stage path delay calculation step to be performed; a power consumption calculation step to calculate the power consumption of the preceding-stage path and the subsequent-stage path or its change; and the path delay calculation result and the power consumption calculation result for the flip-flop of interest. Is compared with preset conditions to determine whether the conditions are met. Comparing and determining step, if the condition is satisfied, the flip-flop is adopted, and if the target flip-flop does not satisfy the condition, the flip-flop is switched to a new flip-flop held in the storage unit, and the delay calculation and the This is achieved by a semiconductor integrated circuit mounting design method comprising: a flip-flop switching step for performing a power consumption calculation and selecting a flip-flop satisfying the above condition.

  Another object of the present invention is to provide a device for designing and mounting a semiconductor integrated circuit including a plurality of types of flip-flops using a computer, and a plurality of types of flip-flops having the same logical function but different power consumption and delay characteristics. And a two-stage path for calculating path delays of both the path from the target flip-flop of the semiconductor integrated circuit to the preceding flip-flop and the path to the subsequent flip-flop of the semiconductor integrated circuit The delay calculation unit, the power consumption calculation unit for calculating the power consumption of the preceding path and the subsequent path or the change amount thereof, and the flip-flop of interest, the path delay calculation result and the power consumption calculation result are preset. A comparison / determination unit that determines whether the condition is satisfied and When the flip-flop satisfies the condition, the flip-flop is adopted, and when the flip-flop does not satisfy the condition, the delay calculation and the power consumption calculation are performed by switching to a new flip-flop held in the storage unit, This is achieved by a semiconductor integrated circuit mounting design apparatus having a flip-flop switching unit for selecting a flip-flop that satisfies a condition as the target flip-flop.

  According to the present invention, when designing the mounting of a semiconductor integrated circuit, a two-stage path delay calculation is performed, and a layout / switching to a low power consumption flip-flop is performed so as not to deteriorate the target machine cycle (or delay). Provide an implementation pattern. As a result, when designing an LSI, it is possible to provide a semiconductor integrated circuit in which power consumption is reduced by satisfying a target machine cycle by mounting design based on highly accurate delay calculation or power consumption calculation. Furthermore, even when the driving force of the cell is changed at the time of placement and routing, it is possible to provide a highly efficient semiconductor integrated circuit design method that is highly accurate and reduces the occurrence of design reversion.

  As an implementation design method for a semiconductor integrated circuit according to the present invention, an embodiment of power consumption and delay control method by flip-flop switching will be described in detail with reference to the drawings.

  FIG. 1 is a diagram showing a system configuration of a semiconductor integrated circuit mounting design apparatus according to an embodiment of the present invention. FIG. 2 shows a mounting design support program executed in the apparatus of FIG. It is a figure explaining the processing operation of the low-power-consumption flip-flop switching method.

  In FIG. 1, the mounting design apparatus 10 includes a power consumption calculation unit 11, a two-stage path delay calculation unit 12, a comparison determination unit 13, and a flip-flop switching unit 14. The mounting design device 10 is realized by a predetermined program for performing processing operations of each functional unit using a computer having a CPU, a memory, a storage device, and the like.

  The logical information file 111 as a storage device stores logical information data, and the library 112 stores basic cell information (cell type, cell size, terminal position) for layout, and constant information for delay calculation. Is stored. Further, the layout information file 113 stores result information of the placement and routing (cell placement position, wiring pattern, etc.). Reference numeral 114 denotes an input / output unit. The mounting design apparatus 10 includes an input / output control unit, a communication control unit, and the like.

Next, a processing flow of the mounting design apparatus 10 will be described with reference to FIG.
First, as data input, information necessary for mounting design processing of the target semiconductor integrated circuit is input to the memory (storage unit) of the mounting design apparatus 10 from the logic information file 111, the library 112, and the layout information file 113 ( Step 101).
Next, the power consumption calculation unit 11 calculates the power consumption of the target layout pattern, and obtains the power consumed by each cell and the power consumption of the entire semiconductor integrated circuit (step 102).

Further, the two-stage path delay calculation unit 12 calculates all the path delays of the target layout pattern, and obtains the two-stage path delay for each flip-flop (step 103).
Here, the two-stage path delay is a process for obtaining the maximum path delay values of the preceding logic and the succeeding logic for a certain flip-flop, and an example of this processing step will be described with reference to FIG.

  FIG. 3 shows a conceptual diagram of a two-stage path delay. As the target flip-flop (201), for example, the flip-flop having the largest path delay value in the entire target semiconductor integrated circuit is selected. Next, the target flip-flop is replaced with a flip-flop having the same logical function but different power consumption or a different delay characteristic. In this case, since the input capacitance of the replaced flip-flop changes, it affects not only the post-stage path delay but also the pre-stage path delay. Therefore, the maximum path delay values (205 and 206) of the preceding logic (203) and the succeeding logic (204) are calculated for the target flip-flop.

  In FIG. 2, the order of processing of the power consumption calculation (step 102) and the two-stage path delay calculation (step 103) does not matter.

  Next, the comparison determination unit 13 determines a delay violation or power consumption violation from the two-stage path delay calculation result and the power consumption calculation result (step 104).

  First, it is determined from the calculation result of the two-stage path delay whether the preceding and succeeding maximum path delay values (Da and Db) of the cell of interest do not exceed the target delay value.

Target delay value ≥ Da and target delay value ≥ Db (Formula 1)
Further, it is determined from the power consumption calculation result (P) whether the LSI target power consumption value is exceeded.

Target power consumption value ≧ P (Formula 2)
If there is a delay violation or power consumption violation according to the determinations of (Equation 1) and (Equation 2), the flip-flop switching unit 14 performs the flip-flop switching trial (step 105) and subsequent steps.

  Next, using FIG. 4 and FIG. 5, the flip-flop switching trial is performed using the processing of the flip-flop switching unit 14, that is, the results of the power consumption calculation (step 102) and the two-stage path delay calculation (step 103). The process to be performed (step 105) will be described.

  When there are a plurality of flip-flops having the same function but different power consumption or delay characteristics with respect to the target flip-flop, the target flip-flop is selected. On the other hand, if there is no flip-flop having the same function as the target flip-flop, it is excluded from switching (step 301). If it is determined to be switched, the next process (step 302) is performed.

  It is determined whether the switching target is a flip-flop with a sufficient delay (step 302). That is, with respect to the target flip-flop 201 in FIG. 3, when the upstream maximum path delay Da (205) and the downstream maximum path delay Db (206) are smaller than the respective threshold values Dα or Dβ (207 or 208) (equation 3), The flip-flop is set as a candidate for switching as “there is a delay”.

Here, the threshold value Dα or Dβ (207 or 208) is a value calculated based on the target machine cycle. For example, the threshold Dα or Dβ (207 or 208) is a value obtained by subtracting, from the target machine cycle, the predicted delay deterioration when switching to the low-consumption flip-flop. It is a thing.
Da <Dα & Db <Dβ (Formula 3)
If it is determined that there is a margin in the delay, then an attempt to switch the flip-flop is performed (step 303). That is, when the maximum path delay values of the preceding stage and the subsequent stage satisfy (Equation 3), the target cell is replaced with a low-consumption flip-flop.

  On the other hand, if it is determined in step 301 that the switching process is not to be performed or it is determined in step 302 that there is no delay, the process proceeds to the next flip-flop, and the process proceeds to step 104 in FIG.

  Further, power consumption and delay are recalculated after the switching trial process (step 106).

  The two-stage path delay calculation is performed again only for the front-stage and rear-stage paths of the flip-flop that has been switched. In addition, a change in power consumption of the flip-flop that has been switched is calculated.

  For example, as shown in FIG. 8, in the switching of the target flip-flop (801) between the front-stage flip-flop (800) and the rear-stage flip-flop (802), consider a case where the driving power is increased by switching to the one with a large boost. In general, when the boost is increased, the path delay decreases, but the power consumption increases and the cell size also increases. Therefore, when the driving force of the target flip-flop (801) is increased, the micropath delay 2 (806) between the target flip-flop and the cell (804) is improved, and the subsequent maximum path delay (808) can be improved. .

  On the other hand, by raising the driving force of the target flip-flop, the micropath delay 1 (805) between the target flip-flop and the cell (803) also changes. For example, since the input capacity of the target flip-flop changes due to the switching of the driving force, the load capacity as viewed from the output terminal side of the cell (803) changes, and as a result, the micropath delay 1 changes.

  In the prior art, only one of the maximum path delay of the subsequent stage or the previous stage is considered, and it is difficult to realize the optimum switching of the driving force of the flip-flop. In the present invention, in order to consider the change in the load capacity, the maximum path delay of the two stages (the rear stage and the front stage) accompanying the switching is calculated and adopted. In addition to the case where the maximum path delay accompanying switching is improved in both of the two stages, for example, it is conceivable that if one of the two stages is improved and the other deteriorates, the worse is within the target.

  That is, it is determined whether or not to adopt the switching trial result from the result of recalculation (step 107).

Here, when it is determined that any one of the following three conditions is satisfied, switching is adopted (step 108).
(A) When (Expression 1) and (Expression 4) are satisfied (b) When (Expression 2) and (Expression 5) are satisfied (c) When (Expression 6) is satisfied
Pnew ≦ P (Formula 4)
DaNew ≦ Da and DbNew ≦ Db (Formula 5)
Pnew ≤ P and
DaNew ≦ Da and DbNew ≦ Db (Formula 6)
Here, P is the power consumption value before switching, Pnew is the power consumption value after switching, Da is the previous maximum path delay value before switching, DaNew is the previous maximum path delay value after switching, and Da is the maximum after the switching. The path delay value, DaNew, indicates the maximum post-path delay value after switching.

  When it is determined that the switching trial result is adopted, flip-flop switching is adopted (step 108).

  When flip-flop switching is adopted, the information on the target flip-flop is updated to the information on the flip-flop after switching.

  Steps 104 to 108 are repeated until there is no power consumption violation and no delay violation or all flip-flops of the LSI (step 116).

On the other hand, in step 104, there is no delay violation or power consumption violation for the entire LSI (Equations 1 and 2 are satisfied), or the processing of steps 104 to 108 is completed for all flip-flops of the LSI. If so, the data is output (step 109) and the process is terminated (step 110). In the data output (step 109), the flip-flop information after switching is output to the logical file (114), and the layout information file (115) is updated when the layout is changed.
With the above processing, it is possible to reduce the power consumption of the LSI in consideration of the delay. In other words, when designing a semiconductor integrated circuit, a two-stage path delay calculation is performed, and the target machine cycle (or delay) is considered so as not to deteriorate. It is possible to effectively reduce the power consumption of the LSI without causing a reversion in the flow.

  As another embodiment of the present invention, an example in which a processing method is set first will be described. First, an embodiment of the present invention when designing an LSI having a high target machine cycle value and sufficient target power consumption will be described with reference to FIG.

  In FIG. 9, after inputting necessary data (step 101), the processing method is set (step 122). For example, high-speed flip-flops are set as initial values for all flip-flops. Alternatively, instead of setting the processing method, when inputting data (step 101), a logical file (111) using high-speed flip-flops in which all flip-flops have a high boost delay characteristic may be input.

  Thereafter, processing similar to the processing flow shown in FIG. 2 (steps 104 to 116) is performed, and in the flip-flop switching trial (step 105), flip-flops having a sufficient delay are replaced with low-power consumption flip-flops. . By reducing the power consumption of each flip-flop in this way, a high-speed LSI can be designed in consideration of the power consumption.

  Further, in the setting of the processing method in step 122, low boost or low power consumption flip-flops may be set as initial values for all flip-flops, and then the same flow as in FIG. 2 may be performed. According to this method, it is possible to design an LSI that realizes a strict target power consumption value. Alternatively, instead of setting the processing method, data of a low booster or low power consumption flip-flop may be input to all flip-flops.

  As another embodiment, a different type of logical file, for example, a logical file using a high-speed flip-flop having a high boost delay characteristic, or a low boost or low power consumption flip-flop is used as the logical file (111). A plurality of used logical files may be prepared in advance. Then, in setting the processing method (step 122 in FIG. 9), the user may be able to appropriately select the target logical file as an initial value according to the design conditions.

  Next, as another embodiment of the present invention, for example, a part of the flip-flop group of the semiconductor integrated circuit in which the optimum design has already been completed may be designated in advance so as not to perform switching. it can. In other words, when switching flip-flops according to the criterion, a flip-flop that is not switched is designated from the outside, and switching is not performed for the designated flip-flop. An example of this method will be described with reference to FIGS.

  At the time of data input in FIG. 2 (step 101) or setting of the processing method in FIG. 9 (step 122), a flip-flop not to be switched is designated from the outside. FIG. 5 shows an example of a designation method. A unique name (instance name) (401) of a flip-flop that does not perform switching or an output signal name (403) of a flip-flop that does not perform switching is described in a file. There is a way to input the file. It is also possible to specify the instance name or signal name hierarchically including the logical block to which each belongs (402, 404). Here, the “separation” between the logical block and the instance can be described using an arbitrary symbol such as “space, described by Δ in FIG. 5”, “/”, “:”. Furthermore, it is also possible to designate a logical block name and make all flip-flops belonging to the logical block non-switching flip-flops (405). The designation methods shown in FIG. 5 can be designated in combination.

  After the data input (step 101), the processing flow shown in FIG. 2 is performed. When the flip-flop of interest is a flip-flop that does not perform the externally designated switching when the flip-flop switching is attempted (step 105), the subsequent processing ( Steps 105-108) are skipped.

  In the same manner, it is also possible to designate a flip-flop to be switched from the outside and switch only the designated flip-flop.

  With the above processing, it is possible to realize power consumption and delay control by switching a specific logic in the LSI or a specific range of flip-flops.

  As another embodiment of the present invention, a flip-flop group having the same cell size as a processing method may be employed, or a flip-flop group having a different cell size as another processing method may be employed. . Which processing method is to be used may be specified as the initial value setting in, for example, step 122 of setting the processing method in FIG.

  With respect to this embodiment, FIG. 6 shows a method for designing a semiconductor integrated circuit employing flip-flop groups having the same cell size in comparison with a method employing flip-flop groups having different cell sizes. In the former design method, flip-flop switching can be performed before and after the placement (502) and the wiring (504) as indicated by the solid line (501, 503, 505). Here, all of the three flip-flop switching processes in FIG. When the present invention is implemented in the layout design process, the delay calculation is performed using the actual layout pattern (placement and wiring result) as the processing process proceeds, and therefore, a highly accurate switching process using the actual delay value is performed. (503, 505).

  On the other hand, even in the case of a system employing flip-flop groups with different cell sizes, the logical function is switched to the same cell after placement or wiring. In this case, as indicated by a broken line in FIG. 6, a backtrack occurs due to re-arrangement or wiring.

  With reference to FIG. 7, the relationship between the layout design by the above two methods and the backward man-hours will be compared and explained. The left column of FIG. 7 shows a case where flip-flops having different cell sizes are adopted, and the right column shows a case where flip-flops having the same cell size are adopted.

  Use flip-flop groups with the same cell size, that is, (1) the same logical function, (2) different power consumption and delay characteristics, and (3) multiple types of flip-flops with the same size (4) By using flip-flop groups in which the patterns in the cells are different, but the terminal positions serving as connection points with the inter-cell wiring and the cell wiring-prohibited areas are the same, the number of reversing steps increases. Can be solved. That is, since the cell size before and after switching is the same, there is no overlap with other cells after switching, and there is no need to change the wiring pattern because the terminal positions and prohibited areas related to wiring are the same, so that the layout There is a great advantage that no backtracking occurs.

  The present invention can also be applied to the case where flip-flops having different cell sizes are employed. When the flip-flop switching is performed after wiring by the method of the present invention, the calculation accuracy increases. In other words, (1) flip-flop groups having the same logical function and (2) different power consumption and delay characteristics need to be re-arranged and rewired. High switching processing can be performed. However, when flip-flops with different cell sizes are used, for example, when the target flip-flop with delay violation is switched to a high-speed high-speed flip-flop, the size of the flip-flop generally increases, and other adjacent cells Overlap occurs. Also, the terminal position in the flip-flop and the cell wiring prohibition region change. In other words, if flip-flop switching using highly accurate delay calculation or power consumption calculation is performed, layout rework occurs, and the number of steps for returning increases.

It is a figure which shows the system configuration | structure of the mounting design support apparatus of the semiconductor integrated circuit which becomes one Example of this invention. It is a flowchart explaining the processing flow of the mounting design support apparatus by one Example of this invention, ie, the processing flow from data input to low power consumption flip-flop switching. It is a figure explaining the concept of two-stage path delay in one Example of this invention. 3 is a flowchart for explaining a flip-flop switching trial process in the processing flow of FIG. 2. It is a figure explaining the designation | designated method of the flip-flop which does not implement switching from the outside as another Example of this invention. It is a flowchart explaining an example at the time of implementing this invention within the processing flow of a layout (placement wiring) design. It is a figure which compares and demonstrates the relationship between the layout design which employ | adopted this invention, and the backtracking man-hour. It is a figure explaining the effect of this invention regarding switching of a flip-flop. It is a figure explaining the processing flow of the example which sets a processing system first as another Example of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Mounting design apparatus, 11 ... Power consumption calculation part, 12 ... Two-stage path delay calculation part, 13 ... Comparison determination part, 14 ... Flip-flop switching part, 111 ... Logic information file, 112 ... Library, 113 ... Layout information file , 114 ... input / output unit, 200 ... flip-flop, 201 ... flip-flop, 202 ... flip-flop, 203 ... previous stage logic group, 204 ... latter stage logic group, 205 ... previous stage maximum path delay, 206 ... rear stage maximum path delay, 207 ... Pre-stage path delay threshold, 208...

Claims (7)

A method of mounting design of a semiconductor integrated circuit having a plurality of types of flip-flops using a computer,
Holding data on flip-flop groups including a plurality of types of flip-flops having the same logical function and different power consumption and delay characteristics in a storage unit;
A two-stage path delay calculation step for calculating path delays of both the preceding path from the target flip-flop of the semiconductor integrated circuit to the preceding flip-flop and the succeeding path to the succeeding flip-flop;
A power consumption calculating step for calculating the power consumption of the preceding path and the subsequent path or a change amount thereof, and
A comparison determination step for comparing the result of the path delay calculation and the calculation result of the power consumption with a preset condition with respect to the flip-flop of interest, and determining whether the condition is satisfied,
When the condition is satisfied, the flip-flop is used. When the target flip-flop does not satisfy the condition, the flip-flop is switched to a new flip-flop held in the storage unit to perform the delay calculation and the power consumption calculation. And a flip-flop switching step for selecting a flip-flop that satisfies the above condition. In claim 1,
A step of setting a high-speed flip-flop having a high boost delay characteristic as an initial value for all flip-flops;
Using the result of the two-stage path delay calculation based on the initial value for the flip-flop of interest, switching to a flip-flop having a low boost delay characteristic or a low-power consumption flip-flop, the front-stage path delay, the rear-stage path delay, and the power consumption Calculating the change,
The calculation result is compared with a reference value of path delay or power consumption, and if there is a margin with respect to the reference value, the target flip-flop is switched to a flip-flop having a low boost delay characteristic or a low power consumption flip-flop. And a mounting design method for a semiconductor integrated circuit. In claim 1,
Setting low power consumption or low driving power flip-flops as initial values for all flip-flops;
Calculating the two-stage path delay of the flip-flop of interest;
Using the result of the two-stage path delay calculation, if there is a margin for the above condition, the front-stage path delay, the rear-stage path delay, and the power consumption change by switching the flip-flop of interest to a flip-flop having a high boost delay characteristic Calculating the minutes;
Comparing the calculation result with the condition of path delay or power consumption, and switching the target flip-flop to a flip-flop having a delay characteristic of high boost when there is a margin with respect to the condition. A mounting design method for a semiconductor integrated circuit. In claim 1,
Among the plurality of types of flip-flops of the semiconductor integrated circuit, a flip-flop that does not perform the switching is designated in advance,
A method for designing and designing a semiconductor integrated circuit, wherein the designated flip-flop is excluded from the switching target, only the non-designated flip-flop is subjected to the comparison determination, and switching is performed according to the result. In an apparatus for designing a semiconductor integrated circuit including a plurality of types of flip-flops using a computer,
A storage unit for storing data relating to a flip-flop group including a plurality of types of flip-flops having the same logical function and different power consumption and delay characteristics;
A two-stage path delay calculation unit that performs path delay calculations for both the path from the target flip-flop of the semiconductor integrated circuit to the preceding flip-flop and the path to the subsequent flip-flop;
A power consumption calculation unit for calculating the power consumption of the preceding path and the subsequent path or a change amount thereof, and
A comparison determination unit that compares the result of the path delay calculation and the calculation result of the power consumption with a preset condition with respect to the target flip-flop, and determines whether the condition is satisfied,
When the target flip-flop satisfies the condition, the flip-flop is adopted. When the condition is not satisfied, the flip-flop is switched to a new flip-flop held in the storage unit to perform the delay calculation and the power consumption calculation. And a flip-flop switching unit for selecting a flip-flop satisfying the condition as the target flip-flop. In a semiconductor integrated circuit mounting design method,
There are multiple types of flip-flops with the same logical function, different power consumption and delay characteristics, and the same cell size, and the pattern in each cell is different, but the connection point with the inter-cell wiring Using the flip-flop group in which the terminal location and the cell wiring prohibition region are the same,
Calculate the two-stage path delay of the flip-flop of interest,
Using the result of the two-stage path delay calculation, calculate the former stage path delay, the latter stage path delay, and the change in power consumption by switching the flip-flop,
A mounting design method for a semiconductor integrated circuit, wherein the target flip-flop is switched so that the path delay calculation result and the power consumption calculation result are compared with a preset condition and the condition is satisfied. A semiconductor integrated circuit mounting design support program comprising:
The semiconductor integrated circuit includes a plurality of types of flip-flops,
On the computer,
A two-stage path delay calculation function for calculating path delays of both the path from the target flip-flop of the semiconductor integrated circuit to the preceding flip-flop and the path to the subsequent flip-flop;
A power consumption calculation function for calculating the power consumption of the preceding path and the subsequent path or a change amount thereof, and
A comparison determination function for comparing the result of the path delay calculation and the calculation result of the power consumption with a preset condition with respect to the flip-flop of interest, and determining whether the condition is satisfied,
If the target flip-flop satisfies the condition, the flip-flop is used. If the target flip-flop does not satisfy the condition, a plurality of types of flip-flops having the same logical function and different power consumption and delay characteristics are stored in the storage unit. A flip-flop switching function for selecting the flip-flop satisfying the condition as the flip-flop of interest by switching to a new flip-flop of the above and performing the delay calculation and the power consumption calculation Integrated circuit packaging design support program.

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