JP2005182263A - Controller with memory test function and computer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a controller with a memory test function and a computer mounted with the controller for normally maintaining picture display on the display monitor of the computer, and for easily and precisely performing memory tests in all the regions of a main memory mounted on the computer. <P>SOLUTION: A controller 2 having a memory test function and mounted on a computer 1 is provided with: a memory testing means 10 for testing a main memory 5 by generating a test pattern for memory test and a memory access signal; a test display memory 11 for storing data for picture display during the memory test; and a switching means 12 for transmitting the memory access signal from the memory testing means 10 to the main memory 5 when the memory test is performed, transmitting the memory access signal from a memory control means 9 to the test display memory 11, and switching the memory access signal from the memory control means 9 to the main memory 5 when the memory test is not performed. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a controller with a memory test function and a computer on which the controller is mounted, and in particular, a complex memory test is performed on the entire area of the main memory while the main memory mounted on the computer is mounted on the computer. The present invention relates to the controller and the computer.

  Computers such as personal computers (hereinafter referred to as personal computers) and servers that have become popular in recent years have become enormous in the memory capacity of main memories mounted on such computers in order to improve effective performance. Therefore, simplicity, reliability, and shortening of the memory test for the entire main memory area in the main memory mounted state similar to the computer product shipment form or the actual product use form have become important.

  In a conventional computer that does not have special hardware for performing a memory test of the main memory in the computer itself, for example, after a predetermined initialization of the computer at the time of power-on or restart of the computer, it is generally MSCAN. A predetermined memory test called (Memory Scan) is performed by the CPU in the computer. In this MSCAN, for example, when the CPU writes all “0” data in the address unit of the main memory, the data is read and collation matching confirmation between the original data and the read data is performed for all address areas. "Similarly, it is performed by data, and the entire memory area of the main memory can be tested in a short time with a simple test pattern.

  However, in such MSCAN, for example, it is difficult to detect with a simple test pattern such as all “0” or all “1”, that is, a memory failure (or memory operation failure) having test pattern dependency cannot be detected. There is. Therefore, when trying to perform a memory test by generating a complex test pattern that can be detected even if such a memory failure occurs, the execution time of the memory test depends on the effective processing performance of the computer, and the memory test takes a lot of time. Problem arises.

  In addition, before mounting (or inserting) the main memory (memory chip, memory unit, memory module, etc.) on a computer board such as a motherboard, the main memory alone is subjected to a detailed memory test with a dedicated memory test device, etc. There is also a method of mounting a main memory that is free of defects on the computer board based on the test results, but in such a method, on the signal line that appears in the actual use form when the main memory is mounted on the computer board Reduced reliability of computer products due to difficulty in detecting malfunctions in main memory caused by reflection, crosstalk, power supply voltage fluctuations, etc. There is a problem that it may become.

  In order to solve such a problem, when a test circuit dedicated to memory test is provided in front of the memory board and the memory test is performed, data sent to the memory board, memory access signals, etc. are generated by the test circuit. When the data pattern generated by the test circuit is written to the memory and read out and the data is collated and confirmed in the entire memory area, the memory test is performed independently from the central processor. Yes (see, for example, Patent Document 1).

  When such a technique is applied to a recent personal computer, a configuration as shown in FIG. 5 can be easily considered. FIG. 5 shows a block diagram of a conventional computer configuration limited to at least the components related to the memory test.

  In FIG. 5, a computer 81 includes a CPU 83, video display processing means 84 for displaying a screen on a display monitor, a main memory 85 in which a part of a memory area is shared by an image memory 86 for screen display, and a predetermined BIOS. A ROM (Basic Input / Output System-ROM) 93, and a controller chip 82 with a memory test function, which is a controller that the CPU 83 controls to transmit / receive predetermined data to / from the main memory 85, the video display processing means 84, etc. It is the composition provided.

  The controller chip 82 has a function of a chip set generally called a North Bridge mounted on a recent ordinary personal computer or the like. Further, sharing the image memory 86 with a part of the area of the main memory 85 tends to be found in recent personal computer configurations because of advantages such as simplification of circuit configuration and cost reduction.

  The controller chip 82 includes a memory provided in a normal north bridge such as an image processing unit 88 for transmitting / receiving data to / from the video display processing unit 84 and a memory control unit 89 for generating a predetermined memory access signal. Memory test means 90 for performing a memory test by generating a test pattern for test or a predetermined memory access signal, and switching for switching the output of the memory control means 89 and the output of the memory test means 90 to the main memory 85 Means 92.

When the memory test of the main memory 85 is performed, the switching unit 92 switches the memory access signal including the memory address and data output from the memory testing unit 90 to be sent to the main memory 85, and the memory testing unit 90 generates. When complex test pattern data is written into the main memory 85, the memory test is performed by confirming the collation with the data read from the same memory address and repeating the same over the entire memory area. When the memory test is not performed, the switching unit 92 switches the memory access signal from the memory control unit 89 to be sent to the main memory 85, and performs normal operation (for example, a commercial application installed in the computer).・ The use form of software etc.) is made possible.
Japanese Patent Laid-Open No. 5-210598

  However, in the conventional technique of FIG. 5 described above, the main memory is partly used as an image memory for screen display of the display monitor, so that the memory test target area in the memory test operation is the image. When the memory area is reached, the display image data already stored in the image memory area is rewritten with the test pattern data, resulting in a problem such as an abnormal screen display on the display monitor. .

  In addition, since a computer usually allocates and executes a program use area for BIOS-ROM data and an execution program in the main memory, when the target area of the memory test reaches the program use area, it is already in the program use area. The program data stored in the computer may be rewritten by the test pattern data, causing the computer to malfunction. However, to avoid such a problem, the program usage area cannot perform memory tests. There is.

  Therefore, the present invention can normally maintain the screen display of the computer operating state on the display monitor installed in the computer, and can easily and in detail test the entire area of the main memory mounted in the computer. An object is to provide a controller with a memory test function and a computer with a memory test function.

  FIG. 1 is a principle block diagram of the present invention. Hereinafter, a description will be given with reference to FIG. FIG. 1 is a diagram showing the configuration of a computer, but it does not cover all the components necessary for functioning as a normal computer, and is a diagram limited to components related to the present invention for convenience of explanation. It is.

  The controller 2 with a memory test function of the first invention includes a CPU 3, video display processing means 4 for displaying a screen on a display monitor (display such as CRT or liquid crystal), and an image memory 6 for displaying a part of the memory area on the screen. Connection interfaces 7-1, 7-2, and 7-3 connected to the main memory 5 shared by the image processing means 8 for transmitting data to the video display processing means 4 and a memory access signal. A memory control means 9; and a memory test means 10 for generating a test pattern for memory test and a memory access signal to test the main memory 5. The CPU 3, the main memory 5 and the video display processing means 4 It is controlled so that data can be transmitted and received and a memory test of the main memory 5 can be performed. It is intended to be.

  The controller 2 further includes a test display memory 11 for holding data for screen display of the memory test, and the memory access including the test pattern data from the memory test means 10 when the memory test is performed. A signal is sent to the main memory 5, and the memory access signal from the memory control means 9 is sent to the test display memory 11. When the memory test is not performed, the memory from the memory control means 9 is sent. The access signal is configured to include switching means 12 for switching so that the access signal is sent to the main memory 5.

  The controller 2 with a memory test function according to the second invention comprises a CPU 3, a video display processing means 4 for displaying a screen on the display monitor, a main memory 5 in which a part of a memory area is shared by an image memory for screen display, and A connection interface connected to a test display memory 11 for holding data for screen display during a test of the main memory 5, an image processing means 8 for sending data to the video display processing means 4, and a memory access signal And a memory test means 10 for generating a memory test test pattern and a memory access signal to test the main memory 5, and the CPU 3, the main memory 5 and the video display process. Control is performed so that the means 4 can transmit and receive data, and a memory test of the main memory 5 can be performed. It is those, in which is mounted on, for example, a computer 1.

  Further, when performing the memory test, the controller 2 sends the memory access signal including the test pattern data from the memory test means 10 to the main memory 5 and also sends the memory access signal from the memory control means 9. A switching means 12 for sending a memory access signal to the test display memory 11 and switching the memory access signal from the memory control means 9 to be sent to the main memory 5 when the memory test is not performed. It is set as the structure provided.

  The computer 1 of the third invention comprises a CPU 3, a video display processing means 4 for displaying a screen on the display monitor, a main memory 5 in which a part of a memory area is shared by an image memory 6 for screen display, The computer 1 having the activation ROM 13 is configured to include the controller 2 with a memory test function according to the first invention.

  The computer 1 of the fourth invention comprises a CPU 3, a video display processing means 4 for displaying the screen on the display monitor, a main memory 5 in which a part of the memory area is shared by the image memory 6 for screen display, A computer 1 having a startup ROM 13 and a test display memory 11 for holding data for screen display during a test of the main memory 5 is configured to include the controller 2 with a memory test function of the second invention. .

  According to the first invention, the second invention, the third invention, and the fourth invention, the data for the screen display on the display monitor in the case of the memory test is the same as when the normal operation of the computer is used. Is not held in a part of the main memory (image memory area), but is held in a separate test display memory that is a physical space different from the main memory. It is possible to avoid the data being rewritten by the test pattern data and to prevent the screen display on the display monitor from becoming abnormal.

  A computer 1 according to a fifth aspect of the present invention is the computer 1 with a memory test function according to the third aspect or the fourth aspect of the present invention, wherein a program necessary for testing the main memory 5 is stored in the basic boot ROM 13.

  According to the fifth aspect of the present invention, since all the programs necessary for executing the memory test are stored in the basic boot ROM (BIOS-ROM) and the main memory does not need to be accessed as the program use area, the main memory It can be avoided that the program data stored in the memory is rewritten by the test pattern data.

  According to the present invention, when the memory test of the main memory is performed, the data for screen display on the display monitor is held in a separate test display memory in a physical space different from the main memory, and the test pattern from the memory test means -Since the entire address area of the main memory can be tested by data, the screen display of the computer operating status on the standard display monitor equipped with the computer (or optional) can be maintained normally. The entire memory area of the mounted main memory can be easily and in detail tested.

  Therefore, a detailed memory test can be performed in the product shipment form or customer use form (maximum implementation of main memory, etc.) in which the main memory is mounted on the computer without using a special external device for the memory test. become. This means that the memory test can be performed under the same conditions as when the computer is used by the customer, and the memory test at the time of computer product shipment and the incidental work can be simplified. This has the effect of reducing investment, shortening product shipping time, and reducing manufacturing costs.

  The purpose of the memory test operation is to maintain the normal display of the computer operating status on the display monitor installed in the computer, and to perform a detailed memory test on all address areas of the main memory mounted on the computer. This was realized by providing a small-capacity test display memory independent of the main memory as a display data storage area.

  Embodiments of the present invention will be described below with reference to the drawings. FIG. 2 is a diagram showing the configuration of the computer with a memory test function according to the first embodiment of the present invention, and FIG. 4 is a flowchart showing the processing of the present invention. For convenience of explanation, the portions not directly related to the present invention are omitted here, and the configuration of the computer of FIG. 2 is a configuration diagram limited to at least the components directly related to the memory test operation according to the present invention. The other predetermined components required for configuring the computer are omitted. Similarly in FIG. 4, description of processing not directly related to the present invention is omitted.

  In FIG. 2, a computer 1 with a memory test function such as a personal computer or a server includes a CPU 3 and a controller chip 22a with a memory test function that is directly or indirectly controlled by the CPU 3 (corresponding to the controller 2 with a memory test function) The video display processing unit 24, a predetermined main memory 5 that shares a part of the memory area with the image memory, a BIOS-ROM 33, and the like are connected by predetermined connection interfaces 7-1, 7-2, and 7-3. Has been.

  The video display processing unit 24 has a configuration or function equivalent to or equivalent to a video card generally called an AGP (Accelerated Graphics Port) video card, and includes a display monitor (not shown) for screen display connected to the video card. It is a waste. The display monitor is preferably provided as a standard equipment at the time of shipment of the computer 1, but may be optionally provided as a retrofit.

  In the BIOS-ROM 33, in addition to predetermined storage data (such as computer initialization information) of a BIOS-ROM provided in a normal computer, setup information and various memory tests of the memory test unit 30 are provided as programs for a memory test operation. And a test display processing program for realizing a human interface using a test display memory 31a and an input unit (not shown) such as a keyboard and a mouse. Moreover, when the computer 1 starts up in the memory test mode, programs and data necessary for the operation of the computer 1 are not expanded on the main memory 5, and instead, the CPU 3 processes with the BIOS-ROM 33. It is incorporated as possible. Therefore, in the case of the memory test operation, the CPU 3 never accesses the main memory 5 for the program operation, and the access to the BIOS-ROM 33 is restricted.

  The controller chip 22a with a memory test function basically has a function or configuration equivalent to or equivalent to a chip set generally called a north bridge as a function or configuration for a normal operation other than a memory test operation. For example, the image processing unit 28, the memory control unit 29, and the like correspond to some of them.

  The memory test unit 30 included in the controller chip 22a with a memory test function generates various complex test pattern data for performing a memory test on the main memory 5 using a DRAM (Dynamic Random Access Memory) or the like. A predetermined memory access signal for accessing the main memory 5 is generated by the test pattern data. The memory test unit 30 preferably has a function equivalent to or more than that of a pattern generation circuit generally called an ALPG (Algorithmic Pattern Generator) that can generate various complex predetermined test pattern data for memory tests.

  Further, the memory test unit 30 includes one or more input / output registers (not shown), and the CPU 3 exchanges various information with the memory test unit 30 and executes instructions based on various input designation conditions via the input / output registers. And so on.

  The test display memory 31a stores data for screen display to be displayed on the display monitor during the memory test operation, and corresponds to the image memory 6 in the main memory 5 area used during normal operation. Is. Since the test display memory 31a is used exclusively for the memory test, its memory capacity can be made smaller than that of the image memory 6 area. For example, if the display quality of the screen display during the memory test operation is not questioned, it is possible to reduce the capacity by setting the screen resolution to a lower resolution than during normal operation, and to reduce the number of display colors to be reproduced. If it is limited to monochrome, the capacity can be further reduced.

  As an example, when the screen display is limited to monochrome and the screen resolution is set to a width of 640 × height of 480 pixels, a memory capacity of about 38 KB is sufficient. Such a reduction in the capacity of the test display memory 31a is advantageous, for example, by reducing the total number of gates at the time of chipset development and manufacture of the controller chip 22a with a memory test function.

  The image processing unit 28 has a configuration or function equivalent to or equivalent to a controller generally called an AGP controller in the north bridge, and directly or functions with the CPU 3, the video display processing unit 24, the memory control unit 29, and the like. Are connected to each other to enable screen display on a display monitor based on image data in the image memory 6 and the test display memory 31a.

  The memory control unit 29 is provided in the north bridge and has a controller function generally called a DRAM controller for controlling access to the main memory. The memory control unit 29 is directly or functionally connected to the CPU 3 and other components that need to exchange memory information. Are connected to each other, and a predetermined memory access signal is generated to control access to the main memory 5 and the test display memory 31a.

  The test mode register 34 is an operation mode in the computer 1, that is, a memory test mode (for example, logical value “1”) when performing a memory test operation, and a normal operation by application software or the like. A normal operation mode (for example, logical value “0”) is set by the CPU 3, and this output is supplied to the first switching unit 32-1 and the second switching unit 32-2.

  The first switching unit 32-1 exchanges the memory access signal of the memory control unit 29 on the input side with the test display memory 31a side in the memory test mode, and on the other hand, the main memory 5 in the normal operation mode. The output side is switched so that it can be performed on the side (that is, the second switching unit 32-2 side). The second switching unit 32-2 exchanges the memory access signal with the main memory 5 on the output side in the memory test mode, and controls the memory in the normal operation mode. The input side is switched so that it can be performed on the unit 29 side (that is, on the first switching unit 32-1 side).

  As described above, here, for example, a controller chip normally paired with the north bridge, and various peripheral devices connected by PCI (Peripheral Component Interconnect), USB (Universal Serial Bus), etc. A controller chip called a South Bridge (SouthBridge) or a component circuit corresponding to the controller chip and various peripheral devices connected to various parts are omitted.

  Next, processing of the computer 1 with a memory test function of the present invention will be described with reference to the flowchart shown in FIG.

  When the power of the computer 1 is turned on, for example, the CPU 3 sets a specific bit of the Test mode register 34 (the definition bit of the memory test operation / normal operation mode, here, the memory test mode is set to the logical value “1”). Initialization is performed by writing a logical value “0” or by hardware clear (“0” value) by system reset at power-on, etc., and set to a normal operation mode (S1).

  In the process of starting up the computer 1 after the power of the computer 1 is turned on, for example, in the Windows (registered trademark) OS (Operating System) of Microsoft Corporation, function keys (“ There is a slight time interval during which the key press such as the “F2” key is valid, but a switch designation key for shifting to the memory test mode during this period, for example, any of the function keys that are not currently used Such a key is defined as a switching designation key, and it is monitored whether or not the switching designation key is pressed (S2). Note that there may be a plurality of switching designation keys. In this case, for example, simultaneous pressing of these keys is monitored.

  If it is recognized in step S2 that the switch designation key has been pressed (Yes determination), the computer 1 operates as a memory test mode, initializes the computer 1 according to the data in the BIOS-ROM 33 (S3), and further tests the test mode register. A logical value “1” is written in the 34 specific bits, and the memory test mode is set (S4).

  As the test mode register 34 is set to the memory test mode, the output side of the first switching unit 32-1 is the test display memory 31a side, and the input side of the second switching unit 32-2 is the memory test. Switching is performed so that the unit 30 side becomes effective (S5). Next, as a pre-operation preparation of the memory test unit 30, the CPU 3 initializes the input / output register of the memory test unit 30 (S6).

  The data developed for screen display based on the initialized information of the input / output register is stored in the test display memory 31a via the memory control unit 29 and the first switching unit 32-1 (S7). The data stored in the test display memory 31a is transferred to the display monitor via the first switching unit 32-1, the memory control unit 29, the image processing unit 28, and the video display processing unit 24. Display (S8).

  Usually, the operator of the computer 1 who is a person who performs the memory test performs various settings (test pattern settings, etc.) necessary for performing the memory test based on the contents displayed on the display monitor. The operation is performed by operating an input unit (not shown) such as a keyboard or a mouse. The CPU 3 monitors whether or not various inputs are designated for the memory test by the input unit (S9).

  If it is recognized in the step S9 that there is an input designation (Yes determination), then it is confirmed whether or not there is a memory test execution designation in the input designation (cancellation designation) (S10) When the designation is recognized (Yes determination), the input / output register of the memory test unit 30 is set based on various input designation conditions (S11). Based on the setting, the memory test unit 30 starts a memory test operation (S12).

  Test pattern data sequentially generated by the memory test unit 30 based on the set conditions and a memory access signal generated in response thereto are supplied to the main memory 5 via the second switching unit 32-2, and the main memory 5 The memory test is performed (S13).

  Whether or not the designated memory test is completed is monitored (S14), and the memory test is performed until the memory test is completed. Although not shown in the drawing, the memory test ends when the memory test of the memory area based on the designation has been completed or when a failure that prevents the memory test from being continued is detected. .

  When the end of the memory test is recognized in step S14 (Yes determination), the information of the input / output register of the memory test unit 30 is expanded, and the memory control unit 29 and the first switching unit 32-1 are And stored in the test display memory 31a (S15). The stored data in the test display memory 31a is transferred to the display monitor via the first switching unit 32-1, the memory control unit 29, the image processing unit 28, and the video display processing unit 24. Displayed (S16).

  Based on the memory test results displayed on the display monitor, the operator conducts new memory tests as needed, for further analysis of the memory test results or for memory tests under different conditions. In the case of making it, various settings necessary for this are performed again by operating the input unit. Subsequent processing returns to step S9 and is processed in the same manner as described above.

  If it is recognized in step S10 that the memory test execution designation has been rejected (cancellation designation) (No determination), it is determined that the memory test has been stopped and the process returns to step S1 to be processed.

  If it is not recognized in step S2 that the switch designation key has been pressed (No determination), the computer 1 is operated in the normal operation mode, and the predetermined contents of the BIOS-ROM 33 are expanded on the main memory 5 ( S20). Thereafter, the computer 1 is initialized in accordance with the BIOS data expanded on the main memory 5 (S21).

  Next, the CPU 3 performs a memory test on the main memory 5 with the predetermined MSCAN (S22), and if there is no abnormality, starts the OS as predetermined (S23).

  With the configuration and processing as described above, the screen display of the computer operating status on the display monitor that is standard (or optional) installed in the computer is maintained normally with the main memory installed in the computer. Thus, the memory test can be performed in detail for all the address areas of the main memory. Therefore, a detailed memory test can be performed only by the computer itself in the configuration of the product shipment form in which the main memory is mounted on the computer.

  Note that the flowchart shown in FIG. 4 is an example for explaining a flow of processing steps suitable for the computer 1 with a memory test function of the present invention to achieve the object, and is not fixed to this. Therefore, if the object of the present invention can be achieved, the contents of processing steps, the order of flow, etc. may be changed.

  FIG. 3 is a diagram showing a configuration of a computer with a memory test function according to the second embodiment of the present invention. As in the first embodiment, the portions not directly related to the present invention are here also for convenience of explanation. Shall be omitted.

  In FIG. 3, the configuration is the same as that of the computer with the memory test function of the first embodiment shown in FIG. 2 except that the test display memory 31b is provided outside the controller chip 22b with the memory test function. Therefore, in FIG. 3, those given the same reference numerals as those in FIG. 2 are the same as those in FIG. 2, and therefore their explanation is omitted here.

  Similar to the test display memory 31a of the first embodiment, the test display memory 31b stores data for screen display to be displayed on the display monitor during the memory test operation, but the controller chip 22b with a memory test function is used. Provided outside. For this reason, the controller chip 22b with a memory test function has a connection interface for connection with the test display memory 31b, that is, an external connection signal. The test display memory 31b is identical to the description of the test display memory 31a described in the first embodiment except that it is provided outside the controller chip 22b with a memory test function.

  Since the description of the processing of the computer 1 with a memory test function of the present invention is the same as that described in the first embodiment with reference to the flowchart shown in FIG. 4, the description of the processing is omitted here. . In the description of the above-described processing, the controller chip 22a with a memory test function needs to be renamed to the controller chip 22b with a memory test function, and the test display memory 31a needs to be renamed to the test display memory 31b.

  With the above configuration, a connection connector or the like can be used for the test display memory 31b provided outside the controller chip 22b with a memory test function, so that the test display memory 31b can be physically attached to and detached from the computer 1. From this, it is possible to connect (mount) the test display memory 31b only when the memory test is performed, and to remove the test display memory 31b after the memory test is completed, that is, at the time of product shipment. As a result of mounting and using the main memory 5 of the computer 1 under the same conditions as the product used by the customer, the manufacturing cost can be reduced.

  Further, since the test display memory 31b can be selected and mounted from various memory capacities, the test display memory having a memory capacity corresponding to the quality of the display image (screen resolution, etc.), the number of display colors to be reproduced, etc. By mounting 31b, a desired display capability on the display monitor can be freely set.

  Although not shown, in the configurations of the first and second embodiments, a means for changing the power supply voltage supplied to the main memory 5 is provided in the computer 1 so that the power supply voltage can be changed. By performing the memory test under conditions, the power supply voltage margin of the main memory 5 can be investigated. Further, based on the margin investigation result, the supply power supply voltage is reset to a power supply voltage (for example, a center value based on the power supply voltage margin upper limit value and lower limit value) that is optimal for the mounted main memory 5. Thus, a more stable operation can be obtained from the main memory 5, and the reliability of the product of the computer 1 can be improved.

Principle block diagram of the present invention The figure which shows the structure of the computer with a memory test function of Example 1 of this invention. The figure which shows the structure of the computer with a memory test function of Example 2 of this invention. Flow chart showing processing of the present invention Conventional computer with memory test function

Explanation of symbols

1 Computer 2 Controller with Memory Test Function 3,83 CPU
4,84 Video display processing means 5,85 Main memory 6,86 Image memory 7-1,7-2,7-3,87-1,87-2,87-3 Connection interface 9,89 Memory control means 10, 90 memory test means 11, 31a, 31b test display memory 12, 92 switching means 13, 93 basic activation ROM 22a, 22b, 82 controller chip with memory test function 24 video display processing section 28 image processing section 29 memory control section 30 memory test Portion 32-1 First Switching Unit 32-2 Second Switching Unit 33 BIOS-ROM
34 Test mode register

Claims (5)

CPU, video display processing means for displaying on screen, connection interface connected to main memory partly shared with image memory for screen display, and image processing means for sending data to said video display processing means A memory control means for generating a memory access signal, and a memory test means for testing the main memory by generating a test pattern and a memory access signal, wherein the CPU, the main memory and the video display processing means receive and transmit data In a controller with a memory test function capable of controlling the main memory and performing a memory test of the main memory,
A test display memory for holding data for screen display of the memory test;
When performing the memory test, the memory access signal from the memory test means is sent to the main memory, the memory access signal from the memory control means is sent to the test display memory, and the memory test is performed. If not, switching means for switching so that the memory access signal from the memory control means is sent to the main memory;
A controller with a memory test function. CPU, video display processing means for displaying a screen, a main memory partly connected to an image memory for screen display, and a test display memory for holding data for screen display during testing of the main memory A connection interface; image processing means for sending data to the video display processing means; memory control means for generating a memory access signal; and a memory test for testing the main memory by generating a test pattern and a memory access signal A controller with a memory test function capable of controlling the CPU, the main memory, and the video display processing means to perform data transmission and reception and performing a memory test of the main memory,
When performing the memory test, the memory access signal from the memory test means is sent to the main memory, the memory access signal from the memory control means is sent to the test display memory, and the memory test is performed. If not, switching means for switching so that the memory access signal from the memory control means is sent to the main memory;
A controller with a memory test function. In a computer having a CPU, video display processing means for displaying a screen, a main memory partly shared by an image memory for screen display, and a basic boot ROM,
A computer with a memory test function, comprising the controller with a memory test function according to claim 1. CPU, video display processing means for screen display, main memory partially shared by image memory for screen display, basic start-up ROM, and data for screen display during testing of main memory In a computer having a test display memory
A computer with a memory test function, comprising the controller with a memory test function according to claim 2. The computer with a memory test function according to claim 3 or 4,
A computer with a memory test function, wherein a program required for testing the main memory is stored in the basic boot ROM.

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