JP2005175910A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit capable of switching an external output voltage by a simple constitution without requiring control by a CPU. <P>SOLUTION: A switching signal to take a first or a second level from a memory board 5 is added to a switching terminal 4b. When the switching signal is at the first level, a voltage switching circuit 4 converts a signal (the address signal of the memory board 5) to be outputted to a signal based on a 5 V power supply voltage and outputs it. When the switching signal is at the second level, the voltage switching circuit 4 converts a signal to be outputted to a signal based on a 3.3 V power supply voltage and outputs it. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor integrated circuit capable of signal output from two power sources.

Conventionally, for example, the memory access voltage is generally 5V, but in recent years, 3.3V memory is also used, and 5V memory and 3.3V memory are mixed. For this reason, a semiconductor integrated circuit (hereinafter referred to as LSI) having a memory control circuit is required to be able to drive both a 5V memory and a 3.3V memory.
Conventionally, various types of LSIs satisfying such requirements have been manufactured. However, this type of conventional LSI has a built-in CPU (central processing unit) that controls switching of the drive voltage of the memory, which requires various control circuits and registers, and the configuration is complicated. There was a problem. In addition, it is necessary to execute an initial program when the power is turned on by the CPU before the system initialization sequence, resulting in a problem that the rise of the entire circuit is delayed.
Patent Document 1 is known as a conventional technical document of this type.
Japanese Patent No. 3133175

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor integrated circuit that can switch an external output voltage with a simple configuration without requiring control by a CPU.

  According to a first aspect of the present invention, in a semiconductor integrated circuit having a first power supply voltage and a second power supply voltage, a switching terminal to which a switching signal that takes the first or second level is applied from the outside; When the switching signal is at the first level, the signal to be output is converted into a signal based on the first power supply voltage and output. When the switching signal is at the second level, the signal to be output is converted to the first level. And a voltage switching circuit that converts the signal into a signal based on the power supply voltage and outputs the signal.

  According to a second aspect of the present invention, in the semiconductor integrated circuit according to the first aspect, the voltage switching circuit controls the first and second power supply voltages and outputs them to an output terminal, and And a control circuit for generating a signal for controlling on / off of the transistor based on a switching signal.

According to a third aspect of the present invention, in the semiconductor integrated circuit according to the second aspect, the plurality of transistors include a first transistor that controls on / off of the first power supply voltage, and the second power supply voltage. A second transistor for on / off control and a third transistor for on / off control of a ground voltage are characterized.
According to a fourth aspect of the present invention, in the semiconductor integrated circuit according to the third aspect, a substrate of a transistor that performs on / off control of a low-voltage power source among the first and second transistors is based on the switching signal. A fourth transistor which is turned on / off is provided.

  According to a fifth aspect of the present invention, in the semiconductor integrated circuit according to the second aspect, the control circuit further includes a circuit that turns off the plurality of transistors in response to a signal indicating a disabled state of the switching circuit. It is characterized by having.

  According to the present invention, when the switching signal is at the first level, the signal to be output is converted into a signal based on the first power supply voltage and output, and when the switching signal is at the second level, the signal to be output Since the voltage switching circuit for converting and outputting the signal to the signal based on the second power supply voltage is provided, the external output voltage can be switched with a simple configuration without requiring the control by the CPU.

  Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration of LSI 1 according to an embodiment of the present invention. The LSI 1 shown in FIG. 1 includes a CPU 2, a memory control circuit 3, and a voltage switching circuit 4. Then, an address voltage corresponding to the address signal is output from the output terminal 4 a of the voltage switching circuit 4 to the memory board 5, and a “high” voltage or a “low” voltage is received from the memory board 5 at the switching terminal 4 b. The memory board 5 is a board on which a plurality of memory chips are mounted, and outputs a “high” voltage to the voltage switching circuit 4 when the driving voltage of the memory chip is 5V and a “low” voltage when the driving voltage is 3.3V. .

  FIG. 2 is a circuit diagram showing a configuration of the voltage switching circuit 4. In this figure, 4a and 4b are the output terminals and switching terminals described above, 4c is an address terminal to which an address signal is supplied from the memory control circuit 3, and 4d is an enable terminal to which an output enable signal is supplied from the memory control circuit 3. is there. Reference numerals 11 to 13 denote level shift circuits which raise the input voltage to a predetermined level and output it. 16 and 17 are inverters, 20 and 21 are negative logic AND gates, 22 and 23 are NAND gates, and 24 is a negative logic AND gate. And the switching control part 27 for switching an output voltage is comprised by the component 16-24 mentioned above.

  Reference numeral 31 denotes a P-channel FET (field effect transistor) having a source connected to the 3.3V power supply VD3, a gate connected to the output terminal of the NAND gate 22, a drain connected to the drain of the FET 33, and a substrate connected to the FET 32. Connected to the drain. The FET 32 is a P-channel FET, the source is connected to the 3.3V power supply VD3, the gate is connected to the output terminal of the inverter 16, and the substrate is connected to the drain. The FET 33 is an N-channel FET, the gate is connected to the output terminal of the AND gate 24, the source is grounded, and the substrate is connected to the source. The connection point between the drain of the FET 31 and the drain of the FET 33 is connected to the output terminal 4a.

  Reference numeral 34 denotes a P-channel FET, the source of which is connected to the 5V power supply VD5, the gate of which is connected to the output terminal of the AND gate 23, the drain of which is connected to the output terminal 4a, and the substrate of which is connected to the source. The FETs 31 to 34 described above constitute a voltage output circuit 37 that outputs a voltage of 5V or 3.3V based on the address signal. Reference numeral 35 denotes a P-channel FET having a source connected to the 5V power source VD5, a gate connected to the source, a drain connected to the output terminal 4a, and a substrate connected to the source. Reference numeral 36 denotes an N-channel FET having a drain connected to the output terminal 4a, a gate connected to the source, a source grounded, and a substrate connected to the source. These FETs 35 and 36 both function as diodes and absorb the surge voltage generated by the output terminal.

Next, the operation of the circuit described above will be described.
First, when a “high” voltage is supplied as an output enable signal to the enable terminal 4d, the outputs of the AND gates 20 and 21 both become “low” voltages. As a result, a “low” voltage is supplied to the second input terminals of the NAND gates 22 and 23, a “high” voltage is output from the NAND gates 22 and 23, and the FETs 31 and 34 are turned off. Further, the output of the AND gate 24 becomes a “low” voltage, and the FET 33 is turned off. As described above, when the “high” voltage is supplied to the enable terminal 4d, the FETs 31, 33, and 34 are turned off, and the voltage switching circuit 4 is disabled.

  Next, when the “low” voltage is supplied as an output enable signal to the enable terminal 4d, the voltage switching circuit 4 is enabled, and corresponds to the address signal from the output terminal 4a to the address terminal 4c in the process described below. Address voltage is output. That is, first, when the “low” voltage is supplied to the switching terminal 4b, the output of the inverter 16 becomes the “high” voltage, the output of the inverter 17 becomes the “low” voltage, and the output of the AND gate 20 becomes “low”. The voltage and the output of the AND gate 21 become the “high” voltage. As a result, a “low” voltage is supplied to the second input terminal of the NAND gate 22, the output of the NAND gate 22 becomes a “low” voltage regardless of the signal at the first input terminal, and the FET 31 is turned off. At this time, the FET 32 is also turned off because the gate is high. On the other hand, since the output of the AND gate 21 is “high”, when the “high” voltage is supplied to the second input terminal of the NAND gate 23, the output of the NAND gate 23 becomes “low”. , In other words, it changes according to the address signal of the address terminal 4c. When the address signal is “high” voltage, it becomes “low” voltage, the FET 34 turns on, and the address signal becomes “low” voltage. At that time, the voltage becomes “high”, and the FET 34 is turned off.

On the other hand, when the “low” voltage is supplied to the enable terminal 4d, the input terminal of the AND gate 24 becomes “low”. Thus, when the address signal is “high” voltage, the output of the AND gate 24 becomes “low” voltage, the FET 33 is turned off, and when the address signal is “low” voltage, the output of the AND gate 24 is “high” voltage. Thus, the FET 33 is turned on.
Thus, when the switching terminal 4b is at the "low" voltage, the FET 34 is turned on and the FET 33 is turned off when the address signal at the address terminal 4c is at the "high" voltage, and the voltage of the 5V power supply VD5 is output from the output terminal 4a. The On the other hand, when the address signal at the address terminal 4c is a "low" voltage, the FET 34 is turned off and the FET 33 is turned on, and the ground voltage is output from the output terminal 4a. That is, 5V output is obtained.

  Next, when the signal at the switching terminal 4b is “high” voltage, the output of the inverter 16 is “low” voltage, the output of the inverter 17 is “high” voltage, and the output of the AND gate 20 is “high” voltage. The output of the gate 21 becomes a “low” voltage. As a result, a “low” voltage is supplied to the second input terminal of the NAND gate 23, the output of the NAND gate 23 becomes the “high” voltage regardless of the signal at the first input terminal, and the FET 34 is turned off. On the other hand, since the second input terminal of the NAND gate 22 (connected to the output of the AND gate 20) is “high”, the output of the NAND gate 22 changes according to the address signal of the address terminal 4c, and the address signal is “high”. When the voltage is “low” voltage, the FET 31 is turned on. When the address signal is “low” voltage, the FET 31 is turned “high” and the FET 31 is turned off. At this time, the FET 32 is turned on, and the source of the FET 31 and the substrate are connected. The output of the AND gate 24 operates in the same manner as described above. That is, when the address signal is “high” voltage, the output of the AND gate 24 becomes “low” voltage, the FET 33 is turned off, and when the address signal is “low” voltage, the output of the AND gate 24 becomes “high” voltage. FET 33 is turned on.

Thus, when the switching terminal 4b is at the “high” voltage, the FET 31 is turned on and the FET 33 is turned off when the address signal at the address terminal 4c is at the “high” voltage, and the voltage of the 3.3V power supply VD3 is output from the output terminal 4a. On the other hand, when the address signal of the address terminal 4c is “low” voltage, the FET 31 is turned off and the FET 37 is turned on, and the ground voltage is outputted from the output terminal 4a. That is, 3V output is obtained.
The details of the embodiment shown in FIGS. 1 and 2 have been described above. According to this embodiment, the output of the LSI 1 can be set to 3.3V or 5V simply by applying a “low” voltage or a “high” voltage to the switching terminal 4b.

In the above configuration, the FET 32 turns off the connection between the substrate and the source of the FET 31 at the time of 5V output (the switching terminal 4b is “low” voltage), and thereby the voltage of the output terminal 4a at the time of 5V output. This is to prevent a current from flowing from the drain of the FET 31 to the gate through the diode connection of the FET 31 when the voltage becomes 5V.
Further, although the above embodiment is an LSI for driving a memory board, the present invention is not limited to a memory board, and can be applied to an LSI for driving various other circuits.

1 is a block diagram showing a configuration of a semiconductor integrated circuit according to an embodiment of the present invention. It is a circuit diagram which shows the structure of the voltage switching circuit 4 in the embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Semiconductor integrated circuit, 4 ... Voltage switching circuit, 4a ... Output terminal, 4b ... Switching terminal, 4c ... Address terminal, 4d ... Enable terminal, 5 ... Memory board, 11-13 ... Level shifter, 16, 17 ... Inverter, 20 , 21, 24 ... negative logic AND gates, 22, 23 ... NAND gates, 27 ... switching control units, 31-34 ... FETs, 37 ... voltage output circuits.

Claims (5)

In a semiconductor integrated circuit having a first power supply voltage and a second power supply voltage,
A switching terminal to which a switching signal taking the first or second level is applied from the outside;
When the switching signal is at the first level, the signal to be output is converted into a signal based on the first power supply voltage and output, and when the switching signal is at the second level, the signal to be output is A voltage switching circuit that converts and outputs a signal based on the second power supply voltage;
A semiconductor integrated circuit comprising: The voltage switching circuit is
A plurality of transistors for controlling the first and second power supply voltages and outputting them to an output terminal;
A control circuit for generating a signal for controlling on / off of the transistor based on the switching signal;
The semiconductor integrated circuit according to claim 1, comprising:   The plurality of transistors include a first transistor that controls on / off of the first power supply voltage, a second transistor that controls on / off of the second power supply voltage, and a third transistor that controls on / off of the ground voltage. The semiconductor integrated circuit according to claim 2, wherein the transistor is a transistor.   4. A fourth transistor for turning on / off a substrate of a transistor for controlling on / off of a low-voltage power source among the first and second transistors based on the switching signal is provided. The semiconductor integrated circuit as described.   The semiconductor integrated circuit according to claim 2, wherein the control circuit further includes a circuit that turns off the plurality of transistors in response to a signal instructing a disabled state of the switching circuit.

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