JP2005175698A - Local generator and wireless communication apparatus provided with local generator - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem of a conventional local generator for high speed frequency hopping that other frequencies are simultaneously outputted actually at a particular time during frequency hopping although only a particular frequency (band) should substantially be outputted because respective frequencies are generated in each frequency divider and thereafter selected by a selector and coupling takes place among the respective frequencies due to wires existing on the way until the frequencies reach the selector. <P>SOLUTION: A sub band generator 2 generates only one frequency at any time. Since the frequency divider itself is stopped, no other frequencies than the required frequency are produced. Thus, leakage of unnecessary frequencies due to coupling among the wires is not caused. Further, since only one frequency at a time is generated, no high speed selector operating among a plurality of ports is required and outputs of the sub band generator have only to be added and the configuration is simplified. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a local generator capable of high-speed frequency switching used for high-speed frequency hopping, and a radio communication apparatus including the local generator.

  The speed of wireless communication is remarkable. In recent years, the US FCC (Federal Communications Commission) has allowed a band from 3.1 GHz to 10.6 GHz to be used for UWB (Ultra-Wideband) communication on condition of low power transmission. Although this is limited to a short distance, it has become possible to realize ultrahigh-speed wireless communication using a bandwidth of 7.5 GHz.

  On the other hand, the IEEE standardization committee 802.15.3a standardizes a wireless personal area network (WPAN) of 100 Mbps to 480 Mbps using a UWB band.

  Many of the methods proposed at present are frequency hopping in a 7.5 GHz band at high speed. There are various conventional methods for frequency hopping, but the method proposed in IEEE 802.15.3a performs frequency hopping much faster than the conventional method as the bit rate increases. In the conventional frequency hopping, the output frequency of the frequency synthesizer in the oscillator is changed, or the frequency is changed at most by using a PLL arranged in the subsequent stage. However, the method proposed in IEEE 802.15.3a has a frequency hopping speed that is too high for the conventional method.

  In view of this, an implementation method by switching lines as shown in FIG. 14 has been proposed (see, for example, Non-Patent Document 1).

  In FIG. 14, the output (5280 MHz) from the frequency synthesizer 101 is branched into three. One is connected to the subband generator 102, one is connected to the frequency divider 103-6, and the other is connected to the frequency converter 105. In the subband generator 102, there are five frequency dividers 103-1 to 103-5, and these generate four frequencies 440MHz, 880MHz, 1320MHz, and 1760MHz. Specifically, the 5280 MHz clock input from the frequency synthesizer 1 is branched into two. One is frequency-divided into four by two cascade-connected two frequency dividers 103-4 and 103-5 to become a 1320 MHz clock. On the other hand, the frequency divided by 3 by the frequency divider 103-1 to 1760 MHz is branched into two, and one is output as it is as a 1760 MHz clock. The other is further divided by 2 by the frequency divider 103-2 to become 880 MHz. 880 MHz is divided into two, one is output as it is as 880 MHz, and the other is divided by 2 by the frequency divider 103-3 to be output as 440 MHz. Five inputs obtained by adding DC to these are input to the selector 4. The selector 104 selects one of these five inputs and outputs it to the frequency converter 105. The other input of the frequency converter 105 receives 5280 MHz which is a branch of the output of the frequency synthesizer 101. The frequency converter 105 mixes these two inputs and converts the frequency. The frequency converter 105 is a down converter, and a clock corresponding to the frequency of the difference between 5280 MHz and the output frequency of the selector 4, that is, any one of 5280 MHz, 4840 MHz, 4400 MHz, 3960 MHz, and 3520 MHz is output from the frequency converter 105. . Note that the frequency divider 103-6 is a frequency divider of 5 and generates a data clock of 1056 MHz.

In FIG. 14, four types of frequencies (five types including direct current) are generated in advance and selected by the selector. In this way, in principle, switching can be performed at a speed determined by the switching speed of the selector 104, and high-speed frequency hopping can be handled.
Gadi Shor, IEEE 802.15-03 / 151r3, Slide 47, [online], May 5, 2003, [May 12, 2003 search], Internet <URL: http: // grouper .ieee.org / groups / 802/15 / pub / 2003 / May03 / 03151r3P802-15-_TG3a-Wisair-CFP-Presentation.ppt>

As described above, the conventional local for high-speed frequency hopping branches the output of the frequency synthesizer as appropriate and frequency-converts each with a frequency divider etc. to generate all frequencies of frequency hopping. The method of selecting with the selector was used.
WPAN is for general consumers to build a wireless network in an office or home, and is required to be small and low cost. Therefore, there is no doubt that the local generator as shown in FIG. 14 is entirely built in one IC. In such a case, the coupling between the respective frequencies is caused by the wiring from when the signal of each frequency is generated by each frequency divider until reaching the selector.

  For example, in FIG. 14, even if the selector 104 selects a 1760 MHz line, the line on which 1760 MHz is placed is 880 MHz or 1056 MHz adjacent to the line due to the coupling between the lines until the selector 104 is reached. The 440MHz and 1320MHz clocks are also on the 1760MHz line. The amount of coupling varies depending on the IC layout, but the coupling amount tends to be large even with a short wiring at a high frequency exceeding 1 GHz. When such a coupling occurs, as a result, only a specific frequency (band) must be output at a specific time during frequency hopping, but other frequencies are actually output at the same time. Will occur.

  In order to solve such a problem, in the first invention of the present application, a frequency synthesizer and a signal of each frequency used in frequency hopping are individually generated from the frequency synthesizer output, and the signal of each frequency is individually wired. An output control means for controlling the output timing to the wiring for each frequency, and an adder that receives the signal output to the wiring, and the output of the frequency synthesizer And a local generator for generating a local signal for frequency hopping by mixing the output of the adder and the output of the adder.

  In the second invention of the present application, the frequency generation unit includes a plurality of systems that generate the signals of the respective frequencies, and each system is used to generate the signals of the respective frequencies, and the operation of frequency division is stopped or activated. A local generator is provided, characterized in that there is a controllable externally controlled frequency divider.

  According to a third aspect of the present invention, there is provided a local generator characterized in that the external control type frequency divider is the final stage of the frequency conversion operation of the system for generating the signal of each frequency.

In the fourth invention of the present application, the frequency generation unit is composed of a plurality of systems that generate the signals of the respective frequencies, and in the system in which there is a frequency divider used for generating only the signals of the frequencies of the respective systems, The frequency divider is an external control type frequency divider capable of controlling the operation / stop of the frequency dividing operation, and the external control type is controlled by controlling the operation / stop of the output buffer in the external control type frequency divider. In systems where there is no frequency divider that controls the frequency division operation of the frequency divider and is used only to generate signals of the frequency of each system, the external control type frequency division before the output to the wiring There is provided a local generator characterized in that an on / off switch configured by a buffer having the same configuration as the output buffer of the generator is arranged to control the operation / stop of the on / off switch.

  In a fifth aspect of the present application, the output control means includes a timing signal generation unit that generates a timing signal that indicates an output timing of the signal of each frequency output from the frequency generation unit, and the timing signal is A local generator is provided wherein the output of the frequency synthesizer is generated as a reference clock and supplied to the frequency generator.

  In the sixth invention of the present application, the timing signal is characterized in that, for each frequency, the time from one operation instruction to the next operation instruction is an integral multiple of a time period corresponding to the frequency. A local generator is provided.

  In the seventh invention of the present application, the external control type frequency divider is a digital frequency divider using a counter, and the counter until the first rise or fall of the output after receiving an operation instruction by the timing signal is provided. There is provided a local generator characterized in that the count number is changed by a predetermined amount each time.

  In the eighth invention of this application, in the frequency generation unit, the final stage that outputs the signal of each frequency is configured by a digital circuit, and when the output to the wiring is stopped, the signal of each frequency is output. The final stage is stopped in a low state, and the adder comprises a logical sum circuit.

  In the ninth invention of the present application, in the frequency generation unit, the final stage is configured by a digital circuit, and when the output to the wiring is stopped, the final stage that outputs the signal of each frequency is in a high state. And providing a local generator characterized in that the adder comprises an AND circuit.

  In the tenth invention of the present application, the adder is a current adder, and in the frequency generator, the final stage that outputs the signal of each frequency stops the adder when the output to the wiring is stopped. A local generator is provided which is configured to stop in a state where no current flows.

  In the eleventh aspect of the present invention, in a wireless communication apparatus including a local generator for generating a signal having a frequency used in a frequency hopping method in which communication is performed by switching the frequency of a carrier wave at a certain period, a frequency synthesizer; A signal for each frequency used for frequency hopping is individually generated from the frequency synthesizer output, and each frequency is output to an individual wiring, and the output timing to the wiring is controlled for each frequency. An output control means and an adder that receives the signal output to the wiring, and generates a local signal for frequency hopping by mixing the output of the frequency synthesizer and the output of the adder. A wireless communication device is provided.

  According to the present invention, there is an effect that unnecessary frequency leakage due to coupling between wirings does not occur. In addition, a high-speed selector that operates between a plurality of ports is unnecessary, and the configuration can be simplified.

  Embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a diagram showing a first embodiment of the present invention, in which a configuration for realizing the same function as the conventional example of FIG. 14 described above and for achieving the effect of the present invention is included. FIG.

  In FIG. 1, the frequency synthesizer 1 generates a reference frequency of 5280 MHz. The 5280 MHz clock is divided into four branches, one is divided by 5 by the frequency divider 3-6, one is for data clock generation, one is for timing signal generation, and one is for upconversion. Is used for subband generation.

  The subband generator 2 mainly includes frequency dividers 3-1 to 3-5 and generates four types of frequencies from 5280 MHz to 440 MHz, 880 MHz, 1320 MHz, and 1760 MHz. In the subband generator 2, the output from the frequency synthesizer 1 is divided into three branches, one of which is divided by 3 by the frequency divider 3-2 to generate 1760 MHz, which is output to the wiring 7-1. One is divided by 4 by a frequency divider 3-5 to generate 1320 MHz, which is output to the wiring 7-4. The other is divided into three by the frequency divider 3-1, and then branched into two. In FIG. 1, a plurality of consecutive frequency dividers that do not include a branch or the like in the middle are illustrated as one integrated frequency divider. For example, the two frequency dividers 103-4 and 103-5 in FIG. 14 are illustrated as one quadrant.

  One of the outputs of the frequency divider 3-1 is divided by 2 by the frequency divider 3-3 to generate 880 MHz and is output to the wiring 7-2. The other is divided by 4 by the frequency divider 3-4, becomes 440 MHz, and is output to the wiring 7-3. Signals from these wirings 7-1 to 7-4 are input to the adder 4, added, and output to the frequency converter 5.

  In addition to the input from the adder 4, 5280 MHz from the frequency synthesizer 1 is input to the frequency converter 5, and both are mixed. From the frequency converter 5, a signal having a frequency corresponding to the difference between the signal from the adder 4 and the signal from the frequency synthesizer 1 is output as the LO output 9.

  The frequency divider 3-2, the frequency divider 3-3, the frequency divider 3-4, and the frequency divider 3-5 correspond to external control signals and can change their states between operation and stop. It is a control type frequency divider. The timing signal generator 6 that receives the input from the frequency synthesizer 1 controls the operations of the frequency divider 3-2, the frequency divider 3-3, the frequency divider 3-4, and the frequency divider 3-5. Is generated. For example, if the output frequency of the adder 4 is switched in the order of 1760 MHz, 1320 MHz, 880 MHz, 440 MHz, and 0 Hz (DC), a timing signal as shown in FIG. 2 is generated. That is, at the beginning of one cycle of frequency hopping, a signal for operating the frequency divider 3-2 for generating 1760 MHz is sent, and after the duration has elapsed, the frequency divider 3-2 is stopped, Simultaneously or after some guard time, send a signal to activate the frequency divider 3-5 generating 1320 MHz. Similarly, after the frequency divider 3-5 is stopped, the frequency divider 3-3 is operated to generate 880 MHz, and after the frequency divider 3-3 is stopped at the next timing, the frequency divider 3-4 Is operated to generate 440 MHz. After stopping the frequency divider 3-4 of the system that generates 440 MHz in this way, when the next period of frequency hopping starts with the same duration for DC, the frequency divider 3 again. -2 is activated.

  Here, the slight guard time when the frequency divider to be operated is switched may be as long as two frequencies are not simultaneously input to the adder 4. Even when the time when the previous frequency divider is instructed to stop and the time when the next frequency divider is instructed to operate are almost simultaneous, the two frequencies are simultaneously added by the adder 4 due to, for example, a delay in starting the frequency divider. If there is no input to the timing signal, there is no need to provide a guard time on the timing signal generator 6 side.

There are several methods for making the output of the adder 4 DC in order to output 0 Hz. For example, when the adder 4 is composed of an adder using a digital circuit such as an AND circuit or an OR circuit, when the output is input to the frequency converter 5, the DC level is shifted by the level shifter circuit, and high and low There is a high possibility that the middle is the operation center point of the input of the frequency converter 5. In such a form, if the adder 4 is designed to stop at a constant value of either high or low when all the frequency dividers 3-2 to 3-5 are stopped, the frequency conversion is performed. A direct current is naturally input to the device 5, and 5280 MHz from the frequency synthesizer 1 is output from the LO output 9 without being converted.

  As another method, similarly to FIG. 14, a terminal dedicated to direct current is provided on the input side of the adder 4, a direct current generator and a buffer for controlling the direct current generator are connected to the direct current dedicated terminal, and another frequency series is provided. The buffer may be activated / stopped from the timing signal generator 6 in the same manner as described above. In that case, in FIG. 2, a pulse having the same frequency as that of the other frequency is also input to the direct current.

  In this way, only one frequency can be generated at any time in the subband generator 2. Since the frequency divider itself is stopped except for the necessary frequency, no unnecessary frequency is generated. Therefore, unnecessary frequency leakage due to coupling between wirings, which has been a problem in the past, does not occur. Further, since only one frequency is generated at one time, there is no need for a high-speed selector that operates between a plurality of ports, and the outputs of the subband generator 2 need only be added.

  In FIG. 1, an output control means for controlling the presence / absence of output to the wiring by a mechanism for controlling the operation / stop of the operation in the external control type frequency divider of the subband generator 2 and the timing signal generator 6; It has become.

  Further, in FIG. 1, there is always one frequency divider that is used only for generating a frequency in a system that generates one frequency, and this is an externally controlled frequency divider, and its operation is activated. It can be changed between stops. By configuring in this way, all the frequencies are activated and stopped with the same configuration, so the performance of the obtained signal, such as the rising and falling shapes, does not depend on the frequency, and as a frequency hopping local generator Can be expected to be homogeneous.

  In FIG. 1, there is one frequency divider used only for generating a frequency in a system that generates one frequency, but there may be two or more frequency dividers. For example, the frequency divider 3-5 may be one frequency divider with four divisions, or two frequency dividers with two divisions may be cascaded as shown in FIG.

  In the configuration in which two frequency dividers are connected, two or both frequency dividers may be basically operated / stopped by the timing signal. However, the performance varies depending on which frequency divider is selected. When the upstream frequency divider is controlled, the frequency generation mechanism stops upstream, so that unnecessary frequency leaks from the system to other systems while the system is stopped. However, when operating, since the upstream frequency divider is sequentially operated, the unstable time until the system is completely operated becomes longer. Among a plurality of frequency generation sequences, most of them have only one divider, and when a sequence having two or more sets control to an upstream divider, only such a sequence, particularly, The operation at the moment when the sequence starts to operate and the moment when the sequence stops are different, and the homogeneity as a subband generator is lost. Such heterogeneous operation complicates subsequent circuit design. If there are multiple frequency dividers in one series and both of them can be controlled, the frequency divider in the final stage can be made an external control type frequency divider, making it more uniform as a subband generator. Operation is possible.

It should be noted that there are roughly two methods for configuring the external control type frequency divider, and in particular, how to operate and stop when an external timing signal is input. That is, there are two ways to stop the frequency divider, which is the main body of the frequency divider, or to stop the buffer provided in the output unit in order to suppress output jitter. FIG. 3 shows each configuration.

In FIG. 3, (a) is a configuration in which the frequency divider is stopped. The clock input to the input 12 is frequency-divided by the frequency divider 10-1, retimed by the buffer 11-1, and output from the output 13. Is done. The buffer 11-1 is composed of a D flip-flop and the like, and the retiming clock 15 is input to the clock input thereof, and the jitter generated in the frequency dividing unit 10-1 is about the jitter of the retiming clock 15. Be suppressed. In most cases, the retiming clock 15 is branched from the input 12, but when the input 12 does not have sufficient jitter characteristics, it is branched from the frequency synthesizer output. A timing signal 14-1 is input to the frequency divider 10-1, and the operation / stop of the frequency divider 10-1 is controlled. The frequency divider 10-1 is a counter type digital frequency divider, and the timing signal 14-1 controls the start / stop of the count. In the configuration of FIG. 3A, the frequency dividing operation itself is stopped, so that the performance of suppressing the coupling to other systems is high. The configuration (a) is desirable if importance is attached to the performance of suppressing the coupling to other systems.
On the other hand, FIG. 3B shows a configuration for controlling the output buffer. Most of the configuration is the same as that of FIG. 3A, but the operation of the buffer 11-2 can be controlled from the outside, and the timing signal 14-2 controls the operation / stop of the buffer 11-2. The point is very different. In this configuration, the frequency dividing operation itself does not stop, and only whether or not the divided clock is output is changed. The frequency divider 10-2 may be either a digital frequency divider or an analog frequency divider. (The analog frequency divider is not suitable for the configuration of (a) because the operation starts using disturbance such as noise in the feedback loop as a seed.) In such a configuration, the frequency-divided clock is continuously generated. The ability to suppress coupling to other systems is lower than (a). However, this is a desirable form in the embodiment as shown in FIG.

  In the present invention, only one frequency is generated at any time in the subband generator. Since the frequency divider itself is stopped except for the necessary frequency, no unnecessary frequency is generated. Therefore, unnecessary frequency leakage due to coupling between wirings does not occur. Further, since only one frequency is generated at one time, there is no need for a high-speed selector that operates between a plurality of ports, and the outputs of the subband generators can be simply added, and the configuration can be simplified.

FIG. 4 is a diagram showing a second embodiment of the present application. As in FIG. 1, the embodiment of FIG. 14 is realized by the configuration of the present application. Since the configuration other than the subband generator 2 is the same as that shown in FIG. As will be described later, unlike FIG. 1, the timing signal generator 6 does not necessarily require an input from the frequency synthesizer 1.
The subband generator 2 is more similar to the configuration of FIG. 14, and unlike FIG. 1, there is not always one or more frequency dividers in the generation system of each frequency. Shared by the grid. A switch 16 is inserted in a system that cannot be controlled by the operation / stop of the frequency divider. The operation of the subband generator 2 will be described below.

  The clock from the frequency synthesizer 1 is branched into two, one of which is divided by 4 by the frequency divider 17-3 and output to the wiring 7-4. The other is divided into three by the frequency divider 17-1, and then branched into two. One is output to the wiring 7-1 through the switch 16, the other is divided by 2 by the frequency divider 17-2, and further branched into two. One of them is output to the wiring 7-2 via the switch 16-2, and the other is divided by 2 by the frequency divider 17-4 and then output to the wiring 7-3. The frequency dividers 17-3 and 4 are external control type frequency dividers configured as shown in FIG.

The switches 16-1 and 16-2 are on / off switches having the same configuration as the buffer 11-2 in the frequency divider having the configuration shown in FIG. 3B, and their operations are controlled by an external timing signal. The timing signal output from the timing signal generator 6 is the same as that in FIG. 2 and is controlled so that only one frequency is output from the subband generator 2 at one time. Elements that control the output to the wiring are frequency dividers, switches, or the like. However, the externally controlled frequency divider used here is a type that controls the output buffer as shown in FIG. 3B, and the switch has the same configuration as the output buffer. The transitional behavior when this is performed is the same in all systems, and the overall homogeneity is maintained. Here, from the viewpoint of suppressing the coupling to other systems as much as possible, the switch 16 should be inserted as close as possible to the immediately preceding branch point, and the frequency dividers 17-3 and 4 The output buffer should be as close as possible to the divider.
In this way, in the subband generator 2 in which the presence / absence of the output of the system is controlled by the buffer, a switch in cascade connection to another frequency conversion element, for example, a multiplier or a mixer, is used as the final stage of the system. It is also possible to use it. (Of course, even in the configuration of FIG. 1, a multiplier or a mixer can be used if it is other than the final stage. The frequency converter used in the subband generator is not limited to the frequency divider.)
Next, the configuration of the adder 4 will be described. In the present invention, basically, only one frequency is output from the subband generator at the same time, and therefore the adder 4 can be configured on the premise of such a configuration. For example, as shown in FIG.

  In FIG. 5, an OR circuit 18 is used as an adder. At this time, the sub-band generator is configured so that the final stage of each system is composed of digital circuits (digital divider, buffer, etc.), and when each system stops, its output always stops at a low level. Has been. Since the operating system repeats high and low, and all other systems are stopped at low, the output of the OR circuit 18 becomes the output of the operating system itself. In FIG. 5, an OR circuit is used, but a NOR circuit may be used.

  Similarly, an AND circuit 19 can be used as shown in FIG. Similarly, at this time, the sub-band generator is configured such that the final stage of each system is configured by a digital circuit (digital divider, buffer, etc.), and when each system stops, its output always stops high. It is configured. Since the operating system repeats high and low, and all other systems are stopped at high, the output of the AND circuit 19 becomes the output of the operating system itself. Although an AND circuit is used in FIG. 6, a NAND circuit may naturally be used.

  In this way, since the adder is constituted by a digital circuit, the design is facilitated.

  Further, the adder may be composed of a current adder as shown in FIG. The signals input from the wiring 7-1 to the wiring 7-4 drive each FET of the current adder 21. The collectors of the FETs are connected, and the currents flowing through the FETs are added and flow through the resistors. Therefore, a voltage proportional to the added current is obtained at the output terminal 20 that outputs the voltage at one end of the resistor. The system corresponding to each frequency in the subband generator needs to be configured to stop at a low (or low voltage) level so that no extra current flows when the operation is stopped. Although the operation is close to NOR, since it is an analog adder using current, it can be handled even if the final stage of the subband generator is constituted by an analog circuit.

  In the configuration of FIG. 7 as well, if the inputs from all of the wirings 7-1 to 7-4 are stopped at a low level, the output of the output terminal 20 is stopped at a high level. Such a problem of generating 0 Hz has been solved.

  FIG. 8 shows a desirable operation of the subband generator. An embodiment for obtaining such an operation will be described with reference to the drawings.

First, FIG. 8 will be described. The upper stage is the output of the frequency synthesizer, and the lower stage is one system output in the subband generator. (For ease of explanation, a rectangular wave is used for illustration, but it is actually a digital waveform having a sine wave or a gentle rise / fall.)
The lower part is the output of the series of divide by 4, and the solid line is the signal that is actually output from that series. The broken line waveform is shown for explanation. In the lower part of the figure, after the second pulse is output, it pauses while another series is outputting, and then the output is again from that series. At this time, what is important is that, when the series resumes output, the phase is continuous with the output immediately before the previous stop. That is, the pause period needs to be an integral multiple of one period of the frequency of the series. (In actual operation, when stopping or restarting, there is a high possibility that the waveform will be transiently disturbed. In such a case, the previous stable output is output except for the time when the waveform is transiently disturbed. (It is necessary that the time from the end of the part that is output to the beginning of the part that is stably output after restarting is an integral multiple of one period of the frequency of the series.)
The local generator of the present application is assumed to be used for wireless communication using high-speed frequency hopping. In high-speed frequency hopping, the hopping period and the duration of one frequency are very short. Therefore, on the receiving side, every time a frequency hops, it does not re-synchronize with that frequency, but remembers the synchronization state when the frequency was received last time, and it became the same frequency next time In some cases, there is a high possibility of reception in the same synchronized state. Therefore, if the phase during the period in which the frequency is paused is not maintained, synchronization on the receiving side becomes impossible when resuming. Therefore, it is necessary to operate as shown in FIG.

  In order to realize the phase continuity as shown in FIG. 8, an external control type frequency divider as shown in FIG. 3B, which controls the operation / stop of the output buffer by turning on / off, is used. If the switch is used to control the operation of the series as described above, it can be realized without using a special mechanism. This is because in such a configuration, the frequency dividing operation itself does not stop, and only whether or not to output it to the wiring is controlled.

  However, when a frequency divider that stops the frequency dividing operation itself as shown in FIG. 3A is used, a mechanism for ensuring phase continuity is required.

  First of all, it is necessary to synchronize the timing signal with the frequency synthesizer output. All the frequency dividers in the subband generator operate in synchronization with the frequency synthesizer, so if the timing signal that controls the operation of the frequency divider is not synchronized with the frequency synthesizer output, It is impossible to maintain the phase.

Next, the timing signal is preferably configured as shown in FIG. The external control type frequency divider in the sub-band generator is configured to start counting with the rise of the frequency synthesizer output as a trigger after being instructed by the timing signal, and the initial output at the start of the count is low. It shall be. Therefore, if a predetermined number (in the example of the division by 4 in the figure, the half is twice) is counted, the divider output becomes high and the frequency dividing operation is continued in the same manner. (Normally, in such a circuit, there is a slight delay between input and output, which is not shown here.)
In FIG. 9, the timing signal first instructs the frequency divider to start operation (rising on the left in the figure), then stops, and pauses (not shown). It is preferable that the time until the instructed time is an integral multiple of one period of the divided output of the frequency dividing system (m × T, T in FIG. 9 is one period of the frequency after division, m is an integer). In addition, when the externally controlled frequency divider is operating with the rising edge of the frequency synthesizer as a trigger, the timing signal must be externally controlled so that there is no mistake in counting with the externally controlled frequency divider near the operation start instruction time. It is preferable that the rising edge of the timing signal reaching the frequency divider does not overlap with the rising edge of the frequency synthesizer reaching the external control frequency divider.

  In the example of FIG. 9, since the delay in the IC is not taken into consideration, the timing signal operates with the falling edge of the frequency synthesizer output as a trigger, that is, deviates from the count of the frequency divider by a half cycle. At this time, the problem is that the frequency hopping cycle is mostly determined by the system standard and cannot be freely determined at the time of designing the radio. Therefore, the standard frequency hopping cycle is not always equal to m × T in FIG. In such a case, m is not set to a fixed number, but may be increased or decreased as necessary. FIG. 10 shows such an example.

  In FIG. 10, the upper part shows the frequency hopping period, and the lower part shows the timing signal. FIG. 10 is a diagram in which the horizontal axis is greatly reduced compared to FIGS. 8 and 9. For a constant frequency hopping period, the period of the timing signal is slightly longer at m × T and clearly shorter at (m−1) × T. Therefore, a timing signal having a cycle of (m−1) × T is inserted once every several times of m × T (once in FIG. 3 once). Usually, the frequency hopping period is much longer than the time T corresponding to one frequency after the frequency division, and if it is about T, even if the frequency hopping period is shifted, the reception operation is not greatly affected. At this time, the signal that is output after the frequency division operation is started after (m−1) × T is output before the signal generated in the other frequency series is stopped, and the signal immediately before is not overlapped. It is advisable to stop the series of signals slightly early (about one cycle of the frequency). However, if the adder and frequency converter in the subsequent stage do not saturate, they may be output in an overlapping manner. Of course, if the guard time at the time of switching is set in advance, there is no overlap even if no special action is taken.

  Different embodiments for maintaining phase continuity will be described with reference to FIGS. In this embodiment, as shown in FIG. 11, the period of the timing signal is not limited to an integral multiple of T, and matches the frequency hopping period. However, it is synchronized with the frequency synthesizer output. When phase continuity cannot be guaranteed in synchronization with the frequency hopping period, a mechanism for compensating for this is provided in the external control type frequency divider as shown in FIG. That is, the count number from the start of operation by the timing signal to the rising of the first output (falling when stopped at high when stopped) changes every time. In the figure, the frequency divider counts 2 counts at the time of the first operation start instruction, but the output is raised after the next count is counted 3 counts. In this way, the number of counts up to the first rise is changed each time by the number of counts corresponding to the frequency hopping period and the deviation of m × T. If the number of counts until the first rise is larger than the number of counts for one cycle of the frequency divider output (4 in the figure), reset the count to the number of counts for one cycle, and again in the same way Change it. When decreasing the count every time, when the count reaches 1, the count for one cycle is added. By doing so, it is possible to ensure continuity of phases.

FIG. 13 shows a configuration example of a wireless communication apparatus equipped with the above-described local generator of the present invention. 13A shows a transmission system of the wireless communication apparatus, and FIG. 13B shows a reception system of the wireless communication apparatus. 13A includes a modulator 201 to which data to be transmitted is input, a frequency converter 202 to which an output (LO output 9) from the local generator for high-speed frequency hopping of the present invention is input, a filter 203, a power amplifier 204, and a transmission antenna 205. Data 200 to be transmitted is modulated by a modulator 201. The modulated data is input to the frequency converter 202 and mixed with the upconverting local signal (Lo output 9) generated from the local generator of the present invention. From the local generator
Only one frequency local signal is generated at any time. The signal frequency-converted by the frequency converter 202 is subjected to predetermined filtering processing by the filter 203, amplified by the power amplifier 204, and transmitted from the transmission antenna 205 to the air.

  On the other hand, the receiving system of FIG. 13B includes a receiving antenna 206, a preamplifier 207, a frequency converter 208 to which an output (LO output 9) from the local generator for high-speed frequency hopping of the present invention is input, and a demodulator 209. Composed. Data 210 received by the receiving antenna is amplified by the preamplifier 207 and then input to the frequency converter 208. Here, it is mixed with the down-converting local signal (Lo output 9) generated from the local generator of the present invention. Only one frequency local signal is generated from the local generator at any time. The signal frequency-converted by the frequency converter 202 is demodulated by the demodulator 209, and necessary data 211 is extracted. Note that the transmission antenna 205, the reception antenna 206, and the frequency converters 202 and 208 may be configured in common for transmission and reception.

  The embodiment according to the present invention has been described above. However, the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying constituent elements without departing from the scope of the invention in the implementation stage. In addition, various inventions can be formed by appropriately combining a plurality of components disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, constituent elements over different embodiments may be appropriately combined.

It is a figure which shows 1st Embodiment of this invention. It is a figure for demonstrating operation | movement of a timing signal generation part. It is a figure which shows the structural example of an external control type frequency divider. It is a figure which shows 2nd Embodiment of this invention. It is a figure which shows the form regarding an adder in embodiment of this invention. It is a figure which shows the other example of the form regarding an adder among embodiment of this invention. It is a figure which shows the other example of the form regarding an adder among embodiment of this invention. FIG. 6 is a diagram illustrating a desirable operation of the subband generator. It is a figure which shows embodiment regarding a timing signal. It is a figure which shows embodiment regarding a timing signal. It is a figure which shows embodiment for ensuring the continuity of a phase. It is a figure which shows embodiment for ensuring the continuity of a phase. The structural example of the radio | wireless communication apparatus carrying the local generator of this invention is shown. It is a figure which shows the conventional local generator for high-speed frequency hopping.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1, 101 ... Frequency synthesizer 2, 102 ... Subband generator 3, 17, 103 ... Divider 4 ... Adder 5, 105 ... Frequency converter 6 ... Timing signal Generator 7 ... Wiring 8, 106 ... Data clock output 9 ... LO output 10 ... Divider 11 ... Buffer 14 ... Timing signal 15 ... Retiming clock 16 ... Switch 18 ... OR circuit 19 ... AND circuit 20 ... Current adder output terminal 21 ... Current adder 104 ... Selector

Claims (11)

A frequency synthesizer,
A frequency generation unit that individually generates a signal of each frequency used in frequency hopping from the frequency synthesizer output, and outputs the signal of each frequency to each individual wiring;
Output control means for controlling the output timing to the wiring for each frequency;
An adder that inputs the signal output to the wiring;
A local generator for generating a local signal for frequency hopping by mixing the output of the frequency synthesizer and the output of the adder.   The frequency generation unit is composed of a plurality of systems that generate the signals of the respective frequencies, and each system is used to generate signals of the respective frequencies, and is capable of controlling the operation / stop of the frequency dividing operation. The local generator according to claim 1, further comprising a generator.   3. The local generator according to claim 2, wherein the external control type frequency divider is a final stage of the frequency conversion operation of the system that generates the signal of each frequency. The frequency generation unit includes a plurality of systems that generate signals of each frequency, and in a system in which there is a frequency divider that is used to generate only the signals of the frequency of each system, the frequency divider performs a frequency dividing operation. An external control type frequency divider capable of controlling operation / stopping, and controlling the operation / stop of the output buffer in the external control type frequency divider to control the frequency division operation of the external control type frequency divider. Control operation and stop,
In systems where there is no frequency divider used to generate only signals of each frequency, on / off is configured by a buffer having the same configuration as the output buffer of the external control frequency divider before output to the wiring. 2. The local generator according to claim 1, wherein a switch is arranged to control operation / stop of the on / off switch.   The output control means includes a timing signal generation unit that generates a timing signal that indicates an output timing of the signal of each frequency output from the frequency generation unit, and the timing signal is based on the output of the frequency synthesizer. 4. The local generator according to claim 2, wherein the local generator is generated as a clock and supplied to the frequency generator.   6. The local signal according to claim 5, wherein the timing signal has an integer multiple of a time period corresponding to the frequency from a certain operation instruction to the next operation instruction for each frequency. Generator.   The external control type frequency divider is a digital frequency divider using a counter, and after receiving an operation instruction by the timing signal, the count number of the counter until the first rise or fall of the output is a predetermined amount each time. 6. The local generator of claim 5, wherein the local generator is configured to vary.   In the frequency generation unit, the final stage that outputs the signal of each frequency is configured by a digital circuit, and when the output to the wiring is stopped, the final stage that outputs the signal of each frequency is in a low state. The local generator according to any one of claims 1 to 7, wherein the adder is constituted by an OR circuit.   In the frequency generation unit, the final stage is configured by a digital circuit, and when the output to the wiring is stopped, the final stage outputting each frequency is stopped in a high state, and the adder is an AND circuit. The local generator according to any one of claims 1 to 7, wherein the local generator is configured as follows.   The adder is a current adder, and in the frequency generator, the final stage that outputs the signal of each frequency stops in a state in which no current flows through the adder when the output to the wiring is stopped. The local generator according to any one of claims 1 to 7, wherein the local generator is configured as described above. In a wireless communication apparatus provided with a local generator for generating a signal of a frequency used in a frequency hopping method for performing communication by switching the frequency of a carrier wave,
A frequency synthesizer,
A frequency generation unit that individually generates a signal of each frequency used in frequency hopping from the frequency synthesizer output, and outputs the signal of each frequency to each individual wiring;
Output control means for controlling the output timing to the wiring for each frequency;
An adder that inputs the signal output to the wiring;
A radio communication apparatus, wherein the output of the frequency synthesizer and the output of the adder are mixed to generate a local signal for frequency hopping.

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