JP2005175304A - Electronic component packaging structure and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an electronic component packaging structure which has an electronic component buried in an inter-layer insulating film on a wiring board, and which is prevented from decreasing in yield even if the inter-layer insulating film cracks. <P>SOLUTION: The electronic component 20 having a corner at its outer periphery is packaged on the wiring board, a pattern 13 for cracking protection is arranged nearby outside at least the corner at the outer periphery of the electronic component 20, and the electronic component 20 and pattern 13 for cracking protection are coated with an insulating film 14a. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an electronic component mounting structure and a manufacturing method thereof, and more particularly to an electronic component mounting structure in which a semiconductor chip or the like is mounted on a wiring board in a state where the semiconductor chip is embedded in an insulating film and a manufacturing method thereof.

In response to the demand for higher density mounting technology, multi-chip packages in which a plurality of electronic components are three-dimensionally stacked on a substrate have been developed. As an example, Patent Document 1 discloses that a plurality of semiconductor chips are three-dimensionally mounted on a wiring board in a state of being embedded in an insulating layer, and the semiconductor chip is applied to a wiring pattern formed in multiple layers via the insulating layer. A semiconductor device having a structure in which is flip-chip bonded is described.
JP 2001-196525 A

  However, when a reliability test is performed by applying thermal stress (for example, −55 ° C. to 120 ° C.) to a semiconductor device having a structure in which a rectangular semiconductor chip is embedded in an interlayer insulating film (resin film), as shown in FIG. The crack 104 is likely to be generated in a straight line from the portion of the interlayer insulating film (resin film) 102 adjacent to the corner of the semiconductor chip 100 toward the outside. This is because cracks occur in the weak interlayer insulating film (resin film) due to expansion and contraction caused by thermal stress based on the difference in thermal expansion coefficients of the semiconductor chip (silicon), wiring pattern (copper) and resin film. It is considered a thing.

  When a crack occurs in the interlayer insulating film, the wiring pattern is disconnected or the via hole is opened, which causes a problem that the yield of the semiconductor device is lowered.

  In the above-described Patent Document 1, no consideration is given to the problem that cracks occur in the interlayer insulating film.

  The present invention was created in view of the above problems, and in an electronic component mounting structure having a structure in which an electronic component is embedded in an interlayer insulating film on a wiring board, mounting is performed even if a crack occurs in the interlayer insulating film. It is an object of the present invention to provide an electronic component mounting structure and a method for manufacturing the same, in which a decrease in structure yield is prevented.

  In order to solve the above-described problems, the present invention relates to an electronic component mounting structure, and relates to a wiring board, an electronic component mounted on the wiring board and having corners on the outer periphery, and an outer periphery of the electronic component on the wiring board. And an insulating film covering the electronic component and the crack prevention pattern. The crack prevention pattern is formed at least near the outside of the corner portion.

  In the present invention, an electronic component having a corner portion on the outer periphery (for example, a rectangular thinned semiconductor chip) is mounted on the wiring board, and a crack prevention pattern is formed on a portion of the electronic component near the outside of the corner portion of the electronic component. Is arranged. An insulating film is formed on the electronic component and the crack prevention pattern, and the electronic component is embedded and mounted in the insulating film.

  As described above, when mounting an electronic component having such a corner portion embedded in an insulating film (resin film), when the reliability test is performed by applying thermal stress, the corner of the electronic component is Cracks are likely to occur in a straight line from the portion of the insulating film near the portion to the outside.

  However, in the present invention, since the crack prevention pattern for preventing the progress of the crack of the insulating film is provided near the outside of the corner of the electronic component, the crack of the insulating film is blocked by the crack prevention pattern, and the crack prevention Cracks do not progress in the area outside the pattern for use.

  Accordingly, problems such as disconnection of the wiring pattern connected to the wiring substrate and opening of the via hole are eliminated, and a reduction in the yield of the electronic component mounting structure is prevented.

  The crack prevention pattern only needs to be partially arranged near the outside of at least the corner of the electronic component, but is arranged in a ring shape so as to surround the electronic component near the outside along the outer periphery of the electronic component. It may be.

  In one preferred aspect of the present invention, the wiring board has a structure in which a wiring pattern is formed on an insulating film, and the electronic component is placed in a mounting region where the wiring pattern is not arranged on the insulating film of the wiring board. It is mounted with the surface on which the connection pad is formed facing upward (face-up), and the crack prevention pattern may be formed of the same material as the wiring pattern. In the case of this aspect, the crack prevention pattern is simultaneously formed near the outside of the mounting area in the process of forming the wiring pattern on the wiring board, and then the electronic component is mounted on the mounting area of the wiring board. Thereafter, an insulating film covering the electronic component is formed.

  In one preferred aspect of the present invention, the wiring board has a structure in which a wiring pattern is formed on an insulating film, and the electronic component has a flip chip with a bump of the electronic component on the wiring pattern of the wiring board. The crack prevention pattern may be connected and formed by an inorganic insulating film.

  In this embodiment, the inorganic insulating film is patterned near the outside of the wiring board mounting area where the wiring pattern is exposed to form a crack prevention pattern, and then the bumps of the electronic components are flipped to the wiring pattern in the wiring board mounting area. Chip connected. Thereafter, an insulating film covering the electronic component is formed.

  As described above, even if a crack occurs in the insulating film covering the electronic component from the vicinity of the corner of the electronic component, the progress of the crack is prevented by the crack prevention pattern. Yield reduction is prevented.

  Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

(First embodiment)
2-5 is sectional drawing which shows the manufacturing method of the electronic component mounting structure of 1st Embodiment of this invention. As shown in FIG. 2A, first, a base substrate 10 for manufacturing a build-up wiring substrate is prepared. The base substrate 10 is made of an insulating material such as resin. The base substrate 10 is provided with a through hole 10x, and a through hole plating layer 11a is formed on the inner surface thereof. A first wiring pattern 12 is formed on the base substrate 10, and the first wiring pattern 12 is connected to the through-hole plating layer 11a. Further, the resin body 11b is filled in the through hole 10x.

  Thereafter, as shown in FIG. 2B, a first interlayer insulating film 14 covering the first wiring pattern 12 is formed. As a material for the first interlayer insulating film 14, an epoxy resin, a polyimide resin, a polyphenylene ether resin, or the like is used. After a resin film made of such a material is laminated on the first wiring pattern 12, a resin film is formed by being cured by heat treatment at 80 to 140 ° C. Alternatively, the resin film may be formed by spin coating or printing.

  Next, a first via hole 14x is formed by processing a predetermined portion of the first interlayer insulating film 14 on the first wiring pattern 12 with a laser or the like.

  Subsequently, as shown in FIG. 2C, a second wiring pattern 12 a connected to the first wiring pattern 12 through the first via hole 14 x is formed on the first interlayer insulating film 14. The second wiring pattern is formed by, for example, a semi-additive method. More specifically, after forming a seed Cu layer (not shown) on the inner surface of the first via hole 14x and the first interlayer insulating film 14 by sputtering or electroless plating, a resist film (not shown) having openings of a predetermined pattern. Form. Next, a Cu film pattern is formed in the opening of the resist film by electrolytic plating using the seed Cu film as a plating power feeding layer. Subsequently, after removing the resist film, the seed Cu film is etched using the Cu film pattern as a mask to obtain the second wiring pattern 12a.

  As described above, in the structure in which the semiconductor chip is embedded in the interlayer insulating film (resin film), when thermal stress is applied, cracks tend to occur outward from the portion of the interlayer insulating film adjacent to the corner of the semiconductor chip. . For this reason, in this embodiment, even if a crack occurs in the portion of the interlayer insulating film adjacent to the corner of the semiconductor chip, the crack is prevented from proceeding outward.

  That is, as shown in the lower view (plan view) of FIG. 2C, in the vicinity of the outside of the corner of the mounting area A (area surrounded by the broken line) where the electronic component is mounted on the first interlayer insulating film 14. In the step of forming the second wiring pattern 12a, the crack prevention pattern 13 made of the same material as that is simultaneously formed.

  As a result, a wiring board on which electronic components are mounted (the structure shown in FIG. 2C) is prepared, and the mounting area A is defined on the wiring board.

  Subsequently, as shown in FIG. 3A, a semiconductor chip 20 is prepared in which the connection pads 20a are exposed on the element formation surface and the other portions are covered with the passivation film 20b. The semiconductor chip 20 is thinned to a thickness of about 150 μm (preferably about 50 μm) by grinding the back surface of a semiconductor wafer (not shown) provided with predetermined elements such as transistors and connection pads on the element forming surface side. After that, the semiconductor wafer is diced into individual pieces. In addition, although the semiconductor chip 20 was mentioned as an example of an electronic component, various electronic components, such as a capacitor component, can be used.

  Then, the connection pads 20a of the semiconductor chip 20 are faced up (face up), and the back surface of the semiconductor chip 20 is fixed to the mounting area A (FIG. 2C) of the first interlayer insulating film 14 by the adhesive layer 21. And implement. As a result, as shown in the lower view (plan view) of FIG. 3A, the crack prevention patterns 13 are respectively arranged at positions near the outer side at predetermined intervals from the four corners of the semiconductor chip 20. Become. The crack prevention pattern 13 is preferably arranged so that the side surface thereof is substantially perpendicular to the crack progressing direction (upwardly or downwardly from the corner of the semiconductor chip 20).

  The dimension between the semiconductor chip 20 and the crack prevention pattern 13 may be a dimension that does not allow the semiconductor chip 20 to contact the crack prevention pattern 13 even when the semiconductor chip 20 is displaced. For example, it is set to about 100 μm.

  At this time, the film thickness of the second wiring pattern 12 a and the crack prevention pattern 13 is set to be substantially the same as or greater than the total thickness of the semiconductor chip 20 and the adhesive layer 21. Thereby, the level difference of the semiconductor chip 20 is substantially eliminated by the second wiring pattern 12 a and the crack prevention pattern 13.

  As a modification of the crack prevention pattern 13, as shown in FIG. 3B, it may be formed in a ring shape so as to surround the periphery of the semiconductor chip 20.

  Further, as the crack prevention pattern 13, an inorganic insulating film having high crack resistance such as a silicon oxide film described later in the second embodiment may be used. In this case, before or after forming the second wiring pattern 12a, the inorganic insulating film is patterned at a required position by photolithography, printing, lift-off, or the like.

  Next, as shown in FIG. 4A, a second interlayer insulating film 14a made of the same resin material as that of the first interlayer insulating film 14 is formed on the upper surface of the structure shown in FIG. At this time, since the upper surface of the semiconductor chip 20 and the upper surfaces of the second wiring pattern 12a and the crack prevention pattern 13 are substantially the same height, the second interlayer insulating film 14a is locally formed on the semiconductor chip 20. However, it is formed in a flattened state as a whole.

  As a result, the semiconductor chip 20 is embedded in the flat second interlayer insulating film 14a. In the present embodiment, the crack prevention pattern 13 is arranged near the outside of the four corners of the semiconductor chip 20. Therefore, when a reliability test is performed by applying thermal stress later, even if a crack occurs in the second interlayer insulating film 14a adjacent to the four corners of the semiconductor chip 20, a crack protection pattern Since the progress of the crack is prevented, the crack does not proceed in the outer region.

  Therefore, problems such as the second wiring pattern 12a being disconnected due to a crack generated in the second interlayer insulating film 14a, or the conductor filled in the via hole 14x being broken to open the via hole 14x are eliminated.

  In order to make the function of the crack prevention pattern 13 more reliable, it is important to make the height of the crack prevention pattern 13 higher than the height of the semiconductor chip 20, but the height of the crack prevention pattern 13 is It is set in consideration of the flatness of the second interlayer insulating film 14a.

  Subsequently, as shown in FIG. 4B, the second via hole 14y is formed by processing a predetermined portion of the connection pad 20a of the semiconductor chip 20 and the second interlayer insulating film 14a on the second wiring pattern 12a with a laser or the like. Form.

  Thereafter, as shown in FIG. 4C, the connection pads 20a and the second pads of the semiconductor chip 20 are formed via the second via holes 14y by the same method as the method of forming the second wiring pattern 12a (semi-additive method or the like) described above. A third wiring pattern 12b (upper wiring pattern) connected to each of the two wiring patterns 12a is formed on the second interlayer insulating film 14a. At this time, since the second interlayer insulating film 14a is flattened over the entire surface, defocus does not occur in photolithography when forming the third wiring pattern 12b. 12b can be formed with high accuracy.

  Next, as shown in FIG. 5, a solder resist film 16 having an opening 16x provided on the connection portion 12x of the third wiring pattern 12b is formed on the upper surface of the structure shown in FIG. Subsequently, the upper semiconductor chip 30 (upper electronic component) including the bumps 30a is prepared, and the bumps 30a of the upper semiconductor chip 30 are flip-chip connected to the connection portions 12x of the third wiring pattern 12b. The connection portion 12x of the third wiring pattern 12b is Ni / Au plated.

  At this time, since the connection portion 12x of the third wiring pattern 12b is arranged at substantially the same height on the region above the semiconductor chip 20 and the region where the semiconductor chip 20 does not exist, the bump 30a of the upper semiconductor chip 30 is disposed. Is electrically connected to the connecting portion 12x with high reliability.

  A bump may be formed by mounting a solder ball on the opening 16x of the solder resist 16, and the connection terminals of the upper semiconductor chip 30 may be bonded to the bump.

  Thus, the electronic component mounting structure 1 according to the first embodiment of the present invention is completed.

  In the electronic component mounting structure 1 of the first embodiment, as shown in FIG. 5, a first interlayer insulating film 14 is formed on a base substrate 10 having a first wiring pattern 12, and a first via hole 14x provided in the first interlayer insulating film 14 is formed. A second wiring pattern 12 a connected to the first wiring pattern 12 via the first wiring pattern 12 is formed on the first interlayer insulating film 14. The semiconductor chip 20 is fixed to the mounting region A of the first interlayer insulating film 14 with the connection pads 20a on the upper side (face-up). Then, four crack prevention patterns 13 made of the same material as the second wiring pattern 12 a are formed in the vicinity of the outer sides of the four corners of the semiconductor chip 20 on the first interlayer insulating film 14.

  A second interlayer insulating film 14a is formed on the semiconductor chip 20, the second wiring pattern 12a, and the crack prevention pattern 13, and the semiconductor chip 20 is embedded in the second interlayer insulating film 14a. Implemented in. Second via holes 14y are respectively provided in the connection pads 20a of the semiconductor chip 20 and the portions of the second interlayer insulating film 14a on the second wiring patterns 12a. A third wiring pattern 12b connected to the connection pad 20a of the semiconductor chip 20 and the second wiring pattern 12a through the second via hole 14y is formed on the second interlayer insulating film 14a.

  A solder resist film 16 having an opening 16x provided on the connection portion 12x of the third wiring pattern 12b is formed on the third wiring pattern 12b and the second interlayer insulating film 14a.

  Further, the bump 30a of the upper semiconductor chip 30 is flip-chip connected to the connection portion 12x of the third wiring pattern 12b.

  In the electronic component mounting structure 1 of the present embodiment, since the rectangular semiconductor chip 20 has a structure embedded in the second interlayer insulating film (resin film) 14a, thermal stress (for example, −55 ° C. to 120 ° C.) is applied. When performing the reliability test, cracks are likely to occur outward from the second interlayer insulating film 14a adjacent to the four corners of the semiconductor chip 20.

  However, in this embodiment, since the crack prevention pattern 13 is provided near the outside of the four corners of the semiconductor chip 20, a crack is generated even in the portion of the second interlayer insulating film 14 a near the semiconductor chip 20. Even so, the crack is blocked by the crack prevention pattern 13, and the crack does not advance from the second interlayer insulating film 14 a to the outside.

  Therefore, problems such as disconnection of the second wiring pattern 12a due to occurrence of cracks in the second interlayer insulating film 14a and opening of the second via hole 14y are eliminated, and the yield of the electronic component mounting structure 1 is improved. Is prevented.

  When the crack prevention pattern 13 is formed so as to surround the semiconductor chip 20, the progress of the crack is prevented even when the crack progresses from the portion of the second interlayer insulating film 14 a other than the vicinity of the corner portion of the semiconductor chip 20. Therefore, it is possible to more reliably prevent the yield from being reduced due to cracks.

  In the manufacturing method described above, the process of forming the third wiring pattern 12b from the process of forming the second wiring pattern 12a (including the crack prevention pattern 13) is repeated n times (n is an integer of 1 or more). A plurality of semiconductor chips 20 may be embedded in the interlayer insulating film with the same configuration.

  In addition, a semiconductor chip may be embedded and mounted in an arbitrary interlayer insulating film among a plurality of multilayered interlayer insulating films. Furthermore, a semiconductor chip may be mounted on the back side of the base substrate 10 with the same configuration.

  Even in such a case, since each interlayer insulating film is formed flat, the interlayer insulating film incorporating the semiconductor chip 20 and the wiring pattern can be formed without any problem, and the interlayer insulating film can be formed. A decrease in yield due to the occurrence of cracks in the film is prevented.

(Second Embodiment)
6 to 9 are sectional views showing a method for manufacturing an electronic component mounting structure according to the second embodiment of the present invention. The second embodiment is different from the first embodiment in that the semiconductor chip is mounted face down and the crack prevention pattern is formed of an inorganic insulating film. Detailed description of the same steps and the same elements as those in the first embodiment will be omitted.

  In the manufacturing method of the electronic component mounting structure of the second embodiment, as shown in FIG. 6A, first, a base substrate 10 having the same configuration as that of the first embodiment is prepared, and a first interlayer is formed on the base substrate 10. After forming the insulating film 14, a first via hole 14 x is formed in the portion of the first interlayer insulating film 14 on the first wiring pattern 12. Thereafter, a second wiring pattern 12a connected to the first wiring pattern 12 through the first via hole 14x is formed on the first interlayer insulating film 14 by the same method as in the first embodiment.

  In the second embodiment, since the crack prevention pattern is not formed in the formation process of the second wiring pattern 12a, the film thickness of the second wiring pattern 12a does not need to consider the thickness of the semiconductor chip to be mounted later. In the second embodiment, a mounting region A in which a semiconductor chip is mounted is defined in a region including the second wiring pattern 12a.

  Next, as shown in FIG. 6B, in the vicinity of the outside of the corner of the mounting area A (area surrounded by the broken line) where the semiconductor chip is mounted on the first interlayer insulating film 14 or the second wiring pattern 12a. Then, a crack prevention pattern 13a made of an inorganic insulating film is formed. In the lower diagram (plan view) of FIG. 6B, the second wiring pattern 12a is omitted. In this step, an inorganic insulating film such as a silicon oxide film or a silicon nitride film is patterned on the structure of FIG. 6A by a photolithography method, a printing or a lift-off method, and the crack prevention pattern 13a is obtained. Unlike the organic insulating film (resin film), the inorganic insulating film has high crack resistance, and can function as the crack prevention pattern 13a.

  Next, as shown in FIG. 7A, a resin film having an opening provided in a required portion is prepared, and this resin film is attached to the upper surface of the structure of FIG. 6B and cured by heat treatment. By doing so, the first insulating film 24 provided with the opening 24x exposing the region including the mounting region A and the crack prevention pattern 13a is formed.

  Subsequently, as shown in FIG. 7B, a semiconductor chip 40 (electronic component) having a bump 40a and having a thickness of about 150 μm or less is prepared, and the bump 40a of the semiconductor chip 40 is provided in the mounting region A. Flip chip connection is made to the exposed second wiring pattern 12a.

  As a result, as shown in the lower diagram (plan view) of FIG. 7B, the crack prevention patterns 13a made of the inorganic insulating film are arranged in the vicinity of the outside of the four corners of the semiconductor chip 40, respectively. As described in the first embodiment, the crack prevention pattern 13 a may be formed in a ring shape so as to surround the semiconductor chip 40.

  In the second embodiment, the first insulating film 24 and the crack prevention pattern 13a are formed to have a thickness that is substantially the same as the thickness including the bumps 40a of the semiconductor chip 40. Therefore, as in the first embodiment. The step of the semiconductor chip 40 is almost eliminated.

  Next, as shown in FIG. 8A, the filling resin body 26 is formed by pouring an underfill resin material into the gap on the lower side of the semiconductor chip 40 and the gap on the side surface side of the semiconductor chip 40. As a result, the peripheral region of the semiconductor chip 40 is flattened. Further, a second insulating film 28 covering the semiconductor chip 40 is formed on the entire surface.

  As described above, the second interlayer insulating film 14a constituted by the first insulating film 24, the second insulating film 28, the filling resin body 26, and the crack prevention pattern 13a is formed in a flattened state over the whole, and the semiconductor chip 40 is formed. Is buried in the second interlayer insulating film 14a.

  Subsequently, as shown in FIG. 8B, a second via hole 14y is formed in a predetermined portion of the second interlayer insulating film 14a on the second wiring pattern 12a. Further, as shown in FIG. 8C, the third wiring pattern 12b (upper wiring pattern) connected to the second wiring pattern 12a through the second via hole 14y is formed by the same method as in the first embodiment. It is formed on the two-layer insulating film 14a.

  Next, as shown in FIG. 9, as in the first embodiment, the solder resist film 16 provided with the opening 16x on the connection portion 12x of the third wiring pattern 12b is formed on the upper surface of the structure shown in FIG. To form. Further, the bump 30a of the upper semiconductor chip 30 (upper electronic component) is flip-chip connected to the connection portion 12x of the third wiring pattern 12b.

  Thus, the electronic component mounting structure 1a of the second embodiment is completed.

  In the electronic component mounting structure 1a of the second embodiment, the first interlayer insulating film 14 is formed on the base substrate 10 including the first wiring pattern 12, and the first wiring pattern is formed via the first via hole 14x provided therein. A second wiring pattern 12 a connected to 12 is formed on the first interlayer insulating film 14. The bumps 40a of the semiconductor chip 40 are flip-chip connected to the second wiring pattern 12a, and a crack protection pattern 13a made of an inorganic insulating film is disposed near the outside of the corner of the semiconductor chip 40.

  Further, a resin film 24 having an opening 24x in a region including the semiconductor chip 40 and the crack prevention pattern 13a is formed on the first interlayer insulating film 14 and the second wiring pattern 12a. Further, the filling resin body 26 is filled in the gap on the lower side of the semiconductor chip 40 and the gap on the side surface side of the semiconductor chip 40, and a second resin film 28 that covers the semiconductor chip 40 is formed.

  In this way, the first and second resin films 24 and 28, the filling resin body 26 and the crack prevention pattern 13a constitute the second interlayer insulating film 14a, and the semiconductor chip 40 is embedded in the second interlayer insulating film 14a. Has been implemented.

  A second via hole 14y is formed in the second interlayer insulating film 14a on the second wiring pattern 12a, and a third wiring pattern 12b connected to the second wiring pattern 12a through the second via hole 14y. Is formed on the second interlayer insulating film 14a.

  Further, a solder resist film 16 having an opening 16x is formed on the connection portion 12x of the third wiring pattern 12b, and the bump 30a of the upper semiconductor chip 30 is flip-chip connected to the connection portion 12x of the third wiring pattern 12b. ing.

  In the second embodiment, an example in which the crack prevention pattern 13a made of an inorganic insulating film is provided in a mounting structure in which the semiconductor chip 40 is embedded in the second interlayer insulating film 14a and flip-chip mounted is illustrated. In the second embodiment, even if a crack occurs in the second interlayer insulating film 14a in which the semiconductor chip 40 is embedded, the progress of the crack is prevented by the crack protection pattern 13a made of an inorganic insulating film disposed inside the second interlayer insulating film 14a. Therefore, similarly to the first embodiment, the yield of the electronic component mounting structure 1a is prevented from being lowered.

  Also in the second embodiment, the same modifications and changes as in the first embodiment can be applied.

FIG. 1 is a plan view showing a state in which a crack is generated in an interlayer insulating film in which a semiconductor chip is embedded. 2A to 2C are a cross-sectional view and a plan view (No. 1) showing the method for manufacturing the electronic component mounting structure according to the first embodiment of the present invention. 3A and 3B are a cross-sectional view and a plan view (No. 2) showing the method for manufacturing the electronic component mounting structure according to the first embodiment of the present invention. 4A to 4C are sectional views (No. 3) showing the method for manufacturing the electronic component mounting structure according to the first embodiment of the present invention. FIG. 5: is sectional drawing (the 4) which shows the manufacturing method of the electronic component mounting structure of 1st Embodiment of this invention. 6A and 6B are a cross-sectional view and a plan view (No. 1) showing the method for manufacturing the electronic component mounting structure according to the second embodiment of the present invention. 7A and 7B are a cross-sectional view and a plan view (No. 2) showing the method for manufacturing the electronic component mounting structure according to the second embodiment of the present invention. 8A to 8C are sectional views (No. 3) showing the method for manufacturing the electronic component mounting structure according to the second embodiment of the invention. FIG. 9 is a partial cross-sectional view (No. 4) showing the method for manufacturing the electronic component mounting structure according to the second embodiment of the invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1,1a ... Electronic component mounting structure, 10 ... Base substrate, 11a ... Through-hole plating layer, 11b ... Resin body, 12 ... 1st wiring pattern, 12a ... 2nd wiring pattern, 12b ... 3rd wiring pattern, 12x ... Connection Part, 13, 13a ... crack prevention pattern, 14 ... first interlayer insulating film, 14a ... second interlayer insulating film, 14x ... first via hole, 14y ... second via hole, 16 ... solder resist film, 16x ... opening, DESCRIPTION OF SYMBOLS 20, 40 ... Semiconductor chip (electronic component), 20a ... Connection pad, 20b ... Passivation film | membrane, 21 ... Adhesion layer, 24 ... 1st insulating film, 24x ... Opening part, 26 ... Filling resin body, 28 ... 2nd insulating film , 30 ... Upper semiconductor chip (upper electronic component), 30a, 40a ... Bump, A ... Mounting area.

Claims (18)

A wiring board;
An electronic component mounted on the wiring board and having a corner on the outer periphery;
A crack prevention pattern formed at least near the outside of the corner of the outer periphery of the electronic component on the wiring board;
An electronic component mounting structure comprising: the electronic component and an insulating film covering the crack prevention pattern.   2. The electronic component according to claim 1, wherein the shape of the electronic component is a quadrangle, and the crack prevention patterns are formed in a state of being separated from each other in the vicinity of four corners of the electronic component. Electronic component mounting structure.   2. The electronic component mounting structure according to claim 1, wherein the crack prevention pattern is formed in the vicinity of the outside along the outer periphery of the electronic component so as to surround the electronic component.   The wiring board has a structure in which a wiring pattern is formed on an insulating film, and the electronic component has a connection pad formed in a mounting region of the wiring board on which the wiring pattern is not disposed. It is mounted in a state in which the formed surface is on the upper side, and the crack prevention pattern is formed of the same material as the wiring pattern. Electronic component mounting structure described in 1. Via holes respectively formed in portions of the insulating film on the connection pads and wiring patterns of the electronic components;
5. The device according to claim 4, further comprising an upper wiring pattern formed on an insulating film covering the electronic component and connected to the connection pad of the electronic component and the wiring pattern through the via hole. Electronic component mounting structure.   The wiring board has a structure in which a wiring pattern is formed on an insulating film, and the electronic component has the bump of the electronic component flip-chip connected to the wiring pattern of the wiring board, and the crack prevention The electronic component mounting structure according to claim 1, wherein the pattern for use is formed of an inorganic insulating film. A via hole formed in the insulating film on the wiring pattern;
The electronic component mounting structure according to claim 6, further comprising an upper wiring pattern formed on an insulating film covering the electronic component and connected to the wiring pattern through the via hole.   8. The electronic component mounting structure according to claim 5, wherein bumps of the upper electronic component are flip-chip connected to the upper wiring pattern.   9. The electronic component mounting structure according to claim 1, wherein the electronic component is a semiconductor chip having a thickness of 150 μm or less. Preparing a wiring board having a mounting area corresponding to an electronic component having a corner on the outer periphery;
Forming a crack prevention pattern in the vicinity of the outside of the portion where the corner of the electronic component is disposed in the mounting region of the wiring board;
Mounting the electronic component on the mounting region of the wiring board;
And a step of forming an insulating film covering the electronic component and the crack prevention pattern. The shape of the electronic component is a rectangle, and
In the step of forming the crack prevention pattern, the crack prevention patterns separated from each other are formed in the vicinity of the outside of the portion where the four corners of the electronic component are arranged in the mounting region. The manufacturing method of the electronic component mounting structure of Claim 10.   11. The electron according to claim 10, wherein in the step of forming the crack prevention pattern, the crack prevention pattern is formed in the vicinity of the outside along the outer periphery of the electronic component so as to surround the electronic component. Manufacturing method of component mounting structure. The step of forming the crack prevention pattern includes forming a wiring pattern in a portion excluding the mounting region on the insulating film of the wiring board, and the crack prevention pattern is simultaneously formed of the same material as the wiring pattern. ,
11. The electronic component mounting structure according to claim 10, wherein, in the step of mounting the electronic component, the electronic component is mounted on an insulating film of the wiring board with a connection pad of the electronic component facing upward. . After the step of forming the insulating film,
Forming via holes in the portions of the insulating film on the connection pads of the electronic component and the wiring pattern; and
14. The electronic component mounting according to claim 13, further comprising a step of forming, on the insulating film, an upper wiring pattern connected to the connection pad of the electronic component and the wiring pattern through the via hole. Structure manufacturing method. A wiring pattern is disposed in the mounting region of the wiring board, and the step of forming the crack prevention pattern includes:
It is a step of obtaining the crack prevention pattern by patterning an inorganic insulating film on the wiring board,
11. The method for manufacturing an electronic component mounting structure according to claim 10, wherein in the step of mounting the electronic component, bumps of the electronic component are flip-chip connected to the wiring pattern. After the step of forming the insulating film,
Forming a via hole in the insulating film on the wiring pattern;
The method of manufacturing an electronic component mounting structure according to claim 15, further comprising: forming an upper wiring pattern connected to the wiring pattern through the via hole on the insulating film.   The method of manufacturing an electronic component mounting structure according to claim 14, further comprising a step of flip-chip connecting bumps of the upper electronic component to the upper wiring pattern after the step of forming the upper wiring pattern. .   The method of manufacturing an electronic component mounting structure according to claim 10, wherein the electronic component is a semiconductor chip having a thickness of 150 μm or less.

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