JP2005175227A - Cell structure of standard cell method and its power supply potential wiring method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a cell of a standard cell method which prevents power supply noise generated in power supply wiring from affecting other cells without deteriorating wiring efficiency. <P>SOLUTION: Potential is supplied to a diffusion layer via a contact by using a cell which has the diffusion layer, a contact provided in almost perpendicular direction of the diffusion layer inside a wiring layer A different from the diffusion layer, and vertical wiring which passes through an intermediate layer between the diffusion layer and the wiring layer (a) and connects the diffusion layer and the contact. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a power supply wiring method, and more particularly to a standard cell type power supply wiring method using a library having cells having a plurality of systems of power supply wiring and ground wiring.

  In the standard cell system, a layout of a semiconductor integrated circuit is designed by arranging a plurality of cells having a predetermined function in a one-dimensional direction to form a cell array. At this time, a placement and routing tool using CAD is widely used.

  In this type of conventional placement and routing tool, the layout processing procedure determines the rough layout on the chip according to the floor plan, determines the detailed placement of the cells according to the floor plan, and performs routing. ing.

  For signal wiring other than power supply, various automatic wiring algorithms have been proposed and used. On the other hand, for power supply wiring and ground wiring, generally, a unit structure or unit circuit in which circuit elements are arranged so as to have a predetermined function, so-called cells are arranged in a row, and power supply wiring and ground wiring are incorporated thereon. It is out. In particular, in the case of the standard cell system, the power supply wiring and the ground wiring are incorporated on the cell, and the power supply wiring and the ground wiring of the arranged portion are connected only by arranging the cells side by side.

  Conventional Example 1 relating to a standard cell type cell will be described. Referring to FIGS. 5A and 5B, the inner base of the cell frame 1 is composed of a P-type diffusion layer 2, an N-well 3, and an N-type diffusion layer 4. The power supply wiring 5 is wired in the lowermost metal wiring layer, and is connected to the P-type diffusion layer 2 through the contact 18. Similarly, the ground wiring 6 is wired to the lowermost metal wiring layer, and is connected to the N-type diffusion layer 4 via the contact 19. The input terminal 13 is wired in the metal wiring layer and is connected to the gate polysilicon 15 through a contact. The output terminal 14 is wired in the metal wiring layer, and is connected to the P-type diffusion layer 2 and the N-type diffusion layer 4 through contacts. Here, the description is made with a clock buffer consisting of one set of transistors inside the cell. However, the same applies to a clock buffer in which a plurality of transistors are arranged horizontally and the outputs are enhanced by connecting each input terminal and each output terminal. It is.

  The automatic placement and routing process performed using the cell of the conventional example 1 will be described with reference to FIG. The power supply bus 5 and the ground bus 6 are wired (step S1), then the vertical power supply bus 20 and the vertical ground bus 21 are wired, and are connected to the power supply wiring 5 and the ground wiring 6 via vias (VIA), respectively (step S1). S2). These bus wiring positions are arranged in a line so that the power supply wiring 5 and the ground wiring 6 of the cell of FIG. 5 coincide (step S3). Thus, the power supply potential wirings between the cells are connected to each other at the stage where the cells are arranged. Subsequently, signal lines between the cells are connected (step S4). In this state, the timing is estimated, and it is determined whether or not the design constraint is violated (step S7). If there is a constraint violation, the process returns to step S6 to change the wiring. (Step S8).

  On the other hand, a clock tree synthesis method (hereinafter referred to as CTS) is used as a design method in recent automatic placement and routing. In CTS, clock tree buffers (hereinafter referred to as clock buffers) are randomly arranged in a cell array.

  The clock buffer is switched at high speed, but at this time, switching noise is generated in the power supply wiring. This switching noise affects the operation of other cells in the cell array and becomes a factor of deteriorating characteristics such as operation speed.

  Furthermore, since the clock buffer is a cell that consumes a large amount of power, the current density for the power supply wiring and the ground wiring is exceeded, causing electromigration (EM), which is a factor of deteriorating the life of the product.

  As a proposal to solve these problems, it has been considered to strengthen the power supply wiring and the ground wiring. In Conventional Example 1, it is assumed that the power supply wiring and the ground wiring are wired as shown in FIG. 7A. At this time, for example, as in Conventional Example 2 shown in FIG. 7B, it may be considered that the power supply wiring 5 and the ground wiring 6 of the cell array are strengthened by increasing the width or by increasing the thickness of the metal wiring layer. Alternatively, as in Conventional Example 3 shown in FIG. 7C, it is considered that the number of the vertical power supply wirings 20 and the vertical ground wirings 21 that supply the potential to the cell array is increased and the density of the vertical wirings is increased, thereby strengthening. . In the drawing, three sets of vertical power supply wirings 20 and vertical ground wirings 21 are wired in Conventional Examples 1 and 2, but four sets are wired in Conventional Example 3.

  However, if the power supply wiring 5 and the ground wiring 6 are thickened, the cell density in the vertical direction is deteriorated, and there is a problem that the cost increases due to the increase in the design as a semiconductor product. When the metal wiring layer is made thick, the manufacturing cost increases, which also increases the cost.

  Further, increasing the number of the vertical power supply wirings 20 and the vertical ground wirings 21 increases the power supply wiring and ground wiring areas in the wiring layer, thereby deteriorating the wiring efficiency or reducing the cell arrangement area. Have.

  As another conventional technique related to the present invention, there is a technique described in Patent Document 1. The cell structure described in Patent Document 1 will be described below with reference to FIGS. 8A and 8B.

  The power supply wiring 5 and the power supply wiring 7 are divided, and the power supply wiring 7 is connected to the P-type diffusion layer 2 via the contact 18. The power supply wiring 5 is electrically separated from the inside of the cell. Similarly, the ground wiring 6 and the ground wiring 8 are divided, and the ground wiring 8 is connected to the N-type diffusion layer 4 via the contact 19. The ground wiring 6 is electrically separated from the inside of the cell.

  A plurality of cells are arranged side by side to construct a cell array, and wiring for supplying a potential to the power supply wiring 7 and the ground wiring 8 is drawn from an arbitrary cell array so that a plurality of power supply voltages can be supported in one cell array. Is.

  Similarly, according to another technique described in Patent Document 1, as shown in FIGS. 9A and 9B, a power supply wiring 5 ′ for supplying power having different voltages is wired in an upper wiring layer of the power supply wiring 5. Similarly, a ground power supply 6 ′ is wired in the upper wiring layer of the ground wiring 6. The power supply wiring 5 and the power supply wiring 5 ′ are not connected, and the ground wiring 6 and the ground wiring 6 ′ are not connected.

When a cell array is constructed by arranging a plurality of these cells horizontally, it becomes possible to supply different power supply potentials to the power supply wiring 5 and the power supply wiring 5 ′ and to connect to the power supply wiring 7 inside the cell. Thereby, it is possible to cope with different power supply voltages in the same cell array.
JP 2003-218210 A

  When strengthening the power supply wiring using the technique described in Patent Document 1, the power supply is wired not from the power supply wiring of the cell array including the cell but from another cell array. In other words, current concentration can be avoided by drawing power to be supplied into the cell of the clock buffer with large current consumption from a cell array different from the power supply wiring. However, since the power is supplied from another cell array, the location where the EM is generated moves as a result, which does not provide a fundamental solution.

  Further, since the power supply wiring is independent, it is possible to avoid the influence of EM and switching noise on other cells. However, according to this technique, not only the clock buffer but also the power supply wiring 5 ′ and the ground wiring 6 ′ that may not be used for all the cells of the cell array are wired. For this reason, there is a problem that the wiring efficiency is remarkably deteriorated.

  The present invention has been made in view of the situation as described above, and the problem to be solved by the present invention is to solve the above-mentioned problems and reduce power supply noise generated in the power supply wiring without deteriorating the wiring efficiency. To provide a semiconductor integrated circuit having a cell structure that does not affect other cells, and a power supply wiring method in the semiconductor integrated circuit.

  In order to solve the above-described problems, the present invention provides the following cell, semiconductor integrated circuit, and power supply potential wiring method.

  That is, the present invention relates to a diffusion cell, a contact provided in a wiring layer A different from the diffusion layer and in a substantially vertical direction of the diffusion layer, a diffusion layer, There is provided a cell including a vertical wiring that penetrates an intermediate layer between wiring layers a and connects a diffusion layer and a contact, and supplies a potential to the diffusion layer through the contact.

  According to the conventional cell structure, a potential is supplied to the diffusion layer via a wiring provided in one of the intermediate layers. In general, since the metal wiring layer corresponding to the intermediate layer is thin, the current density is small in the wiring of such a layer. On the other hand, in the structure as described above, the wiring layer a can be thicker than the intermediate layer. Further, the current density of the vertical wiring does not depend on the layer thickness of the intermediate layer. For this reason, according to the cell structure of the present invention, it is possible to give a sufficient cross-sectional area to the wiring from the vertical power supply potential wiring to the diffusion layer.

  From the viewpoint of wiring efficiency, the contact is preferably connected to the vertical power supply potential wiring of the cell array including the cell via the wiring a wired to the wiring layer A.

  It is conceivable that the vertical wiring is formed by connecting the contacts and the intermediate layer to each other through vias.

  In order to effectively prevent the influence of power supply noise in the power supply potential wiring, the intermediate layer is preferably composed of at least three layers.

  In the arranged state, the wiring b for connecting the wiring between two adjacent cells on both sides of the cell is provided in one layer of the intermediate layer, so that the cell having the conventional structure is arranged as in the conventional case. can do.

  A plurality of sets of contacts and vertical wirings may be provided for one diffusion layer. If it does in this way, for example, it will become possible to let other wiring pass between contacts in wiring layer A, and wiring efficiency can be raised more.

  The present invention also provides a semiconductor integrated circuit including the cell as described above.

  Further, according to the present invention, in a method of wiring a power supply potential wiring to a standard cell type cell array, a diffusion layer, a contact provided in a wiring layer A different from the diffusion layer and provided in a substantially vertical direction of the diffusion layer, and a diffusion This is a method of wiring to a cell array including a vertical wiring that passes through an intermediate layer between the layer and the wiring layer A and connects the diffusion layer and the contact, and includes a cell that supplies a potential to the diffusion layer through the contact. Thus, a power supply potential wiring method including the step of wiring a wiring a that connects the contact and the vertical power supply potential wiring of the cell array is provided.

  More specifically, the power supply wiring is sequentially connected from the P-type diffusion layer to at least the third to the third metal wiring layer, and the ground wiring is connected from the N-type diffusion layer to at least the third to the lowest layer. Sequentially connect to the metal wiring layer, make the cell structure electrically separated from the power supply wiring and ground wiring commonly connected between cells, and be close to the cell in the upper metal wiring layer Thus, a cell in which the vertical power supply wiring and the power supply wiring are connected and the vertical ground wiring and the ground wiring are similarly connected is obtained. In addition, a semiconductor integrated circuit including such a cell can be obtained. Further, a power supply potential wiring method using such a cell can be obtained.

  It is possible to prevent the influence of power supply noise generated in the power supply wiring from reaching other cells without reducing the cell arrangement possible area and without deteriorating the wiring efficiency.

  Embodiments of the present invention will be described. In the present specification and claims, the power supply wiring and the ground wiring are collectively referred to as power supply potential wiring. In addition, the vertical power supply wiring and the vertical ground wiring are collectively referred to as a vertical power supply potential wiring.

  In the present invention, like the clock buffer, a cell that generates switching noise in the power supply wiring or exceeds the current density for the power supply wiring and the ground wiring to cause electromigration has the following structure.

  That is, a plurality of metal wiring layers are sandwiched between diffusion layers as intermediate layers, and contacts are provided on the metal wiring layers above the intermediate layers. A wiring connecting the contact and the vertical power supply potential wiring is provided in the same metal wiring layer as the contact, and a potential is supplied to the diffusion layer. The contact and the diffusion layer are connected via vias provided in the intermediate layer. The cells other than those described above have the same cell structure as the conventional one. A layout automatic placement and routing process is performed on the premise of such a cell.

  As a result, the power supply potential wiring for supplying the potential to the diffusion layer of the clock buffer passes through a different path from the wiring for supplying the potential to the other cells and reaches the contact located above the diffusion layer. From the contact, it moves in the direction perpendicular to the diffusion layer via the via and reaches the diffusion layer.

  Since the power supply potential wiring to the clock buffer passes through a position away from the diffusion layer of other cells, it is difficult to adversely affect the operation of other cells. Further, since this cell structure is applied only to the clock buffer, unnecessary wiring does not occur.

  A structure of a cell 100 according to an embodiment of the present invention will be described with reference to FIGS. 1A and 1B. The cell 100 is a clock buffer.

  The internal base of the cell frame 1 is composed of a P-type diffusion layer 2, an N well 3, and an N-type diffusion layer 4.

  The power supply wiring 5 is wired in the lowermost metal wiring layer and is not electrically connected anywhere within the cell. The ground wiring 6 is wired to the lowermost metal wiring layer and is not electrically connected anywhere within the cell. The power supply wiring 5 and the ground wiring 6 are provided for connection to power supply potential wiring of cells other than the clock buffer adjacent to the cell 100.

  The power supply wiring 7 is wired to the lowermost metal wiring layer, and is connected to the P-type diffusion layer 2 via the contact 18. The ground wiring 8 is wired to the lowermost metal wiring layer, and is connected to the N-type diffusion layer 4 through a contact 19. Note that the contacts 18 and 19 are not shown in FIG. 1A for convenience of drawing.

  The power supply wiring 9 is wired in an upper layer than the lowermost layer where the power supply wiring 7 is wired, and is connected through a via provided in a layer between both layers. That is, they are connected through vias provided in a plurality of metal wiring layers arranged and wired on the upper layer of the power supply wiring 7. As can be seen from FIG. 1B being the AA ′ cross section of FIG. 1A, this via is a power supply potential supply wiring extending in the vertical direction from the diffusion layer, such as a metal wiring layer directly above the diffusion layer or a nearby upper metal wiring layer. Compared with the case of wiring with a relatively thin layer, the vertical wiring has a large cross-sectional area. Thereby, it is possible to prevent the influence of the power supply noise generated in the power supply wiring from reaching other cells. In order to effectively remove the influence of power supply noise, it is desirable that the plurality of metal wiring layers serving as intermediate layers be at least three layers. In this example, three metal wiring layers are used as an intermediate layer.

  Similar to the power supply wiring 9, the ground wiring 10 is wired above the lowermost layer where the ground wiring 8 is wired. In this example, the ground wiring 10 is wired in the same layer as the power wiring 9, and three metal wiring layers are sandwiched between the layers where the ground wirings 8 and 10 are wired, and vias provided in these metal wiring layers are provided. The ground wiring 8 and the ground wiring 10 are connected to each other.

  The input terminal 13 is wired in the metal wiring layer and is connected to the gate polysilicon 15 through a contact. The output terminal 14 is wired in the metal wiring layer, and is connected to the P-type diffusion layer 2 and the N-type diffusion layer 4 through contacts.

  The power supply wiring 16 is wired so as to connect the power supply wiring 7 and the power supply wiring 9 vertically, and each wiring layer is connected by a via 11. The ground wiring 17 is wired so as to connect the ground wiring 7 and the ground wiring 9 vertically, and each wiring layer is connected by a via 12.

  An automatic placement and routing process using the cell 100 according to the first embodiment will be described with reference to FIGS. The clock buffer 22 has a structure like the cell 100. For ease of understanding, only the clock buffer 22 is shown in FIG. 3, and the description of other cells is omitted.

  In step S1, the wiring positions of the power supply wiring 5 and the ground wiring 6 of each cell are determined. In step S2, the vertical power supply wiring 20 and the vertical ground wiring 21 are wired, and the vertical power supply wiring 20 and the vertical ground wiring 21 are connected to the power supply wiring 5 and the ground wiring 6 through vias, respectively. In step S3, cells are arranged.

  In step S 4, the power supply wiring 9 and the vertical power supply wiring 20 are connected by the power supply wiring 23. The power supply wiring 23 is wired on the same metal wiring layer as the power supply wiring 9. At this time, the power supply wiring 23 is wired so that the wiring length is the shortest.

  Similarly, in step S5, the ground wiring 10 and the vertical ground wiring 21 are connected by the ground wiring 24. The ground wiring 24 is also wired on the same metal wiring layer as the ground wiring 10 so that the wiring length is the shortest.

  In step S6, signal lines between the cells are connected.

  In step S7, it is verified whether there are violations of various restrictions in the wired state. That is, it is determined whether or not the timing constraint is violated based on the cell timing information that is the timing information of each cell to be arranged and the preset timing constraint. If there is a violation, the process returns to step S6 to rewire.

  Note that a cell that does not cause switching noise in the power supply wiring and does not cause electromigration by exceeding the current density with respect to the power supply wiring and the ground wiring, as in the clock buffer, is similar to the cell 100. It is not necessary to have a simple structure, and a cell structure similar to the conventional one may be used.

  According to the cell 100 of Example 1 and the automatic placement and routing process using the cell 100, it is possible to prevent the influence of switching noise and electromigration from reaching other cells without performing excessive wiring.

  In the cell 100 according to the first embodiment described above, the power supply wirings 7, 9 and 16 are in contact with the lower layer wiring at two locations, respectively, but are formed integrally. The same applies to the ground wirings 8, 10 and 17.

  On the other hand, in the cell 200 of the second embodiment, as shown in FIGS. 4A and 4B, the power supply terminal 9a and the power supply terminal 9b are physically independent and are electrically connected to the same P-type diffusion layer 2. Has been. In addition, the ground terminal 10a and the ground terminal 10b are physically independent and are electrically connected to the same N-type diffusion layer 4. Similarly, the power supply wirings 16a and 16b in the intermediate layer are physically independent, and connect the power supply terminal 9a and the power supply terminal 7a, respectively, and connect the power supply terminal 9b and the power supply terminal 7b. Similarly, the ground wirings 17a and 17b in the intermediate layer are physically independent and connect the ground terminal 10a and the ground terminal 8a, respectively, and connect the ground terminal 10b and the ground terminal 8b.

  As described above, in the cell 100, the power supply wiring / ground wiring integrated in each metal wiring layer is divided into two power supply terminals and two ground terminals in the cell 200, respectively. As a result, it is possible to pass other wiring between the power supply terminals and between the ground terminals, and the wiring efficiency can be further improved.

  The present invention has been described above based on the embodiments. However, the present invention is not limited to this, and it is needless to say that modifications and improvements can be made within the ordinary knowledge of those skilled in the art. .

  For example, in the first and second embodiments, a case where three metal wiring layers are sandwiched as an intermediate layer between the lowermost metal wiring layer and the metal wiring layer to which the vertical power supply wiring and the vertical ground wiring are connected is an example. However, the number of intermediate layers is not limited to three.

  Further, in the first embodiment, the power supply wirings 7, 9, 16 and the ground wirings 8, 10, 17 are all integrated, and in the second embodiment, the power supply terminals corresponding to these are divided into two parts. A metal wiring layer including the metal wiring layer including two pairs of power supply electrodes may be mixed.

It is a top view showing the structure of the cell 100 which is Example 1 of this invention. It is sectional drawing in line A-A 'of FIG. 1A. 4 is a flowchart for explaining automatic placement and routing processing using a cell 100. FIG. 3 is a diagram for explaining a connection between a cell 100 (clock buffer 22) arranged in the automatic arrangement and wiring process of FIG. 2 and a vertical power supply wiring 20 and a vertical ground wiring 21; It is a top view showing the structure of the cell 200 which is Example 2 of this invention. It is sectional drawing in line B-B 'of FIG. 4A. It is a top view which shows the structure of the cell of the prior art example 1. FIG. It is sectional drawing of line C-C 'of FIG. 5A. It is a flowchart for demonstrating the automatic arrangement | positioning wiring process using the cell of the prior art example 1. FIG. It is a figure for demonstrating the power supply wiring 5, the ground wiring 6, the vertical power supply wiring 20, and the vertical ground wiring 21 which were arrange | positioned by the prior art example 1. FIG. It is a figure for demonstrating the power supply wiring 5, the ground wiring 6, the vertical power supply wiring 20, and the vertical ground wiring 21 which were arrange | positioned by the prior art example 2. FIG. It is a figure for demonstrating the power supply wiring 5, the ground wiring 6, the vertical power supply wiring 20, and the vertical ground wiring 21 which were arrange | positioned by the prior art example 3. FIG. 10 is a plan view showing the structure of a cell described in Patent Document 1. FIG. It is sectional drawing of line D-D 'of FIG. 8A. 10 is a plan view showing the structure of a cell described in Patent Document 1. FIG. It is sectional drawing of line E-E 'of FIG. 9A.

Explanation of symbols

1 Cell frame 2 P-type diffusion layer 3 N well 4 N-type diffusion layer 5, 7, 9, 23 Power supply wiring 6, 8, 10, 24 Ground wiring 11, 12, 18, 19 Via (VIA)
20 Vertical power supply wiring 21 Vertical ground wiring 22 Clock buffer 100, 200 cells

Claims (13)

In a standard cell type cell constituting a semiconductor integrated circuit,
A diffusion layer, a contact provided in the wiring layer A different from the diffusion layer and provided in a substantially vertical direction of the diffusion layer, and an intermediate layer between the diffusion layer and the wiring layer a; A vertical wiring connecting the contact,
A cell, wherein a potential is supplied to the diffusion layer through the contact.   2. The cell according to claim 1, wherein the contact is connected to a vertical power supply potential wiring of a cell array including the cell via a wiring a wired in the wiring layer A. 3.   2. The cell according to claim 1, wherein the vertical wiring is formed by connecting each of the contact and the intermediate layer to each other through a via.   The cell according to claim 1, wherein the intermediate layer includes at least three layers.   2. The cell according to claim 1, further comprising a wiring b for connecting a wiring between two adjacent cells adjacent to both sides of the cell in a state of being arranged in one layer of the intermediate layer. .   The cell according to claim 1, wherein a plurality of sets including the contact and the vertical wiring are provided for one diffusion layer.   A semiconductor integrated circuit comprising the cell according to claim 1. In the method of wiring the power supply potential wiring to the standard cell type cell array,
A diffusion layer, a contact provided in the wiring layer A different from the diffusion layer and provided in a substantially vertical direction of the diffusion layer, and an intermediate layer between the diffusion layer and the wiring layer A; A method of wiring a cell array including a cell that includes a vertical wiring that connects the contact and supplies a potential to the diffusion layer via the contact,
A power supply potential wiring method comprising the step of wiring a wiring a that connects the contact and the vertical power supply potential wiring of the cell array.   9. The power supply potential wiring method according to claim 8, wherein the wiring a is wired to the wiring layer A.   9. The power supply potential wiring method according to claim 8, wherein the vertical wiring is formed by connecting each of the contact and the intermediate layer to each other through a via.   9. The power supply potential wiring method according to claim 8, wherein the intermediate layer includes at least three layers.   9. The power supply potential wiring method according to claim 8, wherein in the state in which the cell is arranged, a wiring b for connecting a wiring between two adjacent cells on both sides of the cell is formed in one layer of the intermediate layer. A power supply potential wiring method comprising:   9. The power supply potential wiring method according to claim 8, wherein the cell includes a plurality of sets of the contact and vertical wiring for one diffusion layer.

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