JP2005174991A - Semiconductor device, method of manufacturing the same, circuit board and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device in which bonding reliability between electrodes can be improved in the semiconductor device mounted three-dimensionally. <P>SOLUTION: In the method of manufacturing the semiconductor device, the side face of the distal end of the electrode 34 is exposed together with the distal end face, by polishing the distal end of the electrode 34 projected from the rear surface 10b of a semiconductor board 10 with a polishing cloth 93 supported through an elastic element 92. According to this constitution, when the electrodes 34 of a semiconductor chip laminated up and down are bonded, a bonding member can be held in the side face in addition to the distal end face, and mechanical and electrical connection reliability can be improved. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a semiconductor device, a semiconductor device, a circuit board, and an electronic apparatus.

  Portable electronic devices such as mobile phones, notebook personal computers, and personal data assistance (PDA) are required to be small and light. Along with this, the mounting space of the semiconductor chip in the electronic device described above is extremely limited, and high-density mounting of the semiconductor chip has become a problem. Therefore, a three-dimensional mounting technique has been devised. The three-dimensional mounting technique is a technique for achieving high-density mounting of semiconductor chips by stacking semiconductor chips and wiring-connecting the semiconductor chips. (For example, see Patent Document 1)

FIG. 15 is a side sectional view showing a state in which semiconductor chips are stacked. As shown in FIG. 15, a plurality of electrodes 34 are formed on each semiconductor chip 2 used in the three-dimensional mounting technique. The electrode 34 is formed so as to penetrate the semiconductor chip 2 from an electrode pad (not shown) formed on the active surface 10 a of the semiconductor chip 2 to the back surface 10 b of the semiconductor chip 2.
In order to form the electrode 34, first, a recess is formed from the active surface 10a of the semiconductor substrate to the inside, an insulating film is formed therein, and a conductive material is filled inside. At this time, the tip of the electrode 34 is disposed inside the semiconductor substrate. Therefore, it is necessary to expose the tip of the electrode 34 from the back surface 10b of the semiconductor substrate.

FIG. 21 is an explanatory diagram of the electrode tip exposure method according to the prior art, and is an enlarged view of the periphery of the electrode tip. As shown in FIG. 21A, the front end portion of the electrode 34 disposed inside the semiconductor substrate 10 is exposed from the back surface 10 b of the semiconductor substrate 10. First, as shown in FIG. 21B, the back surface 10 b of the semiconductor substrate 10 is etched to expose the tip of the insulating film 22. For this etching, either dry etching or wet etching can be used. Next, as shown in FIG. 21C, the insulating film 22 covering the tip of the electrode 34 is removed by polishing, and the tip of the electrode 34 is exposed. The insulating film 22 may be removed by etching simultaneously with the etching of the back surface 10b of the semiconductor substrate 10. In this way, the electrode 34 penetrating the semiconductor substrate 10 is formed.
JP 2002-25948 A

  FIG. 12B is an enlarged view of the electrode bonding portion when the semiconductor chips are stacked according to the related art. When the semiconductor chips formed as described above are stacked, the electrodes 34 of the respective semiconductor chips are bonded via the solder layer 40. However, in the semiconductor chip according to the prior art, since the insulating film 22 disposed at the tip of the electrode 34 is removed by planar polishing, the tip surface 37a of the electrode 34 is exposed planarly. In this case, the solder layer 40 is accommodated only in the tip surface 37a of the electrode 34, and improvement in mechanical and electrical joining reliability is desired.

The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a semiconductor device manufacturing method capable of improving the bonding reliability of electrodes.
It is another object of the present invention to provide a highly reliable semiconductor device, circuit board, and electronic device.

In order to achieve the above object, a manufacturing method of a semiconductor device of the present invention is a manufacturing method of a semiconductor device having an electrode penetrating a semiconductor substrate, by polishing a tip portion of the electrode protruding from the semiconductor substrate. The side surface of the tip of the electrode is exposed together with the tip of the electrode.
According to this configuration, when joining the electrodes of the semiconductor devices stacked one above the other, the joining member can be accommodated on the side surface in addition to the tip end surface of the electrode. Thereby, mechanical and electrical joining reliability can be improved.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device having an electrode penetrating a semiconductor substrate, wherein a recess is formed from an active surface of the semiconductor substrate on which an integrated circuit is formed to an inside thereof. A step of forming a first insulating layer on the inner surface of the recess, a step of filling the first insulating layer with a first conductive material to form the electrode, and removing a back surface of the semiconductor substrate. Exposing the first insulating layer disposed at the tip of the electrode, polishing the first insulating layer, and exposing the side surface of the tip of the electrode together with the tip of the electrode; It is characterized by having.
According to this configuration, when joining the electrodes of the semiconductor devices stacked one above the other, the joining member can be accommodated on the side surface in addition to the tip end surface of the electrode. Thereby, mechanical and electrical joining reliability can be improved.

The polishing is preferably performed by bringing a polishing means into contact with the tip of the electrode, and the semiconductor substrate or the polishing means is preferably supported via a first elastic member.
According to this configuration, since the semiconductor substrate or the polishing unit is supported via the first elastic member, the semiconductor substrate or the polishing unit is freely deformed so as to wave. Thus, it is possible to perform polishing by bringing the polishing means into contact with the entire tip of the electrode protruding from the semiconductor substrate. Therefore, the side surface of the tip portion of the electrode can be exposed together with the tip surface of the electrode.

The polishing is preferably performed by bringing a polishing means made of a second elastic member into contact with the tip of the electrode. The second elastic member is preferably a raised brush disposed on the surface of the polishing pad.
According to this configuration, since the polishing means is constituted by the second elastic member, the polishing means can be brought into contact with the entire tip portion of the electrode protruding from the semiconductor substrate for polishing. Therefore, the side surface of the tip portion of the electrode can be exposed together with the tip surface of the electrode.

Moreover, it is desirable to have the process of forming a 2nd insulating layer in the back surface of the said semiconductor substrate.
According to this configuration, even when the bonding member between the electrodes is deformed when the semiconductor devices are stacked, it is possible to prevent a short circuit between the bonding member and the back surface of the semiconductor substrate. Therefore, a short circuit between the signal line and the ground can be prevented.

Moreover, it is desirable to remove the second insulating layer formed at the tip of the electrode by the polishing.
According to this configuration, the manufacturing process can be simplified, and the manufacturing cost can be reduced.

Also, an electrode cap made of a conductive material that is less oxidized than the constituent material of the electrode is formed at the tip of the electrode, and the side surface of the tip of the electrode cap is exposed together with the tip of the electrode cap by the polishing. It is desirable.
According to this configuration, it is possible to prevent the wettability from being deteriorated due to oxidation of the electrode of the semiconductor device. Therefore, even when the semiconductor devices are stacked after a long time has elapsed since the formation of the semiconductor device, the electrodes can be joined to each other, so that a conduction failure between the electrodes can be avoided.

On the other hand, the semiconductor device of the present invention is manufactured by using the semiconductor device manufacturing method described above.
According to this configuration, a highly reliable semiconductor device can be provided.

Alternatively, a plurality of the semiconductor devices described above may be stacked, and the electrodes of the semiconductor devices adjacent above and below may be electrically connected.
According to this configuration, it is possible to improve the reliability of a small semiconductor device mounted with high density.

On the other hand, the circuit board of the present invention is characterized in that the semiconductor device described above is mounted.
According to this configuration, a highly reliable circuit board can be provided.

On the other hand, an electronic apparatus according to the present invention includes the semiconductor device described above.
According to this configuration, a highly reliable electronic device can be provided.

  Embodiments of the present invention will be described below with reference to the drawings. In each drawing used for the following description, the scale of each member is appropriately changed to make each member a recognizable size.

[First Embodiment]
First, a semiconductor chip which is a first embodiment of a semiconductor device according to the present invention will be described with reference to FIG.
FIG. 1 is a side sectional view of an electrode portion of a semiconductor chip according to the present embodiment. The semiconductor chip 2 according to the present embodiment includes a first insulating material in a semiconductor substrate 10 on which an integrated circuit is formed and a through hole H4 formed from the active surface 10a of the semiconductor substrate 10 to the back surface 10b of the semiconductor substrate 10. The electrode 34 is formed through the insulating film 22 that is a layer, and the insulating film 26 that is a second insulating layer formed on the back surface 10 b of the semiconductor substrate 10.

[Semiconductor device]
In the semiconductor chip 2 shown in FIG. 1, an integrated circuit (not shown) made of transistors, memory elements, and other electronic elements is formed on an active surface 10a of a semiconductor substrate 10 made of Si (silicon) or the like. An insulating film 12 made of SiO ₂ (silicon oxide) or the like is formed on the active surface 10 a of the semiconductor substrate 10. Further, an interlayer insulating film 14 made of borophosphosilicate glass (hereinafter referred to as BPSG) or the like is formed on the surface of the insulating film 12.

  An electrode pad 16 is formed on a predetermined portion of the surface of the interlayer insulating film 14. The electrode pad 16 includes a first layer 16a made of Ti (titanium) or the like, a second layer 16b made of TiN (titanium nitride) or the like, a third layer 16c made of AlCu (aluminum / copper) or the like, and TiN or the like. The fourth layer (cap layer) 16d is formed by sequentially stacking. Note that the constituent material of the electrode pad 16 may be appropriately changed according to the electrical characteristics, physical characteristics, and chemical characteristics required for the electrode pad 16. That is, the electrode pad 16 may be formed using only Al generally used as an electrode of the integrated circuit, or the electrode pad 16 may be formed using only Cu having a low electric resistance.

  The electrode pads 16 are formed side by side in the periphery of the semiconductor chip 2 in plan view. The electrode pad 16 may be formed side by side in the periphery of the semiconductor chip 2 or may be formed side by side in the center. When formed in the peripheral portion, the semiconductor chip 2 is formed side by side along at least one side (in many cases, two or four sides). Each electrode pad 16 is electrically connected to the integrated circuit described above at a location not shown. It should be noted that no integrated circuit is formed below the electrode pad 16.

A passivation film 18 is formed on the surface of the interlayer insulating film 14 so as to cover the electrode pad 16. The passivation film 18 is made of SiO ₂ (silicon oxide), SiN (silicon nitride), polyimide resin, or the like, and has a thickness of, for example, about 1 μm.

In the central portion of the electrode pad 16, an opening H1 that penetrates the passivation film 18 and the fourth layer 16d of the electrode pad 16, and an opening that penetrates the remaining electrode pad 16, the interlayer insulating film 14, and the insulating film 12 are provided. H2 is formed. The diameter of the opening H2 is smaller than the diameter of the opening H1, and is set to about 60 μm, for example. On the other hand, an insulating film 20 made of SiO ₂ (silicon oxide) or the like is formed on the surface of the passivation film 18 and the inner surfaces of the opening H1 and the opening H2. This insulating film 20 functions as a mask when the hole H3 described below is formed.

  A hole H3 that penetrates the semiconductor substrate 10 is formed in the center of the electrode pad 16. The diameter of the hole H3 is smaller than the diameter of the opening H2, for example, about 30 μm. The hole H3 is not limited to a circular shape in plan view, and may be formed in a rectangular shape in plan view. The opening H1, the opening H2, and the hole H3 form a through hole H4 that penetrates from the active surface to the back surface of the semiconductor substrate.

An insulating film 22 as a first insulating layer is formed on the inner surface of the through hole H4 and the surface of the insulating film 20. The insulating film 22 prevents current leakage and erosion due to oxygen or moisture, and is formed to a thickness of about 1 μm by an electrically insulating material such as SiO ₂ or SiN. The insulating film 22 is formed so as to protrude from the back surface 10 b of the semiconductor substrate 10. On the other hand, the insulating film 20 and the insulating film 22 are partially removed at the P portion on the surface of the third layer 16 c of the electrode pad 16.

  A base film 24 is formed on the exposed surface of the third layer 16 c of the electrode pad 16 and the remaining surface of the insulating film 22. The base film 24 includes a barrier layer (barrier metal) formed on the surface of the insulating film 22 and the like, and a seed layer (seed electrode) formed on the surface of the barrier layer. The barrier layer prevents the constituent material of the electrode 34 described later from diffusing into the substrate 10 and is made of TiW (titanium tungsten), TiN (titanium nitride), TaN (tantalum nitride), or the like. On the other hand, the seed layer serves as an electrode when an electrode 34 described later is formed by plating, and is made of Cu, Au, Ag, or the like.

  An electrode 34 is formed inside the base film 24. The electrode 34 is made of a conductive material having a low electrical resistance such as Cu or W. Note that if the electrode 34 is formed of a conductive material in which poly-Si (polysilicon) is doped with impurities such as B and P, it is not necessary to prevent diffusion to the substrate 10, so that the barrier layer described above becomes unnecessary. . And the plug part 36 of the electrode 34 is formed by forming the electrode 34 in the through-hole H4. The lower end surface of the plug portion 36 is exposed to the outside. On the other hand, the post 34 of the electrode 34 is formed by extending the electrode 34 also above the electrode pad 16. The post portion 35 is not limited to a circular shape in plan view, and may be formed in a rectangular shape in plan view. Note that the post portion 35 and the electrode pad 16 are electrically connected via the base film 24 at the P portion in FIG.

  A solder layer 40 is formed on the upper surface of the post portion 35 of the electrode 34. The solder layer 40 may be formed of a general PbSn alloy or the like, but is preferably formed of a lead-free solder material such as an AgSn alloy from the viewpoint of the environment. Instead of the solder layer 40 which is a soft wax material, a hard wax material (molten metal) layer made of SnAg alloy or the like, or a metal paste layer made of Ag paste or the like may be formed. It is preferable from the viewpoint of the environment and the like that the hard wax material layer and the metal paste layer are also formed of a lead-free material.

On the other hand, an insulating film 26 that is a second insulating layer is formed on the back surface 10 b of the semiconductor substrate 10. The insulating film 26 is made of an inorganic material such as SiO ₂ (silicon oxide) or SiN (silicon nitride), or an organic material such as PI (polyimide). The insulating film 26 is formed on the entire back surface 10 b of the semiconductor substrate 10 except for the lower end surface of the plug portion 36 of the electrode 34. Note that the insulating film 26 may be selectively formed only around the tip of the electrode 34 on the back surface 10 b of the semiconductor substrate 10.

  Further, the tip end surface of the plug portion 36 of the electrode 34 on the back side of the substrate 10 is formed so as to protrude from the surface of the insulating film 26. The protruding height of the plug part 36 is, for example, about 10 μm to 20 μm. Thereby, when laminating a plurality of semiconductor chips, a space between the semiconductor chips can be ensured, so that the gaps between the semiconductor chips can be easily filled with underfill or the like. Note that by adjusting the protruding height of the plug portion 36, the interval between the stacked semiconductor chips can be adjusted. Further, instead of filling underfill or the like after the lamination, even when a thermosetting resin or the like is applied to the back surface 10b of the semiconductor chip 2 before the lamination, the thermosetting resin or the like is applied while avoiding the protruding plug portion 36. Therefore, the semiconductor chip wiring connection can be reliably performed.

Further, at the tip of the plug portion 36 of the electrode 34, the side surface 37b is exposed together with the tip surface 37a. That is, the insulating film 22 and the base film 24 disposed so as to cover the electrode 34 are removed from the front end surface 37 a to the side surface 37 b at the lower end portion of the electrode 34. In addition, the chamfering may be given to the peripheral part of the front end surface 37a of the electrode 34.
The semiconductor chip 2 according to the present embodiment is configured as described above.

FIG. 2 is a side cross-sectional view of an electrode portion of a modification of the semiconductor chip according to the first embodiment. As shown in FIG. 2, an electrode cap 38 may be formed at the tip of the plug portion 36 of the electrode 34. The electrode cap 38 is made of a conductive material that is less likely to be oxidized than the constituent material of the electrode 34, and is made of, for example, a metal having a low ionization tendency. Specifically, the electrode cap 38 is formed of Au, Ag, Pt (platinum), Pd (palladium), or the like. The electrode cap 38 is formed so as to cover the entire tip end surface of the plug portion 36. Thereby, it can prevent that the front end surface of the plug part 36 is oxidized. The electrode cap may be formed so as to cover a part of the tip surface of the plug portion 36. Even in this case, since the plug portion 36 can be prevented from being oxidized at the portion where the electrode cap is formed, the electrodes can be joined to each other when the semiconductor chips are stacked. Therefore, it is possible to avoid poor conduction between the electrodes.
When the electrode cap 38 is formed, the side surface 37b at the distal end portion of the electrode cap 38 is exposed together with the distal end surface 37a of the electrode cap 38.

[Production method]
Next, the semiconductor chip manufacturing method according to the present embodiment will be described with reference to FIGS. 3 to 7 are explanatory diagrams of the semiconductor chip manufacturing method according to the present embodiment. The semiconductor chip manufacturing method according to the present embodiment includes a step of forming a recess H0 from the active surface to the inside of the semiconductor substrate 10, a step of forming an insulating film 22 on the inner surface of the recess H0, and a step inside the insulating film 22. (1) filling the conductive material to form the electrode 34; etching the back surface 10b of the semiconductor substrate 10 to expose the tip of the insulating film 22; polishing the tip of the insulating film 22; And a step of exposing the tip surface 37a and the side surface 37b in the tip portion. In the following, a case where a plurality of semiconductor chip formation regions in a semiconductor substrate are simultaneously processed will be described as an example. However, the following processing may be performed on each semiconductor chip.

  First, as shown in FIG. 3A, the insulating film 12 and the interlayer insulating film 14 are formed on the surface of the semiconductor substrate 10. Then, an electrode pad 16 is formed on the surface of the interlayer insulating film 14. Specifically, first, the first to fourth layers of the electrode pad 16 are sequentially formed on the entire surface of the interlayer insulating film 14. Each film is formed by sputtering or the like. Next, a resist or the like is applied to the surface. Further, the final shape of the electrode pad 16 is patterned on the resist by photolithography. Then, etching is performed using the patterned resist as a mask to form electrode pads in a predetermined shape (for example, a rectangular shape). Thereafter, a passivation film 18 is formed on the surface of the electrode pad 16.

  Next, an opening H <b> 1 is formed in the passivation film 18. Specifically, a resist or the like is first applied to the entire surface of the passivation film. The resist may be a photoresist, an electron beam resist, an X-ray resist, or the like, and may be either a positive type or a negative type. The resist is applied by spin coating, dipping, spray coating, or the like. Note that pre-baking is performed after the resist is applied. Then, the resist is exposed using a mask in which the pattern of the opening H1 is formed, and further developed to pattern the shape of the opening H1 in the resist. Note that post-baking is performed after resist patterning.

  Then, the passivation film 18 is etched using the patterned resist as a mask. In the present embodiment, the fourth layer of the electrode pad 16 is also etched together with the passivation film 18. As the etching, wet etching can be employed, but dry etching is preferably employed. The dry etching may be reactive ion etching (RIE). Note that after the opening H1 is formed in the passivation film 18, the resist on the passivation film 18 is stripped with a stripping solution. As described above, as shown in FIG. 3A, the opening H1 is formed in the passivation film 18, and the electrode pad 16 is exposed.

  Next, as shown in FIG. 3B, an opening H <b> 2 is formed in the electrode pad 16, the interlayer insulating film 14, and the insulating film 12. Specifically, a resist or the like is applied to the entire exposed electrode pad 16 and passivation film 18 to pattern the shape of the opening H2. Next, the electrode pad 16 is dry-etched using the patterned resist as a mask. Note that RIE can be used for dry etching. Thereafter, when the resist is peeled off, an opening H2 is formed in the electrode pad 16 as shown in FIG.

Next, as shown in FIG. 3C, an insulating film 20 is formed on the entire upper surface of the substrate 10. The insulating film 20 functions as a mask when the hole H3 is drilled in the substrate 10 by dry etching. The film thickness of the insulating film 20 is set to about 2 μm, for example, depending on the depth of the hole H3 drilled in the substrate 10. In the present embodiment, SiO ₂ is used as the insulating film 20, but a photoresist may be used as long as the selection ratio with Si can be obtained. Further, the insulating film 20 is formed of tetraethyl silicate (Si (OC ₂ H ₅ ) ₄ : hereinafter referred to as TEOS), that is, PE-TEOS, formed by using PECVD (Plasma Enhanced Chemical Vapor Deposition). Alternatively, O ₃ -TEOS which is thermal CVD using ozone, silicon oxide formed using CVD, or the like can be used.

  Next, the shape of the hole H3 is patterned in the insulating film 20. Specifically, a resist or the like is first applied to the entire surface of the insulating film 20, and the shape of the hole H3 is patterned. Next, the insulating film 20 is dry etched using the patterned resist as a mask. Thereafter, if the resist is removed, the shape of the hole H3 is patterned in the insulating film 20, and the substrate 10 is exposed.

Next, the hole H3 is drilled in the substrate 10 by high-speed dry etching. Note that RIE or ICP (Inductively Coupled Plasma) can be used as dry etching. At this time, as described above, the insulating film 20 (SiO ₂ ) is used as a mask, but a resist may be used as a mask instead of the insulating film 20. The depth of the hole H3 is appropriately set according to the thickness of the semiconductor chip to be finally formed. That is, the depth of the hole H3 is set so that the tip of the electrode formed inside the hole H3 can be exposed on the back surface of the substrate 10 after the semiconductor chip is etched to the final thickness. As a result, the hole H3 is formed in the substrate 10 as shown in FIG. A recess H0 is formed from the active surface of the substrate 10 to the inside by the opening H1, the opening H2, and the hole H3.

Next, as illustrated in FIG. 4A, an insulating film 22 that is a first insulating layer is formed on the inner surface of the recess H <b> 0 and the surface of the insulating film 20. The insulating film 22 is made of, for example, PE-TEOS or O ₃ -TEOS, and is formed to have a surface film thickness of about 1 μm by, for example, plasma TEOS.

  Next, as shown in FIG. 4B, anisotropic etching is performed on the insulating film 22 and the insulating film 20 to expose a part of the electrode pad 16. In the present embodiment, a part of the surface of the electrode pad 16 is exposed at the peripheral edge of the opening H2. Specifically, a resist or the like is first applied to the entire surface of the insulating film 22, and the exposed portion is patterned. Next, the insulating film 22 and the insulating film 20 are anisotropically etched using the patterned resist as a mask. For this anisotropic etching, it is preferable to use dry etching such as RIE.

  Next, a base film 24 is formed on the exposed surface of the electrode pad 16 and the remaining surface of the insulating film 22. As the base film 24, a barrier layer is first formed, and a seed layer is formed thereon. The barrier layer and the seed layer are formed using, for example, a PVD (Phisical Vapor Deposition) method such as vacuum deposition, sputtering, or ion plating, a CVD method, an IMP (ion metal plasma) method, an electroless plating method, or the like.

  Next, as shown in FIG. 5A, an electrode 34 is formed. Specifically, a resist 32 is first applied on the entire upper surface of the substrate 10. As the resist 32, a liquid resist for plating or a dry film can be employed. In addition, although it is possible to use a resist used when etching an Al electrode generally provided in a semiconductor device or an insulating resin resist, it has resistance to a plating solution and an etching solution used in a process described later. That is the premise.

  The resist 32 is applied by a spin coating method, a dipping method, a spray coating method, or the like. Here, the thickness of the resist 32 is set to be approximately the same as the height of the post portion 35 of the electrode 34 to be formed plus the thickness of the solder layer 40. Note that pre-baking is performed after the resist 32 is applied.

  Next, the planar shape of the post portion 35 of the electrode 34 to be formed is patterned into a resist. Specifically, the resist 32 is patterned by performing exposure processing and development processing using a mask on which a predetermined pattern is formed. Here, if the post portion 35 has a rectangular planar shape, a rectangular opening is patterned in the resist 32. The size of the opening is set according to the pitch of the electrodes 34 in the semiconductor chip, and is formed to have a size of 120 μm square or 80 μm square, for example. Note that the size of the opening is set so that the resist 32 does not fall after patterning.

  The method for forming the resist 32 so as to surround the post portion 35 of the electrode 34 has been described above. However, the resist 32 is not necessarily formed so as to surround the entire circumference of the post portion 35. For example, when the electrodes 34 are formed adjacent to each other only in the left-right direction of the paper surface of FIG. 5A, the resist 32 need not be formed in the depth direction of the paper surface. As described above, the resist 32 is formed along at least a part of the outer shape of the post portion 35.

  The method for forming the resist 32 using the photolithography technique has been described above. However, when the resist 32 is formed by this method, when the resist is applied to the entire surface, a part of the resist may enter the hole H3 and remain as a residue in the hole H3 even if development processing is performed. Therefore, it is preferable to form the resist 32 in a patterned state by using, for example, a dry film or a printing method such as screen printing. Alternatively, the resist 32 may be formed in a patterned state by discharging a droplet of a resist only to a position where the resist 32 is formed using a droplet discharge device such as an inkjet device. Thereby, the resist 32 can be formed without entering the hole H3.

  Next, using this resist 32 as a mask, the electrode material is filled into the recess H0 to form the electrode. The electrode material is filled by a plating process, a CVD method, or the like. For the plating process, for example, an electrochemical plating (ECP) method is used. Note that a seed layer constituting the base film 24 is used as an electrode in the plating process. Moreover, a cup type plating apparatus is used as the plating apparatus. The cup-type plating apparatus is an apparatus that performs plating by ejecting a plating solution from a cup-shaped container. Thereby, the electrode material is filled in the recess H0, and the plug portion 36 is formed. Further, the opening formed in the resist 32 is also filled with the electrode material, and the post portion 35 is formed.

  Next, a solder layer 40 is formed on the upper surface of the electrode 34. The solder layer 40 is formed by a solder plating method or a printing method such as screen printing. A seed layer constituting the base film 24 can be used as an electrode for solder plating. Moreover, a cup type plating apparatus can be used as the plating apparatus. On the other hand, a hard wax material layer made of SnAg or the like may be formed instead of the solder layer 40. The hard wax material layer can also be formed by a plating method or a printing method. As a result, the state shown in FIG.

  Next, as shown in FIG. 5B, the resist 32 is stripped (removed) using a stripping solution or the like. Note that ozone water or the like can be used as the stripping solution. Subsequently, the base film 24 exposed above the substrate 10 is removed. Specifically, a resist or the like is first applied to the entire upper surface of the substrate 10 and the shape of the post portion 35 of the electrode 34 is patterned. Next, the base film 24 is dry-etched using the patterned resist as a mask. When a hard wax material layer is formed instead of the solder layer 40, the base film 24 can be etched using the hard wax material layer as a mask. In this case, since photolithography is not required, the manufacturing process can be simplified.

  Next, as shown in FIG. 6A, the substrate 10 is turned upside down, and the reinforcing member 50 is mounted below the substrate 10. Although a protective film or the like may be employed as the reinforcing member 50, it is preferable to employ a hard material such as glass. Thereby, when processing the back surface 10b of the board | substrate 10, it can prevent that a crack etc. generate | occur | produce in the board | substrate 10. FIG. The reinforcing member 50 is attached to the substrate 10 via an adhesive 52 or the like. As the adhesive 52, it is desirable to use a curable adhesive such as a thermosetting adhesive or a photocurable adhesive. Thereby, the reinforcing member 50 can be firmly attached while absorbing the irregularities on the active surface 10a of the substrate 10. Further, when a photocurable adhesive such as an ultraviolet curable adhesive is used as the adhesive 52, it is preferable to employ a light transmissive material such as glass as the reinforcing member 50. In this case, the adhesive 52 can be easily cured by irradiating light from the outside of the reinforcing member 50.

  Next, as shown in FIG. 6B, the entire back surface 10 b of the substrate 10 is etched to expose the insulating film 22 disposed at the tip of the electrode 34. Further, the exposed insulating film 22 is polished so that the side surface 37 b at the tip of the electrode 34 is exposed together with the tip surface 37 a of the electrode 34. The detailed method will be described later.

Next, as shown in FIG. 7, an insulating film 26 as a second insulating layer is formed in a region other than the region where the electrode 34 is formed on the back surface 10 b of the substrate 10. Specifically, the formation region of the electrode 34 is masked with a resist or the like, the insulating film 26 is formed in the other region, and the mask is finally removed. In the case where a film such as SiO ₂ or SiN is formed as the insulating film 26, it is preferably formed by a CVD method. Further, when a film such as PI is formed as the insulating film 26, it is preferable that the liquid film material is applied by spin coating, dried and baked. Further, the insulating film 26 may be formed using SOG. SOG (Spin On Glass) is a liquid that becomes SiO ₂ by baking at a temperature of about 400 ° C. after being applied, and is used for an interlayer insulating film of an LSI for the purpose of planarization. Specifically, it is a polymer having a siloxane bond as a basic structure, and alcohol or the like is used as a solvent. Also when applying this SOG, a spin coat method is used.

  Instead of masking the formation region of the electrode 34 and forming the insulation film 26 in other regions, the insulation film 26 is formed on the entire back surface 10b of the substrate 10 and disposed in the formation region of the electrode 34. The insulating film 26 may be removed simultaneously with the insulating film 22 by the polishing. In this case, patterning of the mask by photolithography becomes unnecessary, the manufacturing process is simplified, and the manufacturing cost can be reduced.

Thereafter, the adhesive 52 is dissolved with a solvent or the like, and the reinforcing member 50 is removed from the substrate 10. Next, a dicing tape (not shown) is attached to the back surface 10b of the substrate 10, and then the substrate 10 is diced to be separated into individual semiconductor chips. Note that the substrate 10 may be cut by irradiation with CO ₂ laser or YAG laser.
Thus, the state shown in FIG. 1 is obtained, and the semiconductor chip 2 according to the present embodiment is completed.

(Exposing method of electrode tip)
Here, a method for exposing the tip of the electrode 34 will be described. In the present embodiment, the tip of the electrode 34 is exposed by polishing the insulating film 22 disposed at the tip of the electrode 34.
FIG. 8 is an explanatory diagram of a method for exposing the electrode tip. FIG. 8A is an enlarged view around the tip of the electrode 34 in FIG. As shown in FIG. 8A, the tip of the electrode 34 disposed inside the semiconductor substrate 10 is exposed from the back surface 10 b of the semiconductor substrate 10. First, as shown in FIG. 8B, the back surface 10 b of the semiconductor substrate 10 is etched to expose the insulating film 22 disposed at the tip of the electrode 34. For this etching, either wet etching or dry etching may be used. If the back surface 10b of the substrate 10 is roughly polished with a grinder or the like and then etched to expose the insulating film 22, the manufacturing time can be shortened. Further, the insulating film 22 may be exposed by blasting the back surface 10b of the substrate 10.

  Next, as shown in FIG. 8C, the insulating film 22 is polished to expose the tip of the electrode 34. Specifically, the insulating film 22 and the base film 24 disposed at the tip portion of the electrode 34 are removed by polishing, and the side surface 37b at the tip portion of the electrode 34 is exposed together with the tip surface 37a of the electrode 34. At the same time, the peripheral edge of the tip surface 37a of the electrode 34 may be rounded.

  FIG. 9 is an explanatory diagram of various polishing methods. Various polishing methods can be used for the polishing. FIG. 9A shows a polishing method using a grinder. In this method, the substrate 82 is polished by rotating the disk 82 to which the grindstone is fixed, and is used for rough polishing. FIG. 9B shows a polishing method using a lapping machine. In this state, the substrate 10 is polished by rubbing the abrasive in which the free abrasive grains are dispersed between the substrate 10 and the wrap 84. With this lapping machine, it is possible to polish with higher accuracy than with a grinder. FIG. 9C is an explanatory diagram of a polishing method by CMP (Chemical and Mechanical Polishing). In CMP, the substrate 10 is polished by a balance between mechanical polishing by a polishing cloth (pad) 93 and chemical action by a polishing liquid (slurry) supplied thereto. This CMP enables polishing with higher accuracy than a lapping machine or a grinder. Hereinafter, a polishing method by CMP will be described as an example.

  FIG. 10 is an explanatory diagram of the polishing apparatus of the present embodiment. In the polishing apparatus 90 shown in FIG. 10, a surface plate 91 provided with a polishing cloth 93 and a head 95 on which a substrate to be polished is mounted are disposed to face each other. The surface plate 91 and the head 95 can be rotated in opposite directions in the horizontal plane, and the respective rotation axes are offset. On the other hand, slurry supply means 98 is provided near the facing portions of the surface plate 91 and the head 95. The slurry supply means 98 supplies the slurry 99 near the facing portions of the surface plate 91 and the head 95. As the slurry 99, it is possible to employ a slurry in which abrasive grains such as alumina, silica, and ceria are dispersed in a solution such as alkali.

  The surface plate 91 described above includes a polishing cloth 93. The polishing cloth 93 is formed of a hard foamed polyurethane or the like to a thickness of about 1 to 2 mm. As the polishing cloth 93, specifically, IC1000 manufactured by Rodel or the like can be used. The polishing cloth 93 is attached to the surface plate 91 via an elastic body 92 that is a first elastic member. The elastic body 92 is formed with a thickness of about 1 to 5 mm by soft foamed polyurethane or the like. As this elastic body 92, it is desirable to employ a material having a hardness of about 30 to 70, for example, and it is desirable to employ a material having an elastic recovery rate of about 70 to 90%. Specifically, it is possible to use Suba400 manufactured by Rodel.

  Next, a polishing method using the polishing apparatus 90 shown in FIG. 10 will be described. First, the semiconductor substrate 10 to be polished is mounted on the surface of the head 95. The semiconductor substrate 10 has the reinforcing member 50 mounted on the active surface 10a thereof, and the insulating film 22 disposed at the tip of the electrode 34 is exposed from the back surface 10b of the head 95 with the reinforcing member 50 in the back. Attach to the surface. Next, the slurry 99 is supplied from the slurry supply means 98 to the surface of the polishing pad 93 while rotating the surface plate 91 and the head 95. Then, the surface plate 91 and the head 95 are brought close to each other, and the substrate 10 mounted on the head 95 is brought into contact with the surface of the polishing cloth 93 mounted on the surface plate 91.

  Then, the irregularities on the surface of the polishing pad 93 and the abrasive grains contained in the slurry 99 mechanically polish the insulating film 22 disposed at the tip of the electrode 34. Further, an alkaline solution or the like constituting the slurry chemically acts on the insulating film 22. Thereby, the insulating film 22 is removed, and the tip surface of the electrode 34 is exposed. Further, since the polishing pad 93 is formed in a thin plate shape and is supported by the elastic body 92, the polishing pad 93 is freely deformed so as to wave. The polishing cloth 93 deformed in this manner abuts from the peripheral edge to the side of the tip end surface of the electrode 34, and mechanically polishes the insulating film 22 disposed in the portion. Therefore, the front end surface and the side surface of the front end portion of the electrode 34 can be exposed to the outside. As the insulating film 22 disposed at the tip of the electrode 34 is polished, the peripheral edge of the tip surface of the electrode 34 is also polished, and the portion is rounded.

  FIG. 11 is an explanatory view of a modified example of the polishing apparatus of the present embodiment. In this modification, the polishing pad 93 is directly attached to the surface plate 91, while the substrate 10 is attached to the head 95 via an elastic body 96 that is a first elastic member. This elastic body 96 is also made of soft foamed polyurethane or the like. Also in this case, since the substrate 10 is formed in a thin plate shape and is supported by the elastic body 96, the substrate 10 is freely deformed so as to wave. In this case, each electrode 34 formed on the substrate 10 can swing independently and abuts against the polishing pad 93 at various angles, so that the insulating film 22 disposed at the tip of the electrode 34 is polished. . Therefore, the tip surface and the side surface at the tip of the electrode 34 can be exposed to the outside.

  FIG. 12 is an enlarged view of the electrode bonding portion when the semiconductor chips are stacked. FIG. 12A shows the stacked state of the semiconductor chips manufactured according to the present embodiment, and FIG. 12B shows the stacked state of the semiconductor chips manufactured by the conventional technique. In the semiconductor chip manufacturing method according to the prior art, since the insulating film 22 disposed at the tip of the electrode 34 is removed by two-dimensional polishing, only the tip surface 37a of the electrode 34 is shown in FIG. Is exposed. Therefore, the solder layer 40 is accommodated only on the tip surface 37 a of the electrode 34. On the other hand, in the semiconductor chip manufacturing method according to the present embodiment, the insulating film 22 disposed at the tip of the electrode 34 is removed by three-dimensional polishing, so that the electrode as shown in FIG. In addition to the tip end surface 37a of 34, the side surface 37b is exposed. As a result, the solder layer 40 is accommodated on the side surface 37b in addition to the tip end surface 37a of the electrode 34, and the fillet of the solder layer 40 is formed so as to ride on the side surface 37b. Therefore, the bonding area between the electrodes is increased, and the mechanical and electrical bonding reliability can be improved.

[Second Embodiment]
Next, a semiconductor chip manufacturing method according to the second embodiment of the present invention will be described with reference to FIG.
FIG. 13 is an explanatory diagram of a polishing apparatus according to the second embodiment. In the semiconductor chip manufacturing method according to the second embodiment, the raised cloth 94 is disposed on the surface of the polishing pad 93, and the insulating film 22 disposed on the distal end portion of the electrode 34 is polished, so that the distal end surface of the electrode 34 is obtained. The side surface at the tip of the electrode 34 is exposed. Note that a detailed description of portions having the same configuration as the semiconductor chip manufacturing method of the first embodiment is omitted.

  In the polishing apparatus of the second embodiment shown in FIG. 13, a polishing cloth 93 is directly attached to the surface plate 91. And the raising 94 is arranged on the surface of the polishing pad 93. This raising 94 consists of elastic fibers, such as nylon, and is formed in height 1-2mm. Then, the substrate 10 mounted on the head 95 is brought into contact with the polishing cloth 93 mounted on the surface plate 91 to perform polishing. Then, the raised portions 94 arranged on the surface of the polishing cloth 93 are freely deformed, abut against the side surface from the tip surface of the electrode 34, and the insulating film 22 arranged in the portion is mechanically polished. Further, the slurry trapped on the raised brush 94 chemically acts on the side surface from the front end surface of the electrode 34. Therefore, the front end surface and the side surface of the front end portion of the electrode 34 can be exposed to the outside.

  FIG. 14 is an explanatory diagram of a modified example of the polishing apparatus according to the present embodiment. This modification is a combination of the polishing apparatus of the first embodiment, its modification, and the polishing apparatus of the second embodiment. That is, the substrate 10 is attached to the head 95 via the elastic body 96, and the polishing pad 93 is attached to the surface plate 91 via the elastic body 92. Further, raised brushes 94 that can be freely deformed are arranged on the surface of the polishing pad 93. When the substrate 10 is brought into contact with the polishing cloth 93 and polished, the substrate 10 and the polishing cloth 93 are freely deformed so as to wave, and the brushed 94 or the polishing cloth 93 extends from the peripheral edge to the side surface of the tip surface of the electrode 34. Abuts and mechanically polishes the insulating film 22 disposed in the portion. Therefore, the front end surface and the side surface of the front end portion of the electrode 34 can be exposed to the outside.

  As described in detail above, in the semiconductor chip manufacturing method according to the second embodiment, the raised film 94 is disposed on the surface of the polishing pad 93 and the insulating film 22 disposed at the tip of the electrode 34 is polished. Thus, the side surface of the distal end portion of the electrode 34 is exposed together with the distal end surface of the electrode 34. Thereby, in addition to the front end surface of the electrode 34, the solder layer is accommodated on the side surface when the semiconductor chips are stacked. Therefore, the bonding area between the electrodes is increased, and the mechanical and electrical bonding reliability can be improved.

[Laminated structure]
The semiconductor chips formed as described above are stacked to form a three-dimensionally mounted semiconductor device. FIG. 15 is a side cross-sectional view showing a state in which semiconductor chips according to the embodiment are stacked, and FIG. 16 is an enlarged view of a portion A in FIG. Each of the semiconductor chips 2a and 2b is arranged so that the lower end surface of the plug portion of the electrode 34 in the upper semiconductor chip 2a is positioned on the upper surface of the post portion of the electrode 34 in the lower semiconductor chip 2b. Then, as shown in FIG. 16, the electrodes 34 in the respective semiconductor chips 2 a and 2 b are bonded to each other through the solder layer 40. Specifically, the semiconductor chips 2a and 2b are pressed against each other while the solder layer 40 is dissolved by reflow. As a result, a solder alloy is formed at the joint between the solder layer 40 and the electrode 34, and both are mechanically and electrically joined. Thus, the semiconductor chips 2a and 2b are connected by wiring. If necessary, an underfill is filled in the gaps between the stacked semiconductor chips.

  By the way, the melted solder layer 40 is deformed upward along the outer periphery of the plug portion 36 of the electrode in the upper semiconductor chip 2a, and thus may be in contact with the back surface 10b of the upper semiconductor chip 2a. In addition, since a signal line is connected to the solder layer 40 and a ground is connected to the back surface 10b of the semiconductor chip 2a, it is necessary to prevent a short circuit between them. In this respect, in this embodiment, since the insulating film 26 is formed on the back surface 10b of the semiconductor chip 2a, a short circuit between the solder layer 40 and the back surface 10b of the semiconductor chip 2a is prevented when the semiconductor chips are stacked. Is possible. Therefore, three-dimensional mounting can be performed while preventing a short circuit between the signal line and the ground.

[Relocation wiring]
In order to mount the semiconductor device stacked as described above on the circuit board, it is desirable to perform rewiring. First, rewiring will be briefly described. FIG. 17 is an explanatory diagram of the rewiring of the semiconductor chip. Since a plurality of electrodes 62 are formed along the opposite side of the surface of the semiconductor chip 61 shown in FIG. 17A, the pitch between adjacent electrodes is narrowed. When such a semiconductor chip 61 is mounted on a circuit board, adjacent electrodes may be short-circuited. Therefore, in order to widen the pitch between the electrodes, rewiring is performed to draw out the plurality of electrodes 62 formed along the opposite sides of the semiconductor chip 61 to the center.

  FIG. 17B is a plan view of the semiconductor chip on which rewiring has been performed. A plurality of circular electrode pads 63 are arranged on the matrix at the center of the surface of the semiconductor chip 61. Each electrode pad 63 is connected to one or a plurality of electrodes 62 by rewiring 64. As a result, the narrow-pitch electrodes 62 are drawn out to the central portion, and the pitch is increased.

  FIG. 18 is a side cross-sectional view taken along line AA in FIG. A semiconductor resist 65 shown in FIG. 18 is formed at the center of the bottom surface of the semiconductor chip 61 that is the lowermost layer by vertically inverting the semiconductor device formed as described above. A rewiring 64 is formed from the post portion of the electrode 62 to the surface of the solder resist 65. An electrode pad 63 is formed at the end of the rewiring 64 on the solder resist 65 side, and a bump 78 is formed on the surface of the electrode pad. The bump 78 is, for example, a solder bump and is formed by a printing method or the like. A reinforcing resin 66 and the like are molded on the entire bottom surface of the semiconductor chip 61.

[Circuit board]
FIG. 19 is a perspective view of a circuit board. In FIG. 19, the semiconductor device 1 formed by stacking semiconductor chips is mounted on a circuit board 1000. Specifically, bumps formed on the lowermost semiconductor chip in the semiconductor device 1 are mounted by performing reflow, FCB (Flip Chip Bonding), or the like on the electrode pads formed on the surface of the circuit board 1000. Has been. The semiconductor device 1 may be mounted with an anisotropic conductive film or the like sandwiched between the circuit board.

[Electronics]
Next, an example of an electronic device including the above-described semiconductor device is described with reference to FIGS. FIG. 20 is a perspective view of a mobile phone. The semiconductor device described above is arranged inside the housing of the mobile phone 300.

  Note that the semiconductor device described above can be applied to various electronic devices other than mobile phones. For example, LCD projectors, multimedia-compatible personal computers (PCs) and engineering workstations (EWS), pagers, word processors, TVs, viewfinder type or monitor direct view type video tape recorders, electronic notebooks, electronic desk calculators, car navigation systems The present invention can be applied to electronic devices such as a device, a POS terminal, and a device provided with a touch panel.

  It should be noted that an electronic component can be manufactured by replacing the “semiconductor chip” in the above-described embodiment with an “electronic element”. Examples of electronic components manufactured using such electronic elements include optical elements, resistors, capacitors, coils, oscillators, filters, temperature sensors, thermistors, varistors, volumes, and fuses.

  It should be noted that the technical scope of the present invention is not limited to the above-described embodiments, and includes those in which various modifications are made to the above-described embodiments without departing from the spirit of the present invention. In other words, the specific materials and layer configurations described in the embodiments are merely examples, and can be changed as appropriate.

It is side surface sectional drawing in the electrode part of the semiconductor chip which concerns on 1st Embodiment. It is side surface sectional drawing of the modification of the semiconductor chip which concerns on 1st Embodiment. It is explanatory drawing of the manufacturing method of the semiconductor chip which concerns on 1st Embodiment. It is explanatory drawing of the manufacturing method of the semiconductor chip which concerns on 1st Embodiment. It is explanatory drawing of the manufacturing method of the semiconductor chip which concerns on 1st Embodiment. It is explanatory drawing of the manufacturing method of the semiconductor chip which concerns on 1st Embodiment. It is explanatory drawing of the manufacturing method of the semiconductor chip which concerns on 1st Embodiment. It is explanatory drawing of the exposure method of an electrode front-end | tip part. It is explanatory drawing of various grinding | polishing methods. It is explanatory drawing of the grinding | polishing apparatus of 1st Embodiment. It is explanatory drawing of the modification of the grinding | polishing apparatus of 1st Embodiment. It is an enlarged view of the electrode junction part at the time of lamination | stacking of a semiconductor chip. It is explanatory drawing of the grinding | polishing apparatus of 2nd Embodiment. It is explanatory drawing of the modification of the grinding | polishing apparatus of 2nd Embodiment. It is side surface sectional drawing of the whole laminated | stacked semiconductor device. It is side surface sectional drawing in the electrode part of the laminated | stacked semiconductor device. It is explanatory drawing of rewiring. It is explanatory drawing of rewiring. It is explanatory drawing of a circuit board. It is a perspective view of the mobile phone which is an example of an electronic device. It is explanatory drawing of the exposure method of the electrode front-end | tip part which concerns on a prior art.

Explanation of symbols

  10 Semiconductor substrate 10b Back 34 Electrode 92 Elastic body 93 Polishing cloth

Claims (12)

A method of manufacturing a semiconductor device having an electrode penetrating a semiconductor substrate,
A method of manufacturing a semiconductor device, wherein the side surface of the tip of the electrode is exposed together with the tip of the electrode by polishing the tip of the electrode protruding from the semiconductor substrate. A method of manufacturing a semiconductor device having an electrode penetrating a semiconductor substrate,
Forming a recess from the active surface to the inside of the semiconductor substrate on which the integrated circuit is formed;
Forming a first insulating layer on the inner surface of the recess;
Filling the inside of the first insulating layer with a conductive material to form the electrode;
Removing the back surface of the semiconductor substrate to expose the first insulating layer disposed at the tip of the electrode;
Polishing the first insulating layer to expose the side surface of the tip of the electrode together with the tip of the electrode;
A method for manufacturing a semiconductor device, comprising: The polishing is performed by bringing a polishing means into contact with the tip of the electrode,
The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor substrate or the polishing unit is supported via a first elastic member. 4. The method of manufacturing a semiconductor device according to claim 1, wherein the polishing is performed by bringing a polishing means made of a second elastic member into contact with a tip portion of the electrode. The method of manufacturing a semiconductor device according to claim 4, wherein the second elastic member is a raised brush disposed on a surface of a polishing cloth. 6. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of forming a second insulating layer on the back surface of the semiconductor substrate. The method for manufacturing a semiconductor device according to claim 6, wherein the second insulating layer formed at the tip of the electrode is removed by the polishing. Forming an electrode cap made of a conductive material that is less likely to be oxidized than the constituent material of the electrode at the tip of the electrode,
The method for manufacturing a semiconductor device according to claim 1, wherein a side surface of a tip portion of the electrode cap is exposed together with a tip surface of the electrode cap by the polishing. A semiconductor device manufactured using the method for manufacturing a semiconductor device according to claim 1. 10. A semiconductor device comprising a plurality of semiconductor devices according to claim 9, wherein electrodes of adjacent semiconductor devices are electrically connected to each other. A circuit board on which the semiconductor device according to claim 9 or 10 is mounted. An electronic apparatus comprising the semiconductor device according to claim 9.

Images